* [PATCH] drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
@ 2019-10-23 12:06 ` Tapani Pälli
0 siblings, 0 replies; 20+ messages in thread
From: Tapani Pälli @ 2019-10-23 12:06 UTC (permalink / raw)
To: intel-gfx
As with commit 3fe0107e45ab, this change fixes multiple tests that are
using the invocation counts. Documentation doesn't list the workaround
for TGL but applying it fixes the tests.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index af8a8183154a..86ded203b2dd 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1215,6 +1215,26 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
static void tgl_whitelist_build(struct intel_engine_cs *engine)
{
+ struct i915_wa_list *w = &engine->whitelist;
+
+ switch (engine->class) {
+ case RENDER_CLASS:
+ /*
+ * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl
+ *
+ * This covers 4 registers which are next to one another :
+ * - PS_INVOCATION_COUNT
+ * - PS_INVOCATION_COUNT_UDW
+ * - PS_DEPTH_COUNT
+ * - PS_DEPTH_COUNT_UDW
+ */
+ whitelist_reg_ext(w, PS_INVOCATION_COUNT,
+ RING_FORCE_TO_NONPRIV_ACCESS_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4);
+ break;
+ default:
+ break;
+ }
}
void intel_engine_init_whitelist(struct intel_engine_cs *engine)
--
2.21.0
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^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
@ 2019-10-23 12:06 ` Tapani Pälli
0 siblings, 0 replies; 20+ messages in thread
From: Tapani Pälli @ 2019-10-23 12:06 UTC (permalink / raw)
To: intel-gfx
As with commit 3fe0107e45ab, this change fixes multiple tests that are
using the invocation counts. Documentation doesn't list the workaround
for TGL but applying it fixes the tests.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index af8a8183154a..86ded203b2dd 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1215,6 +1215,26 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
static void tgl_whitelist_build(struct intel_engine_cs *engine)
{
+ struct i915_wa_list *w = &engine->whitelist;
+
+ switch (engine->class) {
+ case RENDER_CLASS:
+ /*
+ * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl
+ *
+ * This covers 4 registers which are next to one another :
+ * - PS_INVOCATION_COUNT
+ * - PS_INVOCATION_COUNT_UDW
+ * - PS_DEPTH_COUNT
+ * - PS_DEPTH_COUNT_UDW
+ */
+ whitelist_reg_ext(w, PS_INVOCATION_COUNT,
+ RING_FORCE_TO_NONPRIV_ACCESS_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4);
+ break;
+ default:
+ break;
+ }
}
void intel_engine_init_whitelist(struct intel_engine_cs *engine)
--
2.21.0
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^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH] drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
@ 2019-10-23 12:30 ` Chris Wilson
0 siblings, 0 replies; 20+ messages in thread
From: Chris Wilson @ 2019-10-23 12:30 UTC (permalink / raw)
To: Tapani Pälli, intel-gfx
Quoting Tapani Pälli (2019-10-23 13:06:18)
> As with commit 3fe0107e45ab, this change fixes multiple tests that are
> using the invocation counts. Documentation doesn't list the workaround
> for TGL but applying it fixes the tests.
>
> Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
@ 2019-10-23 12:30 ` Chris Wilson
0 siblings, 0 replies; 20+ messages in thread
From: Chris Wilson @ 2019-10-23 12:30 UTC (permalink / raw)
To: Tapani Pälli, intel-gfx
Quoting Tapani Pälli (2019-10-23 13:06:18)
> As with commit 3fe0107e45ab, this change fixes multiple tests that are
> using the invocation counts. Documentation doesn't list the workaround
> for TGL but applying it fixes the tests.
>
> Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
_______________________________________________
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
@ 2019-10-23 12:47 ` Lionel Landwerlin
0 siblings, 0 replies; 20+ messages in thread
From: Lionel Landwerlin @ 2019-10-23 12:47 UTC (permalink / raw)
To: Tapani Pälli, intel-gfx
On 23/10/2019 15:06, Tapani Pälli wrote:
> As with commit 3fe0107e45ab, this change fixes multiple tests that are
> using the invocation counts. Documentation doesn't list the workaround
> for TGL but applying it fixes the tests.
>
> Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index af8a8183154a..86ded203b2dd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1215,6 +1215,26 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
>
> static void tgl_whitelist_build(struct intel_engine_cs *engine)
> {
> + struct i915_wa_list *w = &engine->whitelist;
> +
> + switch (engine->class) {
> + case RENDER_CLASS:
> + /*
> + * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl
> + *
> + * This covers 4 registers which are next to one another :
> + * - PS_INVOCATION_COUNT
> + * - PS_INVOCATION_COUNT_UDW
> + * - PS_DEPTH_COUNT
> + * - PS_DEPTH_COUNT_UDW
> + */
> + whitelist_reg_ext(w, PS_INVOCATION_COUNT,
> + RING_FORCE_TO_NONPRIV_ACCESS_RD |
> + RING_FORCE_TO_NONPRIV_RANGE_4);
> + break;
> + default:
> + break;
> + }
> }
>
> void intel_engine_init_whitelist(struct intel_engine_cs *engine)
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
@ 2019-10-23 12:47 ` Lionel Landwerlin
0 siblings, 0 replies; 20+ messages in thread
From: Lionel Landwerlin @ 2019-10-23 12:47 UTC (permalink / raw)
To: Tapani Pälli, intel-gfx
On 23/10/2019 15:06, Tapani Pälli wrote:
> As with commit 3fe0107e45ab, this change fixes multiple tests that are
> using the invocation counts. Documentation doesn't list the workaround
> for TGL but applying it fixes the tests.
>
> Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index af8a8183154a..86ded203b2dd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1215,6 +1215,26 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
>
> static void tgl_whitelist_build(struct intel_engine_cs *engine)
> {
> + struct i915_wa_list *w = &engine->whitelist;
> +
> + switch (engine->class) {
> + case RENDER_CLASS:
> + /*
> + * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl
> + *
> + * This covers 4 registers which are next to one another :
> + * - PS_INVOCATION_COUNT
> + * - PS_INVOCATION_COUNT_UDW
> + * - PS_DEPTH_COUNT
> + * - PS_DEPTH_COUNT_UDW
> + */
> + whitelist_reg_ext(w, PS_INVOCATION_COUNT,
> + RING_FORCE_TO_NONPRIV_ACCESS_RD |
> + RING_FORCE_TO_NONPRIV_RANGE_4);
> + break;
> + default:
> + break;
> + }
> }
>
> void intel_engine_init_whitelist(struct intel_engine_cs *engine)
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
@ 2019-10-23 16:12 ` Mika Kuoppala
0 siblings, 0 replies; 20+ messages in thread
From: Mika Kuoppala @ 2019-10-23 16:12 UTC (permalink / raw)
To: Tapani Pälli, intel-gfx
Tapani Pälli <tapani.palli@intel.com> writes:
> As with commit 3fe0107e45ab, this change fixes multiple tests that are
> using the invocation counts. Documentation doesn't list the workaround
> for TGL but applying it fixes the tests.
>
> Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index af8a8183154a..86ded203b2dd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1215,6 +1215,26 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
>
> static void tgl_whitelist_build(struct intel_engine_cs *engine)
> {
> + struct i915_wa_list *w = &engine->whitelist;
> +
> + switch (engine->class) {
> + case RENDER_CLASS:
> + /*
> + * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl
Tried to find info about this but failed.
> + *
> + * This covers 4 registers which are next to one another :
> + * - PS_INVOCATION_COUNT
> + * - PS_INVOCATION_COUNT_UDW
> + * - PS_DEPTH_COUNT
> + * - PS_DEPTH_COUNT_UDW
> + */
> + whitelist_reg_ext(w, PS_INVOCATION_COUNT,
> + RING_FORCE_TO_NONPRIV_ACCESS_RD |
> + RING_FORCE_TO_NONPRIV_RANGE_4);
The register spec is identical with gen11 so ok to whitelist.
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> + break;
> + default:
> + break;
> + }
> }
>
> void intel_engine_init_whitelist(struct intel_engine_cs *engine)
> --
> 2.21.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
@ 2019-10-23 16:12 ` Mika Kuoppala
0 siblings, 0 replies; 20+ messages in thread
From: Mika Kuoppala @ 2019-10-23 16:12 UTC (permalink / raw)
To: Tapani Pälli, intel-gfx
Tapani Pälli <tapani.palli@intel.com> writes:
> As with commit 3fe0107e45ab, this change fixes multiple tests that are
> using the invocation counts. Documentation doesn't list the workaround
> for TGL but applying it fixes the tests.
>
> Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index af8a8183154a..86ded203b2dd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1215,6 +1215,26 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
>
> static void tgl_whitelist_build(struct intel_engine_cs *engine)
> {
> + struct i915_wa_list *w = &engine->whitelist;
> +
> + switch (engine->class) {
> + case RENDER_CLASS:
> + /*
> + * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl
Tried to find info about this but failed.
> + *
> + * This covers 4 registers which are next to one another :
> + * - PS_INVOCATION_COUNT
> + * - PS_INVOCATION_COUNT_UDW
> + * - PS_DEPTH_COUNT
> + * - PS_DEPTH_COUNT_UDW
> + */
> + whitelist_reg_ext(w, PS_INVOCATION_COUNT,
> + RING_FORCE_TO_NONPRIV_ACCESS_RD |
> + RING_FORCE_TO_NONPRIV_RANGE_4);
The register spec is identical with gen11 so ok to whitelist.
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> + break;
> + default:
> + break;
> + }
> }
>
> void intel_engine_init_whitelist(struct intel_engine_cs *engine)
> --
> 2.21.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
@ 2019-10-23 18:59 ` Lionel Landwerlin
0 siblings, 0 replies; 20+ messages in thread
From: Lionel Landwerlin @ 2019-10-23 18:59 UTC (permalink / raw)
To: Mika Kuoppala, Tapani Pälli, intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 2200 bytes --]
On 23/10/2019 19:12, Mika Kuoppala wrote:
> Tapani Pälli <tapani.palli@intel.com> writes:
>
>> As with commit 3fe0107e45ab, this change fixes multiple tests that are
>> using the invocation counts. Documentation doesn't list the workaround
>> for TGL but applying it fixes the tests.
>>
>> Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 ++++++++++++++++++++
>> 1 file changed, 20 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index af8a8183154a..86ded203b2dd 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -1215,6 +1215,26 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
>>
>> static void tgl_whitelist_build(struct intel_engine_cs *engine)
>> {
>> + struct i915_wa_list *w = &engine->whitelist;
>> +
>> + switch (engine->class) {
>> + case RENDER_CLASS:
>> + /*
>> + * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl
> Tried to find info about this but failed.
It probably got renamed, it started with CFL stepping C+ and wasn't
listed for ICL.
¯\_(ツ)_/¯
-Lionel
>
>> + *
>> + * This covers 4 registers which are next to one another :
>> + * - PS_INVOCATION_COUNT
>> + * - PS_INVOCATION_COUNT_UDW
>> + * - PS_DEPTH_COUNT
>> + * - PS_DEPTH_COUNT_UDW
>> + */
>> + whitelist_reg_ext(w, PS_INVOCATION_COUNT,
>> + RING_FORCE_TO_NONPRIV_ACCESS_RD |
>> + RING_FORCE_TO_NONPRIV_RANGE_4);
> The register spec is identical with gen11 so ok to whitelist.
>
> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>
>> + break;
>> + default:
>> + break;
>> + }
>> }
>>
>> void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>> --
>> 2.21.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[-- Attachment #1.2: Type: text/html, Size: 4279 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
@ 2019-10-23 18:59 ` Lionel Landwerlin
0 siblings, 0 replies; 20+ messages in thread
From: Lionel Landwerlin @ 2019-10-23 18:59 UTC (permalink / raw)
To: Mika Kuoppala, Tapani Pälli, intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 2200 bytes --]
On 23/10/2019 19:12, Mika Kuoppala wrote:
> Tapani Pälli <tapani.palli@intel.com> writes:
>
>> As with commit 3fe0107e45ab, this change fixes multiple tests that are
>> using the invocation counts. Documentation doesn't list the workaround
>> for TGL but applying it fixes the tests.
>>
>> Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 ++++++++++++++++++++
>> 1 file changed, 20 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index af8a8183154a..86ded203b2dd 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -1215,6 +1215,26 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
>>
>> static void tgl_whitelist_build(struct intel_engine_cs *engine)
>> {
>> + struct i915_wa_list *w = &engine->whitelist;
>> +
>> + switch (engine->class) {
>> + case RENDER_CLASS:
>> + /*
>> + * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl
> Tried to find info about this but failed.
It probably got renamed, it started with CFL stepping C+ and wasn't
listed for ICL.
¯\_(ツ)_/¯
-Lionel
>
>> + *
>> + * This covers 4 registers which are next to one another :
>> + * - PS_INVOCATION_COUNT
>> + * - PS_INVOCATION_COUNT_UDW
>> + * - PS_DEPTH_COUNT
>> + * - PS_DEPTH_COUNT_UDW
>> + */
>> + whitelist_reg_ext(w, PS_INVOCATION_COUNT,
>> + RING_FORCE_TO_NONPRIV_ACCESS_RD |
>> + RING_FORCE_TO_NONPRIV_RANGE_4);
> The register spec is identical with gen11 so ok to whitelist.
>
> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>
>> + break;
>> + default:
>> + break;
>> + }
>> }
>>
>> void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>> --
>> 2.21.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[-- Attachment #1.2: Type: text/html, Size: 4279 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
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^ permalink raw reply [flat|nested] 20+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
@ 2019-10-23 20:49 ` Patchwork
0 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2019-10-23 20:49 UTC (permalink / raw)
To: Tapani Pälli; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
URL : https://patchwork.freedesktop.org/series/68455/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
aaf5cc0a4c3b drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
-:9: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 3fe0107e45ab ("drm/i915/icl: whitelist PS_(DEPTH|INVOCATION)_COUNT")'
#9:
As with commit 3fe0107e45ab, this change fixes multiple tests that are
total: 1 errors, 0 warnings, 0 checks, 26 lines checked
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
@ 2019-10-23 20:49 ` Patchwork
0 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2019-10-23 20:49 UTC (permalink / raw)
To: Tapani Pälli; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
URL : https://patchwork.freedesktop.org/series/68455/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
aaf5cc0a4c3b drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
-:9: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 3fe0107e45ab ("drm/i915/icl: whitelist PS_(DEPTH|INVOCATION)_COUNT")'
#9:
As with commit 3fe0107e45ab, this change fixes multiple tests that are
total: 1 errors, 0 warnings, 0 checks, 26 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
@ 2019-10-23 21:20 ` Patchwork
0 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2019-10-23 21:20 UTC (permalink / raw)
To: Tapani Pälli; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
URL : https://patchwork.freedesktop.org/series/68455/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7165 -> Patchwork_14947
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_14947 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14947, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14947:
### IGT changes ###
#### Possible regressions ####
* igt@i915_pm_rpm@basic-rte:
- fi-skl-6600u: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-skl-6600u/igt@i915_pm_rpm@basic-rte.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-skl-6600u/igt@i915_pm_rpm@basic-rte.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_workarounds:
- {fi-tgl-u}: [PASS][3] -> [DMESG-FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-tgl-u/igt@i915_selftest@live_workarounds.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-tgl-u/igt@i915_selftest@live_workarounds.html
Known issues
------------
Here are the changes found in Patchwork_14947 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_flink_basic@bad-flink:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-icl-u3/igt@gem_flink_basic@bad-flink.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-icl-u3/igt@gem_flink_basic@bad-flink.html
* igt@i915_selftest@live_coherency:
- fi-cfl-8109u: [PASS][7] -> [TIMEOUT][8] ([fdo#111944])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-cfl-8109u/igt@i915_selftest@live_coherency.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-cfl-8109u/igt@i915_selftest@live_coherency.html
#### Possible fixes ####
* igt@gem_ctx_create@basic-files:
- fi-bxt-dsi: [INCOMPLETE][9] ([fdo#103927]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-bxt-dsi/igt@gem_ctx_create@basic-files.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-bxt-dsi/igt@gem_ctx_create@basic-files.html
- {fi-tgl-u2}: [INCOMPLETE][11] ([fdo#111735]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-tgl-u2/igt@gem_ctx_create@basic-files.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-tgl-u2/igt@gem_ctx_create@basic-files.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14] +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-icl-u3/igt@gem_exec_suspend@basic-s4-devices.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-icl-u3/igt@gem_exec_suspend@basic-s4-devices.html
* {igt@i915_selftest@live_gt_timelines}:
- {fi-tgl-u}: [INCOMPLETE][15] ([fdo#111831]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-tgl-u/igt@i915_selftest@live_gt_timelines.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-tgl-u/igt@i915_selftest@live_gt_timelines.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [FAIL][17] ([fdo#109483]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
- fi-kbl-7500u: [FAIL][19] ([fdo#111407]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-kbl-7500u: [FAIL][21] ([fdo#103375]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-kbl-7500u/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-kbl-7500u/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
[fdo#111831]: https://bugs.freedesktop.org/show_bug.cgi?id=111831
[fdo#111944]: https://bugs.freedesktop.org/show_bug.cgi?id=111944
Participating hosts (51 -> 45)
------------------------------
Additional (1): fi-bwr-2160
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7165 -> Patchwork_14947
CI-20190529: 20190529
CI_DRM_7165: b50cc0bc0f669a3c3ead36573496596b8b8ed8f4 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5236: 8153b95b53bdef26d2c3e318197d174e982b4265 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14947: aaf5cc0a4c3b4e615e589f50f4f509c6ff5d07d0 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
aaf5cc0a4c3b drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
@ 2019-10-23 21:20 ` Patchwork
0 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2019-10-23 21:20 UTC (permalink / raw)
To: Tapani Pälli; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
URL : https://patchwork.freedesktop.org/series/68455/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7165 -> Patchwork_14947
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_14947 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14947, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14947:
### IGT changes ###
#### Possible regressions ####
* igt@i915_pm_rpm@basic-rte:
- fi-skl-6600u: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-skl-6600u/igt@i915_pm_rpm@basic-rte.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-skl-6600u/igt@i915_pm_rpm@basic-rte.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_workarounds:
- {fi-tgl-u}: [PASS][3] -> [DMESG-FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-tgl-u/igt@i915_selftest@live_workarounds.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-tgl-u/igt@i915_selftest@live_workarounds.html
Known issues
------------
Here are the changes found in Patchwork_14947 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_flink_basic@bad-flink:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-icl-u3/igt@gem_flink_basic@bad-flink.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-icl-u3/igt@gem_flink_basic@bad-flink.html
* igt@i915_selftest@live_coherency:
- fi-cfl-8109u: [PASS][7] -> [TIMEOUT][8] ([fdo#111944])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-cfl-8109u/igt@i915_selftest@live_coherency.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-cfl-8109u/igt@i915_selftest@live_coherency.html
#### Possible fixes ####
* igt@gem_ctx_create@basic-files:
- fi-bxt-dsi: [INCOMPLETE][9] ([fdo#103927]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-bxt-dsi/igt@gem_ctx_create@basic-files.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-bxt-dsi/igt@gem_ctx_create@basic-files.html
- {fi-tgl-u2}: [INCOMPLETE][11] ([fdo#111735]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-tgl-u2/igt@gem_ctx_create@basic-files.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-tgl-u2/igt@gem_ctx_create@basic-files.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14] +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-icl-u3/igt@gem_exec_suspend@basic-s4-devices.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-icl-u3/igt@gem_exec_suspend@basic-s4-devices.html
* {igt@i915_selftest@live_gt_timelines}:
- {fi-tgl-u}: [INCOMPLETE][15] ([fdo#111831]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-tgl-u/igt@i915_selftest@live_gt_timelines.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-tgl-u/igt@i915_selftest@live_gt_timelines.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [FAIL][17] ([fdo#109483]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
- fi-kbl-7500u: [FAIL][19] ([fdo#111407]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-kbl-7500u: [FAIL][21] ([fdo#103375]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-kbl-7500u/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-kbl-7500u/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
[fdo#111831]: https://bugs.freedesktop.org/show_bug.cgi?id=111831
[fdo#111944]: https://bugs.freedesktop.org/show_bug.cgi?id=111944
Participating hosts (51 -> 45)
------------------------------
Additional (1): fi-bwr-2160
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7165 -> Patchwork_14947
CI-20190529: 20190529
CI_DRM_7165: b50cc0bc0f669a3c3ead36573496596b8b8ed8f4 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5236: 8153b95b53bdef26d2c3e318197d174e982b4265 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14947: aaf5cc0a4c3b4e615e589f50f4f509c6ff5d07d0 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
aaf5cc0a4c3b drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
@ 2019-10-23 21:49 ` Chris Wilson
0 siblings, 0 replies; 20+ messages in thread
From: Chris Wilson @ 2019-10-23 21:49 UTC (permalink / raw)
To: Tapani Pälli, Patchwork; +Cc: intel-gfx
Quoting Patchwork (2019-10-23 22:20:49)
> * igt@i915_selftest@live_workarounds:
> - {fi-tgl-u}: [PASS][3] -> [DMESG-FAIL][4]
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-tgl-u/igt@i915_selftest@live_workarounds.html
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-tgl-u/igt@i915_selftest@live_workarounds.html
That does seem to be genuine and worth following up with.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
@ 2019-10-23 21:49 ` Chris Wilson
0 siblings, 0 replies; 20+ messages in thread
From: Chris Wilson @ 2019-10-23 21:49 UTC (permalink / raw)
To: Tapani Pälli, Patchwork, intel-gfx; +Cc: intel-gfx
Quoting Patchwork (2019-10-23 22:20:49)
> * igt@i915_selftest@live_workarounds:
> - {fi-tgl-u}: [PASS][3] -> [DMESG-FAIL][4]
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-tgl-u/igt@i915_selftest@live_workarounds.html
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-tgl-u/igt@i915_selftest@live_workarounds.html
That does seem to be genuine and worth following up with.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
@ 2019-10-24 6:39 ` Tapani Pälli
0 siblings, 0 replies; 20+ messages in thread
From: Tapani Pälli @ 2019-10-24 6:39 UTC (permalink / raw)
To: Chris Wilson, Patchwork, intel-gfx
On 10/24/19 12:49 AM, Chris Wilson wrote:
> Quoting Patchwork (2019-10-23 22:20:49)
>> * igt@i915_selftest@live_workarounds:
>> - {fi-tgl-u}: [PASS][3] -> [DMESG-FAIL][4]
>> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-tgl-u/igt@i915_selftest@live_workarounds.html
>> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-tgl-u/igt@i915_selftest@live_workarounds.html
>
> That does seem to be genuine and worth following up with.
> -Chris
>
Yes, I've reproduced this locally. Any ideas appreciated here ..
Thanks;
// Tapani
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
@ 2019-10-24 6:39 ` Tapani Pälli
0 siblings, 0 replies; 20+ messages in thread
From: Tapani Pälli @ 2019-10-24 6:39 UTC (permalink / raw)
To: Chris Wilson, Patchwork, intel-gfx
On 10/24/19 12:49 AM, Chris Wilson wrote:
> Quoting Patchwork (2019-10-23 22:20:49)
>> * igt@i915_selftest@live_workarounds:
>> - {fi-tgl-u}: [PASS][3] -> [DMESG-FAIL][4]
>> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-tgl-u/igt@i915_selftest@live_workarounds.html
>> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-tgl-u/igt@i915_selftest@live_workarounds.html
>
> That does seem to be genuine and worth following up with.
> -Chris
>
Yes, I've reproduced this locally. Any ideas appreciated here ..
Thanks;
// Tapani
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
@ 2019-10-24 6:48 ` Chris Wilson
0 siblings, 0 replies; 20+ messages in thread
From: Chris Wilson @ 2019-10-24 6:48 UTC (permalink / raw)
To: Tapani Pälli, Patchwork, intel-gfx
Quoting Tapani Pälli (2019-10-24 07:39:50)
>
>
> On 10/24/19 12:49 AM, Chris Wilson wrote:
> > Quoting Patchwork (2019-10-23 22:20:49)
> >> * igt@i915_selftest@live_workarounds:
> >> - {fi-tgl-u}: [PASS][3] -> [DMESG-FAIL][4]
> >> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-tgl-u/igt@i915_selftest@live_workarounds.html
> >> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-tgl-u/igt@i915_selftest@live_workarounds.html
> >
> > That does seem to be genuine and worth following up with.
> > -Chris
> >
>
> Yes, I've reproduced this locally. Any ideas appreciated here ..
There are two things the test can take care of, stripping the high bit
and replicating the fuzzing across the entire range. Stripping the high
bit is /likely/ enough to circumvent the issue (depending on root cause
of the issue). But the GPU is not meant to hang on bogus LRI; the HW
validator is meant to no-op them.
-Chris
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
@ 2019-10-24 6:48 ` Chris Wilson
0 siblings, 0 replies; 20+ messages in thread
From: Chris Wilson @ 2019-10-24 6:48 UTC (permalink / raw)
To: Tapani Pälli, Patchwork, intel-gfx
Quoting Tapani Pälli (2019-10-24 07:39:50)
>
>
> On 10/24/19 12:49 AM, Chris Wilson wrote:
> > Quoting Patchwork (2019-10-23 22:20:49)
> >> * igt@i915_selftest@live_workarounds:
> >> - {fi-tgl-u}: [PASS][3] -> [DMESG-FAIL][4]
> >> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-tgl-u/igt@i915_selftest@live_workarounds.html
> >> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-tgl-u/igt@i915_selftest@live_workarounds.html
> >
> > That does seem to be genuine and worth following up with.
> > -Chris
> >
>
> Yes, I've reproduced this locally. Any ideas appreciated here ..
There are two things the test can take care of, stripping the high bit
and replicating the fuzzing across the entire range. Stripping the high
bit is /likely/ enough to circumvent the issue (depending on root cause
of the issue). But the GPU is not meant to hang on bogus LRI; the HW
validator is meant to no-op them.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2019-10-24 6:49 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-10-23 12:06 [PATCH] drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT Tapani Pälli
2019-10-23 12:06 ` [Intel-gfx] " Tapani Pälli
2019-10-23 12:30 ` Chris Wilson
2019-10-23 12:30 ` [Intel-gfx] " Chris Wilson
2019-10-23 12:47 ` Lionel Landwerlin
2019-10-23 12:47 ` [Intel-gfx] " Lionel Landwerlin
2019-10-23 16:12 ` Mika Kuoppala
2019-10-23 16:12 ` [Intel-gfx] " Mika Kuoppala
2019-10-23 18:59 ` Lionel Landwerlin
2019-10-23 18:59 ` [Intel-gfx] " Lionel Landwerlin
2019-10-23 20:49 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2019-10-23 20:49 ` [Intel-gfx] " Patchwork
2019-10-23 21:20 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-10-23 21:20 ` [Intel-gfx] " Patchwork
2019-10-23 21:49 ` Chris Wilson
2019-10-23 21:49 ` [Intel-gfx] " Chris Wilson
2019-10-24 6:39 ` Tapani Pälli
2019-10-24 6:39 ` [Intel-gfx] " Tapani Pälli
2019-10-24 6:48 ` Chris Wilson
2019-10-24 6:48 ` [Intel-gfx] " Chris Wilson
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