From: Jani Nikula <jani.nikula@intel.com> To: Jani Nikula <jani.nikula@intel.com>, intel-gfx@lists.freedesktop.org Subject: [PATCH v2] drm/i915/bios: add compression parameter block definition Date: Thu, 24 Oct 2019 10:56:08 +0300 [thread overview] Message-ID: <20191024075608.11511-1-jani.nikula@intel.com> (raw) In-Reply-To: <20191022140300.20872-1-jani.nikula@intel.com> Add definition for block 56, the compression parameters. v2: add missing slice_height (Vandita) Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index e3045ced4bfe..69a7cb1fa121 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -114,6 +114,7 @@ enum bdb_block_id { BDB_LVDS_POWER = 44, BDB_MIPI_CONFIG = 52, BDB_MIPI_SEQUENCE = 53, + BDB_COMPRESSION_PARAMETERS = 56, BDB_SKIP = 254, /* VBIOS private block, ignore */ }; @@ -811,4 +812,55 @@ struct bdb_mipi_sequence { u8 data[0]; /* up to 6 variable length blocks */ } __packed; +/* + * Block 56 - Compression Parameters + */ + +#define VBT_RC_BUFFER_BLOCK_SIZE_1KB 0 +#define VBT_RC_BUFFER_BLOCK_SIZE_4KB 1 +#define VBT_RC_BUFFER_BLOCK_SIZE_16KB 2 +#define VBT_RC_BUFFER_BLOCK_SIZE_64KB 3 + +#define VBT_DSC_LINE_BUFFER_DEPTH(vbt_value) ((vbt_value) + 8) /* bits */ +#define VBT_DSC_MAX_BPP(vbt_value) (6 + (vbt_value) * 2) + +struct dsc_compression_parameters_entry { + u8 version_major:4; + u8 version_minor:4; + + u8 rc_buffer_block_size:2; + u8 reserved1:6; + + /* + * Buffer size in bytes: + * + * 4 ^ rc_buffer_block_size * 1024 * (rc_buffer_size + 1) bytes + */ + u8 rc_buffer_size; + u32 slices_per_line; + + u8 line_buffer_depth:4; + u8 reserved2:4; + + /* Flag Bits 1 */ + u8 block_prediction_enable:1; + u8 reserved3:7; + + u8 max_bpp; /* mapping */ + + /* Color depth capabilities */ + u8 reserved4:1; + u8 support_8bpc:1; + u8 support_10bpc:1; + u8 support_12bpc:1; + u8 reserved5:4; + + u16 slice_height; +} __packed; + +struct bdb_compression_parameters { + u16 entry_size; + struct dsc_compression_parameters_entry data[16]; +} __packed; + #endif /* _INTEL_VBT_DEFS_H_ */ -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: Jani Nikula <jani.nikula@intel.com> To: Jani Nikula <jani.nikula@intel.com>, intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v2] drm/i915/bios: add compression parameter block definition Date: Thu, 24 Oct 2019 10:56:08 +0300 [thread overview] Message-ID: <20191024075608.11511-1-jani.nikula@intel.com> (raw) Message-ID: <20191024075608.Iwd5WxZ3cZ7NHIhVJQSRlv5PDi8qiIZ9kuW7UpHQPcQ@z> (raw) In-Reply-To: <20191022140300.20872-1-jani.nikula@intel.com> Add definition for block 56, the compression parameters. v2: add missing slice_height (Vandita) Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index e3045ced4bfe..69a7cb1fa121 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -114,6 +114,7 @@ enum bdb_block_id { BDB_LVDS_POWER = 44, BDB_MIPI_CONFIG = 52, BDB_MIPI_SEQUENCE = 53, + BDB_COMPRESSION_PARAMETERS = 56, BDB_SKIP = 254, /* VBIOS private block, ignore */ }; @@ -811,4 +812,55 @@ struct bdb_mipi_sequence { u8 data[0]; /* up to 6 variable length blocks */ } __packed; +/* + * Block 56 - Compression Parameters + */ + +#define VBT_RC_BUFFER_BLOCK_SIZE_1KB 0 +#define VBT_RC_BUFFER_BLOCK_SIZE_4KB 1 +#define VBT_RC_BUFFER_BLOCK_SIZE_16KB 2 +#define VBT_RC_BUFFER_BLOCK_SIZE_64KB 3 + +#define VBT_DSC_LINE_BUFFER_DEPTH(vbt_value) ((vbt_value) + 8) /* bits */ +#define VBT_DSC_MAX_BPP(vbt_value) (6 + (vbt_value) * 2) + +struct dsc_compression_parameters_entry { + u8 version_major:4; + u8 version_minor:4; + + u8 rc_buffer_block_size:2; + u8 reserved1:6; + + /* + * Buffer size in bytes: + * + * 4 ^ rc_buffer_block_size * 1024 * (rc_buffer_size + 1) bytes + */ + u8 rc_buffer_size; + u32 slices_per_line; + + u8 line_buffer_depth:4; + u8 reserved2:4; + + /* Flag Bits 1 */ + u8 block_prediction_enable:1; + u8 reserved3:7; + + u8 max_bpp; /* mapping */ + + /* Color depth capabilities */ + u8 reserved4:1; + u8 support_8bpc:1; + u8 support_10bpc:1; + u8 support_12bpc:1; + u8 reserved5:4; + + u16 slice_height; +} __packed; + +struct bdb_compression_parameters { + u16 entry_size; + struct dsc_compression_parameters_entry data[16]; +} __packed; + #endif /* _INTEL_VBT_DEFS_H_ */ -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-10-24 7:56 UTC|newest] Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-10-22 14:03 [PATCH] drm/i915/bios: add compression parameter block definition Jani Nikula 2019-10-22 22:59 ` ✓ Fi.CI.BAT: success for " Patchwork 2019-10-23 14:25 ` ✓ Fi.CI.IGT: " Patchwork 2019-10-23 14:25 ` [Intel-gfx] " Patchwork 2019-10-23 18:41 ` [PATCH] " Manasi Navare 2019-10-23 18:41 ` [Intel-gfx] " Manasi Navare 2019-10-24 7:51 ` Jani Nikula 2019-10-24 7:51 ` [Intel-gfx] " Jani Nikula 2019-10-24 17:13 ` Manasi Navare 2019-10-24 17:13 ` [Intel-gfx] " Manasi Navare 2019-10-24 7:36 ` Kulkarni, Vandita 2019-10-24 7:36 ` [Intel-gfx] " Kulkarni, Vandita 2019-10-24 8:05 ` Jani Nikula 2019-10-24 8:05 ` [Intel-gfx] " Jani Nikula 2019-10-24 8:07 ` Kulkarni, Vandita 2019-10-24 8:07 ` [Intel-gfx] " Kulkarni, Vandita 2019-10-24 7:56 ` Jani Nikula [this message] 2019-10-24 7:56 ` [Intel-gfx] [PATCH v2] " Jani Nikula 2019-10-24 8:29 ` Kulkarni, Vandita 2019-10-24 8:29 ` [Intel-gfx] " Kulkarni, Vandita 2019-10-24 10:07 ` ✓ Fi.CI.BAT: success for drm/i915/bios: add compression parameter block definition (rev2) Patchwork 2019-10-24 10:07 ` [Intel-gfx] " Patchwork 2019-10-25 11:54 ` ✗ Fi.CI.IGT: failure " Patchwork 2019-10-25 11:54 ` [Intel-gfx] " Patchwork 2019-10-28 11:37 ` Jani Nikula 2019-10-28 11:37 ` [Intel-gfx] " Jani Nikula
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