* [PATCH 1/5] drm/i915/selftests: Drop global engine lookup for gt selftests @ 2019-10-27 22:58 ` Chris Wilson 0 siblings, 0 replies; 24+ messages in thread From: Chris Wilson @ 2019-10-27 22:58 UTC (permalink / raw) To: intel-gfx; +Cc: matthew.auld As we are inside the gt, we have a local gt->engine[] lookup we should be using in preference over the i915->engine[] copy. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index ba761fcf397b..b7207b488391 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -1016,7 +1016,7 @@ static int igt_reset_wait(void *arg) { struct intel_gt *gt = arg; struct i915_gpu_error *global = >->i915->gpu_error; - struct intel_engine_cs *engine = gt->i915->engine[RCS0]; + struct intel_engine_cs *engine = gt->engine[RCS0]; struct i915_request *rq; unsigned int reset_count; struct hang h; @@ -1143,7 +1143,7 @@ static int __igt_reset_evict_vma(struct intel_gt *gt, int (*fn)(void *), unsigned int flags) { - struct intel_engine_cs *engine = gt->i915->engine[RCS0]; + struct intel_engine_cs *engine = gt->engine[RCS0]; struct drm_i915_gem_object *obj; struct task_struct *tsk = NULL; struct i915_request *rq; @@ -1493,7 +1493,7 @@ static int igt_handle_error(void *arg) { struct intel_gt *gt = arg; struct i915_gpu_error *global = >->i915->gpu_error; - struct intel_engine_cs *engine = gt->i915->engine[RCS0]; + struct intel_engine_cs *engine = gt->engine[RCS0]; struct hang h; struct i915_request *rq; struct i915_gpu_state *error; -- 2.24.0.rc1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH 1/5] drm/i915/selftests: Drop global engine lookup for gt selftests @ 2019-10-27 22:58 ` Chris Wilson 0 siblings, 0 replies; 24+ messages in thread From: Chris Wilson @ 2019-10-27 22:58 UTC (permalink / raw) To: intel-gfx; +Cc: matthew.auld As we are inside the gt, we have a local gt->engine[] lookup we should be using in preference over the i915->engine[] copy. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index ba761fcf397b..b7207b488391 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -1016,7 +1016,7 @@ static int igt_reset_wait(void *arg) { struct intel_gt *gt = arg; struct i915_gpu_error *global = >->i915->gpu_error; - struct intel_engine_cs *engine = gt->i915->engine[RCS0]; + struct intel_engine_cs *engine = gt->engine[RCS0]; struct i915_request *rq; unsigned int reset_count; struct hang h; @@ -1143,7 +1143,7 @@ static int __igt_reset_evict_vma(struct intel_gt *gt, int (*fn)(void *), unsigned int flags) { - struct intel_engine_cs *engine = gt->i915->engine[RCS0]; + struct intel_engine_cs *engine = gt->engine[RCS0]; struct drm_i915_gem_object *obj; struct task_struct *tsk = NULL; struct i915_request *rq; @@ -1493,7 +1493,7 @@ static int igt_handle_error(void *arg) { struct intel_gt *gt = arg; struct i915_gpu_error *global = >->i915->gpu_error; - struct intel_engine_cs *engine = gt->i915->engine[RCS0]; + struct intel_engine_cs *engine = gt->engine[RCS0]; struct hang h; struct i915_request *rq; struct i915_gpu_state *error; -- 2.24.0.rc1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 2/5] drm/i915/selftests: Exercise adjusting rpcs over all render-class engines @ 2019-10-27 22:58 ` Chris Wilson 0 siblings, 0 replies; 24+ messages in thread From: Chris Wilson @ 2019-10-27 22:58 UTC (permalink / raw) To: intel-gfx; +Cc: matthew.auld Iterate over all user-accessible render engines when checking whether they can be adjusted for sseu. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- .../drm/i915/gem/selftests/i915_gem_context.c | 127 +++++++++--------- 1 file changed, 61 insertions(+), 66 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c index 2c65c9e95cc5..d1d873f23338 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c @@ -1186,93 +1186,90 @@ __igt_ctx_sseu(struct drm_i915_private *i915, const char *name, unsigned int flags) { - struct intel_engine_cs *engine = i915->engine[RCS0]; struct drm_i915_gem_object *obj; - struct i915_gem_context *ctx; - struct intel_context *ce; - struct intel_sseu pg_sseu; - struct drm_file *file; + int inst = 0; int ret; - if (INTEL_GEN(i915) < 9 || !engine) + if (INTEL_GEN(i915) < 9 || !RUNTIME_INFO(i915)->sseu.has_slice_pg) return 0; - if (!RUNTIME_INFO(i915)->sseu.has_slice_pg) - return 0; - - if (hweight32(engine->sseu.slice_mask) < 2) - return 0; - - /* - * Gen11 VME friendly power-gated configuration with half enabled - * sub-slices. - */ - pg_sseu = engine->sseu; - pg_sseu.slice_mask = 1; - pg_sseu.subslice_mask = - ~(~0 << (hweight32(engine->sseu.subslice_mask) / 2)); - - pr_info("SSEU subtest '%s', flags=%x, def_slices=%u, pg_slices=%u\n", - name, flags, hweight32(engine->sseu.slice_mask), - hweight32(pg_sseu.slice_mask)); - - file = mock_file(i915); - if (IS_ERR(file)) - return PTR_ERR(file); - if (flags & TEST_RESET) igt_global_reset_lock(&i915->gt); - ctx = live_context(i915, file); - if (IS_ERR(ctx)) { - ret = PTR_ERR(ctx); - goto out_unlock; - } - i915_gem_context_clear_bannable(ctx); /* to reset and beyond! */ - obj = i915_gem_object_create_internal(i915, PAGE_SIZE); if (IS_ERR(obj)) { ret = PTR_ERR(obj); goto out_unlock; } - ce = i915_gem_context_get_engine(ctx, RCS0); - if (IS_ERR(ce)) { - ret = PTR_ERR(ce); - goto out_put; - } + do { + struct intel_engine_cs *engine; + struct intel_context *ce; + struct intel_sseu pg_sseu; - ret = intel_context_pin(ce); - if (ret) - goto out_context; + engine = intel_engine_lookup_user(i915, + I915_ENGINE_CLASS_RENDER, + inst++); + if (!engine) + break; - /* First set the default mask. */ - ret = __sseu_test(name, flags, ce, obj, engine->sseu); - if (ret) - goto out_fail; + if (hweight32(engine->sseu.slice_mask) < 2) + continue; - /* Then set a power-gated configuration. */ - ret = __sseu_test(name, flags, ce, obj, pg_sseu); - if (ret) - goto out_fail; + /* + * Gen11 VME friendly power-gated configuration with + * half enabled sub-slices. + */ + pg_sseu = engine->sseu; + pg_sseu.slice_mask = 1; + pg_sseu.subslice_mask = + ~(~0 << (hweight32(engine->sseu.subslice_mask) / 2)); + + pr_info("%s: SSEU subtest '%s', flags=%x, def_slices=%u, pg_slices=%u\n", + engine->name, name, flags, + hweight32(engine->sseu.slice_mask), + hweight32(pg_sseu.slice_mask)); + + ce = intel_context_create(engine->kernel_context->gem_context, + engine); + if (IS_ERR(ce)) { + ret = PTR_ERR(ce); + goto out_put; + } - /* Back to defaults. */ - ret = __sseu_test(name, flags, ce, obj, engine->sseu); - if (ret) - goto out_fail; + ret = intel_context_pin(ce); + if (ret) + goto out_ce; - /* One last power-gated configuration for the road. */ - ret = __sseu_test(name, flags, ce, obj, pg_sseu); - if (ret) - goto out_fail; + /* First set the default mask. */ + ret = __sseu_test(name, flags, ce, obj, engine->sseu); + if (ret) + goto out_unpin; + + /* Then set a power-gated configuration. */ + ret = __sseu_test(name, flags, ce, obj, pg_sseu); + if (ret) + goto out_unpin; + + /* Back to defaults. */ + ret = __sseu_test(name, flags, ce, obj, engine->sseu); + if (ret) + goto out_unpin; + + /* One last power-gated configuration for the road. */ + ret = __sseu_test(name, flags, ce, obj, pg_sseu); + if (ret) + goto out_unpin; + +out_unpin: + intel_context_unpin(ce); +out_ce: + intel_context_put(ce); + } while (!ret); -out_fail: if (igt_flush_test(i915)) ret = -EIO; - intel_context_unpin(ce); -out_context: - intel_context_put(ce); out_put: i915_gem_object_put(obj); @@ -1280,8 +1277,6 @@ __igt_ctx_sseu(struct drm_i915_private *i915, if (flags & TEST_RESET) igt_global_reset_unlock(&i915->gt); - mock_file_free(i915, file); - if (ret) pr_err("%s: Failed with %d!\n", name, ret); -- 2.24.0.rc1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH 2/5] drm/i915/selftests: Exercise adjusting rpcs over all render-class engines @ 2019-10-27 22:58 ` Chris Wilson 0 siblings, 0 replies; 24+ messages in thread From: Chris Wilson @ 2019-10-27 22:58 UTC (permalink / raw) To: intel-gfx; +Cc: matthew.auld Iterate over all user-accessible render engines when checking whether they can be adjusted for sseu. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- .../drm/i915/gem/selftests/i915_gem_context.c | 127 +++++++++--------- 1 file changed, 61 insertions(+), 66 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c index 2c65c9e95cc5..d1d873f23338 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c @@ -1186,93 +1186,90 @@ __igt_ctx_sseu(struct drm_i915_private *i915, const char *name, unsigned int flags) { - struct intel_engine_cs *engine = i915->engine[RCS0]; struct drm_i915_gem_object *obj; - struct i915_gem_context *ctx; - struct intel_context *ce; - struct intel_sseu pg_sseu; - struct drm_file *file; + int inst = 0; int ret; - if (INTEL_GEN(i915) < 9 || !engine) + if (INTEL_GEN(i915) < 9 || !RUNTIME_INFO(i915)->sseu.has_slice_pg) return 0; - if (!RUNTIME_INFO(i915)->sseu.has_slice_pg) - return 0; - - if (hweight32(engine->sseu.slice_mask) < 2) - return 0; - - /* - * Gen11 VME friendly power-gated configuration with half enabled - * sub-slices. - */ - pg_sseu = engine->sseu; - pg_sseu.slice_mask = 1; - pg_sseu.subslice_mask = - ~(~0 << (hweight32(engine->sseu.subslice_mask) / 2)); - - pr_info("SSEU subtest '%s', flags=%x, def_slices=%u, pg_slices=%u\n", - name, flags, hweight32(engine->sseu.slice_mask), - hweight32(pg_sseu.slice_mask)); - - file = mock_file(i915); - if (IS_ERR(file)) - return PTR_ERR(file); - if (flags & TEST_RESET) igt_global_reset_lock(&i915->gt); - ctx = live_context(i915, file); - if (IS_ERR(ctx)) { - ret = PTR_ERR(ctx); - goto out_unlock; - } - i915_gem_context_clear_bannable(ctx); /* to reset and beyond! */ - obj = i915_gem_object_create_internal(i915, PAGE_SIZE); if (IS_ERR(obj)) { ret = PTR_ERR(obj); goto out_unlock; } - ce = i915_gem_context_get_engine(ctx, RCS0); - if (IS_ERR(ce)) { - ret = PTR_ERR(ce); - goto out_put; - } + do { + struct intel_engine_cs *engine; + struct intel_context *ce; + struct intel_sseu pg_sseu; - ret = intel_context_pin(ce); - if (ret) - goto out_context; + engine = intel_engine_lookup_user(i915, + I915_ENGINE_CLASS_RENDER, + inst++); + if (!engine) + break; - /* First set the default mask. */ - ret = __sseu_test(name, flags, ce, obj, engine->sseu); - if (ret) - goto out_fail; + if (hweight32(engine->sseu.slice_mask) < 2) + continue; - /* Then set a power-gated configuration. */ - ret = __sseu_test(name, flags, ce, obj, pg_sseu); - if (ret) - goto out_fail; + /* + * Gen11 VME friendly power-gated configuration with + * half enabled sub-slices. + */ + pg_sseu = engine->sseu; + pg_sseu.slice_mask = 1; + pg_sseu.subslice_mask = + ~(~0 << (hweight32(engine->sseu.subslice_mask) / 2)); + + pr_info("%s: SSEU subtest '%s', flags=%x, def_slices=%u, pg_slices=%u\n", + engine->name, name, flags, + hweight32(engine->sseu.slice_mask), + hweight32(pg_sseu.slice_mask)); + + ce = intel_context_create(engine->kernel_context->gem_context, + engine); + if (IS_ERR(ce)) { + ret = PTR_ERR(ce); + goto out_put; + } - /* Back to defaults. */ - ret = __sseu_test(name, flags, ce, obj, engine->sseu); - if (ret) - goto out_fail; + ret = intel_context_pin(ce); + if (ret) + goto out_ce; - /* One last power-gated configuration for the road. */ - ret = __sseu_test(name, flags, ce, obj, pg_sseu); - if (ret) - goto out_fail; + /* First set the default mask. */ + ret = __sseu_test(name, flags, ce, obj, engine->sseu); + if (ret) + goto out_unpin; + + /* Then set a power-gated configuration. */ + ret = __sseu_test(name, flags, ce, obj, pg_sseu); + if (ret) + goto out_unpin; + + /* Back to defaults. */ + ret = __sseu_test(name, flags, ce, obj, engine->sseu); + if (ret) + goto out_unpin; + + /* One last power-gated configuration for the road. */ + ret = __sseu_test(name, flags, ce, obj, pg_sseu); + if (ret) + goto out_unpin; + +out_unpin: + intel_context_unpin(ce); +out_ce: + intel_context_put(ce); + } while (!ret); -out_fail: if (igt_flush_test(i915)) ret = -EIO; - intel_context_unpin(ce); -out_context: - intel_context_put(ce); out_put: i915_gem_object_put(obj); @@ -1280,8 +1277,6 @@ __igt_ctx_sseu(struct drm_i915_private *i915, if (flags & TEST_RESET) igt_global_reset_unlock(&i915->gt); - mock_file_free(i915, file); - if (ret) pr_err("%s: Failed with %d!\n", name, ret); -- 2.24.0.rc1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 2/5] drm/i915/selftests: Exercise adjusting rpcs over all render-class engines @ 2019-10-28 12:04 ` Matthew Auld 0 siblings, 0 replies; 24+ messages in thread From: Matthew Auld @ 2019-10-28 12:04 UTC (permalink / raw) To: Chris Wilson; +Cc: Intel Graphics Development, Matthew Auld On Sun, 27 Oct 2019 at 22:58, Chris Wilson <chris@chris-wilson.co.uk> wrote: > > Iterate over all user-accessible render engines when checking whether > they can be adjusted for sseu. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 2/5] drm/i915/selftests: Exercise adjusting rpcs over all render-class engines @ 2019-10-28 12:04 ` Matthew Auld 0 siblings, 0 replies; 24+ messages in thread From: Matthew Auld @ 2019-10-28 12:04 UTC (permalink / raw) To: Chris Wilson; +Cc: Intel Graphics Development, Matthew Auld On Sun, 27 Oct 2019 at 22:58, Chris Wilson <chris@chris-wilson.co.uk> wrote: > > Iterate over all user-accessible render engines when checking whether > they can be adjusted for sseu. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 3/5] drm/i915/selftests: Check all blitter engines for client blt @ 2019-10-27 22:58 ` Chris Wilson 0 siblings, 0 replies; 24+ messages in thread From: Chris Wilson @ 2019-10-27 22:58 UTC (permalink / raw) To: intel-gfx; +Cc: matthew.auld Check all user accessible engines that can blit work with our blitter client. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- .../i915/gem/selftests/i915_gem_client_blt.c | 30 ++++++++++++++++--- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c index d8804a847945..da8edee4fe0a 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c @@ -5,6 +5,7 @@ #include "i915_selftest.h" +#include "gt/intel_engine_user.h" #include "gt/intel_gt.h" #include "selftests/igt_flush_test.h" @@ -12,10 +13,9 @@ #include "huge_gem_object.h" #include "mock_context.h" -static int igt_client_fill(void *arg) +static int __igt_client_fill(struct intel_engine_cs *engine) { - struct drm_i915_private *i915 = arg; - struct intel_context *ce = i915->engine[BCS0]->kernel_context; + struct intel_context *ce = engine->kernel_context; struct drm_i915_gem_object *obj; struct rnd_state prng; IGT_TIMEOUT(end); @@ -37,7 +37,7 @@ static int igt_client_fill(void *arg) pr_debug("%s with phys_sz= %x, sz=%x, val=%x\n", __func__, phys_sz, sz, val); - obj = huge_gem_object(i915, phys_sz, sz); + obj = huge_gem_object(engine->i915, phys_sz, sz); if (IS_ERR(obj)) { err = PTR_ERR(obj); goto err_flush; @@ -103,6 +103,28 @@ static int igt_client_fill(void *arg) return err; } +static int igt_client_fill(void *arg) +{ + int inst = 0; + + do { + struct intel_engine_cs *engine; + int err; + + engine = intel_engine_lookup_user(arg, + I915_ENGINE_CLASS_COPY, + inst++); + if (!engine) + return 0; + + err = __igt_client_fill(engine); + if (err == -ENOMEM) + err = 0; + if (err) + return err; + } while (1); +} + int i915_gem_client_blt_live_selftests(struct drm_i915_private *i915) { static const struct i915_subtest tests[] = { -- 2.24.0.rc1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH 3/5] drm/i915/selftests: Check all blitter engines for client blt @ 2019-10-27 22:58 ` Chris Wilson 0 siblings, 0 replies; 24+ messages in thread From: Chris Wilson @ 2019-10-27 22:58 UTC (permalink / raw) To: intel-gfx; +Cc: matthew.auld Check all user accessible engines that can blit work with our blitter client. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- .../i915/gem/selftests/i915_gem_client_blt.c | 30 ++++++++++++++++--- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c index d8804a847945..da8edee4fe0a 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c @@ -5,6 +5,7 @@ #include "i915_selftest.h" +#include "gt/intel_engine_user.h" #include "gt/intel_gt.h" #include "selftests/igt_flush_test.h" @@ -12,10 +13,9 @@ #include "huge_gem_object.h" #include "mock_context.h" -static int igt_client_fill(void *arg) +static int __igt_client_fill(struct intel_engine_cs *engine) { - struct drm_i915_private *i915 = arg; - struct intel_context *ce = i915->engine[BCS0]->kernel_context; + struct intel_context *ce = engine->kernel_context; struct drm_i915_gem_object *obj; struct rnd_state prng; IGT_TIMEOUT(end); @@ -37,7 +37,7 @@ static int igt_client_fill(void *arg) pr_debug("%s with phys_sz= %x, sz=%x, val=%x\n", __func__, phys_sz, sz, val); - obj = huge_gem_object(i915, phys_sz, sz); + obj = huge_gem_object(engine->i915, phys_sz, sz); if (IS_ERR(obj)) { err = PTR_ERR(obj); goto err_flush; @@ -103,6 +103,28 @@ static int igt_client_fill(void *arg) return err; } +static int igt_client_fill(void *arg) +{ + int inst = 0; + + do { + struct intel_engine_cs *engine; + int err; + + engine = intel_engine_lookup_user(arg, + I915_ENGINE_CLASS_COPY, + inst++); + if (!engine) + return 0; + + err = __igt_client_fill(engine); + if (err == -ENOMEM) + err = 0; + if (err) + return err; + } while (1); +} + int i915_gem_client_blt_live_selftests(struct drm_i915_private *i915) { static const struct i915_subtest tests[] = { -- 2.24.0.rc1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 3/5] drm/i915/selftests: Check all blitter engines for client blt @ 2019-10-28 11:16 ` Matthew Auld 0 siblings, 0 replies; 24+ messages in thread From: Matthew Auld @ 2019-10-28 11:16 UTC (permalink / raw) To: Chris Wilson; +Cc: Intel Graphics Development, Matthew Auld On Sun, 27 Oct 2019 at 22:58, Chris Wilson <chris@chris-wilson.co.uk> wrote: > > Check all user accessible engines that can blit work with our blitter > client. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 3/5] drm/i915/selftests: Check all blitter engines for client blt @ 2019-10-28 11:16 ` Matthew Auld 0 siblings, 0 replies; 24+ messages in thread From: Matthew Auld @ 2019-10-28 11:16 UTC (permalink / raw) To: Chris Wilson; +Cc: Intel Graphics Development, Matthew Auld On Sun, 27 Oct 2019 at 22:58, Chris Wilson <chris@chris-wilson.co.uk> wrote: > > Check all user accessible engines that can blit work with our blitter > client. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 4/5] drm/i915/selftests: Use a random engine for GEM coherency tests @ 2019-10-27 22:58 ` Chris Wilson 0 siblings, 0 replies; 24+ messages in thread From: Chris Wilson @ 2019-10-27 22:58 UTC (permalink / raw) To: intel-gfx; +Cc: matthew.auld Select a random user accessible engine for checking coherency results. While we should check all engines, we use a random selection so that over repeated runs we cover all. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- .../i915/gem/selftests/i915_gem_coherency.c | 168 ++++++++++-------- 1 file changed, 89 insertions(+), 79 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c index 0877ef4dff63..0a195e5b98e6 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c @@ -13,9 +13,12 @@ #include "i915_selftest.h" #include "selftests/i915_random.h" -static int cpu_set(struct drm_i915_gem_object *obj, - unsigned long offset, - u32 v) +struct context { + struct drm_i915_gem_object *obj; + struct intel_engine_cs *engine; +}; + +static int cpu_set(struct context *ctx, unsigned long offset, u32 v) { unsigned int needs_clflush; struct page *page; @@ -23,11 +26,11 @@ static int cpu_set(struct drm_i915_gem_object *obj, u32 *cpu; int err; - err = i915_gem_object_prepare_write(obj, &needs_clflush); + err = i915_gem_object_prepare_write(ctx->obj, &needs_clflush); if (err) return err; - page = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT); + page = i915_gem_object_get_page(ctx->obj, offset >> PAGE_SHIFT); map = kmap_atomic(page); cpu = map + offset_in_page(offset); @@ -40,14 +43,12 @@ static int cpu_set(struct drm_i915_gem_object *obj, drm_clflush_virt_range(cpu, sizeof(*cpu)); kunmap_atomic(map); - i915_gem_object_finish_access(obj); + i915_gem_object_finish_access(ctx->obj); return 0; } -static int cpu_get(struct drm_i915_gem_object *obj, - unsigned long offset, - u32 *v) +static int cpu_get(struct context *ctx, unsigned long offset, u32 *v) { unsigned int needs_clflush; struct page *page; @@ -55,11 +56,11 @@ static int cpu_get(struct drm_i915_gem_object *obj, u32 *cpu; int err; - err = i915_gem_object_prepare_read(obj, &needs_clflush); + err = i915_gem_object_prepare_read(ctx->obj, &needs_clflush); if (err) return err; - page = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT); + page = i915_gem_object_get_page(ctx->obj, offset >> PAGE_SHIFT); map = kmap_atomic(page); cpu = map + offset_in_page(offset); @@ -69,26 +70,24 @@ static int cpu_get(struct drm_i915_gem_object *obj, *v = *cpu; kunmap_atomic(map); - i915_gem_object_finish_access(obj); + i915_gem_object_finish_access(ctx->obj); return 0; } -static int gtt_set(struct drm_i915_gem_object *obj, - unsigned long offset, - u32 v) +static int gtt_set(struct context *ctx, unsigned long offset, u32 v) { struct i915_vma *vma; u32 __iomem *map; int err = 0; - i915_gem_object_lock(obj); - err = i915_gem_object_set_to_gtt_domain(obj, true); - i915_gem_object_unlock(obj); + i915_gem_object_lock(ctx->obj); + err = i915_gem_object_set_to_gtt_domain(ctx->obj, true); + i915_gem_object_unlock(ctx->obj); if (err) return err; - vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE); + vma = i915_gem_object_ggtt_pin(ctx->obj, NULL, 0, 0, PIN_MAPPABLE); if (IS_ERR(vma)) return PTR_ERR(vma); @@ -109,21 +108,19 @@ static int gtt_set(struct drm_i915_gem_object *obj, return err; } -static int gtt_get(struct drm_i915_gem_object *obj, - unsigned long offset, - u32 *v) +static int gtt_get(struct context *ctx, unsigned long offset, u32 *v) { struct i915_vma *vma; u32 __iomem *map; int err = 0; - i915_gem_object_lock(obj); - err = i915_gem_object_set_to_gtt_domain(obj, false); - i915_gem_object_unlock(obj); + i915_gem_object_lock(ctx->obj); + err = i915_gem_object_set_to_gtt_domain(ctx->obj, false); + i915_gem_object_unlock(ctx->obj); if (err) return err; - vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE); + vma = i915_gem_object_ggtt_pin(ctx->obj, NULL, 0, 0, PIN_MAPPABLE); if (IS_ERR(vma)) return PTR_ERR(vma); @@ -144,73 +141,66 @@ static int gtt_get(struct drm_i915_gem_object *obj, return err; } -static int wc_set(struct drm_i915_gem_object *obj, - unsigned long offset, - u32 v) +static int wc_set(struct context *ctx, unsigned long offset, u32 v) { u32 *map; int err; - i915_gem_object_lock(obj); - err = i915_gem_object_set_to_wc_domain(obj, true); - i915_gem_object_unlock(obj); + i915_gem_object_lock(ctx->obj); + err = i915_gem_object_set_to_wc_domain(ctx->obj, true); + i915_gem_object_unlock(ctx->obj); if (err) return err; - map = i915_gem_object_pin_map(obj, I915_MAP_WC); + map = i915_gem_object_pin_map(ctx->obj, I915_MAP_WC); if (IS_ERR(map)) return PTR_ERR(map); map[offset / sizeof(*map)] = v; - i915_gem_object_unpin_map(obj); + i915_gem_object_unpin_map(ctx->obj); return 0; } -static int wc_get(struct drm_i915_gem_object *obj, - unsigned long offset, - u32 *v) +static int wc_get(struct context *ctx, unsigned long offset, u32 *v) { u32 *map; int err; - i915_gem_object_lock(obj); - err = i915_gem_object_set_to_wc_domain(obj, false); - i915_gem_object_unlock(obj); + i915_gem_object_lock(ctx->obj); + err = i915_gem_object_set_to_wc_domain(ctx->obj, false); + i915_gem_object_unlock(ctx->obj); if (err) return err; - map = i915_gem_object_pin_map(obj, I915_MAP_WC); + map = i915_gem_object_pin_map(ctx->obj, I915_MAP_WC); if (IS_ERR(map)) return PTR_ERR(map); *v = map[offset / sizeof(*map)]; - i915_gem_object_unpin_map(obj); + i915_gem_object_unpin_map(ctx->obj); return 0; } -static int gpu_set(struct drm_i915_gem_object *obj, - unsigned long offset, - u32 v) +static int gpu_set(struct context *ctx, unsigned long offset, u32 v) { - struct drm_i915_private *i915 = to_i915(obj->base.dev); struct i915_request *rq; struct i915_vma *vma; u32 *cs; int err; - i915_gem_object_lock(obj); - err = i915_gem_object_set_to_gtt_domain(obj, true); - i915_gem_object_unlock(obj); + i915_gem_object_lock(ctx->obj); + err = i915_gem_object_set_to_gtt_domain(ctx->obj, true); + i915_gem_object_unlock(ctx->obj); if (err) return err; - vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0); + vma = i915_gem_object_ggtt_pin(ctx->obj, NULL, 0, 0, 0); if (IS_ERR(vma)) return PTR_ERR(vma); - rq = i915_request_create(i915->engine[RCS0]->kernel_context); + rq = i915_request_create(ctx->engine->kernel_context); if (IS_ERR(rq)) { i915_vma_unpin(vma); return PTR_ERR(rq); @@ -223,12 +213,12 @@ static int gpu_set(struct drm_i915_gem_object *obj, return PTR_ERR(cs); } - if (INTEL_GEN(i915) >= 8) { + if (INTEL_GEN(ctx->engine->i915) >= 8) { *cs++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22; *cs++ = lower_32_bits(i915_ggtt_offset(vma) + offset); *cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset); *cs++ = v; - } else if (INTEL_GEN(i915) >= 4) { + } else if (INTEL_GEN(ctx->engine->i915) >= 4) { *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; *cs++ = 0; *cs++ = i915_ggtt_offset(vma) + offset; @@ -253,32 +243,29 @@ static int gpu_set(struct drm_i915_gem_object *obj, return err; } -static bool always_valid(struct drm_i915_private *i915) +static bool always_valid(struct context *ctx) { return true; } -static bool needs_fence_registers(struct drm_i915_private *i915) +static bool needs_fence_registers(struct context *ctx) { - return !intel_gt_is_wedged(&i915->gt); + return !intel_gt_is_wedged(ctx->engine->gt); } -static bool needs_mi_store_dword(struct drm_i915_private *i915) +static bool needs_mi_store_dword(struct context *ctx) { - if (intel_gt_is_wedged(&i915->gt)) - return false; - - if (!HAS_ENGINE(i915, RCS0)) + if (intel_gt_is_wedged(ctx->engine->gt)) return false; - return intel_engine_can_store_dword(i915->engine[RCS0]); + return intel_engine_can_store_dword(ctx->engine); } static const struct igt_coherency_mode { const char *name; - int (*set)(struct drm_i915_gem_object *, unsigned long offset, u32 v); - int (*get)(struct drm_i915_gem_object *, unsigned long offset, u32 *v); - bool (*valid)(struct drm_i915_private *i915); + int (*set)(struct context *ctx, unsigned long offset, u32 v); + int (*get)(struct context *ctx, unsigned long offset, u32 *v); + bool (*valid)(struct context *ctx); } igt_coherency_mode[] = { { "cpu", cpu_set, cpu_get, always_valid }, { "gtt", gtt_set, gtt_get, needs_fence_registers }, @@ -287,18 +274,37 @@ static const struct igt_coherency_mode { { }, }; +static struct intel_engine_cs * +random_engine(struct drm_i915_private *i915, struct rnd_state *prng) +{ + struct intel_engine_cs *engine; + unsigned int count; + + count = 0; + for_each_uabi_engine(engine, i915) + count++; + + count = i915_prandom_u32_max_state(count, prng); + for_each_uabi_engine(engine, i915) + if (count-- == 0) + return engine; + + return NULL; +} + static int igt_gem_coherency(void *arg) { const unsigned int ncachelines = PAGE_SIZE/64; - I915_RND_STATE(prng); struct drm_i915_private *i915 = arg; const struct igt_coherency_mode *read, *write, *over; - struct drm_i915_gem_object *obj; unsigned long count, n; u32 *offsets, *values; + I915_RND_STATE(prng); + struct context ctx; int err = 0; - /* We repeatedly write, overwrite and read from a sequence of + /* + * We repeatedly write, overwrite and read from a sequence of * cachelines in order to try and detect incoherency (unflushed writes * from either the CPU or GPU). Each setter/getter uses our cache * domain API which should prevent incoherency. @@ -312,31 +318,35 @@ static int igt_gem_coherency(void *arg) values = offsets + ncachelines; + ctx.engine = random_engine(i915, &prng); + GEM_BUG_ON(!ctx.engine); + pr_info("%s: using %s\n", __func__, ctx.engine->name); + for (over = igt_coherency_mode; over->name; over++) { if (!over->set) continue; - if (!over->valid(i915)) + if (!over->valid(&ctx)) continue; for (write = igt_coherency_mode; write->name; write++) { if (!write->set) continue; - if (!write->valid(i915)) + if (!write->valid(&ctx)) continue; for (read = igt_coherency_mode; read->name; read++) { if (!read->get) continue; - if (!read->valid(i915)) + if (!read->valid(&ctx)) continue; for_each_prime_number_from(count, 1, ncachelines) { - obj = i915_gem_object_create_internal(i915, PAGE_SIZE); - if (IS_ERR(obj)) { - err = PTR_ERR(obj); + ctx.obj = i915_gem_object_create_internal(i915, PAGE_SIZE); + if (IS_ERR(ctx.obj)) { + err = PTR_ERR(ctx.obj); goto free; } @@ -345,7 +355,7 @@ static int igt_gem_coherency(void *arg) values[n] = prandom_u32_state(&prng); for (n = 0; n < count; n++) { - err = over->set(obj, offsets[n], ~values[n]); + err = over->set(&ctx, offsets[n], ~values[n]); if (err) { pr_err("Failed to set stale value[%ld/%ld] in object using %s, err=%d\n", n, count, over->name, err); @@ -354,7 +364,7 @@ static int igt_gem_coherency(void *arg) } for (n = 0; n < count; n++) { - err = write->set(obj, offsets[n], values[n]); + err = write->set(&ctx, offsets[n], values[n]); if (err) { pr_err("Failed to set value[%ld/%ld] in object using %s, err=%d\n", n, count, write->name, err); @@ -365,7 +375,7 @@ static int igt_gem_coherency(void *arg) for (n = 0; n < count; n++) { u32 found; - err = read->get(obj, offsets[n], &found); + err = read->get(&ctx, offsets[n], &found); if (err) { pr_err("Failed to get value[%ld/%ld] in object using %s, err=%d\n", n, count, read->name, err); @@ -383,7 +393,7 @@ static int igt_gem_coherency(void *arg) } } - i915_gem_object_put(obj); + i915_gem_object_put(ctx.obj); } } } @@ -393,7 +403,7 @@ static int igt_gem_coherency(void *arg) return err; put_object: - i915_gem_object_put(obj); + i915_gem_object_put(ctx.obj); goto free; } -- 2.24.0.rc1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH 4/5] drm/i915/selftests: Use a random engine for GEM coherency tests @ 2019-10-27 22:58 ` Chris Wilson 0 siblings, 0 replies; 24+ messages in thread From: Chris Wilson @ 2019-10-27 22:58 UTC (permalink / raw) To: intel-gfx; +Cc: matthew.auld Select a random user accessible engine for checking coherency results. While we should check all engines, we use a random selection so that over repeated runs we cover all. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- .../i915/gem/selftests/i915_gem_coherency.c | 168 ++++++++++-------- 1 file changed, 89 insertions(+), 79 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c index 0877ef4dff63..0a195e5b98e6 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c @@ -13,9 +13,12 @@ #include "i915_selftest.h" #include "selftests/i915_random.h" -static int cpu_set(struct drm_i915_gem_object *obj, - unsigned long offset, - u32 v) +struct context { + struct drm_i915_gem_object *obj; + struct intel_engine_cs *engine; +}; + +static int cpu_set(struct context *ctx, unsigned long offset, u32 v) { unsigned int needs_clflush; struct page *page; @@ -23,11 +26,11 @@ static int cpu_set(struct drm_i915_gem_object *obj, u32 *cpu; int err; - err = i915_gem_object_prepare_write(obj, &needs_clflush); + err = i915_gem_object_prepare_write(ctx->obj, &needs_clflush); if (err) return err; - page = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT); + page = i915_gem_object_get_page(ctx->obj, offset >> PAGE_SHIFT); map = kmap_atomic(page); cpu = map + offset_in_page(offset); @@ -40,14 +43,12 @@ static int cpu_set(struct drm_i915_gem_object *obj, drm_clflush_virt_range(cpu, sizeof(*cpu)); kunmap_atomic(map); - i915_gem_object_finish_access(obj); + i915_gem_object_finish_access(ctx->obj); return 0; } -static int cpu_get(struct drm_i915_gem_object *obj, - unsigned long offset, - u32 *v) +static int cpu_get(struct context *ctx, unsigned long offset, u32 *v) { unsigned int needs_clflush; struct page *page; @@ -55,11 +56,11 @@ static int cpu_get(struct drm_i915_gem_object *obj, u32 *cpu; int err; - err = i915_gem_object_prepare_read(obj, &needs_clflush); + err = i915_gem_object_prepare_read(ctx->obj, &needs_clflush); if (err) return err; - page = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT); + page = i915_gem_object_get_page(ctx->obj, offset >> PAGE_SHIFT); map = kmap_atomic(page); cpu = map + offset_in_page(offset); @@ -69,26 +70,24 @@ static int cpu_get(struct drm_i915_gem_object *obj, *v = *cpu; kunmap_atomic(map); - i915_gem_object_finish_access(obj); + i915_gem_object_finish_access(ctx->obj); return 0; } -static int gtt_set(struct drm_i915_gem_object *obj, - unsigned long offset, - u32 v) +static int gtt_set(struct context *ctx, unsigned long offset, u32 v) { struct i915_vma *vma; u32 __iomem *map; int err = 0; - i915_gem_object_lock(obj); - err = i915_gem_object_set_to_gtt_domain(obj, true); - i915_gem_object_unlock(obj); + i915_gem_object_lock(ctx->obj); + err = i915_gem_object_set_to_gtt_domain(ctx->obj, true); + i915_gem_object_unlock(ctx->obj); if (err) return err; - vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE); + vma = i915_gem_object_ggtt_pin(ctx->obj, NULL, 0, 0, PIN_MAPPABLE); if (IS_ERR(vma)) return PTR_ERR(vma); @@ -109,21 +108,19 @@ static int gtt_set(struct drm_i915_gem_object *obj, return err; } -static int gtt_get(struct drm_i915_gem_object *obj, - unsigned long offset, - u32 *v) +static int gtt_get(struct context *ctx, unsigned long offset, u32 *v) { struct i915_vma *vma; u32 __iomem *map; int err = 0; - i915_gem_object_lock(obj); - err = i915_gem_object_set_to_gtt_domain(obj, false); - i915_gem_object_unlock(obj); + i915_gem_object_lock(ctx->obj); + err = i915_gem_object_set_to_gtt_domain(ctx->obj, false); + i915_gem_object_unlock(ctx->obj); if (err) return err; - vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE); + vma = i915_gem_object_ggtt_pin(ctx->obj, NULL, 0, 0, PIN_MAPPABLE); if (IS_ERR(vma)) return PTR_ERR(vma); @@ -144,73 +141,66 @@ static int gtt_get(struct drm_i915_gem_object *obj, return err; } -static int wc_set(struct drm_i915_gem_object *obj, - unsigned long offset, - u32 v) +static int wc_set(struct context *ctx, unsigned long offset, u32 v) { u32 *map; int err; - i915_gem_object_lock(obj); - err = i915_gem_object_set_to_wc_domain(obj, true); - i915_gem_object_unlock(obj); + i915_gem_object_lock(ctx->obj); + err = i915_gem_object_set_to_wc_domain(ctx->obj, true); + i915_gem_object_unlock(ctx->obj); if (err) return err; - map = i915_gem_object_pin_map(obj, I915_MAP_WC); + map = i915_gem_object_pin_map(ctx->obj, I915_MAP_WC); if (IS_ERR(map)) return PTR_ERR(map); map[offset / sizeof(*map)] = v; - i915_gem_object_unpin_map(obj); + i915_gem_object_unpin_map(ctx->obj); return 0; } -static int wc_get(struct drm_i915_gem_object *obj, - unsigned long offset, - u32 *v) +static int wc_get(struct context *ctx, unsigned long offset, u32 *v) { u32 *map; int err; - i915_gem_object_lock(obj); - err = i915_gem_object_set_to_wc_domain(obj, false); - i915_gem_object_unlock(obj); + i915_gem_object_lock(ctx->obj); + err = i915_gem_object_set_to_wc_domain(ctx->obj, false); + i915_gem_object_unlock(ctx->obj); if (err) return err; - map = i915_gem_object_pin_map(obj, I915_MAP_WC); + map = i915_gem_object_pin_map(ctx->obj, I915_MAP_WC); if (IS_ERR(map)) return PTR_ERR(map); *v = map[offset / sizeof(*map)]; - i915_gem_object_unpin_map(obj); + i915_gem_object_unpin_map(ctx->obj); return 0; } -static int gpu_set(struct drm_i915_gem_object *obj, - unsigned long offset, - u32 v) +static int gpu_set(struct context *ctx, unsigned long offset, u32 v) { - struct drm_i915_private *i915 = to_i915(obj->base.dev); struct i915_request *rq; struct i915_vma *vma; u32 *cs; int err; - i915_gem_object_lock(obj); - err = i915_gem_object_set_to_gtt_domain(obj, true); - i915_gem_object_unlock(obj); + i915_gem_object_lock(ctx->obj); + err = i915_gem_object_set_to_gtt_domain(ctx->obj, true); + i915_gem_object_unlock(ctx->obj); if (err) return err; - vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0); + vma = i915_gem_object_ggtt_pin(ctx->obj, NULL, 0, 0, 0); if (IS_ERR(vma)) return PTR_ERR(vma); - rq = i915_request_create(i915->engine[RCS0]->kernel_context); + rq = i915_request_create(ctx->engine->kernel_context); if (IS_ERR(rq)) { i915_vma_unpin(vma); return PTR_ERR(rq); @@ -223,12 +213,12 @@ static int gpu_set(struct drm_i915_gem_object *obj, return PTR_ERR(cs); } - if (INTEL_GEN(i915) >= 8) { + if (INTEL_GEN(ctx->engine->i915) >= 8) { *cs++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22; *cs++ = lower_32_bits(i915_ggtt_offset(vma) + offset); *cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset); *cs++ = v; - } else if (INTEL_GEN(i915) >= 4) { + } else if (INTEL_GEN(ctx->engine->i915) >= 4) { *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; *cs++ = 0; *cs++ = i915_ggtt_offset(vma) + offset; @@ -253,32 +243,29 @@ static int gpu_set(struct drm_i915_gem_object *obj, return err; } -static bool always_valid(struct drm_i915_private *i915) +static bool always_valid(struct context *ctx) { return true; } -static bool needs_fence_registers(struct drm_i915_private *i915) +static bool needs_fence_registers(struct context *ctx) { - return !intel_gt_is_wedged(&i915->gt); + return !intel_gt_is_wedged(ctx->engine->gt); } -static bool needs_mi_store_dword(struct drm_i915_private *i915) +static bool needs_mi_store_dword(struct context *ctx) { - if (intel_gt_is_wedged(&i915->gt)) - return false; - - if (!HAS_ENGINE(i915, RCS0)) + if (intel_gt_is_wedged(ctx->engine->gt)) return false; - return intel_engine_can_store_dword(i915->engine[RCS0]); + return intel_engine_can_store_dword(ctx->engine); } static const struct igt_coherency_mode { const char *name; - int (*set)(struct drm_i915_gem_object *, unsigned long offset, u32 v); - int (*get)(struct drm_i915_gem_object *, unsigned long offset, u32 *v); - bool (*valid)(struct drm_i915_private *i915); + int (*set)(struct context *ctx, unsigned long offset, u32 v); + int (*get)(struct context *ctx, unsigned long offset, u32 *v); + bool (*valid)(struct context *ctx); } igt_coherency_mode[] = { { "cpu", cpu_set, cpu_get, always_valid }, { "gtt", gtt_set, gtt_get, needs_fence_registers }, @@ -287,18 +274,37 @@ static const struct igt_coherency_mode { { }, }; +static struct intel_engine_cs * +random_engine(struct drm_i915_private *i915, struct rnd_state *prng) +{ + struct intel_engine_cs *engine; + unsigned int count; + + count = 0; + for_each_uabi_engine(engine, i915) + count++; + + count = i915_prandom_u32_max_state(count, prng); + for_each_uabi_engine(engine, i915) + if (count-- == 0) + return engine; + + return NULL; +} + static int igt_gem_coherency(void *arg) { const unsigned int ncachelines = PAGE_SIZE/64; - I915_RND_STATE(prng); struct drm_i915_private *i915 = arg; const struct igt_coherency_mode *read, *write, *over; - struct drm_i915_gem_object *obj; unsigned long count, n; u32 *offsets, *values; + I915_RND_STATE(prng); + struct context ctx; int err = 0; - /* We repeatedly write, overwrite and read from a sequence of + /* + * We repeatedly write, overwrite and read from a sequence of * cachelines in order to try and detect incoherency (unflushed writes * from either the CPU or GPU). Each setter/getter uses our cache * domain API which should prevent incoherency. @@ -312,31 +318,35 @@ static int igt_gem_coherency(void *arg) values = offsets + ncachelines; + ctx.engine = random_engine(i915, &prng); + GEM_BUG_ON(!ctx.engine); + pr_info("%s: using %s\n", __func__, ctx.engine->name); + for (over = igt_coherency_mode; over->name; over++) { if (!over->set) continue; - if (!over->valid(i915)) + if (!over->valid(&ctx)) continue; for (write = igt_coherency_mode; write->name; write++) { if (!write->set) continue; - if (!write->valid(i915)) + if (!write->valid(&ctx)) continue; for (read = igt_coherency_mode; read->name; read++) { if (!read->get) continue; - if (!read->valid(i915)) + if (!read->valid(&ctx)) continue; for_each_prime_number_from(count, 1, ncachelines) { - obj = i915_gem_object_create_internal(i915, PAGE_SIZE); - if (IS_ERR(obj)) { - err = PTR_ERR(obj); + ctx.obj = i915_gem_object_create_internal(i915, PAGE_SIZE); + if (IS_ERR(ctx.obj)) { + err = PTR_ERR(ctx.obj); goto free; } @@ -345,7 +355,7 @@ static int igt_gem_coherency(void *arg) values[n] = prandom_u32_state(&prng); for (n = 0; n < count; n++) { - err = over->set(obj, offsets[n], ~values[n]); + err = over->set(&ctx, offsets[n], ~values[n]); if (err) { pr_err("Failed to set stale value[%ld/%ld] in object using %s, err=%d\n", n, count, over->name, err); @@ -354,7 +364,7 @@ static int igt_gem_coherency(void *arg) } for (n = 0; n < count; n++) { - err = write->set(obj, offsets[n], values[n]); + err = write->set(&ctx, offsets[n], values[n]); if (err) { pr_err("Failed to set value[%ld/%ld] in object using %s, err=%d\n", n, count, write->name, err); @@ -365,7 +375,7 @@ static int igt_gem_coherency(void *arg) for (n = 0; n < count; n++) { u32 found; - err = read->get(obj, offsets[n], &found); + err = read->get(&ctx, offsets[n], &found); if (err) { pr_err("Failed to get value[%ld/%ld] in object using %s, err=%d\n", n, count, read->name, err); @@ -383,7 +393,7 @@ static int igt_gem_coherency(void *arg) } } - i915_gem_object_put(obj); + i915_gem_object_put(ctx.obj); } } } @@ -393,7 +403,7 @@ static int igt_gem_coherency(void *arg) return err; put_object: - i915_gem_object_put(obj); + i915_gem_object_put(ctx.obj); goto free; } -- 2.24.0.rc1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 4/5] drm/i915/selftests: Use a random engine for GEM coherency tests @ 2019-10-28 11:33 ` Matthew Auld 0 siblings, 0 replies; 24+ messages in thread From: Matthew Auld @ 2019-10-28 11:33 UTC (permalink / raw) To: Chris Wilson; +Cc: Intel Graphics Development, Matthew Auld On Sun, 27 Oct 2019 at 22:58, Chris Wilson <chris@chris-wilson.co.uk> wrote: > > Select a random user accessible engine for checking coherency results. > While we should check all engines, we use a random selection so that > over repeated runs we cover all. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 4/5] drm/i915/selftests: Use a random engine for GEM coherency tests @ 2019-10-28 11:33 ` Matthew Auld 0 siblings, 0 replies; 24+ messages in thread From: Matthew Auld @ 2019-10-28 11:33 UTC (permalink / raw) To: Chris Wilson; +Cc: Intel Graphics Development, Matthew Auld On Sun, 27 Oct 2019 at 22:58, Chris Wilson <chris@chris-wilson.co.uk> wrote: > > Select a random user accessible engine for checking coherency results. > While we should check all engines, we use a random selection so that > over repeated runs we cover all. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 5/5] drm/i915/selftests: Select a random engine for testing memory regions @ 2019-10-27 22:58 ` Chris Wilson 0 siblings, 0 replies; 24+ messages in thread From: Chris Wilson @ 2019-10-27 22:58 UTC (permalink / raw) To: intel-gfx; +Cc: matthew.auld Use any blitter engine at random for prefilling the memory region. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- .../drm/i915/selftests/intel_memory_region.c | 29 +++++++++++++++++-- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c b/drivers/gpu/drm/i915/selftests/intel_memory_region.c index 8bc6fadd14fb..1f5e3ab6f91e 100644 --- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c +++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c @@ -17,6 +17,7 @@ #include "gem/i915_gem_object_blt.h" #include "gem/selftests/igt_gem_utils.h" #include "gem/selftests/mock_context.h" +#include "gt/intel_engine_user.h" #include "gt/intel_gt.h" #include "selftests/igt_flush_test.h" #include "selftests/i915_random.h" @@ -442,6 +443,25 @@ static int igt_lmem_write_gpu(void *arg) return err; } +static struct intel_engine_cs * +random_engine(struct drm_i915_private *i915, + unsigned int class, + struct rnd_state *prng) +{ + struct intel_engine_cs *engine; + unsigned int count; + + count = 0; + for (engine = intel_engine_lookup_user(i915, class, 0); + engine && engine->uabi_class == class; + engine = rb_entry_safe(rb_next(&engine->uabi_node), + typeof(*engine), uabi_node)) + count++; + + count = i915_prandom_u32_max_state(count, prng); + return intel_engine_lookup_user(i915, class, count); +} + static int igt_lmem_write_cpu(void *arg) { struct drm_i915_private *i915 = arg; @@ -458,6 +478,7 @@ static int igt_lmem_write_cpu(void *arg) PAGE_SIZE - sizeof(u64), PAGE_SIZE - 64, }; + struct intel_engine_cs *engine; u32 *vaddr; u32 sz; u32 i; @@ -465,9 +486,12 @@ static int igt_lmem_write_cpu(void *arg) int count; int err; - if (!HAS_ENGINE(i915, BCS0)) + engine = random_engine(i915, I915_ENGINE_CLASS_COPY, &prng); + if (!engine) return 0; + pr_info("%s: using %s\n", __func__, engine->name); + sz = round_up(prandom_u32_state(&prng) % SZ_32M, PAGE_SIZE); sz = max_t(u32, 2 * PAGE_SIZE, sz); @@ -482,8 +506,7 @@ static int igt_lmem_write_cpu(void *arg) } /* Put the pages into a known state -- from the gpu for added fun */ - err = i915_gem_object_fill_blt(obj, i915->engine[BCS0]->kernel_context, - 0xdeadbeaf); + err = i915_gem_object_fill_blt(obj, engine->kernel_context, 0xdeadbeaf); if (err) goto out_unpin; -- 2.24.0.rc1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH 5/5] drm/i915/selftests: Select a random engine for testing memory regions @ 2019-10-27 22:58 ` Chris Wilson 0 siblings, 0 replies; 24+ messages in thread From: Chris Wilson @ 2019-10-27 22:58 UTC (permalink / raw) To: intel-gfx; +Cc: matthew.auld Use any blitter engine at random for prefilling the memory region. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- .../drm/i915/selftests/intel_memory_region.c | 29 +++++++++++++++++-- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c b/drivers/gpu/drm/i915/selftests/intel_memory_region.c index 8bc6fadd14fb..1f5e3ab6f91e 100644 --- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c +++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c @@ -17,6 +17,7 @@ #include "gem/i915_gem_object_blt.h" #include "gem/selftests/igt_gem_utils.h" #include "gem/selftests/mock_context.h" +#include "gt/intel_engine_user.h" #include "gt/intel_gt.h" #include "selftests/igt_flush_test.h" #include "selftests/i915_random.h" @@ -442,6 +443,25 @@ static int igt_lmem_write_gpu(void *arg) return err; } +static struct intel_engine_cs * +random_engine(struct drm_i915_private *i915, + unsigned int class, + struct rnd_state *prng) +{ + struct intel_engine_cs *engine; + unsigned int count; + + count = 0; + for (engine = intel_engine_lookup_user(i915, class, 0); + engine && engine->uabi_class == class; + engine = rb_entry_safe(rb_next(&engine->uabi_node), + typeof(*engine), uabi_node)) + count++; + + count = i915_prandom_u32_max_state(count, prng); + return intel_engine_lookup_user(i915, class, count); +} + static int igt_lmem_write_cpu(void *arg) { struct drm_i915_private *i915 = arg; @@ -458,6 +478,7 @@ static int igt_lmem_write_cpu(void *arg) PAGE_SIZE - sizeof(u64), PAGE_SIZE - 64, }; + struct intel_engine_cs *engine; u32 *vaddr; u32 sz; u32 i; @@ -465,9 +486,12 @@ static int igt_lmem_write_cpu(void *arg) int count; int err; - if (!HAS_ENGINE(i915, BCS0)) + engine = random_engine(i915, I915_ENGINE_CLASS_COPY, &prng); + if (!engine) return 0; + pr_info("%s: using %s\n", __func__, engine->name); + sz = round_up(prandom_u32_state(&prng) % SZ_32M, PAGE_SIZE); sz = max_t(u32, 2 * PAGE_SIZE, sz); @@ -482,8 +506,7 @@ static int igt_lmem_write_cpu(void *arg) } /* Put the pages into a known state -- from the gpu for added fun */ - err = i915_gem_object_fill_blt(obj, i915->engine[BCS0]->kernel_context, - 0xdeadbeaf); + err = i915_gem_object_fill_blt(obj, engine->kernel_context, 0xdeadbeaf); if (err) goto out_unpin; -- 2.24.0.rc1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 5/5] drm/i915/selftests: Select a random engine for testing memory regions @ 2019-10-28 11:39 ` Matthew Auld 0 siblings, 0 replies; 24+ messages in thread From: Matthew Auld @ 2019-10-28 11:39 UTC (permalink / raw) To: Chris Wilson; +Cc: Intel Graphics Development, Matthew Auld On Sun, 27 Oct 2019 at 22:58, Chris Wilson <chris@chris-wilson.co.uk> wrote: > > Use any blitter engine at random for prefilling the memory region. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 5/5] drm/i915/selftests: Select a random engine for testing memory regions @ 2019-10-28 11:39 ` Matthew Auld 0 siblings, 0 replies; 24+ messages in thread From: Matthew Auld @ 2019-10-28 11:39 UTC (permalink / raw) To: Chris Wilson; +Cc: Intel Graphics Development, Matthew Auld On Sun, 27 Oct 2019 at 22:58, Chris Wilson <chris@chris-wilson.co.uk> wrote: > > Use any blitter engine at random for prefilling the memory region. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 24+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915/selftests: Drop global engine lookup for gt selftests @ 2019-10-27 23:33 ` Patchwork 0 siblings, 0 replies; 24+ messages in thread From: Patchwork @ 2019-10-27 23:33 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx == Series Details == Series: series starting with [1/5] drm/i915/selftests: Drop global engine lookup for gt selftests URL : https://patchwork.freedesktop.org/series/68623/ State : success == Summary == CI Bug Log - changes from CI_DRM_7196 -> Patchwork_15016 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_15016: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@runner@aborted: - {fi-tgl-u2}: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/fi-tgl-u2/igt@runner@aborted.html Known issues ------------ Here are the changes found in Patchwork_15016 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_mmap_gtt@basic: - fi-icl-u3: [PASS][2] -> [DMESG-WARN][3] ([fdo#107724]) +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/fi-icl-u3/igt@gem_mmap_gtt@basic.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/fi-icl-u3/igt@gem_mmap_gtt@basic.html #### Possible fixes #### * igt@gem_ctx_switch@legacy-render: - fi-bxt-dsi: [INCOMPLETE][4] ([fdo#103927] / [fdo#111381]) -> [PASS][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html * igt@gem_exec_reloc@basic-write-read: - fi-icl-u3: [DMESG-WARN][6] ([fdo#107724]) -> [PASS][7] +2 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/fi-icl-u3/igt@gem_exec_reloc@basic-write-read.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/fi-icl-u3/igt@gem_exec_reloc@basic-write-read.html * igt@i915_selftest@live_execlists: - {fi-icl-dsi}: [INCOMPLETE][8] ([fdo#107713]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/fi-icl-dsi/igt@i915_selftest@live_execlists.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/fi-icl-dsi/igt@i915_selftest@live_execlists.html * igt@i915_selftest@live_gem_contexts: - {fi-icl-guc}: [INCOMPLETE][10] ([fdo#107713]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/fi-icl-guc/igt@i915_selftest@live_gem_contexts.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/fi-icl-guc/igt@i915_selftest@live_gem_contexts.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381 Participating hosts (48 -> 41) ------------------------------ Additional (1): fi-pnv-d510 Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-bdw-samus fi-byt-clapper fi-skl-6600u Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_7196 -> Patchwork_15016 CI-20190529: 20190529 CI_DRM_7196: 54520983c610850dc9034dfdfeec2a0492949d8f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5245: def00442d5b9cbe6ca18ead23d80e8501d3fd517 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_15016: a0baf3287a6e9ab2c77f1761c566363e93864e3a @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a0baf3287a6e drm/i915/selftests: Select a random engine for testing memory regions adb310b706ac drm/i915/selftests: Use a random engine for GEM coherency tests 582a8c849e89 drm/i915/selftests: Check all blitter engines for client blt 7671002c0bd8 drm/i915/selftests: Exercise adjusting rpcs over all render-class engines b4215ed537d8 drm/i915/selftests: Drop global engine lookup for gt selftests == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 24+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915/selftests: Drop global engine lookup for gt selftests @ 2019-10-27 23:33 ` Patchwork 0 siblings, 0 replies; 24+ messages in thread From: Patchwork @ 2019-10-27 23:33 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx == Series Details == Series: series starting with [1/5] drm/i915/selftests: Drop global engine lookup for gt selftests URL : https://patchwork.freedesktop.org/series/68623/ State : success == Summary == CI Bug Log - changes from CI_DRM_7196 -> Patchwork_15016 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_15016: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@runner@aborted: - {fi-tgl-u2}: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/fi-tgl-u2/igt@runner@aborted.html Known issues ------------ Here are the changes found in Patchwork_15016 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_mmap_gtt@basic: - fi-icl-u3: [PASS][2] -> [DMESG-WARN][3] ([fdo#107724]) +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/fi-icl-u3/igt@gem_mmap_gtt@basic.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/fi-icl-u3/igt@gem_mmap_gtt@basic.html #### Possible fixes #### * igt@gem_ctx_switch@legacy-render: - fi-bxt-dsi: [INCOMPLETE][4] ([fdo#103927] / [fdo#111381]) -> [PASS][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html * igt@gem_exec_reloc@basic-write-read: - fi-icl-u3: [DMESG-WARN][6] ([fdo#107724]) -> [PASS][7] +2 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/fi-icl-u3/igt@gem_exec_reloc@basic-write-read.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/fi-icl-u3/igt@gem_exec_reloc@basic-write-read.html * igt@i915_selftest@live_execlists: - {fi-icl-dsi}: [INCOMPLETE][8] ([fdo#107713]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/fi-icl-dsi/igt@i915_selftest@live_execlists.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/fi-icl-dsi/igt@i915_selftest@live_execlists.html * igt@i915_selftest@live_gem_contexts: - {fi-icl-guc}: [INCOMPLETE][10] ([fdo#107713]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/fi-icl-guc/igt@i915_selftest@live_gem_contexts.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/fi-icl-guc/igt@i915_selftest@live_gem_contexts.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381 Participating hosts (48 -> 41) ------------------------------ Additional (1): fi-pnv-d510 Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-bdw-samus fi-byt-clapper fi-skl-6600u Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_7196 -> Patchwork_15016 CI-20190529: 20190529 CI_DRM_7196: 54520983c610850dc9034dfdfeec2a0492949d8f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5245: def00442d5b9cbe6ca18ead23d80e8501d3fd517 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_15016: a0baf3287a6e9ab2c77f1761c566363e93864e3a @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a0baf3287a6e drm/i915/selftests: Select a random engine for testing memory regions adb310b706ac drm/i915/selftests: Use a random engine for GEM coherency tests 582a8c849e89 drm/i915/selftests: Check all blitter engines for client blt 7671002c0bd8 drm/i915/selftests: Exercise adjusting rpcs over all render-class engines b4215ed537d8 drm/i915/selftests: Drop global engine lookup for gt selftests == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 1/5] drm/i915/selftests: Drop global engine lookup for gt selftests @ 2019-10-28 11:13 ` Matthew Auld 0 siblings, 0 replies; 24+ messages in thread From: Matthew Auld @ 2019-10-28 11:13 UTC (permalink / raw) To: Chris Wilson; +Cc: Intel Graphics Development, Matthew Auld On Sun, 27 Oct 2019 at 22:58, Chris Wilson <chris@chris-wilson.co.uk> wrote: > > As we are inside the gt, we have a local gt->engine[] lookup we should > be using in preference over the i915->engine[] copy. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 1/5] drm/i915/selftests: Drop global engine lookup for gt selftests @ 2019-10-28 11:13 ` Matthew Auld 0 siblings, 0 replies; 24+ messages in thread From: Matthew Auld @ 2019-10-28 11:13 UTC (permalink / raw) To: Chris Wilson; +Cc: Intel Graphics Development, Matthew Auld On Sun, 27 Oct 2019 at 22:58, Chris Wilson <chris@chris-wilson.co.uk> wrote: > > As we are inside the gt, we have a local gt->engine[] lookup we should > be using in preference over the i915->engine[] copy. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 24+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/5] drm/i915/selftests: Drop global engine lookup for gt selftests @ 2019-10-29 2:15 ` Patchwork 0 siblings, 0 replies; 24+ messages in thread From: Patchwork @ 2019-10-29 2:15 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx == Series Details == Series: series starting with [1/5] drm/i915/selftests: Drop global engine lookup for gt selftests URL : https://patchwork.freedesktop.org/series/68623/ State : success == Summary == CI Bug Log - changes from CI_DRM_7196_full -> Patchwork_15016_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_15016_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_isolation@vcs1-clean: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276] / [fdo#112080]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb2/igt@gem_ctx_isolation@vcs1-clean.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb3/igt@gem_ctx_isolation@vcs1-clean.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110854]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb4/igt@gem_exec_balancer@smoke.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb6/igt@gem_exec_balancer@smoke.html * igt@gem_exec_big@single: - shard-iclb: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb3/igt@gem_exec_big@single.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb7/igt@gem_exec_big@single.html * igt@gem_exec_parallel@vcs1-fds: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#112080]) +14 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb2/igt@gem_exec_parallel@vcs1-fds.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb3/igt@gem_exec_parallel@vcs1-fds.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#112146]) +7 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb7/igt@gem_exec_schedule@preempt-other-chain-bsd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb1/igt@gem_exec_schedule@preempt-other-chain-bsd.html * igt@gem_persistent_relocs@forked-faulting-reloc-thrashing: - shard-iclb: [PASS][11] -> [TIMEOUT][12] ([fdo#112068 ]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb7/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb8/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html * igt@gem_persistent_relocs@forked-interruptible-thrashing: - shard-snb: [PASS][13] -> [FAIL][14] ([fdo#112037]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-snb5/igt@gem_persistent_relocs@forked-interruptible-thrashing.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-snb2/igt@gem_persistent_relocs@forked-interruptible-thrashing.html - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#112037]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb1/igt@gem_persistent_relocs@forked-interruptible-thrashing.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb4/igt@gem_persistent_relocs@forked-interruptible-thrashing.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup: - shard-hsw: [PASS][17] -> [DMESG-WARN][18] ([fdo#111870]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-hsw6/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-hsw1/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html * igt@gem_userptr_blits@sync-unmap-after-close: - shard-snb: [PASS][19] -> [DMESG-WARN][20] ([fdo#111870]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-snb7/igt@gem_userptr_blits@sync-unmap-after-close.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-snb4/igt@gem_userptr_blits@sync-unmap-after-close.html * igt@gem_workarounds@suspend-resume-fd: - shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([fdo#108566]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-kbl6/igt@gem_workarounds@suspend-resume-fd.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-kbl2/igt@gem_workarounds@suspend-resume-fd.html * igt@i915_pm_rpm@system-suspend-modeset: - shard-kbl: [PASS][23] -> [INCOMPLETE][24] ([fdo#103665] / [fdo#107807]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-kbl7/igt@i915_pm_rpm@system-suspend-modeset.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-kbl1/igt@i915_pm_rpm@system-suspend-modeset.html * igt@i915_selftest@live_hangcheck: - shard-hsw: [PASS][25] -> [DMESG-FAIL][26] ([fdo#111991]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-hsw2/igt@i915_selftest@live_hangcheck.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-hsw4/igt@i915_selftest@live_hangcheck.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-iclb: [PASS][27] -> [DMESG-WARN][28] ([fdo#111764]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb7/igt@i915_suspend@fence-restore-tiled2untiled.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb1/igt@i915_suspend@fence-restore-tiled2untiled.html * igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: - shard-apl: [PASS][29] -> [INCOMPLETE][30] ([fdo#103927]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-apl7/igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-apl6/igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing.html * igt@kms_color@pipe-a-ctm-0-75: - shard-skl: [PASS][31] -> [DMESG-WARN][32] ([fdo#106107]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-skl10/igt@kms_color@pipe-a-ctm-0-75.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-skl10/igt@kms_color@pipe-a-ctm-0-75.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-skl: [PASS][33] -> [FAIL][34] ([fdo#102670]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][35] -> [FAIL][36] ([fdo#105363]) +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-skl6/igt@kms_flip@flip-vs-expired-vblank.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-skl3/igt@kms_flip@flip-vs-expired-vblank.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-iclb: [PASS][37] -> [FAIL][38] ([fdo#105363]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb1/igt@kms_flip@flip-vs-expired-vblank-interruptible.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-skl: [PASS][39] -> [INCOMPLETE][40] ([fdo#109507]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-skl3/igt@kms_flip@flip-vs-suspend-interruptible.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-skl6/igt@kms_flip@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [PASS][41] -> [FAIL][42] ([fdo#103167]) +3 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][43] -> [FAIL][44] ([fdo#108145]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: [PASS][45] -> [FAIL][46] ([fdo#103166]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-y.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb4/igt@kms_plane_lowres@pipe-a-tiling-y.html * igt@kms_psr@psr2_sprite_plane_onoff: - shard-iclb: [PASS][47] -> [SKIP][48] ([fdo#109441]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb2/igt@kms_psr@psr2_sprite_plane_onoff.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb3/igt@kms_psr@psr2_sprite_plane_onoff.html * igt@kms_setmode@basic: - shard-glk: [PASS][49] -> [FAIL][50] ([fdo#99912]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-glk3/igt@kms_setmode@basic.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-glk1/igt@kms_setmode@basic.html * igt@prime_vgem@fence-wait-bsd2: - shard-iclb: [PASS][51] -> [SKIP][52] ([fdo#109276]) +13 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb3/igt@prime_vgem@fence-wait-bsd2.html #### Possible fixes #### * igt@gem_ctx_isolation@vcs1-dirty-create: - shard-iclb: [SKIP][53] ([fdo#109276] / [fdo#112080]) -> [PASS][54] +1 similar issue [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb6/igt@gem_ctx_isolation@vcs1-dirty-create.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb2/igt@gem_ctx_isolation@vcs1-dirty-create.html * igt@gem_eio@reset-stress: - shard-snb: [FAIL][55] ([fdo#109661]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-snb1/igt@gem_eio@reset-stress.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-snb1/igt@gem_eio@reset-stress.html * igt@gem_exec_nop@basic-series: - {shard-tglb}: [INCOMPLETE][57] ([fdo#111747]) -> [PASS][58] +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-tglb4/igt@gem_exec_nop@basic-series.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-tglb8/igt@gem_exec_nop@basic-series.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [SKIP][59] ([fdo#109276]) -> [PASS][60] +25 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb8/igt@gem_exec_schedule@preempt-queue-bsd1.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb1/igt@gem_exec_schedule@preempt-queue-bsd1.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [SKIP][61] ([fdo#112146]) -> [PASS][62] +4 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb3/igt@gem_exec_schedule@preemptive-hang-bsd.html * igt@gem_userptr_blits@dmabuf-unsync: - shard-hsw: [DMESG-WARN][63] ([fdo#111870]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-hsw2/igt@gem_userptr_blits@dmabuf-unsync.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-hsw1/igt@gem_userptr_blits@dmabuf-unsync.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup: - shard-snb: [DMESG-WARN][65] ([fdo#111870]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-snb1/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-snb2/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html * igt@gem_workarounds@suspend-resume-fd: - shard-apl: [DMESG-WARN][67] ([fdo#108566]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-apl1/igt@gem_workarounds@suspend-resume-fd.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-apl1/igt@gem_workarounds@suspend-resume-fd.html * {igt@i915_pm_dc@dc6-psr}: - shard-iclb: [FAIL][69] ([fdo#110548]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb4/igt@i915_pm_dc@dc6-psr.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb1/igt@i915_pm_dc@dc6-psr.html * igt@i915_selftest@live_hangcheck: - shard-iclb: [INCOMPLETE][71] ([fdo#107713] / [fdo#108569]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb6/igt@i915_selftest@live_hangcheck.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb7/igt@i915_selftest@live_hangcheck.html * igt@i915_suspend@fence-restore-untiled: - shard-kbl: [INCOMPLETE][73] ([fdo#103665]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-kbl4/igt@i915_suspend@fence-restore-untiled.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-kbl3/igt@i915_suspend@fence-restore-untiled.html * igt@kms_cursor_crc@pipe-c-cursor-128x42-offscreen: - shard-apl: [INCOMPLETE][75] ([fdo#103927]) -> [PASS][76] +3 similar issues [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-apl6/igt@kms_cursor_crc@pipe-c-cursor-128x42-offscreen.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-apl4/igt@kms_cursor_crc@pipe-c-cursor-128x42-offscreen.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [DMESG-WARN][77] ([fdo#108566]) -> [PASS][78] +4 similar issues [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-kbl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite: - shard-iclb: [FAIL][79] ([fdo#103167]) -> [PASS][80] +4 similar issues [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbc-suspend: - {shard-tglb}: [INCOMPLETE][81] ([fdo#111832] / [fdo#111850] / [fdo#111884]) -> [PASS][82] [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-suspend.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite: - {shard-tglb}: [INCOMPLETE][83] ([fdo#111747] / [fdo#111884]) -> [PASS][84] [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt: - {shard-tglb}: [FAIL][85] ([fdo#103167]) -> [PASS][86] +5 similar issues [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [FAIL][87] ([fdo#108145] / [fdo#110403]) -> [PASS][88] [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt@kms_psr2_su@page_flip: - shard-iclb: [SKIP][89] ([fdo#109642] / [fdo#111068]) -> [PASS][90] [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb8/igt@kms_psr2_su@page_flip.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb2/igt@kms_psr2_su@page_flip.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [SKIP][91] ([fdo#109441]) -> [PASS][92] +1 similar issue [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb8/igt@kms_psr@psr2_primary_page_flip.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html * igt@kms_psr@psr2_suspend: - {shard-tglb}: [INCOMPLETE][93] ([fdo#111832] / [fdo#111850]) -> [PASS][94] [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-tglb8/igt@kms_psr@psr2_suspend.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-tglb2/igt@kms_psr@psr2_suspend.html * igt@kms_setmode@basic: - shard-apl: [FAIL][95] ([fdo#99912]) -> [PASS][96] [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-apl3/igt@kms_setmode@basic.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-apl1/igt@kms_setmode@basic.html - shard-skl: [FAIL][97] ([fdo#99912]) -> [PASS][98] [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-skl5/igt@kms_setmode@basic.html [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-skl7/igt@kms_setmode@basic.html * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend: - {shard-tglb}: [INCOMPLETE][99] ([fdo#111850]) -> [PASS][100] [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-tglb7/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-tglb1/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html * igt@kms_vblank@pipe-b-ts-continuation-suspend: - shard-skl: [INCOMPLETE][101] ([fdo#104108]) -> [PASS][102] [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-skl7/igt@kms_vblank@pipe-b-ts-continuation-suspend.html [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-skl8/igt@kms_vblank@pipe-b-ts-continuation-suspend.html * igt@perf_pmu@busy-vcs1: - shard-iclb: [SKIP][103] ([fdo#112080]) -> [PASS][104] +9 similar issues [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb8/igt@perf_pmu@busy-vcs1.html [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb2/igt@perf_pmu@busy-vcs1.html #### Warnings #### * igt@gem_mocs_settings@mocs-isolation-bsd2: - shard-iclb: [FAIL][105] ([fdo#111330]) -> [SKIP][106] ([fdo#109276]) [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb2/igt@gem_mocs_settings@mocs-isolation-bsd2.html [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb3/igt@gem_mocs_settings@mocs-isolation-bsd2.html * igt@gem_mocs_settings@mocs-rc6-bsd2: - shard-iclb: [SKIP][107] ([fdo#109276]) -> [FAIL][108] ([fdo#111330]) [107]: http == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 24+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/5] drm/i915/selftests: Drop global engine lookup for gt selftests @ 2019-10-29 2:15 ` Patchwork 0 siblings, 0 replies; 24+ messages in thread From: Patchwork @ 2019-10-29 2:15 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx == Series Details == Series: series starting with [1/5] drm/i915/selftests: Drop global engine lookup for gt selftests URL : https://patchwork.freedesktop.org/series/68623/ State : success == Summary == CI Bug Log - changes from CI_DRM_7196_full -> Patchwork_15016_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_15016_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_isolation@vcs1-clean: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276] / [fdo#112080]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb2/igt@gem_ctx_isolation@vcs1-clean.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb3/igt@gem_ctx_isolation@vcs1-clean.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110854]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb4/igt@gem_exec_balancer@smoke.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb6/igt@gem_exec_balancer@smoke.html * igt@gem_exec_big@single: - shard-iclb: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb3/igt@gem_exec_big@single.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb7/igt@gem_exec_big@single.html * igt@gem_exec_parallel@vcs1-fds: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#112080]) +14 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb2/igt@gem_exec_parallel@vcs1-fds.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb3/igt@gem_exec_parallel@vcs1-fds.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#112146]) +7 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb7/igt@gem_exec_schedule@preempt-other-chain-bsd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb1/igt@gem_exec_schedule@preempt-other-chain-bsd.html * igt@gem_persistent_relocs@forked-faulting-reloc-thrashing: - shard-iclb: [PASS][11] -> [TIMEOUT][12] ([fdo#112068 ]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb7/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb8/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html * igt@gem_persistent_relocs@forked-interruptible-thrashing: - shard-snb: [PASS][13] -> [FAIL][14] ([fdo#112037]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-snb5/igt@gem_persistent_relocs@forked-interruptible-thrashing.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-snb2/igt@gem_persistent_relocs@forked-interruptible-thrashing.html - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#112037]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb1/igt@gem_persistent_relocs@forked-interruptible-thrashing.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb4/igt@gem_persistent_relocs@forked-interruptible-thrashing.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup: - shard-hsw: [PASS][17] -> [DMESG-WARN][18] ([fdo#111870]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-hsw6/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-hsw1/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html * igt@gem_userptr_blits@sync-unmap-after-close: - shard-snb: [PASS][19] -> [DMESG-WARN][20] ([fdo#111870]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-snb7/igt@gem_userptr_blits@sync-unmap-after-close.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-snb4/igt@gem_userptr_blits@sync-unmap-after-close.html * igt@gem_workarounds@suspend-resume-fd: - shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([fdo#108566]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-kbl6/igt@gem_workarounds@suspend-resume-fd.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-kbl2/igt@gem_workarounds@suspend-resume-fd.html * igt@i915_pm_rpm@system-suspend-modeset: - shard-kbl: [PASS][23] -> [INCOMPLETE][24] ([fdo#103665] / [fdo#107807]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-kbl7/igt@i915_pm_rpm@system-suspend-modeset.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-kbl1/igt@i915_pm_rpm@system-suspend-modeset.html * igt@i915_selftest@live_hangcheck: - shard-hsw: [PASS][25] -> [DMESG-FAIL][26] ([fdo#111991]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-hsw2/igt@i915_selftest@live_hangcheck.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-hsw4/igt@i915_selftest@live_hangcheck.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-iclb: [PASS][27] -> [DMESG-WARN][28] ([fdo#111764]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb7/igt@i915_suspend@fence-restore-tiled2untiled.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb1/igt@i915_suspend@fence-restore-tiled2untiled.html * igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: - shard-apl: [PASS][29] -> [INCOMPLETE][30] ([fdo#103927]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-apl7/igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-apl6/igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing.html * igt@kms_color@pipe-a-ctm-0-75: - shard-skl: [PASS][31] -> [DMESG-WARN][32] ([fdo#106107]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-skl10/igt@kms_color@pipe-a-ctm-0-75.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-skl10/igt@kms_color@pipe-a-ctm-0-75.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-skl: [PASS][33] -> [FAIL][34] ([fdo#102670]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][35] -> [FAIL][36] ([fdo#105363]) +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-skl6/igt@kms_flip@flip-vs-expired-vblank.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-skl3/igt@kms_flip@flip-vs-expired-vblank.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-iclb: [PASS][37] -> [FAIL][38] ([fdo#105363]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb1/igt@kms_flip@flip-vs-expired-vblank-interruptible.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-skl: [PASS][39] -> [INCOMPLETE][40] ([fdo#109507]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-skl3/igt@kms_flip@flip-vs-suspend-interruptible.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-skl6/igt@kms_flip@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [PASS][41] -> [FAIL][42] ([fdo#103167]) +3 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][43] -> [FAIL][44] ([fdo#108145]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: [PASS][45] -> [FAIL][46] ([fdo#103166]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-y.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb4/igt@kms_plane_lowres@pipe-a-tiling-y.html * igt@kms_psr@psr2_sprite_plane_onoff: - shard-iclb: [PASS][47] -> [SKIP][48] ([fdo#109441]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb2/igt@kms_psr@psr2_sprite_plane_onoff.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb3/igt@kms_psr@psr2_sprite_plane_onoff.html * igt@kms_setmode@basic: - shard-glk: [PASS][49] -> [FAIL][50] ([fdo#99912]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-glk3/igt@kms_setmode@basic.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-glk1/igt@kms_setmode@basic.html * igt@prime_vgem@fence-wait-bsd2: - shard-iclb: [PASS][51] -> [SKIP][52] ([fdo#109276]) +13 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb3/igt@prime_vgem@fence-wait-bsd2.html #### Possible fixes #### * igt@gem_ctx_isolation@vcs1-dirty-create: - shard-iclb: [SKIP][53] ([fdo#109276] / [fdo#112080]) -> [PASS][54] +1 similar issue [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb6/igt@gem_ctx_isolation@vcs1-dirty-create.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb2/igt@gem_ctx_isolation@vcs1-dirty-create.html * igt@gem_eio@reset-stress: - shard-snb: [FAIL][55] ([fdo#109661]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-snb1/igt@gem_eio@reset-stress.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-snb1/igt@gem_eio@reset-stress.html * igt@gem_exec_nop@basic-series: - {shard-tglb}: [INCOMPLETE][57] ([fdo#111747]) -> [PASS][58] +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-tglb4/igt@gem_exec_nop@basic-series.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-tglb8/igt@gem_exec_nop@basic-series.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [SKIP][59] ([fdo#109276]) -> [PASS][60] +25 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb8/igt@gem_exec_schedule@preempt-queue-bsd1.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb1/igt@gem_exec_schedule@preempt-queue-bsd1.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [SKIP][61] ([fdo#112146]) -> [PASS][62] +4 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb3/igt@gem_exec_schedule@preemptive-hang-bsd.html * igt@gem_userptr_blits@dmabuf-unsync: - shard-hsw: [DMESG-WARN][63] ([fdo#111870]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-hsw2/igt@gem_userptr_blits@dmabuf-unsync.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-hsw1/igt@gem_userptr_blits@dmabuf-unsync.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup: - shard-snb: [DMESG-WARN][65] ([fdo#111870]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-snb1/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-snb2/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html * igt@gem_workarounds@suspend-resume-fd: - shard-apl: [DMESG-WARN][67] ([fdo#108566]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-apl1/igt@gem_workarounds@suspend-resume-fd.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-apl1/igt@gem_workarounds@suspend-resume-fd.html * {igt@i915_pm_dc@dc6-psr}: - shard-iclb: [FAIL][69] ([fdo#110548]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb4/igt@i915_pm_dc@dc6-psr.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb1/igt@i915_pm_dc@dc6-psr.html * igt@i915_selftest@live_hangcheck: - shard-iclb: [INCOMPLETE][71] ([fdo#107713] / [fdo#108569]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb6/igt@i915_selftest@live_hangcheck.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb7/igt@i915_selftest@live_hangcheck.html * igt@i915_suspend@fence-restore-untiled: - shard-kbl: [INCOMPLETE][73] ([fdo#103665]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-kbl4/igt@i915_suspend@fence-restore-untiled.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-kbl3/igt@i915_suspend@fence-restore-untiled.html * igt@kms_cursor_crc@pipe-c-cursor-128x42-offscreen: - shard-apl: [INCOMPLETE][75] ([fdo#103927]) -> [PASS][76] +3 similar issues [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-apl6/igt@kms_cursor_crc@pipe-c-cursor-128x42-offscreen.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-apl4/igt@kms_cursor_crc@pipe-c-cursor-128x42-offscreen.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [DMESG-WARN][77] ([fdo#108566]) -> [PASS][78] +4 similar issues [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-kbl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite: - shard-iclb: [FAIL][79] ([fdo#103167]) -> [PASS][80] +4 similar issues [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbc-suspend: - {shard-tglb}: [INCOMPLETE][81] ([fdo#111832] / [fdo#111850] / [fdo#111884]) -> [PASS][82] [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-suspend.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite: - {shard-tglb}: [INCOMPLETE][83] ([fdo#111747] / [fdo#111884]) -> [PASS][84] [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt: - {shard-tglb}: [FAIL][85] ([fdo#103167]) -> [PASS][86] +5 similar issues [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [FAIL][87] ([fdo#108145] / [fdo#110403]) -> [PASS][88] [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt@kms_psr2_su@page_flip: - shard-iclb: [SKIP][89] ([fdo#109642] / [fdo#111068]) -> [PASS][90] [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb8/igt@kms_psr2_su@page_flip.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb2/igt@kms_psr2_su@page_flip.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [SKIP][91] ([fdo#109441]) -> [PASS][92] +1 similar issue [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb8/igt@kms_psr@psr2_primary_page_flip.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html * igt@kms_psr@psr2_suspend: - {shard-tglb}: [INCOMPLETE][93] ([fdo#111832] / [fdo#111850]) -> [PASS][94] [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-tglb8/igt@kms_psr@psr2_suspend.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-tglb2/igt@kms_psr@psr2_suspend.html * igt@kms_setmode@basic: - shard-apl: [FAIL][95] ([fdo#99912]) -> [PASS][96] [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-apl3/igt@kms_setmode@basic.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-apl1/igt@kms_setmode@basic.html - shard-skl: [FAIL][97] ([fdo#99912]) -> [PASS][98] [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-skl5/igt@kms_setmode@basic.html [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-skl7/igt@kms_setmode@basic.html * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend: - {shard-tglb}: [INCOMPLETE][99] ([fdo#111850]) -> [PASS][100] [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-tglb7/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-tglb1/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html * igt@kms_vblank@pipe-b-ts-continuation-suspend: - shard-skl: [INCOMPLETE][101] ([fdo#104108]) -> [PASS][102] [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-skl7/igt@kms_vblank@pipe-b-ts-continuation-suspend.html [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-skl8/igt@kms_vblank@pipe-b-ts-continuation-suspend.html * igt@perf_pmu@busy-vcs1: - shard-iclb: [SKIP][103] ([fdo#112080]) -> [PASS][104] +9 similar issues [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb8/igt@perf_pmu@busy-vcs1.html [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb2/igt@perf_pmu@busy-vcs1.html #### Warnings #### * igt@gem_mocs_settings@mocs-isolation-bsd2: - shard-iclb: [FAIL][105] ([fdo#111330]) -> [SKIP][106] ([fdo#109276]) [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb2/igt@gem_mocs_settings@mocs-isolation-bsd2.html [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb3/igt@gem_mocs_settings@mocs-isolation-bsd2.html * igt@gem_mocs_settings@mocs-rc6-bsd2: - shard-iclb: [SKIP][107] ([fdo#109276]) -> [FAIL][108] ([fdo#111330]) [107]: http == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2019-10-29 2:15 UTC | newest] Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-10-27 22:58 [PATCH 1/5] drm/i915/selftests: Drop global engine lookup for gt selftests Chris Wilson 2019-10-27 22:58 ` [Intel-gfx] " Chris Wilson 2019-10-27 22:58 ` [PATCH 2/5] drm/i915/selftests: Exercise adjusting rpcs over all render-class engines Chris Wilson 2019-10-27 22:58 ` [Intel-gfx] " Chris Wilson 2019-10-28 12:04 ` Matthew Auld 2019-10-28 12:04 ` [Intel-gfx] " Matthew Auld 2019-10-27 22:58 ` [PATCH 3/5] drm/i915/selftests: Check all blitter engines for client blt Chris Wilson 2019-10-27 22:58 ` [Intel-gfx] " Chris Wilson 2019-10-28 11:16 ` Matthew Auld 2019-10-28 11:16 ` [Intel-gfx] " Matthew Auld 2019-10-27 22:58 ` [PATCH 4/5] drm/i915/selftests: Use a random engine for GEM coherency tests Chris Wilson 2019-10-27 22:58 ` [Intel-gfx] " Chris Wilson 2019-10-28 11:33 ` Matthew Auld 2019-10-28 11:33 ` [Intel-gfx] " Matthew Auld 2019-10-27 22:58 ` [PATCH 5/5] drm/i915/selftests: Select a random engine for testing memory regions Chris Wilson 2019-10-27 22:58 ` [Intel-gfx] " Chris Wilson 2019-10-28 11:39 ` Matthew Auld 2019-10-28 11:39 ` [Intel-gfx] " Matthew Auld 2019-10-27 23:33 ` ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915/selftests: Drop global engine lookup for gt selftests Patchwork 2019-10-27 23:33 ` [Intel-gfx] " Patchwork 2019-10-28 11:13 ` [PATCH 1/5] " Matthew Auld 2019-10-28 11:13 ` [Intel-gfx] " Matthew Auld 2019-10-29 2:15 ` ✓ Fi.CI.IGT: success for series starting with [1/5] " Patchwork 2019-10-29 2:15 ` [Intel-gfx] " Patchwork
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