* [PATCH v6 00/10] Clear Color Support for TGL Render Decompression
@ 2019-10-28 20:40 ` Radhakrishna Sripada
0 siblings, 0 replies; 34+ messages in thread
From: Radhakrishna Sripada @ 2019-10-28 20:40 UTC (permalink / raw)
To: intel-gfx; +Cc: nanley.g.chery, dhinakaran.pandiyan, ville.syrjala
Support for Clear Color is contained in the last two patches
submitted by Radhakrishna Sripada. The first 8 patches are
currently undergoing review/revision changes. The first 8 patches
are cherry-picked from the series
https://patchwork.freedesktop.org/series/67078/
Expecting feedback for the 9th patches. The series is tested with kms_cube
and custom Mesa branch by Nanley. Resending due to a wrong patch sent to the ML.
Dhinakaran Pandiyan (8):
drm/framebuffer: Format modifier for Intel Gen-12 render compression
drm/i915: Use intel_tile_height() instead of re-implementing
drm/i915: Move CCS stride alignment W/A inside
intel_fb_stride_alignment
drm/i915/tgl: Gen-12 render decompression
drm/i915: Extract framebufer CCS offset checks into a function
drm/framebuffer: Format modifier for Intel Gen-12 media compression
drm/fb: Extend format_info member arrays to handle four planes
Gen-12 display can decompress surfaces compressed by the media engine.
Radhakrishna Sripada (2):
drm/framebuffer/tgl: Format modifier for Intel Gen 12 render
compression with Clear Color
drm/i915/tgl: Add Clear Color support for TGL Render Decompression
drivers/gpu/drm/i915/display/intel_display.c | 434 ++++++++++++++----
.../drm/i915/display/intel_display_types.h | 5 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 70 ++-
drivers/gpu/drm/i915/i915_reg.h | 14 +
include/drm/drm_fourcc.h | 8 +-
include/uapi/drm/drm_fourcc.h | 43 ++
6 files changed, 460 insertions(+), 114 deletions(-)
--
2.20.1
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^ permalink raw reply [flat|nested] 34+ messages in thread
* [Intel-gfx] [PATCH v6 00/10] Clear Color Support for TGL Render Decompression
@ 2019-10-28 20:40 ` Radhakrishna Sripada
0 siblings, 0 replies; 34+ messages in thread
From: Radhakrishna Sripada @ 2019-10-28 20:40 UTC (permalink / raw)
To: intel-gfx; +Cc: nanley.g.chery, dhinakaran.pandiyan, ville.syrjala
Support for Clear Color is contained in the last two patches
submitted by Radhakrishna Sripada. The first 8 patches are
currently undergoing review/revision changes. The first 8 patches
are cherry-picked from the series
https://patchwork.freedesktop.org/series/67078/
Expecting feedback for the 9th patches. The series is tested with kms_cube
and custom Mesa branch by Nanley. Resending due to a wrong patch sent to the ML.
Dhinakaran Pandiyan (8):
drm/framebuffer: Format modifier for Intel Gen-12 render compression
drm/i915: Use intel_tile_height() instead of re-implementing
drm/i915: Move CCS stride alignment W/A inside
intel_fb_stride_alignment
drm/i915/tgl: Gen-12 render decompression
drm/i915: Extract framebufer CCS offset checks into a function
drm/framebuffer: Format modifier for Intel Gen-12 media compression
drm/fb: Extend format_info member arrays to handle four planes
Gen-12 display can decompress surfaces compressed by the media engine.
Radhakrishna Sripada (2):
drm/framebuffer/tgl: Format modifier for Intel Gen 12 render
compression with Clear Color
drm/i915/tgl: Add Clear Color support for TGL Render Decompression
drivers/gpu/drm/i915/display/intel_display.c | 434 ++++++++++++++----
.../drm/i915/display/intel_display_types.h | 5 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 70 ++-
drivers/gpu/drm/i915/i915_reg.h | 14 +
include/drm/drm_fourcc.h | 8 +-
include/uapi/drm/drm_fourcc.h | 43 ++
6 files changed, 460 insertions(+), 114 deletions(-)
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v6 01/10] drm/framebuffer: Format modifier for Intel Gen-12 render compression
@ 2019-10-28 20:40 ` Radhakrishna Sripada
0 siblings, 0 replies; 34+ messages in thread
From: Radhakrishna Sripada @ 2019-10-28 20:40 UTC (permalink / raw)
To: intel-gfx
Cc: nanley.g.chery, Lucas De Marchi, dhinakaran.pandiyan, ville.syrjala
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Gen-12 has a new compression format, add a new modifier to indicate that.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
include/uapi/drm/drm_fourcc.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 8caaaf7ff91b..5ba481f49931 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -410,6 +410,17 @@ extern "C" {
#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
#define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
+/*
+ * Intel color control surfaces (CCS) for Gen-12 render compression.
+ *
+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * Y-tile widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
--
2.20.1
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^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Intel-gfx] [PATCH v6 01/10] drm/framebuffer: Format modifier for Intel Gen-12 render compression
@ 2019-10-28 20:40 ` Radhakrishna Sripada
0 siblings, 0 replies; 34+ messages in thread
From: Radhakrishna Sripada @ 2019-10-28 20:40 UTC (permalink / raw)
To: intel-gfx
Cc: nanley.g.chery, Lucas De Marchi, dhinakaran.pandiyan, ville.syrjala
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Gen-12 has a new compression format, add a new modifier to indicate that.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
include/uapi/drm/drm_fourcc.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 8caaaf7ff91b..5ba481f49931 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -410,6 +410,17 @@ extern "C" {
#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
#define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
+/*
+ * Intel color control surfaces (CCS) for Gen-12 render compression.
+ *
+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * Y-tile widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
--
2.20.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v6 02/10] drm/i915: Use intel_tile_height() instead of re-implementing
@ 2019-10-28 20:40 ` Radhakrishna Sripada
0 siblings, 0 replies; 34+ messages in thread
From: Radhakrishna Sripada @ 2019-10-28 20:40 UTC (permalink / raw)
To: intel-gfx; +Cc: nanley.g.chery, dhinakaran.pandiyan, ville.syrjala
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
intel_tile_dims() computes tile height using size and width, when there
is already a function to do just that - intel_tile_height()
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9dce2e9e5376..3796547ba018 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1982,7 +1982,7 @@ static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
unsigned int cpp = fb->format->cpp[color_plane];
*tile_width = tile_width_bytes / cpp;
- *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
+ *tile_height = intel_tile_height(fb, color_plane);
}
unsigned int
--
2.20.1
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^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Intel-gfx] [PATCH v6 02/10] drm/i915: Use intel_tile_height() instead of re-implementing
@ 2019-10-28 20:40 ` Radhakrishna Sripada
0 siblings, 0 replies; 34+ messages in thread
From: Radhakrishna Sripada @ 2019-10-28 20:40 UTC (permalink / raw)
To: intel-gfx; +Cc: nanley.g.chery, dhinakaran.pandiyan, ville.syrjala
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
intel_tile_dims() computes tile height using size and width, when there
is already a function to do just that - intel_tile_height()
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9dce2e9e5376..3796547ba018 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1982,7 +1982,7 @@ static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
unsigned int cpp = fb->format->cpp[color_plane];
*tile_width = tile_width_bytes / cpp;
- *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
+ *tile_height = intel_tile_height(fb, color_plane);
}
unsigned int
--
2.20.1
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^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v6 03/10] drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment
@ 2019-10-28 20:40 ` Radhakrishna Sripada
0 siblings, 0 replies; 34+ messages in thread
From: Radhakrishna Sripada @ 2019-10-28 20:40 UTC (permalink / raw)
To: intel-gfx; +Cc: nanley.g.chery, dhinakaran.pandiyan, ville.syrjala
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Easier to read if all the alignment changes are in one place and contained
within a function.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 31 ++++++++++----------
1 file changed, 16 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 3796547ba018..b8ef99eac254 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2573,7 +2573,22 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
else
return 64;
} else {
- return intel_tile_width_bytes(fb, color_plane);
+ u32 tile_width = intel_tile_width_bytes(fb, color_plane);
+
+ /*
+ * Display WA #0531: skl,bxt,kbl,glk
+ *
+ * Render decompression and plane width > 3840
+ * combined with horizontal panning requires the
+ * plane stride to be a multiple of 4. We'll just
+ * require the entire fb to accommodate that to avoid
+ * potential runtime errors at plane configuration time.
+ */
+ if (IS_GEN(dev_priv, 9) && is_ccs_modifier(fb->modifier) &&
+ color_plane == 0 && fb->width > 3840)
+ tile_width *= 4;
+
+ return tile_width;
}
}
@@ -16306,20 +16321,6 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
}
stride_alignment = intel_fb_stride_alignment(fb, i);
-
- /*
- * Display WA #0531: skl,bxt,kbl,glk
- *
- * Render decompression and plane width > 3840
- * combined with horizontal panning requires the
- * plane stride to be a multiple of 4. We'll just
- * require the entire fb to accommodate that to avoid
- * potential runtime errors at plane configuration time.
- */
- if (IS_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 &&
- is_ccs_modifier(fb->modifier))
- stride_alignment *= 4;
-
if (fb->pitches[i] & (stride_alignment - 1)) {
DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
i, fb->pitches[i], stride_alignment);
--
2.20.1
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^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Intel-gfx] [PATCH v6 03/10] drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment
@ 2019-10-28 20:40 ` Radhakrishna Sripada
0 siblings, 0 replies; 34+ messages in thread
From: Radhakrishna Sripada @ 2019-10-28 20:40 UTC (permalink / raw)
To: intel-gfx; +Cc: nanley.g.chery, dhinakaran.pandiyan, ville.syrjala
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Easier to read if all the alignment changes are in one place and contained
within a function.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 31 ++++++++++----------
1 file changed, 16 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 3796547ba018..b8ef99eac254 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2573,7 +2573,22 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
else
return 64;
} else {
- return intel_tile_width_bytes(fb, color_plane);
+ u32 tile_width = intel_tile_width_bytes(fb, color_plane);
+
+ /*
+ * Display WA #0531: skl,bxt,kbl,glk
+ *
+ * Render decompression and plane width > 3840
+ * combined with horizontal panning requires the
+ * plane stride to be a multiple of 4. We'll just
+ * require the entire fb to accommodate that to avoid
+ * potential runtime errors at plane configuration time.
+ */
+ if (IS_GEN(dev_priv, 9) && is_ccs_modifier(fb->modifier) &&
+ color_plane == 0 && fb->width > 3840)
+ tile_width *= 4;
+
+ return tile_width;
}
}
@@ -16306,20 +16321,6 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
}
stride_alignment = intel_fb_stride_alignment(fb, i);
-
- /*
- * Display WA #0531: skl,bxt,kbl,glk
- *
- * Render decompression and plane width > 3840
- * combined with horizontal panning requires the
- * plane stride to be a multiple of 4. We'll just
- * require the entire fb to accommodate that to avoid
- * potential runtime errors at plane configuration time.
- */
- if (IS_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 &&
- is_ccs_modifier(fb->modifier))
- stride_alignment *= 4;
-
if (fb->pitches[i] & (stride_alignment - 1)) {
DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
i, fb->pitches[i], stride_alignment);
--
2.20.1
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^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v6 04/10] drm/i915/tgl: Gen-12 render decompression
@ 2019-10-28 20:40 ` Radhakrishna Sripada
0 siblings, 0 replies; 34+ messages in thread
From: Radhakrishna Sripada @ 2019-10-28 20:40 UTC (permalink / raw)
To: intel-gfx
Cc: nanley.g.chery, Lucas De Marchi, dhinakaran.pandiyan, ville.syrjala
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Gen-12 display decompression operates on Y-tiled compressed main surface.
The CCS is linear and has 4 bits of metadata for each main surface cache
line pair, a size ratio of 1:256. Gen-12 display decompression is
incompatible with buffers compressed by earlier GPUs, so make use of a new
modifier to identify gen-12 compression. Another notable change is that
render decompression is supported on all planes except cursor and on all
pipes. Start by adding render decompression support for [A,X]BGR888 pixel
formats.
v2: Fix checkpatch warnings (Lucas)
v3:
Rebase, disable color clear, styling changes and modify
intel_tile_width_bytes and intel_tile_height to handle linear CCS
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 85 ++++++++++++++++----
drivers/gpu/drm/i915/display/intel_sprite.c | 23 ++++--
drivers/gpu/drm/i915/i915_reg.h | 1 +
3 files changed, 84 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b8ef99eac254..194e508430db 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1936,6 +1936,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
if (color_plane == 1)
return 128;
/* fall through */
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ if (color_plane == 1)
+ return 64;
+ /* fall through */
case I915_FORMAT_MOD_Y_TILED:
if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
return 128;
@@ -1969,8 +1973,15 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
static unsigned int
intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
{
- return intel_tile_size(to_i915(fb->dev)) /
- intel_tile_width_bytes(fb, color_plane);
+ switch (fb->modifier) {
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ if (color_plane == 1)
+ return 1;
+ /* fall through */
+ default:
+ return intel_tile_size(to_i915(fb->dev)) /
+ intel_tile_width_bytes(fb, color_plane);
+ }
}
/* Return the tile dimensions in pixel units */
@@ -2069,6 +2080,8 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
if (INTEL_GEN(dev_priv) >= 9)
return 256 * 1024;
return 0;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ return 16 * 1024;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED:
@@ -2265,7 +2278,8 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
static bool is_surface_linear(u64 modifier, int color_plane)
{
- return modifier == DRM_FORMAT_MOD_LINEAR;
+ return modifier == DRM_FORMAT_MOD_LINEAR ||
+ (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane == 1);
}
static u32 intel_adjust_aligned_offset(int *x, int *y,
@@ -2452,6 +2466,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
return I915_TILING_X;
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Y_TILED_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return I915_TILING_Y;
default:
return I915_TILING_NONE;
@@ -2472,7 +2487,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
* us a ratio of one byte in the CCS for each 8x16 pixels in the
* main surface.
*/
-static const struct drm_format_info ccs_formats[] = {
+static const struct drm_format_info skl_ccs_formats[] = {
{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
.cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
@@ -2483,6 +2498,24 @@ static const struct drm_format_info ccs_formats[] = {
.cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
};
+/*
+ * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
+ * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
+ * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
+ * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
+ * the main surface.
+ */
+static const struct drm_format_info gen12_ccs_formats[] = {
+ { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+ { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+};
+
static const struct drm_format_info *
lookup_format_info(const struct drm_format_info formats[],
int num_formats, u32 format)
@@ -2503,8 +2536,12 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
switch (cmd->modifier[0]) {
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
- return lookup_format_info(ccs_formats,
- ARRAY_SIZE(ccs_formats),
+ return lookup_format_info(skl_ccs_formats,
+ ARRAY_SIZE(skl_ccs_formats),
+ cmd->pixel_format);
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ return lookup_format_info(gen12_ccs_formats,
+ ARRAY_SIZE(gen12_ccs_formats),
cmd->pixel_format);
default:
return NULL;
@@ -2513,7 +2550,8 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
bool is_ccs_modifier(u64 modifier)
{
- return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
+ return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
@@ -2558,8 +2596,9 @@ static u32
intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
{
struct drm_i915_private *dev_priv = to_i915(fb->dev);
+ u32 tile_width;
- if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
+ if (is_surface_linear(fb->modifier, color_plane)) {
u32 max_stride = intel_plane_fb_max_stride(dev_priv,
fb->format->format,
fb->modifier);
@@ -2568,13 +2607,14 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
* To make remapping with linear generally feasible
* we need the stride to be page aligned.
*/
- if (fb->pitches[color_plane] > max_stride)
+ if (fb->pitches[color_plane] > max_stride && !is_ccs_modifier(fb->modifier))
return intel_tile_size(dev_priv);
else
return 64;
- } else {
- u32 tile_width = intel_tile_width_bytes(fb, color_plane);
+ }
+ tile_width = intel_tile_width_bytes(fb, color_plane);
+ if (is_ccs_modifier(fb->modifier) && color_plane == 0) {
/*
* Display WA #0531: skl,bxt,kbl,glk
*
@@ -2584,12 +2624,16 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
* require the entire fb to accommodate that to avoid
* potential runtime errors at plane configuration time.
*/
- if (IS_GEN(dev_priv, 9) && is_ccs_modifier(fb->modifier) &&
- color_plane == 0 && fb->width > 3840)
+ if (IS_GEN(dev_priv, 9) && fb->width > 3840)
+ tile_width *= 4;
+ /*
+ * The main surface pitch must be padded to a multiple of four
+ * tile widths.
+ */
+ else if (INTEL_GEN(dev_priv) >= 12)
tile_width *= 4;
-
- return tile_width;
}
+ return tile_width;
}
bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
@@ -2698,6 +2742,7 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
int ccs_x, ccs_y;
intel_tile_dims(fb, i, &tile_width, &tile_height);
+
tile_width *= hsub;
tile_height *= vsub;
@@ -4041,7 +4086,7 @@ static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
* The stride is either expressed as a multiple of 64 bytes chunks for
* linear buffers or in number of tiles for tiled buffers.
*/
- if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
+ if (is_surface_linear(fb->modifier, color_plane))
return 64;
else if (drm_rotation_90_or_270(rotation))
return intel_tile_height(fb, color_plane);
@@ -4167,6 +4212,10 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
return PLANE_CTL_TILED_Y;
case I915_FORMAT_MOD_Y_TILED_CCS:
return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ return PLANE_CTL_TILED_Y |
+ PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
+ PLANE_CTL_CLEAR_COLOR_DISABLE;
case I915_FORMAT_MOD_Yf_TILED:
return PLANE_CTL_TILED_YF;
case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -9993,7 +10042,9 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
case PLANE_CTL_TILED_Y:
plane_config->tiling = I915_TILING_Y;
if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
- fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
+ fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
+ I915_FORMAT_MOD_Y_TILED_CCS;
else
fb->modifier = I915_FORMAT_MOD_Y_TILED;
break;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index edc41fc40726..b6494643183d 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -582,6 +582,7 @@ skl_program_plane(struct intel_plane *plane,
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
u32 surf_addr = plane_state->color_plane[color_plane].offset;
u32 stride = skl_plane_stride(plane_state, color_plane);
+ u32 aux_dist = plane_state->color_plane[1].offset - surf_addr;
u32 aux_stride = skl_plane_stride(plane_state, 1);
int crtc_x = plane_state->base.dst.x1;
int crtc_y = plane_state->base.dst.y1;
@@ -623,8 +624,10 @@ skl_program_plane(struct intel_plane *plane,
I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
- I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
- (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
+
+ if (INTEL_GEN(dev_priv) < 12)
+ aux_dist |= aux_stride;
+ I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), aux_dist);
if (icl_is_hdr_plane(dev_priv, plane_id)) {
u32 cus_ctl = 0;
@@ -2110,7 +2113,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
(fb->modifier == I915_FORMAT_MOD_Y_TILED ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
- fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
+ fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
return -EINVAL;
}
@@ -2546,7 +2550,8 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
DRM_FORMAT_MOD_INVALID
};
-static const u64 gen12_plane_format_modifiers_noccs[] = {
+static const u64 gen12_plane_format_modifiers_ccs[] = {
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_LINEAR,
@@ -2710,6 +2715,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
break;
default:
return false;
@@ -2720,6 +2726,9 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_XBGR8888:
case DRM_FORMAT_ARGB8888:
case DRM_FORMAT_ABGR8888:
+ if (is_ccs_modifier(modifier))
+ return true;
+ /* fall through */
case DRM_FORMAT_RGB565:
case DRM_FORMAT_XRGB2101010:
case DRM_FORMAT_XBGR2101010:
@@ -2929,13 +2938,11 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
formats = skl_get_plane_formats(dev_priv, pipe,
plane_id, &num_formats);
+ plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
if (INTEL_GEN(dev_priv) >= 12) {
- /* TODO: Implement support for gen-12 CCS modifiers */
- plane->has_ccs = false;
- modifiers = gen12_plane_format_modifiers_noccs;
+ modifiers = gen12_plane_format_modifiers_ccs;
plane_funcs = &gen12_plane_funcs;
} else {
- plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
if (plane->has_ccs)
modifiers = skl_plane_format_modifiers_ccs;
else
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fb33b164ce55..49fe4f0df24f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6712,6 +6712,7 @@ enum {
#define PLANE_CTL_YUV422_VYUY (3 << 16)
#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15)
#define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
+#define PLANE_CTL_CLEAR_COLOR_DISABLE (1 << 13) /* TGL+ */
#define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */
#define PLANE_CTL_TILED_MASK (0x7 << 10)
#define PLANE_CTL_TILED_LINEAR (0 << 10)
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Intel-gfx] [PATCH v6 04/10] drm/i915/tgl: Gen-12 render decompression
@ 2019-10-28 20:40 ` Radhakrishna Sripada
0 siblings, 0 replies; 34+ messages in thread
From: Radhakrishna Sripada @ 2019-10-28 20:40 UTC (permalink / raw)
To: intel-gfx
Cc: nanley.g.chery, Lucas De Marchi, dhinakaran.pandiyan, ville.syrjala
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Gen-12 display decompression operates on Y-tiled compressed main surface.
The CCS is linear and has 4 bits of metadata for each main surface cache
line pair, a size ratio of 1:256. Gen-12 display decompression is
incompatible with buffers compressed by earlier GPUs, so make use of a new
modifier to identify gen-12 compression. Another notable change is that
render decompression is supported on all planes except cursor and on all
pipes. Start by adding render decompression support for [A,X]BGR888 pixel
formats.
v2: Fix checkpatch warnings (Lucas)
v3:
Rebase, disable color clear, styling changes and modify
intel_tile_width_bytes and intel_tile_height to handle linear CCS
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 85 ++++++++++++++++----
drivers/gpu/drm/i915/display/intel_sprite.c | 23 ++++--
drivers/gpu/drm/i915/i915_reg.h | 1 +
3 files changed, 84 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b8ef99eac254..194e508430db 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1936,6 +1936,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
if (color_plane == 1)
return 128;
/* fall through */
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ if (color_plane == 1)
+ return 64;
+ /* fall through */
case I915_FORMAT_MOD_Y_TILED:
if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
return 128;
@@ -1969,8 +1973,15 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
static unsigned int
intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
{
- return intel_tile_size(to_i915(fb->dev)) /
- intel_tile_width_bytes(fb, color_plane);
+ switch (fb->modifier) {
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ if (color_plane == 1)
+ return 1;
+ /* fall through */
+ default:
+ return intel_tile_size(to_i915(fb->dev)) /
+ intel_tile_width_bytes(fb, color_plane);
+ }
}
/* Return the tile dimensions in pixel units */
@@ -2069,6 +2080,8 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
if (INTEL_GEN(dev_priv) >= 9)
return 256 * 1024;
return 0;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ return 16 * 1024;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED:
@@ -2265,7 +2278,8 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
static bool is_surface_linear(u64 modifier, int color_plane)
{
- return modifier == DRM_FORMAT_MOD_LINEAR;
+ return modifier == DRM_FORMAT_MOD_LINEAR ||
+ (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane == 1);
}
static u32 intel_adjust_aligned_offset(int *x, int *y,
@@ -2452,6 +2466,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
return I915_TILING_X;
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Y_TILED_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return I915_TILING_Y;
default:
return I915_TILING_NONE;
@@ -2472,7 +2487,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
* us a ratio of one byte in the CCS for each 8x16 pixels in the
* main surface.
*/
-static const struct drm_format_info ccs_formats[] = {
+static const struct drm_format_info skl_ccs_formats[] = {
{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
.cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
@@ -2483,6 +2498,24 @@ static const struct drm_format_info ccs_formats[] = {
.cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
};
+/*
+ * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
+ * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
+ * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
+ * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
+ * the main surface.
+ */
+static const struct drm_format_info gen12_ccs_formats[] = {
+ { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+ { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+};
+
static const struct drm_format_info *
lookup_format_info(const struct drm_format_info formats[],
int num_formats, u32 format)
@@ -2503,8 +2536,12 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
switch (cmd->modifier[0]) {
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
- return lookup_format_info(ccs_formats,
- ARRAY_SIZE(ccs_formats),
+ return lookup_format_info(skl_ccs_formats,
+ ARRAY_SIZE(skl_ccs_formats),
+ cmd->pixel_format);
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ return lookup_format_info(gen12_ccs_formats,
+ ARRAY_SIZE(gen12_ccs_formats),
cmd->pixel_format);
default:
return NULL;
@@ -2513,7 +2550,8 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
bool is_ccs_modifier(u64 modifier)
{
- return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
+ return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
@@ -2558,8 +2596,9 @@ static u32
intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
{
struct drm_i915_private *dev_priv = to_i915(fb->dev);
+ u32 tile_width;
- if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
+ if (is_surface_linear(fb->modifier, color_plane)) {
u32 max_stride = intel_plane_fb_max_stride(dev_priv,
fb->format->format,
fb->modifier);
@@ -2568,13 +2607,14 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
* To make remapping with linear generally feasible
* we need the stride to be page aligned.
*/
- if (fb->pitches[color_plane] > max_stride)
+ if (fb->pitches[color_plane] > max_stride && !is_ccs_modifier(fb->modifier))
return intel_tile_size(dev_priv);
else
return 64;
- } else {
- u32 tile_width = intel_tile_width_bytes(fb, color_plane);
+ }
+ tile_width = intel_tile_width_bytes(fb, color_plane);
+ if (is_ccs_modifier(fb->modifier) && color_plane == 0) {
/*
* Display WA #0531: skl,bxt,kbl,glk
*
@@ -2584,12 +2624,16 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
* require the entire fb to accommodate that to avoid
* potential runtime errors at plane configuration time.
*/
- if (IS_GEN(dev_priv, 9) && is_ccs_modifier(fb->modifier) &&
- color_plane == 0 && fb->width > 3840)
+ if (IS_GEN(dev_priv, 9) && fb->width > 3840)
+ tile_width *= 4;
+ /*
+ * The main surface pitch must be padded to a multiple of four
+ * tile widths.
+ */
+ else if (INTEL_GEN(dev_priv) >= 12)
tile_width *= 4;
-
- return tile_width;
}
+ return tile_width;
}
bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
@@ -2698,6 +2742,7 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
int ccs_x, ccs_y;
intel_tile_dims(fb, i, &tile_width, &tile_height);
+
tile_width *= hsub;
tile_height *= vsub;
@@ -4041,7 +4086,7 @@ static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
* The stride is either expressed as a multiple of 64 bytes chunks for
* linear buffers or in number of tiles for tiled buffers.
*/
- if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
+ if (is_surface_linear(fb->modifier, color_plane))
return 64;
else if (drm_rotation_90_or_270(rotation))
return intel_tile_height(fb, color_plane);
@@ -4167,6 +4212,10 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
return PLANE_CTL_TILED_Y;
case I915_FORMAT_MOD_Y_TILED_CCS:
return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ return PLANE_CTL_TILED_Y |
+ PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
+ PLANE_CTL_CLEAR_COLOR_DISABLE;
case I915_FORMAT_MOD_Yf_TILED:
return PLANE_CTL_TILED_YF;
case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -9993,7 +10042,9 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
case PLANE_CTL_TILED_Y:
plane_config->tiling = I915_TILING_Y;
if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
- fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
+ fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
+ I915_FORMAT_MOD_Y_TILED_CCS;
else
fb->modifier = I915_FORMAT_MOD_Y_TILED;
break;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index edc41fc40726..b6494643183d 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -582,6 +582,7 @@ skl_program_plane(struct intel_plane *plane,
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
u32 surf_addr = plane_state->color_plane[color_plane].offset;
u32 stride = skl_plane_stride(plane_state, color_plane);
+ u32 aux_dist = plane_state->color_plane[1].offset - surf_addr;
u32 aux_stride = skl_plane_stride(plane_state, 1);
int crtc_x = plane_state->base.dst.x1;
int crtc_y = plane_state->base.dst.y1;
@@ -623,8 +624,10 @@ skl_program_plane(struct intel_plane *plane,
I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
- I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
- (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
+
+ if (INTEL_GEN(dev_priv) < 12)
+ aux_dist |= aux_stride;
+ I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), aux_dist);
if (icl_is_hdr_plane(dev_priv, plane_id)) {
u32 cus_ctl = 0;
@@ -2110,7 +2113,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
(fb->modifier == I915_FORMAT_MOD_Y_TILED ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
- fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
+ fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
return -EINVAL;
}
@@ -2546,7 +2550,8 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
DRM_FORMAT_MOD_INVALID
};
-static const u64 gen12_plane_format_modifiers_noccs[] = {
+static const u64 gen12_plane_format_modifiers_ccs[] = {
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_LINEAR,
@@ -2710,6 +2715,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
break;
default:
return false;
@@ -2720,6 +2726,9 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_XBGR8888:
case DRM_FORMAT_ARGB8888:
case DRM_FORMAT_ABGR8888:
+ if (is_ccs_modifier(modifier))
+ return true;
+ /* fall through */
case DRM_FORMAT_RGB565:
case DRM_FORMAT_XRGB2101010:
case DRM_FORMAT_XBGR2101010:
@@ -2929,13 +2938,11 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
formats = skl_get_plane_formats(dev_priv, pipe,
plane_id, &num_formats);
+ plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
if (INTEL_GEN(dev_priv) >= 12) {
- /* TODO: Implement support for gen-12 CCS modifiers */
- plane->has_ccs = false;
- modifiers = gen12_plane_format_modifiers_noccs;
+ modifiers = gen12_plane_format_modifiers_ccs;
plane_funcs = &gen12_plane_funcs;
} else {
- plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
if (plane->has_ccs)
modifiers = skl_plane_format_modifiers_ccs;
else
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fb33b164ce55..49fe4f0df24f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6712,6 +6712,7 @@ enum {
#define PLANE_CTL_YUV422_VYUY (3 << 16)
#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15)
#define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
+#define PLANE_CTL_CLEAR_COLOR_DISABLE (1 << 13) /* TGL+ */
#define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */
#define PLANE_CTL_TILED_MASK (0x7 << 10)
#define PLANE_CTL_TILED_LINEAR (0 << 10)
--
2.20.1
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^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v6 05/10] drm/i915: Extract framebufer CCS offset checks into a function
@ 2019-10-28 20:40 ` Radhakrishna Sripada
0 siblings, 0 replies; 34+ messages in thread
From: Radhakrishna Sripada @ 2019-10-28 20:40 UTC (permalink / raw)
To: intel-gfx; +Cc: nanley.g.chery, dhinakaran.pandiyan, ville.syrjala
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
intel_fill_fb_info() has grown quite large and wrapping the offset checks
into a separate function makes the loop a bit easier to follow.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 69 ++++++++++++--------
1 file changed, 40 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 194e508430db..0f22ccc6660d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2704,6 +2704,43 @@ static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
return stride > max_stride;
}
+static int
+intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
+{
+ struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+ int hsub = fb->format->hsub;
+ int vsub = fb->format->vsub;
+ int tile_width, tile_height;
+ int ccs_x, ccs_y;
+ int main_x, main_y;
+
+ intel_tile_dims(fb, 1, &tile_width, &tile_height);
+
+ tile_width *= hsub;
+ tile_height *= vsub;
+
+ ccs_x = (x * hsub) % tile_width;
+ ccs_y = (y * vsub) % tile_height;
+ main_x = intel_fb->normal[0].x % tile_width;
+ main_y = intel_fb->normal[0].y % tile_height;
+
+ /*
+ * CCS doesn't have its own x/y offset register, so the intra CCS tile
+ * x/y offsets must match between CCS and the main surface.
+ */
+ if (main_x != ccs_x || main_y != ccs_y) {
+ DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
+ main_x, main_y,
+ ccs_x, ccs_y,
+ intel_fb->normal[0].x,
+ intel_fb->normal[0].y,
+ x, y);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static int
intel_fill_fb_info(struct drm_i915_private *dev_priv,
struct drm_framebuffer *fb)
@@ -2735,35 +2772,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
}
if (is_ccs_modifier(fb->modifier) && i == 1) {
- int hsub = fb->format->hsub;
- int vsub = fb->format->vsub;
- int tile_width, tile_height;
- int main_x, main_y;
- int ccs_x, ccs_y;
-
- intel_tile_dims(fb, i, &tile_width, &tile_height);
-
- tile_width *= hsub;
- tile_height *= vsub;
-
- ccs_x = (x * hsub) % tile_width;
- ccs_y = (y * vsub) % tile_height;
- main_x = intel_fb->normal[0].x % tile_width;
- main_y = intel_fb->normal[0].y % tile_height;
-
- /*
- * CCS doesn't have its own x/y offset register, so the intra CCS tile
- * x/y offsets must match between CCS and the main surface.
- */
- if (main_x != ccs_x || main_y != ccs_y) {
- DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
- main_x, main_y,
- ccs_x, ccs_y,
- intel_fb->normal[0].x,
- intel_fb->normal[0].y,
- x, y);
- return -EINVAL;
- }
+ ret = intel_fb_check_ccs_xy(fb, x, y);
+ if (ret)
+ return ret;
}
/*
--
2.20.1
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^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Intel-gfx] [PATCH v6 05/10] drm/i915: Extract framebufer CCS offset checks into a function
@ 2019-10-28 20:40 ` Radhakrishna Sripada
0 siblings, 0 replies; 34+ messages in thread
From: Radhakrishna Sripada @ 2019-10-28 20:40 UTC (permalink / raw)
To: intel-gfx; +Cc: nanley.g.chery, dhinakaran.pandiyan, ville.syrjala
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
intel_fill_fb_info() has grown quite large and wrapping the offset checks
into a separate function makes the loop a bit easier to follow.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 69 ++++++++++++--------
1 file changed, 40 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 194e508430db..0f22ccc6660d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2704,6 +2704,43 @@ static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
return stride > max_stride;
}
+static int
+intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
+{
+ struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+ int hsub = fb->format->hsub;
+ int vsub = fb->format->vsub;
+ int tile_width, tile_height;
+ int ccs_x, ccs_y;
+ int main_x, main_y;
+
+ intel_tile_dims(fb, 1, &tile_width, &tile_height);
+
+ tile_width *= hsub;
+ tile_height *= vsub;
+
+ ccs_x = (x * hsub) % tile_width;
+ ccs_y = (y * vsub) % tile_height;
+ main_x = intel_fb->normal[0].x % tile_width;
+ main_y = intel_fb->normal[0].y % tile_height;
+
+ /*
+ * CCS doesn't have its own x/y offset register, so the intra CCS tile
+ * x/y offsets must match between CCS and the main surface.
+ */
+ if (main_x != ccs_x || main_y != ccs_y) {
+ DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
+ main_x, main_y,
+ ccs_x, ccs_y,
+ intel_fb->normal[0].x,
+ intel_fb->normal[0].y,
+ x, y);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static int
intel_fill_fb_info(struct drm_i915_private *dev_priv,
struct drm_framebuffer *fb)
@@ -2735,35 +2772,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
}
if (is_ccs_modifier(fb->modifier) && i == 1) {
- int hsub = fb->format->hsub;
- int vsub = fb->format->vsub;
- int tile_width, tile_height;
- int main_x, main_y;
- int ccs_x, ccs_y;
-
- intel_tile_dims(fb, i, &tile_width, &tile_height);
-
- tile_width *= hsub;
- tile_height *= vsub;
-
- ccs_x = (x * hsub) % tile_width;
- ccs_y = (y * vsub) % tile_height;
- main_x = intel_fb->normal[0].x % tile_width;
- main_y = intel_fb->normal[0].y % tile_height;
-
- /*
- * CCS doesn't have its own x/y offset register, so the intra CCS tile
- * x/y offsets must match between CCS and the main surface.
- */
- if (main_x != ccs_x || main_y != ccs_y) {
- DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
- main_x, main_y,
- ccs_x, ccs_y,
- intel_fb->normal[0].x,
- intel_fb->normal[0].y,
- x, y);
- return -EINVAL;
- }
+ ret = intel_fb_check_ccs_xy(fb, x, y);
+ if (ret)
+ return ret;
}
/*
--
2.20.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v6 06/10] drm/framebuffer: Format modifier for Intel Gen-12 media compression
@ 2019-10-28 20:40 ` Radhakrishna Sripada
0 siblings, 0 replies; 34+ messages in thread
From: Radhakrishna Sripada @ 2019-10-28 20:40 UTC (permalink / raw)
To: intel-gfx
Cc: nanley.g.chery, Lucas De Marchi, dhinakaran.pandiyan, ville.syrjala
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Gen-12 display can decompress surfaces compressed by the media engine, add
a new modifier as the driver needs to know the surface was compressed by
the media or render engine.
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
include/uapi/drm/drm_fourcc.h | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 5ba481f49931..1aa6d468c048 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -421,6 +421,19 @@ extern "C" {
*/
#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+/*
+ * Intel color control surfaces (CCS) for Gen-12 media compression
+ *
+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * Y-tile widths. For semi-planar formats like NV12, CCS plane follows the
+ * Y and UV planes i.e., planes 0 and 2 are used for Y and UV surfaces,
+ * planes 1 and 3 for the respective CCS.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
--
2.20.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Intel-gfx] [PATCH v6 06/10] drm/framebuffer: Format modifier for Intel Gen-12 media compression
@ 2019-10-28 20:40 ` Radhakrishna Sripada
0 siblings, 0 replies; 34+ messages in thread
From: Radhakrishna Sripada @ 2019-10-28 20:40 UTC (permalink / raw)
To: intel-gfx
Cc: nanley.g.chery, Lucas De Marchi, dhinakaran.pandiyan, ville.syrjala
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Gen-12 display can decompress surfaces compressed by the media engine, add
a new modifier as the driver needs to know the surface was compressed by
the media or render engine.
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
include/uapi/drm/drm_fourcc.h | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 5ba481f49931..1aa6d468c048 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -421,6 +421,19 @@ extern "C" {
*/
#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+/*
+ * Intel color control surfaces (CCS) for Gen-12 media compression
+ *
+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * Y-tile widths. For semi-planar formats like NV12, CCS plane follows the
+ * Y and UV planes i.e., planes 0 and 2 are used for Y and UV surfaces,
+ * planes 1 and 3 for the respective CCS.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
--
2.20.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v6 07/10] drm/fb: Extend format_info member arrays to handle four planes
@ 2019-10-28 20:40 ` Radhakrishna Sripada
0 siblings, 0 replies; 34+ messages in thread
From: Radhakrishna Sripada @ 2019-10-28 20:40 UTC (permalink / raw)
To: intel-gfx; +Cc: nanley.g.chery, dhinakaran.pandiyan, ville.syrjala
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
addfb() uAPI has supported four planes for a while now, make format_info
compatible with that.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
include/drm/drm_fourcc.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h
index 306d1efeb5e0..156b122c0ad5 100644
--- a/include/drm/drm_fourcc.h
+++ b/include/drm/drm_fourcc.h
@@ -78,7 +78,7 @@ struct drm_format_info {
* triplet @char_per_block, @block_w, @block_h for better
* describing the pixel format.
*/
- u8 cpp[3];
+ u8 cpp[4];
/**
* @char_per_block:
@@ -104,7 +104,7 @@ struct drm_format_info {
* information from their drm_mode_config.get_format_info hook
* if they want the core to be validating the pitch.
*/
- u8 char_per_block[3];
+ u8 char_per_block[4];
};
/**
@@ -113,7 +113,7 @@ struct drm_format_info {
* Block width in pixels, this is intended to be accessed through
* drm_format_info_block_width()
*/
- u8 block_w[3];
+ u8 block_w[4];
/**
* @block_h:
@@ -121,7 +121,7 @@ struct drm_format_info {
* Block height in pixels, this is intended to be accessed through
* drm_format_info_block_height()
*/
- u8 block_h[3];
+ u8 block_h[4];
/** @hsub: Horizontal chroma subsampling factor */
u8 hsub;
--
2.20.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Intel-gfx] [PATCH v6 07/10] drm/fb: Extend format_info member arrays to handle four planes
@ 2019-10-28 20:40 ` Radhakrishna Sripada
0 siblings, 0 replies; 34+ messages in thread
From: Radhakrishna Sripada @ 2019-10-28 20:40 UTC (permalink / raw)
To: intel-gfx; +Cc: nanley.g.chery, dhinakaran.pandiyan, ville.syrjala
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
addfb() uAPI has supported four planes for a while now, make format_info
compatible with that.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
include/drm/drm_fourcc.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h
index 306d1efeb5e0..156b122c0ad5 100644
--- a/include/drm/drm_fourcc.h
+++ b/include/drm/drm_fourcc.h
@@ -78,7 +78,7 @@ struct drm_format_info {
* triplet @char_per_block, @block_w, @block_h for better
* describing the pixel format.
*/
- u8 cpp[3];
+ u8 cpp[4];
/**
* @char_per_block:
@@ -104,7 +104,7 @@ struct drm_format_info {
* information from their drm_mode_config.get_format_info hook
* if they want the core to be validating the pitch.
*/
- u8 char_per_block[3];
+ u8 char_per_block[4];
};
/**
@@ -113,7 +113,7 @@ struct drm_format_info {
* Block width in pixels, this is intended to be accessed through
* drm_format_info_block_width()
*/
- u8 block_w[3];
+ u8 block_w[4];
/**
* @block_h:
@@ -121,7 +121,7 @@ struct drm_format_info {
* Block height in pixels, this is intended to be accessed through
* drm_format_info_block_height()
*/
- u8 block_h[3];
+ u8 block_h[4];
/** @hsub: Horizontal chroma subsampling factor */
u8 hsub;
--
2.20.1
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^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v6 08/10] Gen-12 display can decompress surfaces compressed by the media engine.
@ 2019-10-28 20:40 ` Radhakrishna Sripada
0 siblings, 0 replies; 34+ messages in thread
From: Radhakrishna Sripada @ 2019-10-28 20:40 UTC (permalink / raw)
To: intel-gfx
Cc: nanley.g.chery, Lucas De Marchi, dhinakaran.pandiyan, ville.syrjala
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Detect the modifier corresponding to media compression to enable
display decompression for YUV and xRGB packed formats. A new modifier is
added so that the driver can distinguish between media and render
compressed buffers. Unlike render decompression, plane 6 and plane 7 do not
support media decompression.
v2: Fix checkpatch warnings on code style (Lucas)
From DK:
Separate modifier array for planes that cannot decompress media (Ville)
v3: Support planar formats
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 237 +++++++++++++-----
.../drm/i915/display/intel_display_types.h | 2 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 44 +++-
drivers/gpu/drm/i915/i915_reg.h | 1 +
4 files changed, 220 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0f22ccc6660d..20ad089da6ee 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1936,6 +1936,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
if (color_plane == 1)
return 128;
/* fall through */
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ if (color_plane == 3)
+ return 64;
+ /* fall through */
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
if (color_plane == 1)
return 64;
@@ -2278,8 +2282,16 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
static bool is_surface_linear(u64 modifier, int color_plane)
{
- return modifier == DRM_FORMAT_MOD_LINEAR ||
- (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane == 1);
+ switch (modifier) {
+ case DRM_FORMAT_MOD_LINEAR:
+ return true;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ return color_plane == 1;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ return color_plane == 1 || color_plane == 3;
+ default:
+ return false;
+ }
}
static u32 intel_adjust_aligned_offset(int *x, int *y,
@@ -2467,6 +2479,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return I915_TILING_Y;
default:
return I915_TILING_NONE;
@@ -2514,6 +2527,10 @@ static const struct drm_format_info gen12_ccs_formats[] = {
.cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
.cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+ { .format = DRM_FORMAT_YUYV, .num_planes = 2,
+ .cpp = { 2, 1, }, .hsub = 4, .vsub = 32, .is_yuv = true },
+ { .format = DRM_FORMAT_NV12, .num_planes = 4,
+ .cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
};
static const struct drm_format_info *
@@ -2551,6 +2568,7 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
bool is_ccs_modifier(u64 modifier)
{
return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
@@ -2614,7 +2632,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
}
tile_width = intel_tile_width_bytes(fb, color_plane);
- if (is_ccs_modifier(fb->modifier) && color_plane == 0) {
+ if (is_ccs_modifier(fb->modifier)) {
/*
* Display WA #0531: skl,bxt,kbl,glk
*
@@ -2624,7 +2642,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
* require the entire fb to accommodate that to avoid
* potential runtime errors at plane configuration time.
*/
- if (IS_GEN(dev_priv, 9) && fb->width > 3840)
+ if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840)
tile_width *= 4;
/*
* The main surface pitch must be padded to a multiple of four
@@ -2704,25 +2722,71 @@ static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
return stride > max_stride;
}
+static void
+intel_fb_plane_get_subsampling(int *hsub, int *vsub, const struct drm_framebuffer *fb, int color_plane)
+{
+ if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS) {
+ static const struct {
+ int cpp[4];
+ int vsub[4];
+ int hsub[4];
+ } mc_ccs_subsampling = {.cpp = {1, 1, 2, 1}, .hsub = {1, 8, 2, 16}, .vsub = {1, 32, 2, 32} };
+
+ *hsub = mc_ccs_subsampling.hsub[color_plane];
+ *vsub = mc_ccs_subsampling.vsub[color_plane];
+ } else {
+ *hsub = fb->format->hsub;
+ *vsub = fb->format->vsub;
+ }
+}
+
+static void
+intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane)
+{
+ int hsub, vsub;
+
+ intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
+ *w = fb->width / hsub;
+ *h = fb->height / vsub;
+}
+
+static bool is_ccs_plane(u64 modifier, int color_plane)
+{
+ if (!is_ccs_modifier(modifier))
+ return false;
+ else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
+ return color_plane == 3 || color_plane == 1;
+ else
+ return color_plane == 1;
+}
+
static int
-intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
+intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int color_plane, int x, int y)
{
struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
- int hsub = fb->format->hsub;
- int vsub = fb->format->vsub;
+ int hsub, vsub;
+ int hsub_main, vsub_main;
int tile_width, tile_height;
int ccs_x, ccs_y;
int main_x, main_y;
- intel_tile_dims(fb, 1, &tile_width, &tile_height);
+ if (!is_ccs_plane(fb->modifier, color_plane))
+ return 0;
+
+ intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
+ intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
+ intel_fb_plane_get_subsampling(&hsub_main, &vsub_main, fb, color_plane - 1);
+
+ hsub /= hsub_main;
+ vsub /= vsub_main;
tile_width *= hsub;
tile_height *= vsub;
ccs_x = (x * hsub) % tile_width;
ccs_y = (y * vsub) % tile_height;
- main_x = intel_fb->normal[0].x % tile_width;
- main_y = intel_fb->normal[0].y % tile_height;
+ main_x = intel_fb->normal[color_plane - 1].x % tile_width;
+ main_y = intel_fb->normal[color_plane - 1].y % tile_height;
/*
* CCS doesn't have its own x/y offset register, so the intra CCS tile
@@ -2732,8 +2796,8 @@ intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
main_x, main_y,
ccs_x, ccs_y,
- intel_fb->normal[0].x,
- intel_fb->normal[0].y,
+ intel_fb->normal[color_plane - 1].x,
+ intel_fb->normal[color_plane - 1].y,
x, y);
return -EINVAL;
}
@@ -2761,8 +2825,7 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
int ret;
cpp = fb->format->cpp[i];
- width = drm_framebuffer_plane_width(fb->width, fb, i);
- height = drm_framebuffer_plane_height(fb->height, fb, i);
+ intel_fb_plane_dims(&width, &height, fb, i);
ret = intel_fb_offset_to_xy(&x, &y, fb, i);
if (ret) {
@@ -2771,11 +2834,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
return ret;
}
- if (is_ccs_modifier(fb->modifier) && i == 1) {
- ret = intel_fb_check_ccs_xy(fb, x, y);
- if (ret)
- return ret;
- }
+ ret = intel_fb_check_ccs_xy(fb, i, x, y);
+ if (ret)
+ return ret;
/*
* The fence (if used) is aligned to the start of the object
@@ -3384,6 +3445,7 @@ static int skl_max_plane_width(const struct drm_framebuffer *fb,
return 5120;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
/* FIXME AUX plane? */
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Yf_TILED:
@@ -3443,16 +3505,18 @@ static int icl_max_plane_height(void)
}
static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
- int main_x, int main_y, u32 main_offset)
+ int main_x, int main_y, u32 main_offset,
+ int aux_plane)
{
const struct drm_framebuffer *fb = plane_state->base.fb;
- int hsub = fb->format->hsub;
- int vsub = fb->format->vsub;
- int aux_x = plane_state->color_plane[1].x;
- int aux_y = plane_state->color_plane[1].y;
- u32 aux_offset = plane_state->color_plane[1].offset;
- u32 alignment = intel_surf_alignment(fb, 1);
-
+ int hsub;
+ int vsub;
+ int aux_x = plane_state->color_plane[aux_plane].x;
+ int aux_y = plane_state->color_plane[aux_plane].y;
+ u32 aux_offset = plane_state->color_plane[aux_plane].offset;
+ u32 alignment = intel_surf_alignment(fb, aux_plane);
+
+ intel_fb_plane_get_subsampling(&hsub, &vsub, fb, aux_plane);
while (aux_offset >= main_offset && aux_y <= main_y) {
int x, y;
@@ -3464,7 +3528,7 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
x = aux_x / hsub;
y = aux_y / vsub;
- aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
+ aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, aux_plane,
aux_offset, aux_offset - alignment);
aux_x = x * hsub + aux_x % hsub;
aux_y = y * vsub + aux_y % vsub;
@@ -3473,9 +3537,9 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
if (aux_x != main_x || aux_y != main_y)
return false;
- plane_state->color_plane[1].offset = aux_offset;
- plane_state->color_plane[1].x = aux_x;
- plane_state->color_plane[1].y = aux_y;
+ plane_state->color_plane[aux_plane].offset = aux_offset;
+ plane_state->color_plane[aux_plane].x = aux_x;
+ plane_state->color_plane[aux_plane].y = aux_y;
return true;
}
@@ -3549,7 +3613,7 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
* they match with the main surface x/y offsets.
*/
if (is_ccs_modifier(fb->modifier)) {
- while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
+ while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset, 1)) {
if (offset == 0)
break;
@@ -3581,7 +3645,8 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
{
const struct drm_framebuffer *fb = plane_state->base.fb;
unsigned int rotation = plane_state->base.rotation;
- int max_width = skl_max_plane_width(fb, 1, rotation);
+ int uv = is_ccs_modifier(fb->modifier) ? 2 : 1;
+ int max_width = skl_max_plane_width(fb, uv, rotation);
int max_height = 4096;
int x = plane_state->base.src.x1 >> 17;
int y = plane_state->base.src.y1 >> 17;
@@ -3589,8 +3654,8 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
int h = drm_rect_height(&plane_state->base.src) >> 17;
u32 offset;
- intel_add_fb_offsets(&x, &y, plane_state, 1);
- offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
+ intel_add_fb_offsets(&x, &y, plane_state, uv);
+ offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, uv);
/* FIXME not quite sure how/if these apply to the chroma plane */
if (w > max_width || h > max_height) {
@@ -3599,9 +3664,41 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
return -EINVAL;
}
- plane_state->color_plane[1].offset = offset;
- plane_state->color_plane[1].x = x;
- plane_state->color_plane[1].y = y;
+ if (is_ccs_modifier(fb->modifier)) {
+ int aux_offset = plane_state->color_plane[3].offset;
+ int alignment = intel_surf_alignment(fb, uv);
+
+ if (offset > aux_offset) {
+ int hsub, vsub;
+ int main_x = x, main_y = y;
+
+ intel_fb_plane_get_subsampling(&hsub, &vsub, fb, uv);
+ x = main_x / hsub;
+ y = main_y / vsub;
+ offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, uv,
+ offset,
+ aux_offset & ~(alignment - 1));
+ x = x * hsub + main_x % hsub;
+ y = y * vsub + main_y % vsub;
+ }
+
+ while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset, 3)) {
+ if (offset == 0)
+ break;
+
+ offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, uv,
+ offset, offset - alignment);
+ }
+
+ if (x != plane_state->color_plane[3].x || y != plane_state->color_plane[3].y) {
+ DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
+ return -EINVAL;
+ }
+ }
+
+ plane_state->color_plane[uv].offset = offset;
+ plane_state->color_plane[uv].x = x;
+ plane_state->color_plane[uv].y = y;
return 0;
}
@@ -3611,19 +3708,30 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
const struct drm_framebuffer *fb = plane_state->base.fb;
int src_x = plane_state->base.src.x1 >> 16;
int src_y = plane_state->base.src.y1 >> 16;
- int hsub = fb->format->hsub;
- int vsub = fb->format->vsub;
- int x = src_x / hsub;
- int y = src_y / vsub;
u32 offset;
+ int ccs;
- intel_add_fb_offsets(&x, &y, plane_state, 1);
- offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
- plane_state->color_plane[1].offset = offset;
- plane_state->color_plane[1].x = x * hsub + src_x % hsub;
- plane_state->color_plane[1].y = y * vsub + src_y % vsub;
+ for (ccs = 1; ccs < fb->format->num_planes; ccs += 2) {
+ int hsub, vsub;
+ int main_hsub, main_vsub;
+ int x, y;
+
+ intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs);
+ intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, ccs - 1);
+ hsub /= main_hsub;
+ vsub /= main_vsub;
+ x = src_x / hsub;
+ y = src_y / vsub;
+
+ intel_add_fb_offsets(&x, &y, plane_state, ccs);
+ offset = intel_plane_compute_aligned_offset(&x, &y,
+ plane_state, ccs);
+ plane_state->color_plane[ccs].offset = offset;
+ plane_state->color_plane[ccs].x = x * hsub + src_x % hsub;
+ plane_state->color_plane[ccs].y = y * vsub + src_y % vsub;
+ }
return 0;
}
@@ -3631,6 +3739,7 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
{
const struct drm_framebuffer *fb = plane_state->base.fb;
int ret;
+ bool needs_aux = false;
ret = intel_plane_compute_gtt(plane_state);
if (ret)
@@ -3640,21 +3749,31 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
return 0;
/*
- * Handle the AUX surface first since
- * the main surface setup depends on it.
+ * Handle the AUX surface first since the main surface setup depends on
+ * it.
*/
- if (drm_format_info_is_yuv_semiplanar(fb->format)) {
- ret = skl_check_nv12_aux_surface(plane_state);
+ if (is_ccs_modifier(fb->modifier)) {
+ needs_aux = true;
+ ret = skl_check_ccs_aux_surface(plane_state);
if (ret)
return ret;
- } else if (is_ccs_modifier(fb->modifier)) {
- ret = skl_check_ccs_aux_surface(plane_state);
+ }
+
+ if (drm_format_info_is_yuv_semiplanar(fb->format)) {
+ needs_aux = true;
+ ret = skl_check_nv12_aux_surface(plane_state);
if (ret)
return ret;
- } else {
- plane_state->color_plane[1].offset = ~0xfff;
- plane_state->color_plane[1].x = 0;
- plane_state->color_plane[1].y = 0;
+ }
+
+ if (!needs_aux) {
+ int i;
+
+ for (i = 1; i < fb->format->num_planes; i++) {
+ plane_state->color_plane[i].offset = ~0xfff;
+ plane_state->color_plane[i].x = 0;
+ plane_state->color_plane[i].y = 0;
+ }
}
ret = skl_check_main_surface(plane_state);
@@ -4227,6 +4346,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
return PLANE_CTL_TILED_Y |
PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
PLANE_CTL_CLEAR_COLOR_DISABLE;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
case I915_FORMAT_MOD_Yf_TILED:
return PLANE_CTL_TILED_YF;
case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -10056,6 +10177,8 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
I915_FORMAT_MOD_Y_TILED_CCS;
+ else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
+ fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
else
fb->modifier = I915_FORMAT_MOD_Y_TILED;
break;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 40184e823c84..e98f212682f6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -538,7 +538,7 @@ struct intel_plane_state {
*/
u32 stride;
int x, y;
- } color_plane[2];
+ } color_plane[4];
/* plane control register */
u32 ctl;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index b6494643183d..a5018fffa8f2 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2114,7 +2114,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
- fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
return -EINVAL;
}
@@ -2550,7 +2551,16 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
DRM_FORMAT_MOD_INVALID
};
-static const u64 gen12_plane_format_modifiers_ccs[] = {
+static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
+ I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+ I915_FORMAT_MOD_Y_TILED,
+ I915_FORMAT_MOD_X_TILED,
+ DRM_FORMAT_MOD_LINEAR,
+ DRM_FORMAT_MOD_INVALID
+};
+
+static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_X_TILED,
@@ -2708,10 +2718,21 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
}
}
+static bool gen12_plane_supports_mc_ccs(enum plane_id plane_id)
+{
+ return plane_id < PLANE_SPRITE4;
+}
+
static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier)
{
+ struct intel_plane *plane = to_intel_plane(_plane);
+
switch (modifier) {
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ if (!gen12_plane_supports_mc_ccs(plane->id))
+ return false;
+ /* fall through */
case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
@@ -2729,14 +2750,17 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
if (is_ccs_modifier(modifier))
return true;
/* fall through */
- case DRM_FORMAT_RGB565:
- case DRM_FORMAT_XRGB2101010:
- case DRM_FORMAT_XBGR2101010:
case DRM_FORMAT_YUYV:
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
+ if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
+ return true;
+ /* fall through */
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_XRGB2101010:
+ case DRM_FORMAT_XBGR2101010:
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
@@ -2873,6 +2897,14 @@ static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv,
}
}
+static const u64 *gen12_get_plane_modifiers(enum plane_id plane_id)
+{
+ if (gen12_plane_supports_mc_ccs(plane_id))
+ return gen12_plane_format_modifiers_mc_ccs;
+ else
+ return gen12_plane_format_modifiers_rc_ccs;
+}
+
static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
enum pipe pipe, enum plane_id plane_id)
{
@@ -2940,7 +2972,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
if (INTEL_GEN(dev_priv) >= 12) {
- modifiers = gen12_plane_format_modifiers_ccs;
+ modifiers = gen12_get_plane_modifiers(plane_id);
plane_funcs = &gen12_plane_funcs;
} else {
if (plane->has_ccs)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 49fe4f0df24f..75cccd498b42 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6720,6 +6720,7 @@ enum {
#define PLANE_CTL_TILED_Y (4 << 10)
#define PLANE_CTL_TILED_YF (5 << 10)
#define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
+#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
#define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
#define PLANE_CTL_ALPHA_DISABLE (0 << 4)
#define PLANE_CTL_ALPHA_SW_PREMULTIPLY (2 << 4)
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Intel-gfx] [PATCH v6 08/10] Gen-12 display can decompress surfaces compressed by the media engine.
@ 2019-10-28 20:40 ` Radhakrishna Sripada
0 siblings, 0 replies; 34+ messages in thread
From: Radhakrishna Sripada @ 2019-10-28 20:40 UTC (permalink / raw)
To: intel-gfx
Cc: nanley.g.chery, Lucas De Marchi, dhinakaran.pandiyan, ville.syrjala
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Detect the modifier corresponding to media compression to enable
display decompression for YUV and xRGB packed formats. A new modifier is
added so that the driver can distinguish between media and render
compressed buffers. Unlike render decompression, plane 6 and plane 7 do not
support media decompression.
v2: Fix checkpatch warnings on code style (Lucas)
From DK:
Separate modifier array for planes that cannot decompress media (Ville)
v3: Support planar formats
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 237 +++++++++++++-----
.../drm/i915/display/intel_display_types.h | 2 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 44 +++-
drivers/gpu/drm/i915/i915_reg.h | 1 +
4 files changed, 220 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0f22ccc6660d..20ad089da6ee 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1936,6 +1936,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
if (color_plane == 1)
return 128;
/* fall through */
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ if (color_plane == 3)
+ return 64;
+ /* fall through */
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
if (color_plane == 1)
return 64;
@@ -2278,8 +2282,16 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
static bool is_surface_linear(u64 modifier, int color_plane)
{
- return modifier == DRM_FORMAT_MOD_LINEAR ||
- (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane == 1);
+ switch (modifier) {
+ case DRM_FORMAT_MOD_LINEAR:
+ return true;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ return color_plane == 1;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ return color_plane == 1 || color_plane == 3;
+ default:
+ return false;
+ }
}
static u32 intel_adjust_aligned_offset(int *x, int *y,
@@ -2467,6 +2479,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return I915_TILING_Y;
default:
return I915_TILING_NONE;
@@ -2514,6 +2527,10 @@ static const struct drm_format_info gen12_ccs_formats[] = {
.cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
.cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+ { .format = DRM_FORMAT_YUYV, .num_planes = 2,
+ .cpp = { 2, 1, }, .hsub = 4, .vsub = 32, .is_yuv = true },
+ { .format = DRM_FORMAT_NV12, .num_planes = 4,
+ .cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
};
static const struct drm_format_info *
@@ -2551,6 +2568,7 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
bool is_ccs_modifier(u64 modifier)
{
return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
@@ -2614,7 +2632,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
}
tile_width = intel_tile_width_bytes(fb, color_plane);
- if (is_ccs_modifier(fb->modifier) && color_plane == 0) {
+ if (is_ccs_modifier(fb->modifier)) {
/*
* Display WA #0531: skl,bxt,kbl,glk
*
@@ -2624,7 +2642,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
* require the entire fb to accommodate that to avoid
* potential runtime errors at plane configuration time.
*/
- if (IS_GEN(dev_priv, 9) && fb->width > 3840)
+ if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840)
tile_width *= 4;
/*
* The main surface pitch must be padded to a multiple of four
@@ -2704,25 +2722,71 @@ static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
return stride > max_stride;
}
+static void
+intel_fb_plane_get_subsampling(int *hsub, int *vsub, const struct drm_framebuffer *fb, int color_plane)
+{
+ if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS) {
+ static const struct {
+ int cpp[4];
+ int vsub[4];
+ int hsub[4];
+ } mc_ccs_subsampling = {.cpp = {1, 1, 2, 1}, .hsub = {1, 8, 2, 16}, .vsub = {1, 32, 2, 32} };
+
+ *hsub = mc_ccs_subsampling.hsub[color_plane];
+ *vsub = mc_ccs_subsampling.vsub[color_plane];
+ } else {
+ *hsub = fb->format->hsub;
+ *vsub = fb->format->vsub;
+ }
+}
+
+static void
+intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane)
+{
+ int hsub, vsub;
+
+ intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
+ *w = fb->width / hsub;
+ *h = fb->height / vsub;
+}
+
+static bool is_ccs_plane(u64 modifier, int color_plane)
+{
+ if (!is_ccs_modifier(modifier))
+ return false;
+ else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
+ return color_plane == 3 || color_plane == 1;
+ else
+ return color_plane == 1;
+}
+
static int
-intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
+intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int color_plane, int x, int y)
{
struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
- int hsub = fb->format->hsub;
- int vsub = fb->format->vsub;
+ int hsub, vsub;
+ int hsub_main, vsub_main;
int tile_width, tile_height;
int ccs_x, ccs_y;
int main_x, main_y;
- intel_tile_dims(fb, 1, &tile_width, &tile_height);
+ if (!is_ccs_plane(fb->modifier, color_plane))
+ return 0;
+
+ intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
+ intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
+ intel_fb_plane_get_subsampling(&hsub_main, &vsub_main, fb, color_plane - 1);
+
+ hsub /= hsub_main;
+ vsub /= vsub_main;
tile_width *= hsub;
tile_height *= vsub;
ccs_x = (x * hsub) % tile_width;
ccs_y = (y * vsub) % tile_height;
- main_x = intel_fb->normal[0].x % tile_width;
- main_y = intel_fb->normal[0].y % tile_height;
+ main_x = intel_fb->normal[color_plane - 1].x % tile_width;
+ main_y = intel_fb->normal[color_plane - 1].y % tile_height;
/*
* CCS doesn't have its own x/y offset register, so the intra CCS tile
@@ -2732,8 +2796,8 @@ intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
main_x, main_y,
ccs_x, ccs_y,
- intel_fb->normal[0].x,
- intel_fb->normal[0].y,
+ intel_fb->normal[color_plane - 1].x,
+ intel_fb->normal[color_plane - 1].y,
x, y);
return -EINVAL;
}
@@ -2761,8 +2825,7 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
int ret;
cpp = fb->format->cpp[i];
- width = drm_framebuffer_plane_width(fb->width, fb, i);
- height = drm_framebuffer_plane_height(fb->height, fb, i);
+ intel_fb_plane_dims(&width, &height, fb, i);
ret = intel_fb_offset_to_xy(&x, &y, fb, i);
if (ret) {
@@ -2771,11 +2834,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
return ret;
}
- if (is_ccs_modifier(fb->modifier) && i == 1) {
- ret = intel_fb_check_ccs_xy(fb, x, y);
- if (ret)
- return ret;
- }
+ ret = intel_fb_check_ccs_xy(fb, i, x, y);
+ if (ret)
+ return ret;
/*
* The fence (if used) is aligned to the start of the object
@@ -3384,6 +3445,7 @@ static int skl_max_plane_width(const struct drm_framebuffer *fb,
return 5120;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
/* FIXME AUX plane? */
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Yf_TILED:
@@ -3443,16 +3505,18 @@ static int icl_max_plane_height(void)
}
static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
- int main_x, int main_y, u32 main_offset)
+ int main_x, int main_y, u32 main_offset,
+ int aux_plane)
{
const struct drm_framebuffer *fb = plane_state->base.fb;
- int hsub = fb->format->hsub;
- int vsub = fb->format->vsub;
- int aux_x = plane_state->color_plane[1].x;
- int aux_y = plane_state->color_plane[1].y;
- u32 aux_offset = plane_state->color_plane[1].offset;
- u32 alignment = intel_surf_alignment(fb, 1);
-
+ int hsub;
+ int vsub;
+ int aux_x = plane_state->color_plane[aux_plane].x;
+ int aux_y = plane_state->color_plane[aux_plane].y;
+ u32 aux_offset = plane_state->color_plane[aux_plane].offset;
+ u32 alignment = intel_surf_alignment(fb, aux_plane);
+
+ intel_fb_plane_get_subsampling(&hsub, &vsub, fb, aux_plane);
while (aux_offset >= main_offset && aux_y <= main_y) {
int x, y;
@@ -3464,7 +3528,7 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
x = aux_x / hsub;
y = aux_y / vsub;
- aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
+ aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, aux_plane,
aux_offset, aux_offset - alignment);
aux_x = x * hsub + aux_x % hsub;
aux_y = y * vsub + aux_y % vsub;
@@ -3473,9 +3537,9 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
if (aux_x != main_x || aux_y != main_y)
return false;
- plane_state->color_plane[1].offset = aux_offset;
- plane_state->color_plane[1].x = aux_x;
- plane_state->color_plane[1].y = aux_y;
+ plane_state->color_plane[aux_plane].offset = aux_offset;
+ plane_state->color_plane[aux_plane].x = aux_x;
+ plane_state->color_plane[aux_plane].y = aux_y;
return true;
}
@@ -3549,7 +3613,7 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
* they match with the main surface x/y offsets.
*/
if (is_ccs_modifier(fb->modifier)) {
- while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
+ while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset, 1)) {
if (offset == 0)
break;
@@ -3581,7 +3645,8 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
{
const struct drm_framebuffer *fb = plane_state->base.fb;
unsigned int rotation = plane_state->base.rotation;
- int max_width = skl_max_plane_width(fb, 1, rotation);
+ int uv = is_ccs_modifier(fb->modifier) ? 2 : 1;
+ int max_width = skl_max_plane_width(fb, uv, rotation);
int max_height = 4096;
int x = plane_state->base.src.x1 >> 17;
int y = plane_state->base.src.y1 >> 17;
@@ -3589,8 +3654,8 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
int h = drm_rect_height(&plane_state->base.src) >> 17;
u32 offset;
- intel_add_fb_offsets(&x, &y, plane_state, 1);
- offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
+ intel_add_fb_offsets(&x, &y, plane_state, uv);
+ offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, uv);
/* FIXME not quite sure how/if these apply to the chroma plane */
if (w > max_width || h > max_height) {
@@ -3599,9 +3664,41 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
return -EINVAL;
}
- plane_state->color_plane[1].offset = offset;
- plane_state->color_plane[1].x = x;
- plane_state->color_plane[1].y = y;
+ if (is_ccs_modifier(fb->modifier)) {
+ int aux_offset = plane_state->color_plane[3].offset;
+ int alignment = intel_surf_alignment(fb, uv);
+
+ if (offset > aux_offset) {
+ int hsub, vsub;
+ int main_x = x, main_y = y;
+
+ intel_fb_plane_get_subsampling(&hsub, &vsub, fb, uv);
+ x = main_x / hsub;
+ y = main_y / vsub;
+ offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, uv,
+ offset,
+ aux_offset & ~(alignment - 1));
+ x = x * hsub + main_x % hsub;
+ y = y * vsub + main_y % vsub;
+ }
+
+ while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset, 3)) {
+ if (offset == 0)
+ break;
+
+ offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, uv,
+ offset, offset - alignment);
+ }
+
+ if (x != plane_state->color_plane[3].x || y != plane_state->color_plane[3].y) {
+ DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
+ return -EINVAL;
+ }
+ }
+
+ plane_state->color_plane[uv].offset = offset;
+ plane_state->color_plane[uv].x = x;
+ plane_state->color_plane[uv].y = y;
return 0;
}
@@ -3611,19 +3708,30 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
const struct drm_framebuffer *fb = plane_state->base.fb;
int src_x = plane_state->base.src.x1 >> 16;
int src_y = plane_state->base.src.y1 >> 16;
- int hsub = fb->format->hsub;
- int vsub = fb->format->vsub;
- int x = src_x / hsub;
- int y = src_y / vsub;
u32 offset;
+ int ccs;
- intel_add_fb_offsets(&x, &y, plane_state, 1);
- offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
- plane_state->color_plane[1].offset = offset;
- plane_state->color_plane[1].x = x * hsub + src_x % hsub;
- plane_state->color_plane[1].y = y * vsub + src_y % vsub;
+ for (ccs = 1; ccs < fb->format->num_planes; ccs += 2) {
+ int hsub, vsub;
+ int main_hsub, main_vsub;
+ int x, y;
+
+ intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs);
+ intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, ccs - 1);
+ hsub /= main_hsub;
+ vsub /= main_vsub;
+ x = src_x / hsub;
+ y = src_y / vsub;
+
+ intel_add_fb_offsets(&x, &y, plane_state, ccs);
+ offset = intel_plane_compute_aligned_offset(&x, &y,
+ plane_state, ccs);
+ plane_state->color_plane[ccs].offset = offset;
+ plane_state->color_plane[ccs].x = x * hsub + src_x % hsub;
+ plane_state->color_plane[ccs].y = y * vsub + src_y % vsub;
+ }
return 0;
}
@@ -3631,6 +3739,7 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
{
const struct drm_framebuffer *fb = plane_state->base.fb;
int ret;
+ bool needs_aux = false;
ret = intel_plane_compute_gtt(plane_state);
if (ret)
@@ -3640,21 +3749,31 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
return 0;
/*
- * Handle the AUX surface first since
- * the main surface setup depends on it.
+ * Handle the AUX surface first since the main surface setup depends on
+ * it.
*/
- if (drm_format_info_is_yuv_semiplanar(fb->format)) {
- ret = skl_check_nv12_aux_surface(plane_state);
+ if (is_ccs_modifier(fb->modifier)) {
+ needs_aux = true;
+ ret = skl_check_ccs_aux_surface(plane_state);
if (ret)
return ret;
- } else if (is_ccs_modifier(fb->modifier)) {
- ret = skl_check_ccs_aux_surface(plane_state);
+ }
+
+ if (drm_format_info_is_yuv_semiplanar(fb->format)) {
+ needs_aux = true;
+ ret = skl_check_nv12_aux_surface(plane_state);
if (ret)
return ret;
- } else {
- plane_state->color_plane[1].offset = ~0xfff;
- plane_state->color_plane[1].x = 0;
- plane_state->color_plane[1].y = 0;
+ }
+
+ if (!needs_aux) {
+ int i;
+
+ for (i = 1; i < fb->format->num_planes; i++) {
+ plane_state->color_plane[i].offset = ~0xfff;
+ plane_state->color_plane[i].x = 0;
+ plane_state->color_plane[i].y = 0;
+ }
}
ret = skl_check_main_surface(plane_state);
@@ -4227,6 +4346,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
return PLANE_CTL_TILED_Y |
PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
PLANE_CTL_CLEAR_COLOR_DISABLE;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
case I915_FORMAT_MOD_Yf_TILED:
return PLANE_CTL_TILED_YF;
case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -10056,6 +10177,8 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
I915_FORMAT_MOD_Y_TILED_CCS;
+ else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
+ fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
else
fb->modifier = I915_FORMAT_MOD_Y_TILED;
break;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 40184e823c84..e98f212682f6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -538,7 +538,7 @@ struct intel_plane_state {
*/
u32 stride;
int x, y;
- } color_plane[2];
+ } color_plane[4];
/* plane control register */
u32 ctl;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index b6494643183d..a5018fffa8f2 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2114,7 +2114,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
- fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
return -EINVAL;
}
@@ -2550,7 +2551,16 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
DRM_FORMAT_MOD_INVALID
};
-static const u64 gen12_plane_format_modifiers_ccs[] = {
+static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
+ I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+ I915_FORMAT_MOD_Y_TILED,
+ I915_FORMAT_MOD_X_TILED,
+ DRM_FORMAT_MOD_LINEAR,
+ DRM_FORMAT_MOD_INVALID
+};
+
+static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_X_TILED,
@@ -2708,10 +2718,21 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
}
}
+static bool gen12_plane_supports_mc_ccs(enum plane_id plane_id)
+{
+ return plane_id < PLANE_SPRITE4;
+}
+
static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier)
{
+ struct intel_plane *plane = to_intel_plane(_plane);
+
switch (modifier) {
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ if (!gen12_plane_supports_mc_ccs(plane->id))
+ return false;
+ /* fall through */
case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
@@ -2729,14 +2750,17 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
if (is_ccs_modifier(modifier))
return true;
/* fall through */
- case DRM_FORMAT_RGB565:
- case DRM_FORMAT_XRGB2101010:
- case DRM_FORMAT_XBGR2101010:
case DRM_FORMAT_YUYV:
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
+ if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
+ return true;
+ /* fall through */
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_XRGB2101010:
+ case DRM_FORMAT_XBGR2101010:
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
@@ -2873,6 +2897,14 @@ static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv,
}
}
+static const u64 *gen12_get_plane_modifiers(enum plane_id plane_id)
+{
+ if (gen12_plane_supports_mc_ccs(plane_id))
+ return gen12_plane_format_modifiers_mc_ccs;
+ else
+ return gen12_plane_format_modifiers_rc_ccs;
+}
+
static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
enum pipe pipe, enum plane_id plane_id)
{
@@ -2940,7 +2972,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
if (INTEL_GEN(dev_priv) >= 12) {
- modifiers = gen12_plane_format_modifiers_ccs;
+ modifiers = gen12_get_plane_modifiers(plane_id);
plane_funcs = &gen12_plane_funcs;
} else {
if (plane->has_ccs)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 49fe4f0df24f..75cccd498b42 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6720,6 +6720,7 @@ enum {
#define PLANE_CTL_TILED_Y (4 << 10)
#define PLANE_CTL_TILED_YF (5 << 10)
#define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
+#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
#define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
#define PLANE_CTL_ALPHA_DISABLE (0 << 4)
#define PLANE_CTL_ALPHA_SW_PREMULTIPLY (2 << 4)
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
@ 2019-10-28 20:40 ` Radhakrishna Sripada
0 siblings, 0 replies; 34+ messages in thread
From: Radhakrishna Sripada @ 2019-10-28 20:40 UTC (permalink / raw)
To: intel-gfx
Cc: nanley.g.chery, dhinakaran.pandiyan, Kalyan Kondapally, ville.syrjala
Gen12 display can decompress surfaces compressed by render engine with
Clear Color, add a new modifier as the driver needs to know the surface
was compressed by render engine.
V2: Description changes as suggested by Rafael.
V3: Mention the Clear Color size of 64 bits in the comments(DK)
v4: Fix trailing whitespaces
v5: Explain Clear Color in the documentation.
v6: Documentation Nitpicks(Nanley)
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 1aa6d468c048..4aa7f3f9712a 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -434,6 +434,25 @@ extern "C" {
*/
#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
+/*
+ * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
+ * compression.
+ *
+ * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
+ * and at index 1. The clear color is stored at index 2, and the pitch should
+ * be ignored. The clear color structure is 256 bits. The first 128 bits
+ * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
+ * by 32 bits. The raw clear color is consumed by the 3d engine and generates
+ * the converted clear color of size 64 bits. The first 32 bits store the Lower
+ * Converted Clear Color value and the next 32 bits store the Higher Converted
+ * Clear Color value when applicable. The Converted Clear Color values are
+ * consumed by the DE. The last 64 bits are used to store Color Discard Enable
+ * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
+ * corresponds to an area of 4x1 tiles in the main surface. The main surface
+ * pitch is required to be a multiple of 4 tile widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
--
2.20.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Intel-gfx] [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
@ 2019-10-28 20:40 ` Radhakrishna Sripada
0 siblings, 0 replies; 34+ messages in thread
From: Radhakrishna Sripada @ 2019-10-28 20:40 UTC (permalink / raw)
To: intel-gfx
Cc: nanley.g.chery, dhinakaran.pandiyan, Kalyan Kondapally, ville.syrjala
Gen12 display can decompress surfaces compressed by render engine with
Clear Color, add a new modifier as the driver needs to know the surface
was compressed by render engine.
V2: Description changes as suggested by Rafael.
V3: Mention the Clear Color size of 64 bits in the comments(DK)
v4: Fix trailing whitespaces
v5: Explain Clear Color in the documentation.
v6: Documentation Nitpicks(Nanley)
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 1aa6d468c048..4aa7f3f9712a 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -434,6 +434,25 @@ extern "C" {
*/
#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
+/*
+ * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
+ * compression.
+ *
+ * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
+ * and at index 1. The clear color is stored at index 2, and the pitch should
+ * be ignored. The clear color structure is 256 bits. The first 128 bits
+ * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
+ * by 32 bits. The raw clear color is consumed by the 3d engine and generates
+ * the converted clear color of size 64 bits. The first 32 bits store the Lower
+ * Converted Clear Color value and the next 32 bits store the Higher Converted
+ * Clear Color value when applicable. The Converted Clear Color values are
+ * consumed by the DE. The last 64 bits are used to store Color Discard Enable
+ * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
+ * corresponds to an area of 4x1 tiles in the main surface. The main surface
+ * pitch is required to be a multiple of 4 tile widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v6 10/10] drm/i915/tgl: Add Clear Color support for TGL Render Decompression
@ 2019-10-28 20:40 ` Radhakrishna Sripada
0 siblings, 0 replies; 34+ messages in thread
From: Radhakrishna Sripada @ 2019-10-28 20:40 UTC (permalink / raw)
To: intel-gfx; +Cc: nanley.g.chery, dhinakaran.pandiyan, ville.syrjala
Render Decompression is supported with Y-Tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Additional Clear Color information is passed from the
user-space through an offset in the GEM BO. Add a new modifier to identify
and parse new Clear Color information and extend Gen12 render decompression
functionality to the newly added modifier.
v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
plane config(Matt). Fix Lookup error.
v3: Fix the panic while running kms_cube
v4: Add alignment check and reuse the comments for ge12_ccs_formats(Matt)
v5: Fix typos and wrap comments(Matt)
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Ville Syrjala <ville.syrjala@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 52 +++++++++++++++++++
.../drm/i915/display/intel_display_types.h | 3 ++
drivers/gpu/drm/i915/display/intel_sprite.c | 11 +++-
drivers/gpu/drm/i915/i915_reg.h | 12 +++++
4 files changed, 77 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 20ad089da6ee..6d6eab8d4776 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1944,6 +1944,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
if (color_plane == 1)
return 64;
/* fall through */
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ if (color_plane == 1 || color_plane == 2)
+ return 64;
+ /* fall through */
case I915_FORMAT_MOD_Y_TILED:
if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
return 128;
@@ -2085,6 +2089,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
return 256 * 1024;
return 0;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return 16 * 1024;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -2287,6 +2292,8 @@ static bool is_surface_linear(u64 modifier, int color_plane)
return true;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return color_plane == 1;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ return color_plane == 1 || color_plane == 2;
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return color_plane == 1 || color_plane == 3;
default:
@@ -2480,6 +2487,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return I915_TILING_Y;
default:
return I915_TILING_NONE;
@@ -2533,6 +2541,21 @@ static const struct drm_format_info gen12_ccs_formats[] = {
.cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
};
+/*
+ * Same as gen12_ccs_formats[] above, but with additional surface used
+ * to pass Clear Color information in plane 2 with 64 bits of data.
+ */
+static const struct drm_format_info gen12_ccs_cc_formats[] = {
+ { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+ { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+};
+
static const struct drm_format_info *
lookup_format_info(const struct drm_format_info formats[],
int num_formats, u32 format)
@@ -2560,6 +2583,10 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
return lookup_format_info(gen12_ccs_formats,
ARRAY_SIZE(gen12_ccs_formats),
cmd->pixel_format);
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ return lookup_format_info(gen12_ccs_cc_formats,
+ ARRAY_SIZE(gen12_ccs_cc_formats),
+ cmd->pixel_format);
default:
return NULL;
}
@@ -2569,6 +2596,7 @@ bool is_ccs_modifier(u64 modifier)
{
return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
@@ -2756,6 +2784,8 @@ static bool is_ccs_plane(u64 modifier, int color_plane)
return false;
else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
return color_plane == 3 || color_plane == 1;
+ else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+ return color_plane == 1 || color_plane == 2;
else
return color_plane == 1;
}
@@ -2824,6 +2854,18 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
int x, y;
int ret;
+ /*
+ * Plane 2 of Render Compression with Clear Color fb modifier
+ * is consumed by the driver and not passed to DE. Skip the
+ * arithmetic related to alignment and offset calculation.
+ */
+ if (i == 2 && fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
+ if (IS_ALIGNED(fb->offsets[2], PAGE_SIZE))
+ continue;
+ else
+ return -EINVAL;
+ }
+
cpp = fb->format->cpp[i];
intel_fb_plane_dims(&width, &height, fb, i);
@@ -4341,6 +4383,7 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
case I915_FORMAT_MOD_Y_TILED:
return PLANE_CTL_TILED_Y;
case I915_FORMAT_MOD_Y_TILED_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return PLANE_CTL_TILED_Y |
@@ -15212,6 +15255,15 @@ static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
plane_state->vma = vma;
+ if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
+ u32 *ccaddr = kmap_atomic(i915_gem_object_get_page(intel_fb_obj(fb),
+ fb->offsets[2] >> PAGE_SHIFT));
+
+ plane_state->ccval = ((u64)*(ccaddr + CC_VAL_HIGHER_OFFSET) << 32)
+ | *(ccaddr + CC_VAL_LOWER_OFFSET);
+ kunmap_atomic(ccaddr);
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e98f212682f6..9e147bba092e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -587,6 +587,9 @@ struct intel_plane_state {
u32 planar_slave;
struct drm_intel_sprite_colorkey ckey;
+
+ /* Clear Color Value */
+ u64 ccval;
};
struct intel_initial_plane_config {
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index a5018fffa8f2..f8d2985e6c01 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -596,6 +596,7 @@ skl_program_plane(struct intel_plane *plane,
u32 plane_color_ctl = 0;
unsigned long irqflags;
u32 keymsk, keymax;
+ u64 ccval = plane_state->ccval;
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
@@ -656,6 +657,10 @@ skl_program_plane(struct intel_plane *plane,
if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
icl_program_input_csc(plane, crtc_state, plane_state);
+ if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+ intel_uncore_write64_fw(&dev_priv->uncore,
+ PLANE_CC_VAL(pipe, plane_id), ccval);
+
skl_write_plane_wm(plane, crtc_state);
I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
@@ -2115,7 +2120,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
- fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
return -EINVAL;
}
@@ -2554,6 +2560,7 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_LINEAR,
@@ -2562,6 +2569,7 @@ static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_LINEAR,
@@ -2737,6 +2745,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
break;
default:
return false;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 75cccd498b42..8a24707ea697 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6753,6 +6753,8 @@ enum {
#define _PLANE_KEYMAX_1_A 0x701a0
#define _PLANE_KEYMAX_2_A 0x702a0
#define PLANE_KEYMAX_ALPHA(a) ((a) << 24)
+#define _PLANE_CC_VAL_1_A 0x701b4
+#define _PLANE_CC_VAL_2_A 0x702b4
#define _PLANE_AUX_DIST_1_A 0x701c0
#define _PLANE_AUX_DIST_2_A 0x702c0
#define _PLANE_AUX_OFFSET_1_A 0x701c4
@@ -6792,6 +6794,16 @@ enum {
#define _PLANE_NV12_BUF_CFG_1_A 0x70278
#define _PLANE_NV12_BUF_CFG_2_A 0x70378
+#define _PLANE_CC_VAL_1_B 0x711b4
+#define _PLANE_CC_VAL_2_B 0x712b4
+#define _PLANE_CC_VAL_1(pipe) _PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B)
+#define _PLANE_CC_VAL_2(pipe) _PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B)
+#define PLANE_CC_VAL(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
+
+#define CC_VAL_LOWER_OFFSET 4
+#define CC_VAL_HIGHER_OFFSET 5
+
/* Input CSC Register Definitions */
#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
--
2.20.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Intel-gfx] [PATCH v6 10/10] drm/i915/tgl: Add Clear Color support for TGL Render Decompression
@ 2019-10-28 20:40 ` Radhakrishna Sripada
0 siblings, 0 replies; 34+ messages in thread
From: Radhakrishna Sripada @ 2019-10-28 20:40 UTC (permalink / raw)
To: intel-gfx; +Cc: nanley.g.chery, dhinakaran.pandiyan, ville.syrjala
Render Decompression is supported with Y-Tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Additional Clear Color information is passed from the
user-space through an offset in the GEM BO. Add a new modifier to identify
and parse new Clear Color information and extend Gen12 render decompression
functionality to the newly added modifier.
v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
plane config(Matt). Fix Lookup error.
v3: Fix the panic while running kms_cube
v4: Add alignment check and reuse the comments for ge12_ccs_formats(Matt)
v5: Fix typos and wrap comments(Matt)
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Ville Syrjala <ville.syrjala@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 52 +++++++++++++++++++
.../drm/i915/display/intel_display_types.h | 3 ++
drivers/gpu/drm/i915/display/intel_sprite.c | 11 +++-
drivers/gpu/drm/i915/i915_reg.h | 12 +++++
4 files changed, 77 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 20ad089da6ee..6d6eab8d4776 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1944,6 +1944,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
if (color_plane == 1)
return 64;
/* fall through */
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ if (color_plane == 1 || color_plane == 2)
+ return 64;
+ /* fall through */
case I915_FORMAT_MOD_Y_TILED:
if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
return 128;
@@ -2085,6 +2089,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
return 256 * 1024;
return 0;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return 16 * 1024;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -2287,6 +2292,8 @@ static bool is_surface_linear(u64 modifier, int color_plane)
return true;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return color_plane == 1;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ return color_plane == 1 || color_plane == 2;
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return color_plane == 1 || color_plane == 3;
default:
@@ -2480,6 +2487,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return I915_TILING_Y;
default:
return I915_TILING_NONE;
@@ -2533,6 +2541,21 @@ static const struct drm_format_info gen12_ccs_formats[] = {
.cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
};
+/*
+ * Same as gen12_ccs_formats[] above, but with additional surface used
+ * to pass Clear Color information in plane 2 with 64 bits of data.
+ */
+static const struct drm_format_info gen12_ccs_cc_formats[] = {
+ { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+ { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+};
+
static const struct drm_format_info *
lookup_format_info(const struct drm_format_info formats[],
int num_formats, u32 format)
@@ -2560,6 +2583,10 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
return lookup_format_info(gen12_ccs_formats,
ARRAY_SIZE(gen12_ccs_formats),
cmd->pixel_format);
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ return lookup_format_info(gen12_ccs_cc_formats,
+ ARRAY_SIZE(gen12_ccs_cc_formats),
+ cmd->pixel_format);
default:
return NULL;
}
@@ -2569,6 +2596,7 @@ bool is_ccs_modifier(u64 modifier)
{
return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
@@ -2756,6 +2784,8 @@ static bool is_ccs_plane(u64 modifier, int color_plane)
return false;
else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
return color_plane == 3 || color_plane == 1;
+ else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+ return color_plane == 1 || color_plane == 2;
else
return color_plane == 1;
}
@@ -2824,6 +2854,18 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
int x, y;
int ret;
+ /*
+ * Plane 2 of Render Compression with Clear Color fb modifier
+ * is consumed by the driver and not passed to DE. Skip the
+ * arithmetic related to alignment and offset calculation.
+ */
+ if (i == 2 && fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
+ if (IS_ALIGNED(fb->offsets[2], PAGE_SIZE))
+ continue;
+ else
+ return -EINVAL;
+ }
+
cpp = fb->format->cpp[i];
intel_fb_plane_dims(&width, &height, fb, i);
@@ -4341,6 +4383,7 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
case I915_FORMAT_MOD_Y_TILED:
return PLANE_CTL_TILED_Y;
case I915_FORMAT_MOD_Y_TILED_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return PLANE_CTL_TILED_Y |
@@ -15212,6 +15255,15 @@ static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
plane_state->vma = vma;
+ if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
+ u32 *ccaddr = kmap_atomic(i915_gem_object_get_page(intel_fb_obj(fb),
+ fb->offsets[2] >> PAGE_SHIFT));
+
+ plane_state->ccval = ((u64)*(ccaddr + CC_VAL_HIGHER_OFFSET) << 32)
+ | *(ccaddr + CC_VAL_LOWER_OFFSET);
+ kunmap_atomic(ccaddr);
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e98f212682f6..9e147bba092e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -587,6 +587,9 @@ struct intel_plane_state {
u32 planar_slave;
struct drm_intel_sprite_colorkey ckey;
+
+ /* Clear Color Value */
+ u64 ccval;
};
struct intel_initial_plane_config {
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index a5018fffa8f2..f8d2985e6c01 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -596,6 +596,7 @@ skl_program_plane(struct intel_plane *plane,
u32 plane_color_ctl = 0;
unsigned long irqflags;
u32 keymsk, keymax;
+ u64 ccval = plane_state->ccval;
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
@@ -656,6 +657,10 @@ skl_program_plane(struct intel_plane *plane,
if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
icl_program_input_csc(plane, crtc_state, plane_state);
+ if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+ intel_uncore_write64_fw(&dev_priv->uncore,
+ PLANE_CC_VAL(pipe, plane_id), ccval);
+
skl_write_plane_wm(plane, crtc_state);
I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
@@ -2115,7 +2120,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
- fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
return -EINVAL;
}
@@ -2554,6 +2560,7 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_LINEAR,
@@ -2562,6 +2569,7 @@ static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_LINEAR,
@@ -2737,6 +2745,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
break;
default:
return false;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 75cccd498b42..8a24707ea697 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6753,6 +6753,8 @@ enum {
#define _PLANE_KEYMAX_1_A 0x701a0
#define _PLANE_KEYMAX_2_A 0x702a0
#define PLANE_KEYMAX_ALPHA(a) ((a) << 24)
+#define _PLANE_CC_VAL_1_A 0x701b4
+#define _PLANE_CC_VAL_2_A 0x702b4
#define _PLANE_AUX_DIST_1_A 0x701c0
#define _PLANE_AUX_DIST_2_A 0x702c0
#define _PLANE_AUX_OFFSET_1_A 0x701c4
@@ -6792,6 +6794,16 @@ enum {
#define _PLANE_NV12_BUF_CFG_1_A 0x70278
#define _PLANE_NV12_BUF_CFG_2_A 0x70378
+#define _PLANE_CC_VAL_1_B 0x711b4
+#define _PLANE_CC_VAL_2_B 0x712b4
+#define _PLANE_CC_VAL_1(pipe) _PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B)
+#define _PLANE_CC_VAL_2(pipe) _PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B)
+#define PLANE_CC_VAL(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
+
+#define CC_VAL_LOWER_OFFSET 4
+#define CC_VAL_HIGHER_OFFSET 5
+
/* Input CSC Register Definitions */
#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev9)
@ 2019-10-29 0:02 ` Patchwork
0 siblings, 0 replies; 34+ messages in thread
From: Patchwork @ 2019-10-29 0:02 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx
== Series Details ==
Series: Clear Color Support for TGL Render Decompression (rev9)
URL : https://patchwork.freedesktop.org/series/66814/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
10f566048768 drm/framebuffer: Format modifier for Intel Gen-12 render compression
7d2dee12e37d drm/i915: Use intel_tile_height() instead of re-implementing
12645a88b91a drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment
32c32c8b500b drm/i915/tgl: Gen-12 render decompression
ba040ad811f0 drm/i915: Extract framebufer CCS offset checks into a function
39c6f2f2c9f9 drm/framebuffer: Format modifier for Intel Gen-12 media compression
124bad1a7799 drm/fb: Extend format_info member arrays to handle four planes
c36e200e5975 Gen-12 display can decompress surfaces compressed by the media engine.
-:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#13:
compressed buffers. Unlike render decompression, plane 6 and plane 7 do not
-:113: WARNING:LONG_LINE: line over 100 characters
#113: FILE: drivers/gpu/drm/i915/display/intel_display.c:2726:
+intel_fb_plane_get_subsampling(int *hsub, int *vsub, const struct drm_framebuffer *fb, int color_plane)
-:120: WARNING:LONG_LINE: line over 100 characters
#120: FILE: drivers/gpu/drm/i915/display/intel_display.c:2733:
+ } mc_ccs_subsampling = {.cpp = {1, 1, 2, 1}, .hsub = {1, 8, 2, 16}, .vsub = {1, 32, 2, 32} };
total: 0 errors, 3 warnings, 0 checks, 509 lines checked
2858e81f6a9e drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
e9980fa6b761 drm/i915/tgl: Add Clear Color support for TGL Render Decompression
-:253: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#253: FILE: drivers/gpu/drm/i915/i915_reg.h:6801:
+#define PLANE_CC_VAL(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
total: 0 errors, 0 warnings, 1 checks, 198 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev9)
@ 2019-10-29 0:02 ` Patchwork
0 siblings, 0 replies; 34+ messages in thread
From: Patchwork @ 2019-10-29 0:02 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx
== Series Details ==
Series: Clear Color Support for TGL Render Decompression (rev9)
URL : https://patchwork.freedesktop.org/series/66814/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
10f566048768 drm/framebuffer: Format modifier for Intel Gen-12 render compression
7d2dee12e37d drm/i915: Use intel_tile_height() instead of re-implementing
12645a88b91a drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment
32c32c8b500b drm/i915/tgl: Gen-12 render decompression
ba040ad811f0 drm/i915: Extract framebufer CCS offset checks into a function
39c6f2f2c9f9 drm/framebuffer: Format modifier for Intel Gen-12 media compression
124bad1a7799 drm/fb: Extend format_info member arrays to handle four planes
c36e200e5975 Gen-12 display can decompress surfaces compressed by the media engine.
-:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#13:
compressed buffers. Unlike render decompression, plane 6 and plane 7 do not
-:113: WARNING:LONG_LINE: line over 100 characters
#113: FILE: drivers/gpu/drm/i915/display/intel_display.c:2726:
+intel_fb_plane_get_subsampling(int *hsub, int *vsub, const struct drm_framebuffer *fb, int color_plane)
-:120: WARNING:LONG_LINE: line over 100 characters
#120: FILE: drivers/gpu/drm/i915/display/intel_display.c:2733:
+ } mc_ccs_subsampling = {.cpp = {1, 1, 2, 1}, .hsub = {1, 8, 2, 16}, .vsub = {1, 32, 2, 32} };
total: 0 errors, 3 warnings, 0 checks, 509 lines checked
2858e81f6a9e drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
e9980fa6b761 drm/i915/tgl: Add Clear Color support for TGL Render Decompression
-:253: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#253: FILE: drivers/gpu/drm/i915/i915_reg.h:6801:
+#define PLANE_CC_VAL(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
total: 0 errors, 0 warnings, 1 checks, 198 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* ✗ Fi.CI.BAT: failure for Clear Color Support for TGL Render Decompression (rev9)
@ 2019-10-29 0:49 ` Patchwork
0 siblings, 0 replies; 34+ messages in thread
From: Patchwork @ 2019-10-29 0:49 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx
== Series Details ==
Series: Clear Color Support for TGL Render Decompression (rev9)
URL : https://patchwork.freedesktop.org/series/66814/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7206 -> Patchwork_15035
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15035 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15035, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15035:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live_blt:
- fi-cml-u2: [PASS][1] -> [TIMEOUT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-cml-u2/igt@i915_selftest@live_blt.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-cml-u2/igt@i915_selftest@live_blt.html
- fi-cfl-guc: [PASS][3] -> [TIMEOUT][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-cfl-guc/igt@i915_selftest@live_blt.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-cfl-guc/igt@i915_selftest@live_blt.html
Known issues
------------
Here are the changes found in Patchwork_15035 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: [PASS][5] -> [FAIL][6] ([fdo#103167])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html
- fi-hsw-peppy: [PASS][7] -> [DMESG-WARN][8] ([fdo#102614])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
#### Possible fixes ####
* igt@gem_ctx_create@basic-files:
- {fi-icl-dsi}: [INCOMPLETE][9] ([fdo#107713] / [fdo#109100]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-dsi/igt@gem_ctx_create@basic-files.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-icl-dsi/igt@gem_ctx_create@basic-files.html
* igt@gem_exec_suspend@basic-s3:
- {fi-cml-s}: [DMESG-WARN][11] ([fdo#111764]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-cml-s/igt@gem_exec_suspend@basic-s3.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-cml-s/igt@gem_exec_suspend@basic-s3.html
* igt@gem_mmap_gtt@basic-read-write-distinct:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14] +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u3/igt@gem_mmap_gtt@basic-read-write-distinct.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-icl-u3/igt@gem_mmap_gtt@basic-read-write-distinct.html
* igt@i915_selftest@live_blt:
- fi-kbl-guc: [TIMEOUT][15] -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-kbl-guc/igt@i915_selftest@live_blt.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-kbl-guc/igt@i915_selftest@live_blt.html
- fi-kbl-r: [TIMEOUT][17] -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-kbl-r/igt@i915_selftest@live_blt.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-kbl-r/igt@i915_selftest@live_blt.html
- fi-icl-u2: [TIMEOUT][19] -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u2/igt@i915_selftest@live_blt.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-icl-u2/igt@i915_selftest@live_blt.html
- {fi-icl-u4}: [TIMEOUT][21] -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u4/igt@i915_selftest@live_blt.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-icl-u4/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_client:
- fi-cfl-8700k: [INCOMPLETE][23] -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-cfl-8700k/igt@i915_selftest@live_client.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-cfl-8700k/igt@i915_selftest@live_client.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
[fdo#111764]: https://bugs.freedesktop.org/show_bug.cgi?id=111764
[fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096
Participating hosts (50 -> 39)
------------------------------
Missing (11): fi-ilk-m540 fi-bxt-dsi fi-bsw-n3050 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-apl-guc fi-icl-y fi-bdw-samus fi-byt-clapper fi-skl-6700k2
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7206 -> Patchwork_15035
CI-20190529: 20190529
CI_DRM_7206: 197ff4c24c6762ac5bbd8c5364d6f840fb9929c5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5248: 81e55f1f97d73e48f00caa7e4fb98295023c5afa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15035: e9980fa6b7616e6db7473e475a320f425aa49c06 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e9980fa6b761 drm/i915/tgl: Add Clear Color support for TGL Render Decompression
2858e81f6a9e drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
c36e200e5975 Gen-12 display can decompress surfaces compressed by the media engine.
124bad1a7799 drm/fb: Extend format_info member arrays to handle four planes
39c6f2f2c9f9 drm/framebuffer: Format modifier for Intel Gen-12 media compression
ba040ad811f0 drm/i915: Extract framebufer CCS offset checks into a function
32c32c8b500b drm/i915/tgl: Gen-12 render decompression
12645a88b91a drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment
7d2dee12e37d drm/i915: Use intel_tile_height() instead of re-implementing
10f566048768 drm/framebuffer: Format modifier for Intel Gen-12 render compression
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for Clear Color Support for TGL Render Decompression (rev9)
@ 2019-10-29 0:49 ` Patchwork
0 siblings, 0 replies; 34+ messages in thread
From: Patchwork @ 2019-10-29 0:49 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx
== Series Details ==
Series: Clear Color Support for TGL Render Decompression (rev9)
URL : https://patchwork.freedesktop.org/series/66814/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7206 -> Patchwork_15035
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15035 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15035, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15035:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live_blt:
- fi-cml-u2: [PASS][1] -> [TIMEOUT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-cml-u2/igt@i915_selftest@live_blt.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-cml-u2/igt@i915_selftest@live_blt.html
- fi-cfl-guc: [PASS][3] -> [TIMEOUT][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-cfl-guc/igt@i915_selftest@live_blt.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-cfl-guc/igt@i915_selftest@live_blt.html
Known issues
------------
Here are the changes found in Patchwork_15035 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: [PASS][5] -> [FAIL][6] ([fdo#103167])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html
- fi-hsw-peppy: [PASS][7] -> [DMESG-WARN][8] ([fdo#102614])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
#### Possible fixes ####
* igt@gem_ctx_create@basic-files:
- {fi-icl-dsi}: [INCOMPLETE][9] ([fdo#107713] / [fdo#109100]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-dsi/igt@gem_ctx_create@basic-files.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-icl-dsi/igt@gem_ctx_create@basic-files.html
* igt@gem_exec_suspend@basic-s3:
- {fi-cml-s}: [DMESG-WARN][11] ([fdo#111764]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-cml-s/igt@gem_exec_suspend@basic-s3.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-cml-s/igt@gem_exec_suspend@basic-s3.html
* igt@gem_mmap_gtt@basic-read-write-distinct:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14] +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u3/igt@gem_mmap_gtt@basic-read-write-distinct.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-icl-u3/igt@gem_mmap_gtt@basic-read-write-distinct.html
* igt@i915_selftest@live_blt:
- fi-kbl-guc: [TIMEOUT][15] -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-kbl-guc/igt@i915_selftest@live_blt.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-kbl-guc/igt@i915_selftest@live_blt.html
- fi-kbl-r: [TIMEOUT][17] -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-kbl-r/igt@i915_selftest@live_blt.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-kbl-r/igt@i915_selftest@live_blt.html
- fi-icl-u2: [TIMEOUT][19] -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u2/igt@i915_selftest@live_blt.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-icl-u2/igt@i915_selftest@live_blt.html
- {fi-icl-u4}: [TIMEOUT][21] -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u4/igt@i915_selftest@live_blt.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-icl-u4/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_client:
- fi-cfl-8700k: [INCOMPLETE][23] -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-cfl-8700k/igt@i915_selftest@live_client.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-cfl-8700k/igt@i915_selftest@live_client.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
[fdo#111764]: https://bugs.freedesktop.org/show_bug.cgi?id=111764
[fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096
Participating hosts (50 -> 39)
------------------------------
Missing (11): fi-ilk-m540 fi-bxt-dsi fi-bsw-n3050 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-apl-guc fi-icl-y fi-bdw-samus fi-byt-clapper fi-skl-6700k2
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7206 -> Patchwork_15035
CI-20190529: 20190529
CI_DRM_7206: 197ff4c24c6762ac5bbd8c5364d6f840fb9929c5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5248: 81e55f1f97d73e48f00caa7e4fb98295023c5afa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15035: e9980fa6b7616e6db7473e475a320f425aa49c06 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e9980fa6b761 drm/i915/tgl: Add Clear Color support for TGL Render Decompression
2858e81f6a9e drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
c36e200e5975 Gen-12 display can decompress surfaces compressed by the media engine.
124bad1a7799 drm/fb: Extend format_info member arrays to handle four planes
39c6f2f2c9f9 drm/framebuffer: Format modifier for Intel Gen-12 media compression
ba040ad811f0 drm/i915: Extract framebufer CCS offset checks into a function
32c32c8b500b drm/i915/tgl: Gen-12 render decompression
12645a88b91a drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment
7d2dee12e37d drm/i915: Use intel_tile_height() instead of re-implementing
10f566048768 drm/framebuffer: Format modifier for Intel Gen-12 render compression
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
@ 2019-10-30 0:05 ` Chery, Nanley G
0 siblings, 0 replies; 34+ messages in thread
From: Chery, Nanley G @ 2019-10-30 0:05 UTC (permalink / raw)
To: Sripada, Radhakrishna, intel-gfx
Cc: Syrjala, Ville, Ekstrand, Jason, Pandiyan, Dhinakaran
+Jason
Maybe Jason and/or others have some thoughts on the following? Given the
detailed description of the clear color struct, it seems like we'll have to
define a new modifier if the struct fields change in a future generation.
On negative is that we might have to make new modifiers that provide no
additional benefit (assuming the new/changed fields are unused). On positive is
that it's probably a good thing that we mentioned the Raw clear color fields
because I think 3D uses it during rendering operations and we'll be sharing
from 3D-to-3D. Maybe we should specify how the channels should be formatted?
I haven't thought through how fields like Color Discard Enable affect buffer
sharing...
Another comment: I noticed that none of the Y+CCS modifiers explicitly state
that the CCS must be in the same BO as the Y-tiled main surface. We should at
least fix that for newly defined modifiers right?
-Nanley
> ________________________________________
> From: Sripada, Radhakrishna
> Sent: Monday, October 28, 2019 1:40 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Pandiyan, Dhinakaran; Syrjala, Ville; Sharma, Shashank; Antognolli, Rafael; Chery, Nanley G; Sripada, Radhakrishna; Ville Syrjala; Kondapally, Kalyan
> Subject: [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
>
> Gen12 display can decompress surfaces compressed by render engine with
> Clear Color, add a new modifier as the driver needs to know the surface
> was compressed by render engine.
>
> V2: Description changes as suggested by Rafael.
> V3: Mention the Clear Color size of 64 bits in the comments(DK)
> v4: Fix trailing whitespaces
> v5: Explain Clear Color in the documentation.
> v6: Documentation Nitpicks(Nanley)
>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> Cc: Nanley Chery <nanley.g.chery@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 1aa6d468c048..4aa7f3f9712a 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -434,6 +434,25 @@ extern "C" {
> */
> #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
>
> +/*
> + * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
> + * compression.
> + *
> + * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
> + * and at index 1. The clear color is stored at index 2, and the pitch should
> + * be ignored. The clear color structure is 256 bits. The first 128 bits
> + * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
> + * by 32 bits. The raw clear color is consumed by the 3d engine and generates
> + * the converted clear color of size 64 bits. The first 32 bits store the Lower
> + * Converted Clear Color value and the next 32 bits store the Higher Converted
> + * Clear Color value when applicable. The Converted Clear Color values are
> + * consumed by the DE. The last 64 bits are used to store Color Discard Enable
> + * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
> + * corresponds to an area of 4x1 tiles in the main surface. The main surface
> + * pitch is required to be a multiple of 4 tile widths.
> + */
> +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> +
> /*
> * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> *
> --
> 2.20.1
>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [Intel-gfx] [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
@ 2019-10-30 0:05 ` Chery, Nanley G
0 siblings, 0 replies; 34+ messages in thread
From: Chery, Nanley G @ 2019-10-30 0:05 UTC (permalink / raw)
To: Sripada, Radhakrishna, intel-gfx
Cc: Syrjala, Ville, Ekstrand, Jason, Pandiyan, Dhinakaran
+Jason
Maybe Jason and/or others have some thoughts on the following? Given the
detailed description of the clear color struct, it seems like we'll have to
define a new modifier if the struct fields change in a future generation.
On negative is that we might have to make new modifiers that provide no
additional benefit (assuming the new/changed fields are unused). On positive is
that it's probably a good thing that we mentioned the Raw clear color fields
because I think 3D uses it during rendering operations and we'll be sharing
from 3D-to-3D. Maybe we should specify how the channels should be formatted?
I haven't thought through how fields like Color Discard Enable affect buffer
sharing...
Another comment: I noticed that none of the Y+CCS modifiers explicitly state
that the CCS must be in the same BO as the Y-tiled main surface. We should at
least fix that for newly defined modifiers right?
-Nanley
> ________________________________________
> From: Sripada, Radhakrishna
> Sent: Monday, October 28, 2019 1:40 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Pandiyan, Dhinakaran; Syrjala, Ville; Sharma, Shashank; Antognolli, Rafael; Chery, Nanley G; Sripada, Radhakrishna; Ville Syrjala; Kondapally, Kalyan
> Subject: [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
>
> Gen12 display can decompress surfaces compressed by render engine with
> Clear Color, add a new modifier as the driver needs to know the surface
> was compressed by render engine.
>
> V2: Description changes as suggested by Rafael.
> V3: Mention the Clear Color size of 64 bits in the comments(DK)
> v4: Fix trailing whitespaces
> v5: Explain Clear Color in the documentation.
> v6: Documentation Nitpicks(Nanley)
>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> Cc: Nanley Chery <nanley.g.chery@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 1aa6d468c048..4aa7f3f9712a 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -434,6 +434,25 @@ extern "C" {
> */
> #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
>
> +/*
> + * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
> + * compression.
> + *
> + * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
> + * and at index 1. The clear color is stored at index 2, and the pitch should
> + * be ignored. The clear color structure is 256 bits. The first 128 bits
> + * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
> + * by 32 bits. The raw clear color is consumed by the 3d engine and generates
> + * the converted clear color of size 64 bits. The first 32 bits store the Lower
> + * Converted Clear Color value and the next 32 bits store the Higher Converted
> + * Clear Color value when applicable. The Converted Clear Color values are
> + * consumed by the DE. The last 64 bits are used to store Color Discard Enable
> + * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
> + * corresponds to an area of 4x1 tiles in the main surface. The main surface
> + * pitch is required to be a multiple of 4 tile widths.
> + */
> +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> +
> /*
> * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> *
> --
> 2.20.1
>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
@ 2019-11-01 7:00 ` Sripada, Radhakrishna
0 siblings, 0 replies; 34+ messages in thread
From: Sripada, Radhakrishna @ 2019-11-01 7:00 UTC (permalink / raw)
To: Chery, Nanley G, intel-gfx
Cc: Syrjala, Ville, Ekstrand, Jason, Pandiyan, Dhinakaran
Hi Nanley,
> -----Original Message-----
> From: Chery, Nanley G
> Sent: Tuesday, October 29, 2019 5:05 PM
> To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Pandiyan, Dhinakaran <dhinakaran.pandiyan@intel.com>; Syrjala, Ville
> <ville.syrjala@intel.com>; Sharma, Shashank
> <shashank.sharma@intel.com>; Antognolli, Rafael
> <rafael.antognolli@intel.com>; Ville Syrjala <ville.syrjala@linux.intel.com>;
> Ekstrand, Jason <jason.ekstrand@intel.com>
> Subject: RE: [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for Intel
> Gen 12 render compression with Clear Color
>
> +Jason
>
> Maybe Jason and/or others have some thoughts on the following? Given the
> detailed description of the clear color struct, it seems like we'll have to define
> a new modifier if the struct fields change in a future generation.
>
> On negative is that we might have to make new modifiers that provide no
> additional benefit (assuming the new/changed fields are unused). On
> positive is that it's probably a good thing that we mentioned the Raw clear
> color fields because I think 3D uses it during rendering operations and we'll
> be sharing from 3D-to-3D. Maybe we should specify how the channels
> should be formatted?
>
> I haven't thought through how fields like Color Discard Enable affect buffer
> sharing...
>
> Another comment: I noticed that none of the Y+CCS modifiers explicitly state
> that the CCS must be in the same BO as the Y-tiled main surface. We should
> at least fix that for newly defined modifiers right?
I have not tried to use separate bo for the different surfaces. That is probably worth a try.
I wonder if we are using that for any of the modifiers to have an explicit comment?
Thanks,
RK
>
> -Nanley
>
> > ________________________________________
> > From: Sripada, Radhakrishna
> > Sent: Monday, October 28, 2019 1:40 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Pandiyan, Dhinakaran; Syrjala, Ville; Sharma, Shashank;
> > Antognolli, Rafael; Chery, Nanley G; Sripada, Radhakrishna; Ville
> > Syrjala; Kondapally, Kalyan
> > Subject: [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for
> > Intel Gen 12 render compression with Clear Color
> >
> > Gen12 display can decompress surfaces compressed by render engine with
> > Clear Color, add a new modifier as the driver needs to know the
> > surface was compressed by render engine.
> >
> > V2: Description changes as suggested by Rafael.
> > V3: Mention the Clear Color size of 64 bits in the comments(DK)
> > v4: Fix trailing whitespaces
> > v5: Explain Clear Color in the documentation.
> > v6: Documentation Nitpicks(Nanley)
> >
> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
> > Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> > Cc: Nanley Chery <nanley.g.chery@intel.com>
> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > ---
> > include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++
> > 1 file changed, 19 insertions(+)
> >
> > diff --git a/include/uapi/drm/drm_fourcc.h
> > b/include/uapi/drm/drm_fourcc.h index 1aa6d468c048..4aa7f3f9712a
> > 100644
> > --- a/include/uapi/drm/drm_fourcc.h
> > +++ b/include/uapi/drm/drm_fourcc.h
> > @@ -434,6 +434,25 @@ extern "C" {
> > */
> > #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS
> fourcc_mod_code(INTEL,
> > 7)
> >
> > +/*
> > + * Intel Color Control Surface with Clear Color (CCS) for Gen-12
> > +render
> > + * compression.
> > + *
> > + * The main surface is Y-tiled and is at plane index 0 whereas CCS is
> > +linear
> > + * and at index 1. The clear color is stored at index 2, and the
> > +pitch should
> > + * be ignored. The clear color structure is 256 bits. The first 128
> > +bits
> > + * represents Raw Clear Color Red, Green, Blue and Alpha color each
> > +represented
> > + * by 32 bits. The raw clear color is consumed by the 3d engine and
> > +generates
> > + * the converted clear color of size 64 bits. The first 32 bits store
> > +the Lower
> > + * Converted Clear Color value and the next 32 bits store the Higher
> > +Converted
> > + * Clear Color value when applicable. The Converted Clear Color
> > +values are
> > + * consumed by the DE. The last 64 bits are used to store Color
> > +Discard Enable
> > + * and Depth Clear Value Valid which are ignored by the DE. A CCS
> > +cache line
> > + * corresponds to an area of 4x1 tiles in the main surface. The main
> > +surface
> > + * pitch is required to be a multiple of 4 tile widths.
> > + */
> > +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
> > +fourcc_mod_code(INTEL, 8)
> > +
> > /*
> > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > *
> > --
> > 2.20.1
> >
> >
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [Intel-gfx] [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
@ 2019-11-01 7:00 ` Sripada, Radhakrishna
0 siblings, 0 replies; 34+ messages in thread
From: Sripada, Radhakrishna @ 2019-11-01 7:00 UTC (permalink / raw)
To: Chery, Nanley G, intel-gfx
Cc: Syrjala, Ville, Ekstrand, Jason, Pandiyan, Dhinakaran
Hi Nanley,
> -----Original Message-----
> From: Chery, Nanley G
> Sent: Tuesday, October 29, 2019 5:05 PM
> To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Pandiyan, Dhinakaran <dhinakaran.pandiyan@intel.com>; Syrjala, Ville
> <ville.syrjala@intel.com>; Sharma, Shashank
> <shashank.sharma@intel.com>; Antognolli, Rafael
> <rafael.antognolli@intel.com>; Ville Syrjala <ville.syrjala@linux.intel.com>;
> Ekstrand, Jason <jason.ekstrand@intel.com>
> Subject: RE: [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for Intel
> Gen 12 render compression with Clear Color
>
> +Jason
>
> Maybe Jason and/or others have some thoughts on the following? Given the
> detailed description of the clear color struct, it seems like we'll have to define
> a new modifier if the struct fields change in a future generation.
>
> On negative is that we might have to make new modifiers that provide no
> additional benefit (assuming the new/changed fields are unused). On
> positive is that it's probably a good thing that we mentioned the Raw clear
> color fields because I think 3D uses it during rendering operations and we'll
> be sharing from 3D-to-3D. Maybe we should specify how the channels
> should be formatted?
>
> I haven't thought through how fields like Color Discard Enable affect buffer
> sharing...
>
> Another comment: I noticed that none of the Y+CCS modifiers explicitly state
> that the CCS must be in the same BO as the Y-tiled main surface. We should
> at least fix that for newly defined modifiers right?
I have not tried to use separate bo for the different surfaces. That is probably worth a try.
I wonder if we are using that for any of the modifiers to have an explicit comment?
Thanks,
RK
>
> -Nanley
>
> > ________________________________________
> > From: Sripada, Radhakrishna
> > Sent: Monday, October 28, 2019 1:40 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Pandiyan, Dhinakaran; Syrjala, Ville; Sharma, Shashank;
> > Antognolli, Rafael; Chery, Nanley G; Sripada, Radhakrishna; Ville
> > Syrjala; Kondapally, Kalyan
> > Subject: [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for
> > Intel Gen 12 render compression with Clear Color
> >
> > Gen12 display can decompress surfaces compressed by render engine with
> > Clear Color, add a new modifier as the driver needs to know the
> > surface was compressed by render engine.
> >
> > V2: Description changes as suggested by Rafael.
> > V3: Mention the Clear Color size of 64 bits in the comments(DK)
> > v4: Fix trailing whitespaces
> > v5: Explain Clear Color in the documentation.
> > v6: Documentation Nitpicks(Nanley)
> >
> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
> > Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> > Cc: Nanley Chery <nanley.g.chery@intel.com>
> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > ---
> > include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++
> > 1 file changed, 19 insertions(+)
> >
> > diff --git a/include/uapi/drm/drm_fourcc.h
> > b/include/uapi/drm/drm_fourcc.h index 1aa6d468c048..4aa7f3f9712a
> > 100644
> > --- a/include/uapi/drm/drm_fourcc.h
> > +++ b/include/uapi/drm/drm_fourcc.h
> > @@ -434,6 +434,25 @@ extern "C" {
> > */
> > #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS
> fourcc_mod_code(INTEL,
> > 7)
> >
> > +/*
> > + * Intel Color Control Surface with Clear Color (CCS) for Gen-12
> > +render
> > + * compression.
> > + *
> > + * The main surface is Y-tiled and is at plane index 0 whereas CCS is
> > +linear
> > + * and at index 1. The clear color is stored at index 2, and the
> > +pitch should
> > + * be ignored. The clear color structure is 256 bits. The first 128
> > +bits
> > + * represents Raw Clear Color Red, Green, Blue and Alpha color each
> > +represented
> > + * by 32 bits. The raw clear color is consumed by the 3d engine and
> > +generates
> > + * the converted clear color of size 64 bits. The first 32 bits store
> > +the Lower
> > + * Converted Clear Color value and the next 32 bits store the Higher
> > +Converted
> > + * Clear Color value when applicable. The Converted Clear Color
> > +values are
> > + * consumed by the DE. The last 64 bits are used to store Color
> > +Discard Enable
> > + * and Depth Clear Value Valid which are ignored by the DE. A CCS
> > +cache line
> > + * corresponds to an area of 4x1 tiles in the main surface. The main
> > +surface
> > + * pitch is required to be a multiple of 4 tile widths.
> > + */
> > +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
> > +fourcc_mod_code(INTEL, 8)
> > +
> > /*
> > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > *
> > --
> > 2.20.1
> >
> >
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
@ 2019-11-12 17:40 ` Chery, Nanley G
0 siblings, 0 replies; 34+ messages in thread
From: Chery, Nanley G @ 2019-11-12 17:40 UTC (permalink / raw)
To: Sripada, Radhakrishna, intel-gfx
Cc: Syrjala, Ville, Ekstrand, Jason, Pandiyan, Dhinakaran
> From: Sripada, Radhakrishna
> Sent: Friday, November 01, 2019 12:00 AM
> To: Chery, Nanley G; intel-gfx@lists.freedesktop.org
> Cc: Pandiyan, Dhinakaran; Syrjala, Ville; Sharma, Shashank; Antognolli, Rafael; Ville Syrjala; Ekstrand, Jason
> Subject: RE: [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
>
> Hi Nanley,
>
> > -----Original Message-----
> > From: Chery, Nanley G
> > Sent: Tuesday, October 29, 2019 5:05 PM
> > To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>; intel-
> > gfx@lists.freedesktop.org
> > Cc: Pandiyan, Dhinakaran <dhinakaran.pandiyan@intel.com>; Syrjala, Ville
> > <ville.syrjala@intel.com>; Sharma, Shashank
> > <shashank.sharma@intel.com>; Antognolli, Rafael
> > <rafael.antognolli@intel.com>; Ville Syrjala <ville.syrjala@linux.intel.com>;
> > Ekstrand, Jason <jason.ekstrand@intel.com>
> > Subject: RE: [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for Intel
> > Gen 12 render compression with Clear Color
> >
> > +Jason
> >
> > Maybe Jason and/or others have some thoughts on the following? Given the
> > detailed description of the clear color struct, it seems like we'll have to define
> > a new modifier if the struct fields change in a future generation.
> >
> > On negative is that we might have to make new modifiers that provide no
> > additional benefit (assuming the new/changed fields are unused). On
> > positive is that it's probably a good thing that we mentioned the Raw clear
> > color fields because I think 3D uses it during rendering operations and we'll
> > be sharing from 3D-to-3D. Maybe we should specify how the channels
> > should be formatted?
> >
> > I haven't thought through how fields like Color Discard Enable affect buffer
> > sharing...
> >
> > Another comment: I noticed that none of the Y+CCS modifiers explicitly state
> > that the CCS must be in the same BO as the Y-tiled main surface. We should
> > at least fix that for newly defined modifiers right?
> I have not tried to use separate bo for the different surfaces. That is probably worth a try.
> I wonder if we are using that for any of the modifiers to have an explicit comment?
I didn't think it was possible to use a separate BO for the aux data. AFAICT
the location of the aux data is specified as an offset from the main surface
using the PLANE_AUX_DIST register.
-Nanley
>
> Thanks,
> RK
> >
> > -Nanley
> >
> > > ________________________________________
> > > From: Sripada, Radhakrishna
> > > Sent: Monday, October 28, 2019 1:40 PM
> > > To: intel-gfx@lists.freedesktop.org
> > > Cc: Pandiyan, Dhinakaran; Syrjala, Ville; Sharma, Shashank;
> > > Antognolli, Rafael; Chery, Nanley G; Sripada, Radhakrishna; Ville
> > > Syrjala; Kondapally, Kalyan
> > > Subject: [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for
> > > Intel Gen 12 render compression with Clear Color
> > >
> > > Gen12 display can decompress surfaces compressed by render engine with
> > > Clear Color, add a new modifier as the driver needs to know the
> > > surface was compressed by render engine.
> > >
> > > V2: Description changes as suggested by Rafael.
> > > V3: Mention the Clear Color size of 64 bits in the comments(DK)
> > > v4: Fix trailing whitespaces
> > > v5: Explain Clear Color in the documentation.
> > > v6: Documentation Nitpicks(Nanley)
> > >
> > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
> > > Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> > > Cc: Nanley Chery <nanley.g.chery@intel.com>
> > > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > > ---
> > > include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++
> > > 1 file changed, 19 insertions(+)
> > >
> > > diff --git a/include/uapi/drm/drm_fourcc.h
> > > b/include/uapi/drm/drm_fourcc.h index 1aa6d468c048..4aa7f3f9712a
> > > 100644
> > > --- a/include/uapi/drm/drm_fourcc.h
> > > +++ b/include/uapi/drm/drm_fourcc.h
> > > @@ -434,6 +434,25 @@ extern "C" {
> > > */
> > > #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS
> > fourcc_mod_code(INTEL,
> > > 7)
> > >
> > > +/*
> > > + * Intel Color Control Surface with Clear Color (CCS) for Gen-12
> > > +render
> > > + * compression.
> > > + *
> > > + * The main surface is Y-tiled and is at plane index 0 whereas CCS is
> > > +linear
> > > + * and at index 1. The clear color is stored at index 2, and the
> > > +pitch should
> > > + * be ignored. The clear color structure is 256 bits. The first 128
> > > +bits
> > > + * represents Raw Clear Color Red, Green, Blue and Alpha color each
> > > +represented
> > > + * by 32 bits. The raw clear color is consumed by the 3d engine and
> > > +generates
> > > + * the converted clear color of size 64 bits. The first 32 bits store
> > > +the Lower
> > > + * Converted Clear Color value and the next 32 bits store the Higher
> > > +Converted
> > > + * Clear Color value when applicable. The Converted Clear Color
> > > +values are
> > > + * consumed by the DE. The last 64 bits are used to store Color
> > > +Discard Enable
> > > + * and Depth Clear Value Valid which are ignored by the DE. A CCS
> > > +cache line
> > > + * corresponds to an area of 4x1 tiles in the main surface. The main
> > > +surface
> > > + * pitch is required to be a multiple of 4 tile widths.
> > > + */
> > > +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
> > > +fourcc_mod_code(INTEL, 8)
> > > +
> > > /*
> > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > > *
> > > --
> > > 2.20.1
> > >
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [Intel-gfx] [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
@ 2019-11-12 17:40 ` Chery, Nanley G
0 siblings, 0 replies; 34+ messages in thread
From: Chery, Nanley G @ 2019-11-12 17:40 UTC (permalink / raw)
To: Sripada, Radhakrishna, intel-gfx
Cc: Syrjala, Ville, Ekstrand, Jason, Pandiyan, Dhinakaran
> From: Sripada, Radhakrishna
> Sent: Friday, November 01, 2019 12:00 AM
> To: Chery, Nanley G; intel-gfx@lists.freedesktop.org
> Cc: Pandiyan, Dhinakaran; Syrjala, Ville; Sharma, Shashank; Antognolli, Rafael; Ville Syrjala; Ekstrand, Jason
> Subject: RE: [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
>
> Hi Nanley,
>
> > -----Original Message-----
> > From: Chery, Nanley G
> > Sent: Tuesday, October 29, 2019 5:05 PM
> > To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>; intel-
> > gfx@lists.freedesktop.org
> > Cc: Pandiyan, Dhinakaran <dhinakaran.pandiyan@intel.com>; Syrjala, Ville
> > <ville.syrjala@intel.com>; Sharma, Shashank
> > <shashank.sharma@intel.com>; Antognolli, Rafael
> > <rafael.antognolli@intel.com>; Ville Syrjala <ville.syrjala@linux.intel.com>;
> > Ekstrand, Jason <jason.ekstrand@intel.com>
> > Subject: RE: [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for Intel
> > Gen 12 render compression with Clear Color
> >
> > +Jason
> >
> > Maybe Jason and/or others have some thoughts on the following? Given the
> > detailed description of the clear color struct, it seems like we'll have to define
> > a new modifier if the struct fields change in a future generation.
> >
> > On negative is that we might have to make new modifiers that provide no
> > additional benefit (assuming the new/changed fields are unused). On
> > positive is that it's probably a good thing that we mentioned the Raw clear
> > color fields because I think 3D uses it during rendering operations and we'll
> > be sharing from 3D-to-3D. Maybe we should specify how the channels
> > should be formatted?
> >
> > I haven't thought through how fields like Color Discard Enable affect buffer
> > sharing...
> >
> > Another comment: I noticed that none of the Y+CCS modifiers explicitly state
> > that the CCS must be in the same BO as the Y-tiled main surface. We should
> > at least fix that for newly defined modifiers right?
> I have not tried to use separate bo for the different surfaces. That is probably worth a try.
> I wonder if we are using that for any of the modifiers to have an explicit comment?
I didn't think it was possible to use a separate BO for the aux data. AFAICT
the location of the aux data is specified as an offset from the main surface
using the PLANE_AUX_DIST register.
-Nanley
>
> Thanks,
> RK
> >
> > -Nanley
> >
> > > ________________________________________
> > > From: Sripada, Radhakrishna
> > > Sent: Monday, October 28, 2019 1:40 PM
> > > To: intel-gfx@lists.freedesktop.org
> > > Cc: Pandiyan, Dhinakaran; Syrjala, Ville; Sharma, Shashank;
> > > Antognolli, Rafael; Chery, Nanley G; Sripada, Radhakrishna; Ville
> > > Syrjala; Kondapally, Kalyan
> > > Subject: [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for
> > > Intel Gen 12 render compression with Clear Color
> > >
> > > Gen12 display can decompress surfaces compressed by render engine with
> > > Clear Color, add a new modifier as the driver needs to know the
> > > surface was compressed by render engine.
> > >
> > > V2: Description changes as suggested by Rafael.
> > > V3: Mention the Clear Color size of 64 bits in the comments(DK)
> > > v4: Fix trailing whitespaces
> > > v5: Explain Clear Color in the documentation.
> > > v6: Documentation Nitpicks(Nanley)
> > >
> > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
> > > Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> > > Cc: Nanley Chery <nanley.g.chery@intel.com>
> > > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > > ---
> > > include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++
> > > 1 file changed, 19 insertions(+)
> > >
> > > diff --git a/include/uapi/drm/drm_fourcc.h
> > > b/include/uapi/drm/drm_fourcc.h index 1aa6d468c048..4aa7f3f9712a
> > > 100644
> > > --- a/include/uapi/drm/drm_fourcc.h
> > > +++ b/include/uapi/drm/drm_fourcc.h
> > > @@ -434,6 +434,25 @@ extern "C" {
> > > */
> > > #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS
> > fourcc_mod_code(INTEL,
> > > 7)
> > >
> > > +/*
> > > + * Intel Color Control Surface with Clear Color (CCS) for Gen-12
> > > +render
> > > + * compression.
> > > + *
> > > + * The main surface is Y-tiled and is at plane index 0 whereas CCS is
> > > +linear
> > > + * and at index 1. The clear color is stored at index 2, and the
> > > +pitch should
> > > + * be ignored. The clear color structure is 256 bits. The first 128
> > > +bits
> > > + * represents Raw Clear Color Red, Green, Blue and Alpha color each
> > > +represented
> > > + * by 32 bits. The raw clear color is consumed by the 3d engine and
> > > +generates
> > > + * the converted clear color of size 64 bits. The first 32 bits store
> > > +the Lower
> > > + * Converted Clear Color value and the next 32 bits store the Higher
> > > +Converted
> > > + * Clear Color value when applicable. The Converted Clear Color
> > > +values are
> > > + * consumed by the DE. The last 64 bits are used to store Color
> > > +Discard Enable
> > > + * and Depth Clear Value Valid which are ignored by the DE. A CCS
> > > +cache line
> > > + * corresponds to an area of 4x1 tiles in the main surface. The main
> > > +surface
> > > + * pitch is required to be a multiple of 4 tile widths.
> > > + */
> > > +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
> > > +fourcc_mod_code(INTEL, 8)
> > > +
> > > /*
> > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > > *
> > > --
> > > 2.20.1
> > >
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
@ 2019-11-13 22:33 ` Chery, Nanley G
0 siblings, 0 replies; 34+ messages in thread
From: Chery, Nanley G @ 2019-11-13 22:33 UTC (permalink / raw)
To: Sripada, Radhakrishna, intel-gfx
Cc: Syrjala, Ville, Ekstrand, Jason, Pandiyan, Dhinakaran
> From: Chery, Nanley G
> Sent: Tuesday, November 12, 2019 9:40 AM
> To: Sripada, Radhakrishna; intel-gfx@lists.freedesktop.org
> Cc: Pandiyan, Dhinakaran; Syrjala, Ville; Sharma, Shashank; Antognolli, Rafael; Ville Syrjala; Ekstrand, Jason
> Subject: RE: [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
>
> > From: Sripada, Radhakrishna
> > Sent: Friday, November 01, 2019 12:00 AM
> > To: Chery, Nanley G; intel-gfx@lists.freedesktop.org
> > Cc: Pandiyan, Dhinakaran; Syrjala, Ville; Sharma, Shashank; Antognolli, Rafael; Ville Syrjala; Ekstrand, Jason
> > Subject: RE: [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
> >
> > Hi Nanley,
> >
> > > -----Original Message-----
> > > From: Chery, Nanley G
> > > Sent: Tuesday, October 29, 2019 5:05 PM
> > > To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>; intel-
> > > gfx@lists.freedesktop.org
> > > Cc: Pandiyan, Dhinakaran <dhinakaran.pandiyan@intel.com>; Syrjala, Ville
> > > <ville.syrjala@intel.com>; Sharma, Shashank
> > > <shashank.sharma@intel.com>; Antognolli, Rafael
> > > <rafael.antognolli@intel.com>; Ville Syrjala <ville.syrjala@linux.intel.com>;
> > > Ekstrand, Jason <jason.ekstrand@intel.com>
> > > Subject: RE: [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for Intel
> > > Gen 12 render compression with Clear Color
> > >
> > > +Jason
> > >
> > > Maybe Jason and/or others have some thoughts on the following? Given the
> > > detailed description of the clear color struct, it seems like we'll have to define
> > > a new modifier if the struct fields change in a future generation.
> > >
> > > On negative is that we might have to make new modifiers that provide no
> > > additional benefit (assuming the new/changed fields are unused). On
> > > positive is that it's probably a good thing that we mentioned the Raw clear
> > > color fields because I think 3D uses it during rendering operations and we'll
> > > be sharing from 3D-to-3D. Maybe we should specify how the channels
> > > should be formatted?
> > >
> > > I haven't thought through how fields like Color Discard Enable affect buffer
> > > sharing...
> > >
After some more thought, I don't think it's a problem to have a detailed
description here. We have a lot of space allocated for making new modifiers
(and the header suggests doing so!).
We could go into more detail about the non-DE-specific fields, but I suppose
users can access PRMs.
> > > Another comment: I noticed that none of the Y+CCS modifiers explicitly state
> > > that the CCS must be in the same BO as the Y-tiled main surface. We should
> > > at least fix that for newly defined modifiers right?
> > I have not tried to use separate bo for the different surfaces. That is probably worth a try.
> > I wonder if we are using that for any of the modifiers to have an explicit comment?
>
> I didn't think it was possible to use a separate BO for the aux data. AFAICT
> the location of the aux data is specified as an offset from the main surface
> using the PLANE_AUX_DIST register.
>
Great, I got some clarification that this is actually possible.
Lastly, can we replace:
* The raw clear color is consumed by the 3d engine and generates
* the converted clear color of size 64 bits.
with something like:
* The 3D engine can use the raw clear color and the surface format to
* generate a converted clear color of size 64 bits.
so that the subject is constant throughout the sentence and so that it's a bit
more obvious what is in the Converted Clear Color field? Also, we don't
explicitly state that the Converted Clear Color comes right after the raw clear
color, but I'd think the implication is strong enough.
With the above suggestion implemented, this patch is
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
-Nanley
> -Nanley
>
> >
> > Thanks,
> > RK
> > >
> > > -Nanley
> > >
> > > > ________________________________________
> > > > From: Sripada, Radhakrishna
> > > > Sent: Monday, October 28, 2019 1:40 PM
> > > > To: intel-gfx@lists.freedesktop.org
> > > > Cc: Pandiyan, Dhinakaran; Syrjala, Ville; Sharma, Shashank;
> > > > Antognolli, Rafael; Chery, Nanley G; Sripada, Radhakrishna; Ville
> > > > Syrjala; Kondapally, Kalyan
> > > > Subject: [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for
> > > > Intel Gen 12 render compression with Clear Color
> > > >
> > > > Gen12 display can decompress surfaces compressed by render engine with
> > > > Clear Color, add a new modifier as the driver needs to know the
> > > > surface was compressed by render engine.
> > > >
> > > > V2: Description changes as suggested by Rafael.
> > > > V3: Mention the Clear Color size of 64 bits in the comments(DK)
> > > > v4: Fix trailing whitespaces
> > > > v5: Explain Clear Color in the documentation.
> > > > v6: Documentation Nitpicks(Nanley)
> > > >
> > > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > > Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
> > > > Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> > > > Cc: Nanley Chery <nanley.g.chery@intel.com>
> > > > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > > > ---
> > > > include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++
> > > > 1 file changed, 19 insertions(+)
> > > >
> > > > diff --git a/include/uapi/drm/drm_fourcc.h
> > > > b/include/uapi/drm/drm_fourcc.h index 1aa6d468c048..4aa7f3f9712a
> > > > 100644
> > > > --- a/include/uapi/drm/drm_fourcc.h
> > > > +++ b/include/uapi/drm/drm_fourcc.h
> > > > @@ -434,6 +434,25 @@ extern "C" {
> > > > */
> > > > #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS
> > > fourcc_mod_code(INTEL,
> > > > 7)
> > > >
> > > > +/*
> > > > + * Intel Color Control Surface with Clear Color (CCS) for Gen-12
> > > > +render
> > > > + * compression.
> > > > + *
> > > > + * The main surface is Y-tiled and is at plane index 0 whereas CCS is
> > > > +linear
> > > > + * and at index 1. The clear color is stored at index 2, and the
> > > > +pitch should
> > > > + * be ignored. The clear color structure is 256 bits. The first 128
> > > > +bits
> > > > + * represents Raw Clear Color Red, Green, Blue and Alpha color each
> > > > +represented
> > > > + * by 32 bits. The raw clear color is consumed by the 3d engine and
> > > > +generates
> > > > + * the converted clear color of size 64 bits. The first 32 bits store
> > > > +the Lower
> > > > + * Converted Clear Color value and the next 32 bits store the Higher
> > > > +Converted
> > > > + * Clear Color value when applicable. The Converted Clear Color
> > > > +values are
> > > > + * consumed by the DE. The last 64 bits are used to store Color
> > > > +Discard Enable
> > > > + * and Depth Clear Value Valid which are ignored by the DE. A CCS
> > > > +cache line
> > > > + * corresponds to an area of 4x1 tiles in the main surface. The main
> > > > +surface
> > > > + * pitch is required to be a multiple of 4 tile widths.
> > > > + */
> > > > +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
> > > > +fourcc_mod_code(INTEL, 8)
> > > > +
> > > > /*
> > > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > > > *
> > > > --
> > > > 2.20.1
> > > >
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [Intel-gfx] [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
@ 2019-11-13 22:33 ` Chery, Nanley G
0 siblings, 0 replies; 34+ messages in thread
From: Chery, Nanley G @ 2019-11-13 22:33 UTC (permalink / raw)
To: Sripada, Radhakrishna, intel-gfx
Cc: Syrjala, Ville, Ekstrand, Jason, Pandiyan, Dhinakaran
> From: Chery, Nanley G
> Sent: Tuesday, November 12, 2019 9:40 AM
> To: Sripada, Radhakrishna; intel-gfx@lists.freedesktop.org
> Cc: Pandiyan, Dhinakaran; Syrjala, Ville; Sharma, Shashank; Antognolli, Rafael; Ville Syrjala; Ekstrand, Jason
> Subject: RE: [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
>
> > From: Sripada, Radhakrishna
> > Sent: Friday, November 01, 2019 12:00 AM
> > To: Chery, Nanley G; intel-gfx@lists.freedesktop.org
> > Cc: Pandiyan, Dhinakaran; Syrjala, Ville; Sharma, Shashank; Antognolli, Rafael; Ville Syrjala; Ekstrand, Jason
> > Subject: RE: [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
> >
> > Hi Nanley,
> >
> > > -----Original Message-----
> > > From: Chery, Nanley G
> > > Sent: Tuesday, October 29, 2019 5:05 PM
> > > To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>; intel-
> > > gfx@lists.freedesktop.org
> > > Cc: Pandiyan, Dhinakaran <dhinakaran.pandiyan@intel.com>; Syrjala, Ville
> > > <ville.syrjala@intel.com>; Sharma, Shashank
> > > <shashank.sharma@intel.com>; Antognolli, Rafael
> > > <rafael.antognolli@intel.com>; Ville Syrjala <ville.syrjala@linux.intel.com>;
> > > Ekstrand, Jason <jason.ekstrand@intel.com>
> > > Subject: RE: [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for Intel
> > > Gen 12 render compression with Clear Color
> > >
> > > +Jason
> > >
> > > Maybe Jason and/or others have some thoughts on the following? Given the
> > > detailed description of the clear color struct, it seems like we'll have to define
> > > a new modifier if the struct fields change in a future generation.
> > >
> > > On negative is that we might have to make new modifiers that provide no
> > > additional benefit (assuming the new/changed fields are unused). On
> > > positive is that it's probably a good thing that we mentioned the Raw clear
> > > color fields because I think 3D uses it during rendering operations and we'll
> > > be sharing from 3D-to-3D. Maybe we should specify how the channels
> > > should be formatted?
> > >
> > > I haven't thought through how fields like Color Discard Enable affect buffer
> > > sharing...
> > >
After some more thought, I don't think it's a problem to have a detailed
description here. We have a lot of space allocated for making new modifiers
(and the header suggests doing so!).
We could go into more detail about the non-DE-specific fields, but I suppose
users can access PRMs.
> > > Another comment: I noticed that none of the Y+CCS modifiers explicitly state
> > > that the CCS must be in the same BO as the Y-tiled main surface. We should
> > > at least fix that for newly defined modifiers right?
> > I have not tried to use separate bo for the different surfaces. That is probably worth a try.
> > I wonder if we are using that for any of the modifiers to have an explicit comment?
>
> I didn't think it was possible to use a separate BO for the aux data. AFAICT
> the location of the aux data is specified as an offset from the main surface
> using the PLANE_AUX_DIST register.
>
Great, I got some clarification that this is actually possible.
Lastly, can we replace:
* The raw clear color is consumed by the 3d engine and generates
* the converted clear color of size 64 bits.
with something like:
* The 3D engine can use the raw clear color and the surface format to
* generate a converted clear color of size 64 bits.
so that the subject is constant throughout the sentence and so that it's a bit
more obvious what is in the Converted Clear Color field? Also, we don't
explicitly state that the Converted Clear Color comes right after the raw clear
color, but I'd think the implication is strong enough.
With the above suggestion implemented, this patch is
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
-Nanley
> -Nanley
>
> >
> > Thanks,
> > RK
> > >
> > > -Nanley
> > >
> > > > ________________________________________
> > > > From: Sripada, Radhakrishna
> > > > Sent: Monday, October 28, 2019 1:40 PM
> > > > To: intel-gfx@lists.freedesktop.org
> > > > Cc: Pandiyan, Dhinakaran; Syrjala, Ville; Sharma, Shashank;
> > > > Antognolli, Rafael; Chery, Nanley G; Sripada, Radhakrishna; Ville
> > > > Syrjala; Kondapally, Kalyan
> > > > Subject: [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for
> > > > Intel Gen 12 render compression with Clear Color
> > > >
> > > > Gen12 display can decompress surfaces compressed by render engine with
> > > > Clear Color, add a new modifier as the driver needs to know the
> > > > surface was compressed by render engine.
> > > >
> > > > V2: Description changes as suggested by Rafael.
> > > > V3: Mention the Clear Color size of 64 bits in the comments(DK)
> > > > v4: Fix trailing whitespaces
> > > > v5: Explain Clear Color in the documentation.
> > > > v6: Documentation Nitpicks(Nanley)
> > > >
> > > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > > Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
> > > > Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> > > > Cc: Nanley Chery <nanley.g.chery@intel.com>
> > > > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > > > ---
> > > > include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++
> > > > 1 file changed, 19 insertions(+)
> > > >
> > > > diff --git a/include/uapi/drm/drm_fourcc.h
> > > > b/include/uapi/drm/drm_fourcc.h index 1aa6d468c048..4aa7f3f9712a
> > > > 100644
> > > > --- a/include/uapi/drm/drm_fourcc.h
> > > > +++ b/include/uapi/drm/drm_fourcc.h
> > > > @@ -434,6 +434,25 @@ extern "C" {
> > > > */
> > > > #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS
> > > fourcc_mod_code(INTEL,
> > > > 7)
> > > >
> > > > +/*
> > > > + * Intel Color Control Surface with Clear Color (CCS) for Gen-12
> > > > +render
> > > > + * compression.
> > > > + *
> > > > + * The main surface is Y-tiled and is at plane index 0 whereas CCS is
> > > > +linear
> > > > + * and at index 1. The clear color is stored at index 2, and the
> > > > +pitch should
> > > > + * be ignored. The clear color structure is 256 bits. The first 128
> > > > +bits
> > > > + * represents Raw Clear Color Red, Green, Blue and Alpha color each
> > > > +represented
> > > > + * by 32 bits. The raw clear color is consumed by the 3d engine and
> > > > +generates
> > > > + * the converted clear color of size 64 bits. The first 32 bits store
> > > > +the Lower
> > > > + * Converted Clear Color value and the next 32 bits store the Higher
> > > > +Converted
> > > > + * Clear Color value when applicable. The Converted Clear Color
> > > > +values are
> > > > + * consumed by the DE. The last 64 bits are used to store Color
> > > > +Discard Enable
> > > > + * and Depth Clear Value Valid which are ignored by the DE. A CCS
> > > > +cache line
> > > > + * corresponds to an area of 4x1 tiles in the main surface. The main
> > > > +surface
> > > > + * pitch is required to be a multiple of 4 tile widths.
> > > > + */
> > > > +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
> > > > +fourcc_mod_code(INTEL, 8)
> > > > +
> > > > /*
> > > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > > > *
> > > > --
> > > > 2.20.1
> > > >
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
end of thread, other threads:[~2019-11-13 22:33 UTC | newest]
Thread overview: 34+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-10-28 20:40 [PATCH v6 00/10] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
2019-10-28 20:40 ` [Intel-gfx] " Radhakrishna Sripada
2019-10-28 20:40 ` [PATCH v6 01/10] drm/framebuffer: Format modifier for Intel Gen-12 render compression Radhakrishna Sripada
2019-10-28 20:40 ` [Intel-gfx] " Radhakrishna Sripada
2019-10-28 20:40 ` [PATCH v6 02/10] drm/i915: Use intel_tile_height() instead of re-implementing Radhakrishna Sripada
2019-10-28 20:40 ` [Intel-gfx] " Radhakrishna Sripada
2019-10-28 20:40 ` [PATCH v6 03/10] drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment Radhakrishna Sripada
2019-10-28 20:40 ` [Intel-gfx] " Radhakrishna Sripada
2019-10-28 20:40 ` [PATCH v6 04/10] drm/i915/tgl: Gen-12 render decompression Radhakrishna Sripada
2019-10-28 20:40 ` [Intel-gfx] " Radhakrishna Sripada
2019-10-28 20:40 ` [PATCH v6 05/10] drm/i915: Extract framebufer CCS offset checks into a function Radhakrishna Sripada
2019-10-28 20:40 ` [Intel-gfx] " Radhakrishna Sripada
2019-10-28 20:40 ` [PATCH v6 06/10] drm/framebuffer: Format modifier for Intel Gen-12 media compression Radhakrishna Sripada
2019-10-28 20:40 ` [Intel-gfx] " Radhakrishna Sripada
2019-10-28 20:40 ` [PATCH v6 07/10] drm/fb: Extend format_info member arrays to handle four planes Radhakrishna Sripada
2019-10-28 20:40 ` [Intel-gfx] " Radhakrishna Sripada
2019-10-28 20:40 ` [PATCH v6 08/10] Gen-12 display can decompress surfaces compressed by the media engine Radhakrishna Sripada
2019-10-28 20:40 ` [Intel-gfx] " Radhakrishna Sripada
2019-10-28 20:40 ` [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color Radhakrishna Sripada
2019-10-28 20:40 ` [Intel-gfx] " Radhakrishna Sripada
2019-10-30 0:05 ` Chery, Nanley G
2019-10-30 0:05 ` [Intel-gfx] " Chery, Nanley G
2019-11-01 7:00 ` Sripada, Radhakrishna
2019-11-01 7:00 ` [Intel-gfx] " Sripada, Radhakrishna
2019-11-12 17:40 ` Chery, Nanley G
2019-11-12 17:40 ` [Intel-gfx] " Chery, Nanley G
2019-11-13 22:33 ` Chery, Nanley G
2019-11-13 22:33 ` [Intel-gfx] " Chery, Nanley G
2019-10-28 20:40 ` [PATCH v6 10/10] drm/i915/tgl: Add Clear Color support for TGL Render Decompression Radhakrishna Sripada
2019-10-28 20:40 ` [Intel-gfx] " Radhakrishna Sripada
2019-10-29 0:02 ` ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev9) Patchwork
2019-10-29 0:02 ` [Intel-gfx] " Patchwork
2019-10-29 0:49 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-10-29 0:49 ` [Intel-gfx] " Patchwork
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