* [PATCH 0/5] tgl: MST support
@ 2019-10-30 1:24 ` Lucas De Marchi
0 siblings, 0 replies; 28+ messages in thread
From: Lucas De Marchi @ 2019-10-30 1:24 UTC (permalink / raw)
To: intel-gfx
Additional code to support more than one display when using MST with
TGL. It's still WIP! From what I could check on my tests we are correctly
tracking the master transcoder and setting it accordingly on
TRANS_DDI_FUNC_CTL and DP_TP_CTL.
I tried also setting MST mode on the slave's DP_TP_CTL. I could get the
second display to show up some times and we don't get stuck on "timeout
waiting for ACT" error message. This is not according to the spec
though, and it still doesn't work most of the time. So... I didn't add
it here.
I guess now I need another pair of eyes to check what I'm doing wrong
since continuing to stare at the spec and code isn't helping. José,
Imre?
José Roberto de Souza (2):
drm/i915: Add for_each_new_intel_connector_in_state()
drm/i915/tgl: Select master transcoder in DP MST
Lucas De Marchi (3):
drm/i915: add wrappers to get intel connector state
drm/i915/tgl: do not enable transcoder clock twice on MST
drm/i915: avoid reading DP_TP_CTL twice
drivers/gpu/drm/i915/display/intel_ddi.c | 54 +++---
drivers/gpu/drm/i915/display/intel_display.c | 16 ++
drivers/gpu/drm/i915/display/intel_display.h | 8 +
.../drm/i915/display/intel_display_types.h | 21 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 159 +++++++++++++++++-
drivers/gpu/drm/i915/display/intel_dp_mst.h | 2 +
6 files changed, 236 insertions(+), 24 deletions(-)
--
2.23.0
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [Intel-gfx] [PATCH 0/5] tgl: MST support
@ 2019-10-30 1:24 ` Lucas De Marchi
0 siblings, 0 replies; 28+ messages in thread
From: Lucas De Marchi @ 2019-10-30 1:24 UTC (permalink / raw)
To: intel-gfx
Additional code to support more than one display when using MST with
TGL. It's still WIP! From what I could check on my tests we are correctly
tracking the master transcoder and setting it accordingly on
TRANS_DDI_FUNC_CTL and DP_TP_CTL.
I tried also setting MST mode on the slave's DP_TP_CTL. I could get the
second display to show up some times and we don't get stuck on "timeout
waiting for ACT" error message. This is not according to the spec
though, and it still doesn't work most of the time. So... I didn't add
it here.
I guess now I need another pair of eyes to check what I'm doing wrong
since continuing to stare at the spec and code isn't helping. José,
Imre?
José Roberto de Souza (2):
drm/i915: Add for_each_new_intel_connector_in_state()
drm/i915/tgl: Select master transcoder in DP MST
Lucas De Marchi (3):
drm/i915: add wrappers to get intel connector state
drm/i915/tgl: do not enable transcoder clock twice on MST
drm/i915: avoid reading DP_TP_CTL twice
drivers/gpu/drm/i915/display/intel_ddi.c | 54 +++---
drivers/gpu/drm/i915/display/intel_display.c | 16 ++
drivers/gpu/drm/i915/display/intel_display.h | 8 +
.../drm/i915/display/intel_display_types.h | 21 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 159 +++++++++++++++++-
drivers/gpu/drm/i915/display/intel_dp_mst.h | 2 +
6 files changed, 236 insertions(+), 24 deletions(-)
--
2.23.0
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 1/5] drm/i915: Add for_each_new_intel_connector_in_state()
@ 2019-10-30 1:24 ` Lucas De Marchi
0 siblings, 0 replies; 28+ messages in thread
From: Lucas De Marchi @ 2019-10-30 1:24 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
The same macro as for_each_new_connector_in_state() but it uses
intel/i915 types instead of the drm ones.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190823082055.5992-11-lucas.demarchi@intel.com
---
drivers/gpu/drm/i915/display/intel_display.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index ca7ca2804d8b..fe598ec3cbdc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -452,6 +452,14 @@ enum phy_fia {
for_each_if ((plane_state = \
to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->base.state, &plane->base))))
+#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->base.num_connector; \
+ (__i)++) \
+ for_each_if ((__state)->base.connectors[__i].ptr && \
+ ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
+ (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
+
void intel_link_compute_m_n(u16 bpp, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
--
2.23.0
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^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Intel-gfx] [PATCH 1/5] drm/i915: Add for_each_new_intel_connector_in_state()
@ 2019-10-30 1:24 ` Lucas De Marchi
0 siblings, 0 replies; 28+ messages in thread
From: Lucas De Marchi @ 2019-10-30 1:24 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
The same macro as for_each_new_connector_in_state() but it uses
intel/i915 types instead of the drm ones.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190823082055.5992-11-lucas.demarchi@intel.com
---
drivers/gpu/drm/i915/display/intel_display.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index ca7ca2804d8b..fe598ec3cbdc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -452,6 +452,14 @@ enum phy_fia {
for_each_if ((plane_state = \
to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->base.state, &plane->base))))
+#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->base.num_connector; \
+ (__i)++) \
+ for_each_if ((__state)->base.connectors[__i].ptr && \
+ ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
+ (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
+
void intel_link_compute_m_n(u16 bpp, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
--
2.23.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 2/5] drm/i915: add wrappers to get intel connector state
@ 2019-10-30 1:24 ` Lucas De Marchi
0 siblings, 0 replies; 28+ messages in thread
From: Lucas De Marchi @ 2019-10-30 1:24 UTC (permalink / raw)
To: intel-gfx
Wrap drm_atomic_get_old_connector_state so we can get the
intel_digital_connector_state and make it easier to migrate to intel
types.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../gpu/drm/i915/display/intel_display_types.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 40184e823c84..a550abb48b3c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1527,6 +1527,24 @@ intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
&crtc->base));
}
+static inline struct intel_digital_connector_state *
+intel_atomic_get_new_connector_state(struct intel_atomic_state *state,
+ struct intel_connector *connector)
+{
+ return to_intel_digital_connector_state(
+ drm_atomic_get_new_connector_state(&state->base,
+ &connector->base));
+}
+
+static inline struct intel_digital_connector_state *
+intel_atomic_get_old_connector_state(struct intel_atomic_state *state,
+ struct intel_connector *connector)
+{
+ return to_intel_digital_connector_state(
+ drm_atomic_get_old_connector_state(&state->base,
+ &connector->base));
+}
+
/* intel_display.c */
static inline bool
intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
--
2.23.0
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^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Intel-gfx] [PATCH 2/5] drm/i915: add wrappers to get intel connector state
@ 2019-10-30 1:24 ` Lucas De Marchi
0 siblings, 0 replies; 28+ messages in thread
From: Lucas De Marchi @ 2019-10-30 1:24 UTC (permalink / raw)
To: intel-gfx
Wrap drm_atomic_get_old_connector_state so we can get the
intel_digital_connector_state and make it easier to migrate to intel
types.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../gpu/drm/i915/display/intel_display_types.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 40184e823c84..a550abb48b3c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1527,6 +1527,24 @@ intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
&crtc->base));
}
+static inline struct intel_digital_connector_state *
+intel_atomic_get_new_connector_state(struct intel_atomic_state *state,
+ struct intel_connector *connector)
+{
+ return to_intel_digital_connector_state(
+ drm_atomic_get_new_connector_state(&state->base,
+ &connector->base));
+}
+
+static inline struct intel_digital_connector_state *
+intel_atomic_get_old_connector_state(struct intel_atomic_state *state,
+ struct intel_connector *connector)
+{
+ return to_intel_digital_connector_state(
+ drm_atomic_get_old_connector_state(&state->base,
+ &connector->base));
+}
+
/* intel_display.c */
static inline bool
intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
--
2.23.0
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^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 3/5] drm/i915/tgl: do not enable transcoder clock twice on MST
@ 2019-10-30 1:24 ` Lucas De Marchi
0 siblings, 0 replies; 28+ messages in thread
From: Lucas De Marchi @ 2019-10-30 1:24 UTC (permalink / raw)
To: intel-gfx
For MST on Tiger Lake there are different moments when we need to
configure the transcoder clock select. For the first link this is in step
7.a of the spec, before training the link. For additional streams this
should be done as part of step 8.b after programming receiver VC Payload
ID.
Bspec: 49190
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 7 ++++---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 +++++++++++++---
2 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index fed7fc56dd92..2ce998529d08 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3462,9 +3462,10 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
icl_program_mg_dp_mode(dig_port, crtc_state);
/*
- * 7.a - Steps in this function should only be executed over MST
- * master, what will be taken in care by MST hook
- * intel_mst_pre_enable_dp()
+ * 7.a - single stream or multi-stream master transcoder: Configure
+ * Transcoder Clock Select. For additional MST streams this will be done
+ * by intel_mst_pre_enable_dp() after programming VC Payload ID through
+ * AUX.
*/
intel_ddi_enable_pipe_clock(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index a9962846a503..ad54618f6142 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -299,21 +299,23 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
to_intel_connector(conn_state->connector);
int ret;
u32 temp;
+ bool first_mst_stream;
/* MST encoders are bound to a crtc, not to a connector,
* force the mapping here for get_hw_state.
*/
connector->encoder = encoder;
intel_mst->connector = connector;
+ first_mst_stream = intel_dp->active_mst_links == 0;
DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
- if (intel_dp->active_mst_links == 0)
+ if (first_mst_stream)
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
- if (intel_dp->active_mst_links == 0)
+ if (first_mst_stream)
intel_dig_port->base.pre_enable(&intel_dig_port->base,
pipe_config, NULL);
@@ -330,7 +332,15 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr);
- intel_ddi_enable_pipe_clock(pipe_config);
+ /*
+ * Before Gen 12 this is not done as part of
+ * intel_dig_port->base.pre_enable() and should be done here. For
+ * Gen 12+ the step in which this should be done is different for the
+ * first MST stream, so it's done on the DDI for the first stream and
+ * here for the following ones.
+ */
+ if (INTEL_GEN(dev_priv) < 12 || !first_mst_stream)
+ intel_ddi_enable_pipe_clock(pipe_config);
}
static void intel_mst_enable_dp(struct intel_encoder *encoder,
--
2.23.0
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^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Intel-gfx] [PATCH 3/5] drm/i915/tgl: do not enable transcoder clock twice on MST
@ 2019-10-30 1:24 ` Lucas De Marchi
0 siblings, 0 replies; 28+ messages in thread
From: Lucas De Marchi @ 2019-10-30 1:24 UTC (permalink / raw)
To: intel-gfx
For MST on Tiger Lake there are different moments when we need to
configure the transcoder clock select. For the first link this is in step
7.a of the spec, before training the link. For additional streams this
should be done as part of step 8.b after programming receiver VC Payload
ID.
Bspec: 49190
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 7 ++++---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 +++++++++++++---
2 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index fed7fc56dd92..2ce998529d08 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3462,9 +3462,10 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
icl_program_mg_dp_mode(dig_port, crtc_state);
/*
- * 7.a - Steps in this function should only be executed over MST
- * master, what will be taken in care by MST hook
- * intel_mst_pre_enable_dp()
+ * 7.a - single stream or multi-stream master transcoder: Configure
+ * Transcoder Clock Select. For additional MST streams this will be done
+ * by intel_mst_pre_enable_dp() after programming VC Payload ID through
+ * AUX.
*/
intel_ddi_enable_pipe_clock(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index a9962846a503..ad54618f6142 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -299,21 +299,23 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
to_intel_connector(conn_state->connector);
int ret;
u32 temp;
+ bool first_mst_stream;
/* MST encoders are bound to a crtc, not to a connector,
* force the mapping here for get_hw_state.
*/
connector->encoder = encoder;
intel_mst->connector = connector;
+ first_mst_stream = intel_dp->active_mst_links == 0;
DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
- if (intel_dp->active_mst_links == 0)
+ if (first_mst_stream)
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
- if (intel_dp->active_mst_links == 0)
+ if (first_mst_stream)
intel_dig_port->base.pre_enable(&intel_dig_port->base,
pipe_config, NULL);
@@ -330,7 +332,15 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr);
- intel_ddi_enable_pipe_clock(pipe_config);
+ /*
+ * Before Gen 12 this is not done as part of
+ * intel_dig_port->base.pre_enable() and should be done here. For
+ * Gen 12+ the step in which this should be done is different for the
+ * first MST stream, so it's done on the DDI for the first stream and
+ * here for the following ones.
+ */
+ if (INTEL_GEN(dev_priv) < 12 || !first_mst_stream)
+ intel_ddi_enable_pipe_clock(pipe_config);
}
static void intel_mst_enable_dp(struct intel_encoder *encoder,
--
2.23.0
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^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 4/5] drm/i915: avoid reading DP_TP_CTL twice
@ 2019-10-30 1:24 ` Lucas De Marchi
0 siblings, 0 replies; 28+ messages in thread
From: Lucas De Marchi @ 2019-10-30 1:24 UTC (permalink / raw)
To: intel-gfx
Just avoid the additional read in case DP_TP_CTL is enabled:
read it once and save the value.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 33 ++++++++++++------------
1 file changed, 17 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 2ce998529d08..41b9b9a6772a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4148,37 +4148,38 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv =
to_i915(intel_dig_port->base.base.dev);
enum port port = intel_dig_port->base.port;
- u32 val;
+ u32 dp_tp_ctl, ddi_buf_ctl;
bool wait = false;
- if (I915_READ(intel_dp->regs.dp_tp_ctl) & DP_TP_CTL_ENABLE) {
- val = I915_READ(DDI_BUF_CTL(port));
- if (val & DDI_BUF_CTL_ENABLE) {
- val &= ~DDI_BUF_CTL_ENABLE;
- I915_WRITE(DDI_BUF_CTL(port), val);
+ dp_tp_ctl = I915_READ(intel_dp->regs.dp_tp_ctl);
+
+ if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
+ ddi_buf_ctl = I915_READ(DDI_BUF_CTL(port));
+ if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) {
+ I915_WRITE(DDI_BUF_CTL(port),
+ ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE);
wait = true;
}
- val = I915_READ(intel_dp->regs.dp_tp_ctl);
- val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
- val |= DP_TP_CTL_LINK_TRAIN_PAT1;
- I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
+ dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
+ dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;
+ I915_WRITE(intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
POSTING_READ(intel_dp->regs.dp_tp_ctl);
if (wait)
intel_wait_ddi_buf_idle(dev_priv, port);
}
- val = DP_TP_CTL_ENABLE |
- DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
+ dp_tp_ctl = DP_TP_CTL_ENABLE |
+ DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
if (intel_dp->link_mst)
- val |= DP_TP_CTL_MODE_MST;
+ dp_tp_ctl |= DP_TP_CTL_MODE_MST;
else {
- val |= DP_TP_CTL_MODE_SST;
+ dp_tp_ctl |= DP_TP_CTL_MODE_SST;
if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
- val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
+ dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
}
- I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
+ I915_WRITE(intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
POSTING_READ(intel_dp->regs.dp_tp_ctl);
intel_dp->DP |= DDI_BUF_CTL_ENABLE;
--
2.23.0
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^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Intel-gfx] [PATCH 4/5] drm/i915: avoid reading DP_TP_CTL twice
@ 2019-10-30 1:24 ` Lucas De Marchi
0 siblings, 0 replies; 28+ messages in thread
From: Lucas De Marchi @ 2019-10-30 1:24 UTC (permalink / raw)
To: intel-gfx
Just avoid the additional read in case DP_TP_CTL is enabled:
read it once and save the value.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 33 ++++++++++++------------
1 file changed, 17 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 2ce998529d08..41b9b9a6772a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4148,37 +4148,38 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv =
to_i915(intel_dig_port->base.base.dev);
enum port port = intel_dig_port->base.port;
- u32 val;
+ u32 dp_tp_ctl, ddi_buf_ctl;
bool wait = false;
- if (I915_READ(intel_dp->regs.dp_tp_ctl) & DP_TP_CTL_ENABLE) {
- val = I915_READ(DDI_BUF_CTL(port));
- if (val & DDI_BUF_CTL_ENABLE) {
- val &= ~DDI_BUF_CTL_ENABLE;
- I915_WRITE(DDI_BUF_CTL(port), val);
+ dp_tp_ctl = I915_READ(intel_dp->regs.dp_tp_ctl);
+
+ if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
+ ddi_buf_ctl = I915_READ(DDI_BUF_CTL(port));
+ if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) {
+ I915_WRITE(DDI_BUF_CTL(port),
+ ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE);
wait = true;
}
- val = I915_READ(intel_dp->regs.dp_tp_ctl);
- val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
- val |= DP_TP_CTL_LINK_TRAIN_PAT1;
- I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
+ dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
+ dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;
+ I915_WRITE(intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
POSTING_READ(intel_dp->regs.dp_tp_ctl);
if (wait)
intel_wait_ddi_buf_idle(dev_priv, port);
}
- val = DP_TP_CTL_ENABLE |
- DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
+ dp_tp_ctl = DP_TP_CTL_ENABLE |
+ DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
if (intel_dp->link_mst)
- val |= DP_TP_CTL_MODE_MST;
+ dp_tp_ctl |= DP_TP_CTL_MODE_MST;
else {
- val |= DP_TP_CTL_MODE_SST;
+ dp_tp_ctl |= DP_TP_CTL_MODE_SST;
if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
- val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
+ dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
}
- I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
+ I915_WRITE(intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
POSTING_READ(intel_dp->regs.dp_tp_ctl);
intel_dp->DP |= DDI_BUF_CTL_ENABLE;
--
2.23.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 5/5] drm/i915/tgl: Select master transcoder in DP MST
@ 2019-10-30 1:24 ` Lucas De Marchi
0 siblings, 0 replies; 28+ messages in thread
From: Lucas De Marchi @ 2019-10-30 1:24 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
On TGL the blending of all the streams have moved from DDI to
transcoder, so now every transcoder working over the same MST port must
send its stream to a master transcoder and master will send to DDI
respecting the time slots.
So here it is picking the lowest pipe/transcoder as it will be
enabled first and disabled last.
BSpec: 50493
BSpec: 49190
v2: Missed set mst_master_trans to TRANSCODER_INVALID when computing HSW
encoder config. HSW CRT hw state readout calls
hsw_crt_get_config()->intel_ddi_get_config() that will set
mst_master_trans to TRANSCODER_INVALID causing the mismatch when
verifying CRTC state after a modeset. (José)
v3: Add WARN_ON() requested by Jani.
Add FIXME. From Jani: double check
PIPE_CONF_CHECK_I(mst_master_trans) - it's now checking for all
platforms and MST and non-MST alike. Perhaps in general I'd like
the approach of only doing the readout when it's relevant, and only
checking the value when it's relevant.
v4 (Lucas): Revamp previous implementation:
- Make sure we only compute master once; the compute function will
be called for each crtc, so we don't need to recompute during check.
Now the check simply compares the master from before and after.
- Don't loop on all crtcs and connectors, we can just loop over the
connectors and find the lowest crtc
- Move the setting of INVALID_TRANSCODER around to make it similar
to the places where we got it added for master transport sync.
- Move all added code to use intel types
- Use REG_FIELD_GET()
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 14 +-
drivers/gpu/drm/i915/display/intel_display.c | 16 ++
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 143 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp_mst.h | 2 +
5 files changed, 176 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 41b9b9a6772a..2c0da46ac8e2 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1906,8 +1906,13 @@ intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
temp |= TRANS_DDI_MODE_SELECT_DP_MST;
temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
- if (INTEL_GEN(dev_priv) >= 12)
- temp |= TRANS_DDI_MST_TRANSPORT_SELECT(crtc_state->cpu_transcoder);
+ if (INTEL_GEN(dev_priv) >= 12) {
+ enum transcoder master =
+ crtc_state->mst_master_transcoder;
+
+ WARN_ON(master == INVALID_TRANSCODER);
+ temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
+ }
} else {
temp |= TRANS_DDI_MODE_SELECT_DP_SST;
temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
@@ -4304,6 +4309,11 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
pipe_config->lane_count =
((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ pipe_config->mst_master_transcoder =
+ REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
+
intel_dp_get_m_n(intel_crtc, pipe_config);
break;
default:
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e56a75c07043..4dd1ec1300f1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -46,6 +46,7 @@
#include "display/intel_crt.h"
#include "display/intel_ddi.h"
#include "display/intel_dp.h"
+#include "display/intel_dp_mst.h"
#include "display/intel_dsi.h"
#include "display/intel_dvo.h"
#include "display/intel_gmbus.h"
@@ -8896,6 +8897,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
pipe_config->shared_dpll = NULL;
pipe_config->master_transcoder = INVALID_TRANSCODER;
+ pipe_config->mst_master_transcoder = INVALID_TRANSCODER;
ret = false;
@@ -10087,6 +10089,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
pipe_config->shared_dpll = NULL;
pipe_config->master_transcoder = INVALID_TRANSCODER;
+ pipe_config->mst_master_transcoder = INVALID_TRANSCODER;
ret = false;
tmp = I915_READ(PIPECONF(crtc->pipe));
@@ -10602,6 +10605,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
intel_crtc_init_scalers(crtc, pipe_config);
pipe_config->master_transcoder = INVALID_TRANSCODER;
+ pipe_config->mst_master_transcoder = INVALID_TRANSCODER;
power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
@@ -12478,6 +12482,11 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
pipe_config->csc_mode, pipe_config->gamma_mode,
pipe_config->gamma_enable, pipe_config->csc_enable);
+ if (INTEL_GEN(dev_priv) >= 12 &&
+ intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
+ DRM_DEBUG_KMS("MST master transcoder: %s\n",
+ transcoder_name(pipe_config->mst_master_transcoder));
+
dump_planes:
if (!state)
return;
@@ -12694,6 +12703,8 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
return ret;
}
+ pipe_config->mst_master_transcoder = INVALID_TRANSCODER;
+
/* Pass our mode to the connectors and the CRTC to give them a chance to
* adjust it according to limitations or connector properties, and also
* a chance to reject the mode entirely.
@@ -13215,6 +13226,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_I(sync_mode_slaves_mask);
PIPE_CONF_CHECK_I(master_transcoder);
+ PIPE_CONF_CHECK_I(mst_master_transcoder);
#undef PIPE_CONF_CHECK_X
#undef PIPE_CONF_CHECK_I
@@ -14003,6 +14015,10 @@ static int intel_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
+ ret = intel_dp_mst_atomic_add_affected_crtcs(state);
+ if (ret)
+ return ret;
+
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
if (!needs_modeset(new_crtc_state))
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index a550abb48b3c..40753d1a29e5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1002,6 +1002,9 @@ struct intel_crtc_state {
/* Forward Error correction State */
bool fec_enable;
+ /* MST master transcoder for all streams, only used on TGL+ */
+ enum transcoder mst_master_transcoder;
+
/* Pointer to master transcoder in case of tiled displays */
enum transcoder master_transcoder;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index ad54618f6142..1c040de3a396 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -87,6 +87,50 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
return 0;
}
+/*
+ * Iterate over all the CRTCs and return the transcoder of the lowest CRTC that
+ * shares the same MST connector.
+ */
+void
+intel_dp_mst_compute_master_transcoder(struct intel_connector *mst_connector,
+ struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(crtc_state->base.crtc->dev);
+ struct intel_atomic_state *state =
+ to_intel_atomic_state(crtc_state->base.state);
+ enum transcoder mst_master_transcoder = crtc_state->cpu_transcoder;
+ struct intel_crtc_state *other_crtc_state;
+ struct intel_digital_connector_state *conn_state;
+ struct intel_connector *conn;
+ int i;
+
+ if (INTEL_GEN(i915) < 12)
+ return;
+
+ for_each_new_intel_connector_in_state(state, conn, conn_state, i) {
+ struct intel_crtc *crtc = to_intel_crtc(conn_state->base.crtc);
+
+ if (conn == mst_connector ||
+ conn->mst_port != mst_connector->mst_port ||
+ !crtc)
+ continue;
+
+ other_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+ if (!other_crtc_state->base.active)
+ continue;
+
+ if (other_crtc_state->cpu_transcoder < mst_master_transcoder)
+ mst_master_transcoder = other_crtc_state->cpu_transcoder;
+ }
+
+ crtc_state->mst_master_transcoder = mst_master_transcoder;
+
+ DRM_DEBUG_KMS("[CRTC:%d:%s] MST master transcoder: %s\n",
+ crtc_state->base.crtc->base.id,
+ crtc_state->base.crtc->name,
+ transcoder_name(mst_master_transcoder));
+}
+
static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
@@ -154,6 +198,42 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
+ intel_dp_mst_compute_master_transcoder(connector, pipe_config);
+
+ return 0;
+}
+
+static int
+intel_dp_mst_master_transcoder_check(struct intel_connector *connector,
+ struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct intel_digital_connector_state *new_conn_state =
+ intel_atomic_get_new_connector_state(state, connector);
+ struct intel_digital_connector_state *old_conn_state =
+ intel_atomic_get_old_connector_state(state, connector);
+ struct intel_crtc_state *new_crtc_state, *old_crtc_state;
+ struct intel_crtc *crtc;
+
+ if (INTEL_GEN(i915) < 12)
+ return 0;
+
+ /*
+ * A modeset will be triggered when checking other affected crtcs if
+ * this was connected to a master transcoder
+ */
+ if (!new_conn_state->base.crtc)
+ return 0;
+
+ crtc = to_intel_crtc(new_conn_state->base.crtc);
+ new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+ old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
+
+ if (!old_conn_state ||
+ new_crtc_state->mst_master_transcoder !=
+ old_crtc_state->mst_master_transcoder)
+ new_crtc_state->base.mode_changed = true;
+
return 0;
}
@@ -176,6 +256,11 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
if (ret)
return ret;
+ ret = intel_dp_mst_master_transcoder_check(intel_connector,
+ to_intel_atomic_state(state));
+ if (ret)
+ return ret;
+
if (!old_conn_state->crtc)
return 0;
@@ -706,3 +791,61 @@ intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port)
drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr);
/* encoders will get killed by normal cleanup */
}
+
+/**
+ * intel_dp_mst_atomic_add_affected_crtcs - Add all CRTCs that share the MST
+ * port with the CRTCs in the current atomic state.
+ * @state: state to add CRTCs
+ *
+ * We need to make the CRTCs trigger a call to atomic_check() to every connector
+ * attached to the CRTC in case a new master transcoder is needed.
+ */
+int intel_dp_mst_atomic_add_affected_crtcs(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_digital_connector_state *intel_conn_state;
+ struct drm_device *dev = state->base.dev;
+ struct intel_connector *intel_conn;
+ int i;
+
+ if (INTEL_GEN(dev_priv) < 12)
+ return 0;
+
+ for_each_new_intel_connector_in_state(state, intel_conn, intel_conn_state, i) {
+ struct drm_connector_list_iter conn_list_iter;
+ struct drm_connector *conn_iter;
+
+ if (!intel_conn->mst_port)
+ continue;
+
+ drm_connector_list_iter_begin(dev, &conn_list_iter);
+ drm_for_each_connector_iter(conn_iter, &conn_list_iter) {
+ struct drm_connector_state *conn_iter_state;
+ struct intel_connector *intel_conn_iter;
+ struct drm_crtc_state *crtc_state;
+
+ intel_conn_iter = to_intel_connector(conn_iter);
+
+ if (intel_conn_iter->mst_port != intel_conn->mst_port)
+ continue;
+
+ conn_iter_state = drm_atomic_get_connector_state(&state->base, conn_iter);
+ if (IS_ERR(conn_iter_state)) {
+ drm_connector_list_iter_end(&conn_list_iter);
+ return PTR_ERR(conn_iter_state);
+ }
+ if (!conn_iter_state->crtc)
+ continue;
+
+ crtc_state = drm_atomic_get_crtc_state(&state->base,
+ conn_iter_state->crtc);
+ if (IS_ERR(crtc_state)) {
+ drm_connector_list_iter_end(&conn_list_iter);
+ return PTR_ERR(crtc_state);
+ }
+ }
+ drm_connector_list_iter_end(&conn_list_iter);
+ }
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.h b/drivers/gpu/drm/i915/display/intel_dp_mst.h
index f660ad80db04..9e654f77a2d2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.h
@@ -7,9 +7,11 @@
#define __INTEL_DP_MST_H__
struct intel_digital_port;
+struct intel_atomic_state;
int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
int intel_dp_mst_encoder_active_links(struct intel_digital_port *intel_dig_port);
+int intel_dp_mst_atomic_add_affected_crtcs(struct intel_atomic_state *state);
#endif /* __INTEL_DP_MST_H__ */
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Intel-gfx] [PATCH 5/5] drm/i915/tgl: Select master transcoder in DP MST
@ 2019-10-30 1:24 ` Lucas De Marchi
0 siblings, 0 replies; 28+ messages in thread
From: Lucas De Marchi @ 2019-10-30 1:24 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
On TGL the blending of all the streams have moved from DDI to
transcoder, so now every transcoder working over the same MST port must
send its stream to a master transcoder and master will send to DDI
respecting the time slots.
So here it is picking the lowest pipe/transcoder as it will be
enabled first and disabled last.
BSpec: 50493
BSpec: 49190
v2: Missed set mst_master_trans to TRANSCODER_INVALID when computing HSW
encoder config. HSW CRT hw state readout calls
hsw_crt_get_config()->intel_ddi_get_config() that will set
mst_master_trans to TRANSCODER_INVALID causing the mismatch when
verifying CRTC state after a modeset. (José)
v3: Add WARN_ON() requested by Jani.
Add FIXME. From Jani: double check
PIPE_CONF_CHECK_I(mst_master_trans) - it's now checking for all
platforms and MST and non-MST alike. Perhaps in general I'd like
the approach of only doing the readout when it's relevant, and only
checking the value when it's relevant.
v4 (Lucas): Revamp previous implementation:
- Make sure we only compute master once; the compute function will
be called for each crtc, so we don't need to recompute during check.
Now the check simply compares the master from before and after.
- Don't loop on all crtcs and connectors, we can just loop over the
connectors and find the lowest crtc
- Move the setting of INVALID_TRANSCODER around to make it similar
to the places where we got it added for master transport sync.
- Move all added code to use intel types
- Use REG_FIELD_GET()
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 14 +-
drivers/gpu/drm/i915/display/intel_display.c | 16 ++
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 143 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp_mst.h | 2 +
5 files changed, 176 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 41b9b9a6772a..2c0da46ac8e2 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1906,8 +1906,13 @@ intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
temp |= TRANS_DDI_MODE_SELECT_DP_MST;
temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
- if (INTEL_GEN(dev_priv) >= 12)
- temp |= TRANS_DDI_MST_TRANSPORT_SELECT(crtc_state->cpu_transcoder);
+ if (INTEL_GEN(dev_priv) >= 12) {
+ enum transcoder master =
+ crtc_state->mst_master_transcoder;
+
+ WARN_ON(master == INVALID_TRANSCODER);
+ temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
+ }
} else {
temp |= TRANS_DDI_MODE_SELECT_DP_SST;
temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
@@ -4304,6 +4309,11 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
pipe_config->lane_count =
((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ pipe_config->mst_master_transcoder =
+ REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
+
intel_dp_get_m_n(intel_crtc, pipe_config);
break;
default:
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e56a75c07043..4dd1ec1300f1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -46,6 +46,7 @@
#include "display/intel_crt.h"
#include "display/intel_ddi.h"
#include "display/intel_dp.h"
+#include "display/intel_dp_mst.h"
#include "display/intel_dsi.h"
#include "display/intel_dvo.h"
#include "display/intel_gmbus.h"
@@ -8896,6 +8897,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
pipe_config->shared_dpll = NULL;
pipe_config->master_transcoder = INVALID_TRANSCODER;
+ pipe_config->mst_master_transcoder = INVALID_TRANSCODER;
ret = false;
@@ -10087,6 +10089,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
pipe_config->shared_dpll = NULL;
pipe_config->master_transcoder = INVALID_TRANSCODER;
+ pipe_config->mst_master_transcoder = INVALID_TRANSCODER;
ret = false;
tmp = I915_READ(PIPECONF(crtc->pipe));
@@ -10602,6 +10605,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
intel_crtc_init_scalers(crtc, pipe_config);
pipe_config->master_transcoder = INVALID_TRANSCODER;
+ pipe_config->mst_master_transcoder = INVALID_TRANSCODER;
power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
@@ -12478,6 +12482,11 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
pipe_config->csc_mode, pipe_config->gamma_mode,
pipe_config->gamma_enable, pipe_config->csc_enable);
+ if (INTEL_GEN(dev_priv) >= 12 &&
+ intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
+ DRM_DEBUG_KMS("MST master transcoder: %s\n",
+ transcoder_name(pipe_config->mst_master_transcoder));
+
dump_planes:
if (!state)
return;
@@ -12694,6 +12703,8 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
return ret;
}
+ pipe_config->mst_master_transcoder = INVALID_TRANSCODER;
+
/* Pass our mode to the connectors and the CRTC to give them a chance to
* adjust it according to limitations or connector properties, and also
* a chance to reject the mode entirely.
@@ -13215,6 +13226,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_I(sync_mode_slaves_mask);
PIPE_CONF_CHECK_I(master_transcoder);
+ PIPE_CONF_CHECK_I(mst_master_transcoder);
#undef PIPE_CONF_CHECK_X
#undef PIPE_CONF_CHECK_I
@@ -14003,6 +14015,10 @@ static int intel_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
+ ret = intel_dp_mst_atomic_add_affected_crtcs(state);
+ if (ret)
+ return ret;
+
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
if (!needs_modeset(new_crtc_state))
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index a550abb48b3c..40753d1a29e5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1002,6 +1002,9 @@ struct intel_crtc_state {
/* Forward Error correction State */
bool fec_enable;
+ /* MST master transcoder for all streams, only used on TGL+ */
+ enum transcoder mst_master_transcoder;
+
/* Pointer to master transcoder in case of tiled displays */
enum transcoder master_transcoder;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index ad54618f6142..1c040de3a396 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -87,6 +87,50 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
return 0;
}
+/*
+ * Iterate over all the CRTCs and return the transcoder of the lowest CRTC that
+ * shares the same MST connector.
+ */
+void
+intel_dp_mst_compute_master_transcoder(struct intel_connector *mst_connector,
+ struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(crtc_state->base.crtc->dev);
+ struct intel_atomic_state *state =
+ to_intel_atomic_state(crtc_state->base.state);
+ enum transcoder mst_master_transcoder = crtc_state->cpu_transcoder;
+ struct intel_crtc_state *other_crtc_state;
+ struct intel_digital_connector_state *conn_state;
+ struct intel_connector *conn;
+ int i;
+
+ if (INTEL_GEN(i915) < 12)
+ return;
+
+ for_each_new_intel_connector_in_state(state, conn, conn_state, i) {
+ struct intel_crtc *crtc = to_intel_crtc(conn_state->base.crtc);
+
+ if (conn == mst_connector ||
+ conn->mst_port != mst_connector->mst_port ||
+ !crtc)
+ continue;
+
+ other_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+ if (!other_crtc_state->base.active)
+ continue;
+
+ if (other_crtc_state->cpu_transcoder < mst_master_transcoder)
+ mst_master_transcoder = other_crtc_state->cpu_transcoder;
+ }
+
+ crtc_state->mst_master_transcoder = mst_master_transcoder;
+
+ DRM_DEBUG_KMS("[CRTC:%d:%s] MST master transcoder: %s\n",
+ crtc_state->base.crtc->base.id,
+ crtc_state->base.crtc->name,
+ transcoder_name(mst_master_transcoder));
+}
+
static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
@@ -154,6 +198,42 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
+ intel_dp_mst_compute_master_transcoder(connector, pipe_config);
+
+ return 0;
+}
+
+static int
+intel_dp_mst_master_transcoder_check(struct intel_connector *connector,
+ struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct intel_digital_connector_state *new_conn_state =
+ intel_atomic_get_new_connector_state(state, connector);
+ struct intel_digital_connector_state *old_conn_state =
+ intel_atomic_get_old_connector_state(state, connector);
+ struct intel_crtc_state *new_crtc_state, *old_crtc_state;
+ struct intel_crtc *crtc;
+
+ if (INTEL_GEN(i915) < 12)
+ return 0;
+
+ /*
+ * A modeset will be triggered when checking other affected crtcs if
+ * this was connected to a master transcoder
+ */
+ if (!new_conn_state->base.crtc)
+ return 0;
+
+ crtc = to_intel_crtc(new_conn_state->base.crtc);
+ new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+ old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
+
+ if (!old_conn_state ||
+ new_crtc_state->mst_master_transcoder !=
+ old_crtc_state->mst_master_transcoder)
+ new_crtc_state->base.mode_changed = true;
+
return 0;
}
@@ -176,6 +256,11 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
if (ret)
return ret;
+ ret = intel_dp_mst_master_transcoder_check(intel_connector,
+ to_intel_atomic_state(state));
+ if (ret)
+ return ret;
+
if (!old_conn_state->crtc)
return 0;
@@ -706,3 +791,61 @@ intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port)
drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr);
/* encoders will get killed by normal cleanup */
}
+
+/**
+ * intel_dp_mst_atomic_add_affected_crtcs - Add all CRTCs that share the MST
+ * port with the CRTCs in the current atomic state.
+ * @state: state to add CRTCs
+ *
+ * We need to make the CRTCs trigger a call to atomic_check() to every connector
+ * attached to the CRTC in case a new master transcoder is needed.
+ */
+int intel_dp_mst_atomic_add_affected_crtcs(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_digital_connector_state *intel_conn_state;
+ struct drm_device *dev = state->base.dev;
+ struct intel_connector *intel_conn;
+ int i;
+
+ if (INTEL_GEN(dev_priv) < 12)
+ return 0;
+
+ for_each_new_intel_connector_in_state(state, intel_conn, intel_conn_state, i) {
+ struct drm_connector_list_iter conn_list_iter;
+ struct drm_connector *conn_iter;
+
+ if (!intel_conn->mst_port)
+ continue;
+
+ drm_connector_list_iter_begin(dev, &conn_list_iter);
+ drm_for_each_connector_iter(conn_iter, &conn_list_iter) {
+ struct drm_connector_state *conn_iter_state;
+ struct intel_connector *intel_conn_iter;
+ struct drm_crtc_state *crtc_state;
+
+ intel_conn_iter = to_intel_connector(conn_iter);
+
+ if (intel_conn_iter->mst_port != intel_conn->mst_port)
+ continue;
+
+ conn_iter_state = drm_atomic_get_connector_state(&state->base, conn_iter);
+ if (IS_ERR(conn_iter_state)) {
+ drm_connector_list_iter_end(&conn_list_iter);
+ return PTR_ERR(conn_iter_state);
+ }
+ if (!conn_iter_state->crtc)
+ continue;
+
+ crtc_state = drm_atomic_get_crtc_state(&state->base,
+ conn_iter_state->crtc);
+ if (IS_ERR(crtc_state)) {
+ drm_connector_list_iter_end(&conn_list_iter);
+ return PTR_ERR(crtc_state);
+ }
+ }
+ drm_connector_list_iter_end(&conn_list_iter);
+ }
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.h b/drivers/gpu/drm/i915/display/intel_dp_mst.h
index f660ad80db04..9e654f77a2d2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.h
@@ -7,9 +7,11 @@
#define __INTEL_DP_MST_H__
struct intel_digital_port;
+struct intel_atomic_state;
int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
int intel_dp_mst_encoder_active_links(struct intel_digital_port *intel_dig_port);
+int intel_dp_mst_atomic_add_affected_crtcs(struct intel_atomic_state *state);
#endif /* __INTEL_DP_MST_H__ */
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for tgl: MST support
@ 2019-10-30 3:24 ` Patchwork
0 siblings, 0 replies; 28+ messages in thread
From: Patchwork @ 2019-10-30 3:24 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: tgl: MST support
URL : https://patchwork.freedesktop.org/series/68749/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
dd2dcb37cff0 drm/i915: Add for_each_new_intel_connector_in_state()
-:26: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#26: FILE: drivers/gpu/drm/i915/display/intel_display.h:455:
+#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->base.num_connector; \
+ (__i)++) \
+ for_each_if ((__state)->base.connectors[__i].ptr && \
+ ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
+ (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
-:26: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible side-effects?
#26: FILE: drivers/gpu/drm/i915/display/intel_display.h:455:
+#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->base.num_connector; \
+ (__i)++) \
+ for_each_if ((__state)->base.connectors[__i].ptr && \
+ ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
+ (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
-:26: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#26: FILE: drivers/gpu/drm/i915/display/intel_display.h:455:
+#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->base.num_connector; \
+ (__i)++) \
+ for_each_if ((__state)->base.connectors[__i].ptr && \
+ ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
+ (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
-:30: WARNING:SPACING: space prohibited between function name and open parenthesis '('
#30: FILE: drivers/gpu/drm/i915/display/intel_display.h:459:
+ for_each_if ((__state)->base.connectors[__i].ptr && \
-:31: WARNING:LONG_LINE: line over 100 characters
#31: FILE: drivers/gpu/drm/i915/display/intel_display.h:460:
+ ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
-:32: WARNING:LONG_LINE: line over 100 characters
#32: FILE: drivers/gpu/drm/i915/display/intel_display.h:461:
+ (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
total: 1 errors, 3 warnings, 2 checks, 14 lines checked
19dd8fd8abe5 drm/i915: add wrappers to get intel connector state
-:24: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#24: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:1534:
+ return to_intel_digital_connector_state(
-:26: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#26: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:1536:
+ drm_atomic_get_new_connector_state(&state->base,
+ &connector->base));
-:33: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#33: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:1543:
+ return to_intel_digital_connector_state(
-:35: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#35: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:1545:
+ drm_atomic_get_old_connector_state(&state->base,
+ &connector->base));
total: 0 errors, 0 warnings, 4 checks, 24 lines checked
86b8e6f1be04 drm/i915/tgl: do not enable transcoder clock twice on MST
4bd25aeecad6 drm/i915: avoid reading DP_TP_CTL twice
a52f9afe98d1 drm/i915/tgl: Select master transcoder in DP MST
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for tgl: MST support
@ 2019-10-30 3:24 ` Patchwork
0 siblings, 0 replies; 28+ messages in thread
From: Patchwork @ 2019-10-30 3:24 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: tgl: MST support
URL : https://patchwork.freedesktop.org/series/68749/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
dd2dcb37cff0 drm/i915: Add for_each_new_intel_connector_in_state()
-:26: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#26: FILE: drivers/gpu/drm/i915/display/intel_display.h:455:
+#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->base.num_connector; \
+ (__i)++) \
+ for_each_if ((__state)->base.connectors[__i].ptr && \
+ ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
+ (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
-:26: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible side-effects?
#26: FILE: drivers/gpu/drm/i915/display/intel_display.h:455:
+#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->base.num_connector; \
+ (__i)++) \
+ for_each_if ((__state)->base.connectors[__i].ptr && \
+ ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
+ (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
-:26: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#26: FILE: drivers/gpu/drm/i915/display/intel_display.h:455:
+#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->base.num_connector; \
+ (__i)++) \
+ for_each_if ((__state)->base.connectors[__i].ptr && \
+ ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
+ (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
-:30: WARNING:SPACING: space prohibited between function name and open parenthesis '('
#30: FILE: drivers/gpu/drm/i915/display/intel_display.h:459:
+ for_each_if ((__state)->base.connectors[__i].ptr && \
-:31: WARNING:LONG_LINE: line over 100 characters
#31: FILE: drivers/gpu/drm/i915/display/intel_display.h:460:
+ ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
-:32: WARNING:LONG_LINE: line over 100 characters
#32: FILE: drivers/gpu/drm/i915/display/intel_display.h:461:
+ (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
total: 1 errors, 3 warnings, 2 checks, 14 lines checked
19dd8fd8abe5 drm/i915: add wrappers to get intel connector state
-:24: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#24: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:1534:
+ return to_intel_digital_connector_state(
-:26: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#26: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:1536:
+ drm_atomic_get_new_connector_state(&state->base,
+ &connector->base));
-:33: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#33: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:1543:
+ return to_intel_digital_connector_state(
-:35: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#35: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:1545:
+ drm_atomic_get_old_connector_state(&state->base,
+ &connector->base));
total: 0 errors, 0 warnings, 4 checks, 24 lines checked
86b8e6f1be04 drm/i915/tgl: do not enable transcoder clock twice on MST
4bd25aeecad6 drm/i915: avoid reading DP_TP_CTL twice
a52f9afe98d1 drm/i915/tgl: Select master transcoder in DP MST
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread
* ✗ Fi.CI.SPARSE: warning for tgl: MST support
@ 2019-10-30 3:27 ` Patchwork
0 siblings, 0 replies; 28+ messages in thread
From: Patchwork @ 2019-10-30 3:27 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: tgl: MST support
URL : https://patchwork.freedesktop.org/series/68749/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Add for_each_new_intel_connector_in_state()
Okay!
Commit: drm/i915: add wrappers to get intel connector state
Okay!
Commit: drm/i915/tgl: do not enable transcoder clock twice on MST
Okay!
Commit: drm/i915: avoid reading DP_TP_CTL twice
Okay!
Commit: drm/i915/tgl: Select master transcoder in DP MST
+drivers/gpu/drm/i915/display/intel_dp_mst.c:95:1: warning: symbol 'intel_dp_mst_compute_master_transcoder' was not declared. Should it be static?
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for tgl: MST support
@ 2019-10-30 3:27 ` Patchwork
0 siblings, 0 replies; 28+ messages in thread
From: Patchwork @ 2019-10-30 3:27 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: tgl: MST support
URL : https://patchwork.freedesktop.org/series/68749/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Add for_each_new_intel_connector_in_state()
Okay!
Commit: drm/i915: add wrappers to get intel connector state
Okay!
Commit: drm/i915/tgl: do not enable transcoder clock twice on MST
Okay!
Commit: drm/i915: avoid reading DP_TP_CTL twice
Okay!
Commit: drm/i915/tgl: Select master transcoder in DP MST
+drivers/gpu/drm/i915/display/intel_dp_mst.c:95:1: warning: symbol 'intel_dp_mst_compute_master_transcoder' was not declared. Should it be static?
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread
* ✓ Fi.CI.BAT: success for tgl: MST support
@ 2019-10-30 3:51 ` Patchwork
0 siblings, 0 replies; 28+ messages in thread
From: Patchwork @ 2019-10-30 3:51 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: tgl: MST support
URL : https://patchwork.freedesktop.org/series/68749/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7221 -> Patchwork_15066
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/index.html
Known issues
------------
Here are the changes found in Patchwork_15066 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_close_race@basic-threads:
- fi-cml-u2: [PASS][1] -> [INCOMPLETE][2] ([fdo#110566])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/fi-cml-u2/igt@gem_close_race@basic-threads.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/fi-cml-u2/igt@gem_close_race@basic-threads.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +2 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/fi-icl-u3/igt@gem_exec_suspend@basic-s4-devices.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/fi-icl-u3/igt@gem_exec_suspend@basic-s4-devices.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-icl-u2: [PASS][5] -> [FAIL][6] ([fdo#109570])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/fi-icl-u2/igt@kms_chamelium@hdmi-crc-fast.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/fi-icl-u2/igt@kms_chamelium@hdmi-crc-fast.html
#### Possible fixes ####
* igt@gem_exec_gttfill@basic:
- {fi-tgl-u}: [INCOMPLETE][7] ([fdo#111593]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/fi-tgl-u/igt@gem_exec_gttfill@basic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/fi-tgl-u/igt@gem_exec_gttfill@basic.html
* igt@gem_flink_basic@double-flink:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10] +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/fi-icl-u3/igt@gem_flink_basic@double-flink.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/fi-icl-u3/igt@gem_flink_basic@double-flink.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- {fi-icl-dsi}: [INCOMPLETE][11] ([fdo#107713] / [fdo#108840]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/fi-icl-dsi/igt@i915_pm_rpm@basic-pci-d3-state.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/fi-icl-dsi/igt@i915_pm_rpm@basic-pci-d3-state.html
#### Warnings ####
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][13] ([fdo#111407]) -> [FAIL][14] ([fdo#111045] / [fdo#111096])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109570]: https://bugs.freedesktop.org/show_bug.cgi?id=109570
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
Participating hosts (50 -> 43)
------------------------------
Additional (1): fi-kbl-soraka
Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-apl-guc fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7221 -> Patchwork_15066
CI-20190529: 20190529
CI_DRM_7221: 2892915176b11a8afe7a4dfcbe2e49d498a0cf85 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5251: 6d30ec2314f22f465113f7a972944fee546ecbd9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15066: a52f9afe98d1080a3b6c70f1dbe91ad98ed12c30 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a52f9afe98d1 drm/i915/tgl: Select master transcoder in DP MST
4bd25aeecad6 drm/i915: avoid reading DP_TP_CTL twice
86b8e6f1be04 drm/i915/tgl: do not enable transcoder clock twice on MST
19dd8fd8abe5 drm/i915: add wrappers to get intel connector state
dd2dcb37cff0 drm/i915: Add for_each_new_intel_connector_in_state()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for tgl: MST support
@ 2019-10-30 3:51 ` Patchwork
0 siblings, 0 replies; 28+ messages in thread
From: Patchwork @ 2019-10-30 3:51 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: tgl: MST support
URL : https://patchwork.freedesktop.org/series/68749/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7221 -> Patchwork_15066
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/index.html
Known issues
------------
Here are the changes found in Patchwork_15066 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_close_race@basic-threads:
- fi-cml-u2: [PASS][1] -> [INCOMPLETE][2] ([fdo#110566])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/fi-cml-u2/igt@gem_close_race@basic-threads.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/fi-cml-u2/igt@gem_close_race@basic-threads.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +2 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/fi-icl-u3/igt@gem_exec_suspend@basic-s4-devices.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/fi-icl-u3/igt@gem_exec_suspend@basic-s4-devices.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-icl-u2: [PASS][5] -> [FAIL][6] ([fdo#109570])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/fi-icl-u2/igt@kms_chamelium@hdmi-crc-fast.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/fi-icl-u2/igt@kms_chamelium@hdmi-crc-fast.html
#### Possible fixes ####
* igt@gem_exec_gttfill@basic:
- {fi-tgl-u}: [INCOMPLETE][7] ([fdo#111593]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/fi-tgl-u/igt@gem_exec_gttfill@basic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/fi-tgl-u/igt@gem_exec_gttfill@basic.html
* igt@gem_flink_basic@double-flink:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10] +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/fi-icl-u3/igt@gem_flink_basic@double-flink.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/fi-icl-u3/igt@gem_flink_basic@double-flink.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- {fi-icl-dsi}: [INCOMPLETE][11] ([fdo#107713] / [fdo#108840]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/fi-icl-dsi/igt@i915_pm_rpm@basic-pci-d3-state.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/fi-icl-dsi/igt@i915_pm_rpm@basic-pci-d3-state.html
#### Warnings ####
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][13] ([fdo#111407]) -> [FAIL][14] ([fdo#111045] / [fdo#111096])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109570]: https://bugs.freedesktop.org/show_bug.cgi?id=109570
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
Participating hosts (50 -> 43)
------------------------------
Additional (1): fi-kbl-soraka
Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-apl-guc fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7221 -> Patchwork_15066
CI-20190529: 20190529
CI_DRM_7221: 2892915176b11a8afe7a4dfcbe2e49d498a0cf85 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5251: 6d30ec2314f22f465113f7a972944fee546ecbd9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15066: a52f9afe98d1080a3b6c70f1dbe91ad98ed12c30 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a52f9afe98d1 drm/i915/tgl: Select master transcoder in DP MST
4bd25aeecad6 drm/i915: avoid reading DP_TP_CTL twice
86b8e6f1be04 drm/i915/tgl: do not enable transcoder clock twice on MST
19dd8fd8abe5 drm/i915: add wrappers to get intel connector state
dd2dcb37cff0 drm/i915: Add for_each_new_intel_connector_in_state()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread
* ✓ Fi.CI.IGT: success for tgl: MST support
@ 2019-10-31 8:00 ` Patchwork
0 siblings, 0 replies; 28+ messages in thread
From: Patchwork @ 2019-10-31 8:00 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: tgl: MST support
URL : https://patchwork.freedesktop.org/series/68749/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7221_full -> Patchwork_15066_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15066_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_ctx_persistence@vcs2-persistence}:
- {shard-tglb}: NOTRUN -> [SKIP][1] +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-tglb7/igt@gem_ctx_persistence@vcs2-persistence.html
* {igt@gem_ctx_persistence@vecs0-queued}:
- shard-apl: NOTRUN -> [FAIL][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-apl8/igt@gem_ctx_persistence@vecs0-queued.html
Known issues
------------
Here are the changes found in Patchwork_15066_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_switch@vcs1:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#112080]) +6 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb2/igt@gem_ctx_switch@vcs1.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb8/igt@gem_ctx_switch@vcs1.html
* igt@gem_eio@reset-stress:
- shard-snb: [PASS][5] -> [FAIL][6] ([fdo#109661])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-snb4/igt@gem_eio@reset-stress.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-snb6/igt@gem_eio@reset-stress.html
* igt@gem_exec_reloc@basic-cpu-read-active:
- shard-skl: [PASS][7] -> [DMESG-WARN][8] ([fdo#106107])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-skl5/igt@gem_exec_reloc@basic-cpu-read-active.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-skl5/igt@gem_exec_reloc@basic-cpu-read-active.html
* igt@gem_exec_schedule@independent-bsd2:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +12 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb4/igt@gem_exec_schedule@independent-bsd2.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb5/igt@gem_exec_schedule@independent-bsd2.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112146]) +4 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb6/igt@gem_exec_schedule@preemptive-hang-bsd.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb4/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gem_linear_blits@normal:
- shard-apl: [PASS][13] -> [INCOMPLETE][14] ([fdo#103927])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-apl6/igt@gem_linear_blits@normal.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-apl2/igt@gem_linear_blits@normal.html
* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-iclb: [PASS][15] -> [INCOMPLETE][16] ([fdo#107713] / [fdo#109801])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb1/igt@gem_ppgtt@blt-vs-render-ctxn.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb7/igt@gem_ppgtt@blt-vs-render-ctxn.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
- shard-hsw: [PASS][17] -> [DMESG-WARN][18] ([fdo#111870])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-hsw5/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-hsw2/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
- shard-snb: [PASS][19] -> [DMESG-WARN][20] ([fdo#111870])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-snb2/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-snb2/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-apl: [PASS][21] -> [DMESG-WARN][22] ([fdo#108566]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-apl1/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-apl4/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-hsw: [PASS][23] -> [FAIL][24] ([fdo#105767])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt:
- shard-iclb: [PASS][25] -> [FAIL][26] ([fdo#103167]) +5 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-kbl: [PASS][27] -> [DMESG-WARN][28] ([fdo#108566]) +6 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-kbl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [PASS][29] -> [FAIL][30] ([fdo#108145])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [PASS][31] -> [SKIP][32] ([fdo#109441]) +2 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb8/igt@kms_psr@psr2_no_drrs.html
* igt@tools_test@tools_test:
- shard-iclb: [PASS][33] -> [SKIP][34] ([fdo#109352])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb1/igt@tools_test@tools_test.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb2/igt@tools_test@tools_test.html
#### Possible fixes ####
* igt@gem_busy@busy-vcs1:
- shard-iclb: [SKIP][35] ([fdo#112080]) -> [PASS][36] +9 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb6/igt@gem_busy@busy-vcs1.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb4/igt@gem_busy@busy-vcs1.html
* igt@gem_ctx_isolation@vcs1-none:
- shard-iclb: [SKIP][37] ([fdo#109276] / [fdo#112080]) -> [PASS][38] +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb5/igt@gem_ctx_isolation@vcs1-none.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb1/igt@gem_ctx_isolation@vcs1-none.html
* {igt@gem_ctx_persistence@rcs0-queued}:
- {shard-tglb}: [FAIL][39] -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-tglb5/igt@gem_ctx_persistence@rcs0-queued.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-tglb5/igt@gem_ctx_persistence@rcs0-queued.html
* igt@gem_exec_schedule@out-order-bsd2:
- shard-iclb: [SKIP][41] ([fdo#109276]) -> [PASS][42] +14 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb7/igt@gem_exec_schedule@out-order-bsd2.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb1/igt@gem_exec_schedule@out-order-bsd2.html
* igt@gem_exec_schedule@pi-ringfull-bsd:
- shard-iclb: [SKIP][43] ([fdo#112146]) -> [PASS][44] +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb2/igt@gem_exec_schedule@pi-ringfull-bsd.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb8/igt@gem_exec_schedule@pi-ringfull-bsd.html
* igt@gem_exec_schedule@preempt-queue-chain-bsd1:
- {shard-tglb}: [INCOMPLETE][45] ([fdo#111606] / [fdo#111677]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-tglb6/igt@gem_exec_schedule@preempt-queue-chain-bsd1.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-tglb5/igt@gem_exec_schedule@preempt-queue-chain-bsd1.html
* igt@gem_exec_schedule@preempt-queue-vebox:
- {shard-tglb}: [INCOMPLETE][47] ([fdo#111677]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-tglb6/igt@gem_exec_schedule@preempt-queue-vebox.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-tglb7/igt@gem_exec_schedule@preempt-queue-vebox.html
* {igt@gem_exec_suspend@basic-s0}:
- {shard-tglb}: [INCOMPLETE][49] ([fdo#111832]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-tglb1/igt@gem_exec_suspend@basic-s0.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-tglb5/igt@gem_exec_suspend@basic-s0.html
* igt@gem_persistent_relocs@forked-interruptible-thrashing:
- shard-hsw: [FAIL][51] ([fdo#112037]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-hsw7/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-hsw1/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
* igt@gem_softpin@noreloc-s3:
- shard-iclb: [DMESG-WARN][53] ([fdo#111764]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb2/igt@gem_softpin@noreloc-s3.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb8/igt@gem_softpin@noreloc-s3.html
- shard-skl: [INCOMPLETE][55] ([fdo#104108]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-skl2/igt@gem_softpin@noreloc-s3.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-skl6/igt@gem_softpin@noreloc-s3.html
* igt@gem_sync@basic-all:
- {shard-tglb}: [INCOMPLETE][57] ([fdo#111647]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-tglb6/igt@gem_sync@basic-all.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-tglb1/igt@gem_sync@basic-all.html
* {igt@i915_pm_dc@dc6-dpms}:
- shard-iclb: [FAIL][59] ([fdo#110548]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb5/igt@i915_pm_dc@dc6-dpms.html
* igt@kms_busy@extended-modeset-hang-newfb-render-d:
- {shard-tglb}: [INCOMPLETE][61] -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-tglb3/igt@kms_busy@extended-modeset-hang-newfb-render-d.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-tglb6/igt@kms_busy@extended-modeset-hang-newfb-render-d.html
* igt@kms_cursor_legacy@pipe-a-forked-move:
- shard-apl: [INCOMPLETE][63] ([fdo#103927]) -> [PASS][64] +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-apl4/igt@kms_cursor_legacy@pipe-a-forked-move.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-apl8/igt@kms_cursor_legacy@pipe-a-forked-move.html
* igt@kms_fbcon_fbt@fbc-suspend:
- {shard-tglb}: [INCOMPLETE][65] ([fdo#111747] / [fdo#111832] / [fdo#111850]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-tglb5/igt@kms_fbcon_fbt@fbc-suspend.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-tglb6/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-apl: [DMESG-WARN][67] ([fdo#108566]) -> [PASS][68] +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible.html
- shard-kbl: [DMESG-WARN][69] ([fdo#108566]) -> [PASS][70] +4 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack:
- {shard-tglb}: [FAIL][71] ([fdo#103167]) -> [PASS][72] +3 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html
* igt@kms_frontbuffer_tracking@fbc-tilingchange:
- shard-iclb: [FAIL][73] ([fdo#103167]) -> [PASS][74] +5 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-tilingchange.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-tilingchange.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- {shard-tglb}: [INCOMPLETE][75] ([fdo#111832] / [fdo#111850]) -> [PASS][76] +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-tglb8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-tglb6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [FAIL][77] ([fdo#108145]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [FAIL][79] ([fdo#103166]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-y.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb2/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [SKIP][81] ([fdo#109642] / [fdo#111068]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb6/igt@kms_psr2_su@frontbuffer.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [SKIP][83] ([fdo#109441]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb1/igt@kms_psr@psr2_cursor_render.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
* igt@kms_vblank@pipe-c-query-idle-hang:
- {shard-tglb}: [INCOMPLETE][85] ([fdo#111747]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-tglb5/igt@kms_vblank@pipe-c-query-idle-hang.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-tglb7/igt@kms_vblank@pipe-c-query-idle-hang.html
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- {shard-tglb}: [INCOMPLETE][87] ([fdo#111850]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-tglb3/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-tglb8/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [SKIP][89] ([fdo#109276] / [fdo#112080]) -> [FAIL][90] ([fdo#111329])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb5/igt@gem_ctx_isolation@vcs1-nonpriv.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb1/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@gem_mocs_settings@mocs-reset-bsd2:
- shard-iclb: [FAIL][91] ([fdo#111330]) -> [SKIP][92] ([fdo#109276]) +1 similar issue
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb4/igt@gem_mocs_settings@mocs-reset-bsd2.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb5/igt@gem_mocs_settings@mocs-reset-bsd2.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [DMESG-WARN][93] ([fdo#107724]) -> [SKIP][94] ([fdo#109349])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb8/igt@kms_dp_dsc@basic-dsc-enable-edp.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109352]: https://bugs.freedesktop.org/show_bug.cgi?id=109352
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
[fdo#109801]: https://bugs.freedesktop.org/show_bug.cgi?id=109801
[fdo#110548]: https://bugs.freedesktop.org/show_bug.cgi?id=110548
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
[fdo#111606]: https://bugs.freedesktop.org/show_bug.cgi?id=111606
[fdo#111647]: https://bugs.freedesktop.org/show_bug.cgi?id=111647
[fdo#111677]: https://bugs.freedesktop.org/show_bug.cgi?id=111677
[fdo#111703]: https://bugs.freedesktop.org/show_bug.cgi?id=111703
[fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
[fdo#111764]: https://bugs.freedesktop.org/show_bug.cgi?id=111764
[fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832
[fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
[fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
[fdo#112037]: https://bugs.freedesktop.org/show_bug.cgi?id=112037
[fdo#112080]: https://bugs.freedesktop.org/s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for tgl: MST support
@ 2019-10-31 8:00 ` Patchwork
0 siblings, 0 replies; 28+ messages in thread
From: Patchwork @ 2019-10-31 8:00 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: tgl: MST support
URL : https://patchwork.freedesktop.org/series/68749/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7221_full -> Patchwork_15066_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15066_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_ctx_persistence@vcs2-persistence}:
- {shard-tglb}: NOTRUN -> [SKIP][1] +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-tglb7/igt@gem_ctx_persistence@vcs2-persistence.html
* {igt@gem_ctx_persistence@vecs0-queued}:
- shard-apl: NOTRUN -> [FAIL][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-apl8/igt@gem_ctx_persistence@vecs0-queued.html
Known issues
------------
Here are the changes found in Patchwork_15066_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_switch@vcs1:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#112080]) +6 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb2/igt@gem_ctx_switch@vcs1.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb8/igt@gem_ctx_switch@vcs1.html
* igt@gem_eio@reset-stress:
- shard-snb: [PASS][5] -> [FAIL][6] ([fdo#109661])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-snb4/igt@gem_eio@reset-stress.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-snb6/igt@gem_eio@reset-stress.html
* igt@gem_exec_reloc@basic-cpu-read-active:
- shard-skl: [PASS][7] -> [DMESG-WARN][8] ([fdo#106107])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-skl5/igt@gem_exec_reloc@basic-cpu-read-active.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-skl5/igt@gem_exec_reloc@basic-cpu-read-active.html
* igt@gem_exec_schedule@independent-bsd2:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +12 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb4/igt@gem_exec_schedule@independent-bsd2.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb5/igt@gem_exec_schedule@independent-bsd2.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112146]) +4 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb6/igt@gem_exec_schedule@preemptive-hang-bsd.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb4/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gem_linear_blits@normal:
- shard-apl: [PASS][13] -> [INCOMPLETE][14] ([fdo#103927])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-apl6/igt@gem_linear_blits@normal.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-apl2/igt@gem_linear_blits@normal.html
* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-iclb: [PASS][15] -> [INCOMPLETE][16] ([fdo#107713] / [fdo#109801])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb1/igt@gem_ppgtt@blt-vs-render-ctxn.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb7/igt@gem_ppgtt@blt-vs-render-ctxn.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
- shard-hsw: [PASS][17] -> [DMESG-WARN][18] ([fdo#111870])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-hsw5/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-hsw2/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
- shard-snb: [PASS][19] -> [DMESG-WARN][20] ([fdo#111870])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-snb2/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-snb2/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-apl: [PASS][21] -> [DMESG-WARN][22] ([fdo#108566]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-apl1/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-apl4/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-hsw: [PASS][23] -> [FAIL][24] ([fdo#105767])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt:
- shard-iclb: [PASS][25] -> [FAIL][26] ([fdo#103167]) +5 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-kbl: [PASS][27] -> [DMESG-WARN][28] ([fdo#108566]) +6 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-kbl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [PASS][29] -> [FAIL][30] ([fdo#108145])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [PASS][31] -> [SKIP][32] ([fdo#109441]) +2 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb8/igt@kms_psr@psr2_no_drrs.html
* igt@tools_test@tools_test:
- shard-iclb: [PASS][33] -> [SKIP][34] ([fdo#109352])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb1/igt@tools_test@tools_test.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb2/igt@tools_test@tools_test.html
#### Possible fixes ####
* igt@gem_busy@busy-vcs1:
- shard-iclb: [SKIP][35] ([fdo#112080]) -> [PASS][36] +9 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb6/igt@gem_busy@busy-vcs1.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb4/igt@gem_busy@busy-vcs1.html
* igt@gem_ctx_isolation@vcs1-none:
- shard-iclb: [SKIP][37] ([fdo#109276] / [fdo#112080]) -> [PASS][38] +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb5/igt@gem_ctx_isolation@vcs1-none.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb1/igt@gem_ctx_isolation@vcs1-none.html
* {igt@gem_ctx_persistence@rcs0-queued}:
- {shard-tglb}: [FAIL][39] -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-tglb5/igt@gem_ctx_persistence@rcs0-queued.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-tglb5/igt@gem_ctx_persistence@rcs0-queued.html
* igt@gem_exec_schedule@out-order-bsd2:
- shard-iclb: [SKIP][41] ([fdo#109276]) -> [PASS][42] +14 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb7/igt@gem_exec_schedule@out-order-bsd2.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb1/igt@gem_exec_schedule@out-order-bsd2.html
* igt@gem_exec_schedule@pi-ringfull-bsd:
- shard-iclb: [SKIP][43] ([fdo#112146]) -> [PASS][44] +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb2/igt@gem_exec_schedule@pi-ringfull-bsd.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb8/igt@gem_exec_schedule@pi-ringfull-bsd.html
* igt@gem_exec_schedule@preempt-queue-chain-bsd1:
- {shard-tglb}: [INCOMPLETE][45] ([fdo#111606] / [fdo#111677]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-tglb6/igt@gem_exec_schedule@preempt-queue-chain-bsd1.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-tglb5/igt@gem_exec_schedule@preempt-queue-chain-bsd1.html
* igt@gem_exec_schedule@preempt-queue-vebox:
- {shard-tglb}: [INCOMPLETE][47] ([fdo#111677]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-tglb6/igt@gem_exec_schedule@preempt-queue-vebox.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-tglb7/igt@gem_exec_schedule@preempt-queue-vebox.html
* {igt@gem_exec_suspend@basic-s0}:
- {shard-tglb}: [INCOMPLETE][49] ([fdo#111832]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-tglb1/igt@gem_exec_suspend@basic-s0.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-tglb5/igt@gem_exec_suspend@basic-s0.html
* igt@gem_persistent_relocs@forked-interruptible-thrashing:
- shard-hsw: [FAIL][51] ([fdo#112037]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-hsw7/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-hsw1/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
* igt@gem_softpin@noreloc-s3:
- shard-iclb: [DMESG-WARN][53] ([fdo#111764]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb2/igt@gem_softpin@noreloc-s3.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb8/igt@gem_softpin@noreloc-s3.html
- shard-skl: [INCOMPLETE][55] ([fdo#104108]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-skl2/igt@gem_softpin@noreloc-s3.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-skl6/igt@gem_softpin@noreloc-s3.html
* igt@gem_sync@basic-all:
- {shard-tglb}: [INCOMPLETE][57] ([fdo#111647]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-tglb6/igt@gem_sync@basic-all.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-tglb1/igt@gem_sync@basic-all.html
* {igt@i915_pm_dc@dc6-dpms}:
- shard-iclb: [FAIL][59] ([fdo#110548]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb5/igt@i915_pm_dc@dc6-dpms.html
* igt@kms_busy@extended-modeset-hang-newfb-render-d:
- {shard-tglb}: [INCOMPLETE][61] -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-tglb3/igt@kms_busy@extended-modeset-hang-newfb-render-d.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-tglb6/igt@kms_busy@extended-modeset-hang-newfb-render-d.html
* igt@kms_cursor_legacy@pipe-a-forked-move:
- shard-apl: [INCOMPLETE][63] ([fdo#103927]) -> [PASS][64] +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-apl4/igt@kms_cursor_legacy@pipe-a-forked-move.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-apl8/igt@kms_cursor_legacy@pipe-a-forked-move.html
* igt@kms_fbcon_fbt@fbc-suspend:
- {shard-tglb}: [INCOMPLETE][65] ([fdo#111747] / [fdo#111832] / [fdo#111850]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-tglb5/igt@kms_fbcon_fbt@fbc-suspend.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-tglb6/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-apl: [DMESG-WARN][67] ([fdo#108566]) -> [PASS][68] +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible.html
- shard-kbl: [DMESG-WARN][69] ([fdo#108566]) -> [PASS][70] +4 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack:
- {shard-tglb}: [FAIL][71] ([fdo#103167]) -> [PASS][72] +3 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html
* igt@kms_frontbuffer_tracking@fbc-tilingchange:
- shard-iclb: [FAIL][73] ([fdo#103167]) -> [PASS][74] +5 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-tilingchange.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-tilingchange.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- {shard-tglb}: [INCOMPLETE][75] ([fdo#111832] / [fdo#111850]) -> [PASS][76] +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-tglb8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-tglb6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [FAIL][77] ([fdo#108145]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [FAIL][79] ([fdo#103166]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-y.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb2/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [SKIP][81] ([fdo#109642] / [fdo#111068]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb6/igt@kms_psr2_su@frontbuffer.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [SKIP][83] ([fdo#109441]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb1/igt@kms_psr@psr2_cursor_render.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
* igt@kms_vblank@pipe-c-query-idle-hang:
- {shard-tglb}: [INCOMPLETE][85] ([fdo#111747]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-tglb5/igt@kms_vblank@pipe-c-query-idle-hang.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-tglb7/igt@kms_vblank@pipe-c-query-idle-hang.html
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- {shard-tglb}: [INCOMPLETE][87] ([fdo#111850]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-tglb3/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-tglb8/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [SKIP][89] ([fdo#109276] / [fdo#112080]) -> [FAIL][90] ([fdo#111329])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb5/igt@gem_ctx_isolation@vcs1-nonpriv.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb1/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@gem_mocs_settings@mocs-reset-bsd2:
- shard-iclb: [FAIL][91] ([fdo#111330]) -> [SKIP][92] ([fdo#109276]) +1 similar issue
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb4/igt@gem_mocs_settings@mocs-reset-bsd2.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb5/igt@gem_mocs_settings@mocs-reset-bsd2.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [DMESG-WARN][93] ([fdo#107724]) -> [SKIP][94] ([fdo#109349])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/shard-iclb8/igt@kms_dp_dsc@basic-dsc-enable-edp.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109352]: https://bugs.freedesktop.org/show_bug.cgi?id=109352
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
[fdo#109801]: https://bugs.freedesktop.org/show_bug.cgi?id=109801
[fdo#110548]: https://bugs.freedesktop.org/show_bug.cgi?id=110548
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
[fdo#111606]: https://bugs.freedesktop.org/show_bug.cgi?id=111606
[fdo#111647]: https://bugs.freedesktop.org/show_bug.cgi?id=111647
[fdo#111677]: https://bugs.freedesktop.org/show_bug.cgi?id=111677
[fdo#111703]: https://bugs.freedesktop.org/show_bug.cgi?id=111703
[fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
[fdo#111764]: https://bugs.freedesktop.org/show_bug.cgi?id=111764
[fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832
[fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
[fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
[fdo#112037]: https://bugs.freedesktop.org/show_bug.cgi?id=112037
[fdo#112080]: https://bugs.freedesktop.org/s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15066/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 2/5] drm/i915: add wrappers to get intel connector state
@ 2019-11-01 0:26 ` Souza, Jose
0 siblings, 0 replies; 28+ messages in thread
From: Souza, Jose @ 2019-11-01 0:26 UTC (permalink / raw)
To: intel-gfx, De Marchi, Lucas
On Tue, 2019-10-29 at 18:24 -0700, Lucas De Marchi wrote:
> Wrap drm_atomic_get_old_connector_state so we can get the
> intel_digital_connector_state and make it easier to migrate to intel
> types.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> .../gpu/drm/i915/display/intel_display_types.h | 18
> ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 40184e823c84..a550abb48b3c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1527,6 +1527,24 @@ intel_atomic_get_new_crtc_state(struct
> intel_atomic_state *state,
> &crtc-
> >base));
> }
>
> +static inline struct intel_digital_connector_state *
> +intel_atomic_get_new_connector_state(struct intel_atomic_state
> *state,
> + struct intel_connector *connector)
> +{
> + return to_intel_digital_connector_state(
> + drm_atomic_get_new_connector_state(&state-
> >base,
> + &connector->base));
> +}
> +
> +static inline struct intel_digital_connector_state *
> +intel_atomic_get_old_connector_state(struct intel_atomic_state
> *state,
> + struct intel_connector *connector)
> +{
> + return to_intel_digital_connector_state(
> + drm_atomic_get_old_connector_state(&state-
> >base,
> + &connector->base));
> +}
> +
> /* intel_display.c */
> static inline bool
> intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Intel-gfx] [PATCH 2/5] drm/i915: add wrappers to get intel connector state
@ 2019-11-01 0:26 ` Souza, Jose
0 siblings, 0 replies; 28+ messages in thread
From: Souza, Jose @ 2019-11-01 0:26 UTC (permalink / raw)
To: intel-gfx, De Marchi, Lucas
On Tue, 2019-10-29 at 18:24 -0700, Lucas De Marchi wrote:
> Wrap drm_atomic_get_old_connector_state so we can get the
> intel_digital_connector_state and make it easier to migrate to intel
> types.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> .../gpu/drm/i915/display/intel_display_types.h | 18
> ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 40184e823c84..a550abb48b3c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1527,6 +1527,24 @@ intel_atomic_get_new_crtc_state(struct
> intel_atomic_state *state,
> &crtc-
> >base));
> }
>
> +static inline struct intel_digital_connector_state *
> +intel_atomic_get_new_connector_state(struct intel_atomic_state
> *state,
> + struct intel_connector *connector)
> +{
> + return to_intel_digital_connector_state(
> + drm_atomic_get_new_connector_state(&state-
> >base,
> + &connector->base));
> +}
> +
> +static inline struct intel_digital_connector_state *
> +intel_atomic_get_old_connector_state(struct intel_atomic_state
> *state,
> + struct intel_connector *connector)
> +{
> + return to_intel_digital_connector_state(
> + drm_atomic_get_old_connector_state(&state-
> >base,
> + &connector->base));
> +}
> +
> /* intel_display.c */
> static inline bool
> intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 3/5] drm/i915/tgl: do not enable transcoder clock twice on MST
@ 2019-11-01 0:37 ` Souza, Jose
0 siblings, 0 replies; 28+ messages in thread
From: Souza, Jose @ 2019-11-01 0:37 UTC (permalink / raw)
To: intel-gfx, De Marchi, Lucas
On Tue, 2019-10-29 at 18:24 -0700, Lucas De Marchi wrote:
> For MST on Tiger Lake there are different moments when we need to
> configure the transcoder clock select. For the first link this is in
> step
> 7.a of the spec, before training the link. For additional streams
> this
> should be done as part of step 8.b after programming receiver VC
> Payload
> ID.
>
> Bspec: 49190
>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 7 ++++---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 +++++++++++++---
> 2 files changed, 17 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index fed7fc56dd92..2ce998529d08 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3462,9 +3462,10 @@ static void tgl_ddi_pre_enable_dp(struct
> intel_encoder *encoder,
> icl_program_mg_dp_mode(dig_port, crtc_state);
>
> /*
> - * 7.a - Steps in this function should only be executed over
> MST
> - * master, what will be taken in care by MST hook
> - * intel_mst_pre_enable_dp()
> + * 7.a - single stream or multi-stream master transcoder:
> Configure
> + * Transcoder Clock Select. For additional MST streams this
> will be done
> + * by intel_mst_pre_enable_dp() after programming VC Payload ID
> through
> + * AUX.
> */
> intel_ddi_enable_pipe_clock(crtc_state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index a9962846a503..ad54618f6142 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -299,21 +299,23 @@ static void intel_mst_pre_enable_dp(struct
> intel_encoder *encoder,
> to_intel_connector(conn_state->connector);
> int ret;
> u32 temp;
> + bool first_mst_stream;
>
> /* MST encoders are bound to a crtc, not to a connector,
> * force the mapping here for get_hw_state.
> */
> connector->encoder = encoder;
> intel_mst->connector = connector;
> + first_mst_stream = intel_dp->active_mst_links == 0;
>
> DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
>
> - if (intel_dp->active_mst_links == 0)
> + if (first_mst_stream)
> intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
>
> drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector-
> >port, true);
>
> - if (intel_dp->active_mst_links == 0)
> + if (first_mst_stream)
> intel_dig_port->base.pre_enable(&intel_dig_port->base,
> pipe_config, NULL);
>
> @@ -330,7 +332,15 @@ static void intel_mst_pre_enable_dp(struct
> intel_encoder *encoder,
>
> ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr);
>
> - intel_ddi_enable_pipe_clock(pipe_config);
> + /*
> + * Before Gen 12 this is not done as part of
> + * intel_dig_port->base.pre_enable() and should be done here.
> For
> + * Gen 12+ the step in which this should be done is different
> for the
> + * first MST stream, so it's done on the DDI for the first
> stream and
> + * here for the following ones.
> + */
> + if (INTEL_GEN(dev_priv) < 12 || !first_mst_stream)
> + intel_ddi_enable_pipe_clock(pipe_config);
> }
>
> static void intel_mst_enable_dp(struct intel_encoder *encoder,
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Intel-gfx] [PATCH 3/5] drm/i915/tgl: do not enable transcoder clock twice on MST
@ 2019-11-01 0:37 ` Souza, Jose
0 siblings, 0 replies; 28+ messages in thread
From: Souza, Jose @ 2019-11-01 0:37 UTC (permalink / raw)
To: intel-gfx, De Marchi, Lucas
On Tue, 2019-10-29 at 18:24 -0700, Lucas De Marchi wrote:
> For MST on Tiger Lake there are different moments when we need to
> configure the transcoder clock select. For the first link this is in
> step
> 7.a of the spec, before training the link. For additional streams
> this
> should be done as part of step 8.b after programming receiver VC
> Payload
> ID.
>
> Bspec: 49190
>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 7 ++++---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 +++++++++++++---
> 2 files changed, 17 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index fed7fc56dd92..2ce998529d08 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3462,9 +3462,10 @@ static void tgl_ddi_pre_enable_dp(struct
> intel_encoder *encoder,
> icl_program_mg_dp_mode(dig_port, crtc_state);
>
> /*
> - * 7.a - Steps in this function should only be executed over
> MST
> - * master, what will be taken in care by MST hook
> - * intel_mst_pre_enable_dp()
> + * 7.a - single stream or multi-stream master transcoder:
> Configure
> + * Transcoder Clock Select. For additional MST streams this
> will be done
> + * by intel_mst_pre_enable_dp() after programming VC Payload ID
> through
> + * AUX.
> */
> intel_ddi_enable_pipe_clock(crtc_state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index a9962846a503..ad54618f6142 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -299,21 +299,23 @@ static void intel_mst_pre_enable_dp(struct
> intel_encoder *encoder,
> to_intel_connector(conn_state->connector);
> int ret;
> u32 temp;
> + bool first_mst_stream;
>
> /* MST encoders are bound to a crtc, not to a connector,
> * force the mapping here for get_hw_state.
> */
> connector->encoder = encoder;
> intel_mst->connector = connector;
> + first_mst_stream = intel_dp->active_mst_links == 0;
>
> DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
>
> - if (intel_dp->active_mst_links == 0)
> + if (first_mst_stream)
> intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
>
> drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector-
> >port, true);
>
> - if (intel_dp->active_mst_links == 0)
> + if (first_mst_stream)
> intel_dig_port->base.pre_enable(&intel_dig_port->base,
> pipe_config, NULL);
>
> @@ -330,7 +332,15 @@ static void intel_mst_pre_enable_dp(struct
> intel_encoder *encoder,
>
> ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr);
>
> - intel_ddi_enable_pipe_clock(pipe_config);
> + /*
> + * Before Gen 12 this is not done as part of
> + * intel_dig_port->base.pre_enable() and should be done here.
> For
> + * Gen 12+ the step in which this should be done is different
> for the
> + * first MST stream, so it's done on the DDI for the first
> stream and
> + * here for the following ones.
> + */
> + if (INTEL_GEN(dev_priv) < 12 || !first_mst_stream)
> + intel_ddi_enable_pipe_clock(pipe_config);
> }
>
> static void intel_mst_enable_dp(struct intel_encoder *encoder,
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 4/5] drm/i915: avoid reading DP_TP_CTL twice
@ 2019-11-01 0:39 ` Souza, Jose
0 siblings, 0 replies; 28+ messages in thread
From: Souza, Jose @ 2019-11-01 0:39 UTC (permalink / raw)
To: intel-gfx, De Marchi, Lucas
On Tue, 2019-10-29 at 18:24 -0700, Lucas De Marchi wrote:
> Just avoid the additional read in case DP_TP_CTL is enabled:
> read it once and save the value.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 33 ++++++++++++--------
> ----
> 1 file changed, 17 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 2ce998529d08..41b9b9a6772a 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4148,37 +4148,38 @@ static void
> intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
> struct drm_i915_private *dev_priv =
> to_i915(intel_dig_port->base.base.dev);
> enum port port = intel_dig_port->base.port;
> - u32 val;
> + u32 dp_tp_ctl, ddi_buf_ctl;
> bool wait = false;
>
> - if (I915_READ(intel_dp->regs.dp_tp_ctl) & DP_TP_CTL_ENABLE) {
> - val = I915_READ(DDI_BUF_CTL(port));
> - if (val & DDI_BUF_CTL_ENABLE) {
> - val &= ~DDI_BUF_CTL_ENABLE;
> - I915_WRITE(DDI_BUF_CTL(port), val);
> + dp_tp_ctl = I915_READ(intel_dp->regs.dp_tp_ctl);
> +
> + if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
> + ddi_buf_ctl = I915_READ(DDI_BUF_CTL(port));
> + if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) {
> + I915_WRITE(DDI_BUF_CTL(port),
> + ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE);
> wait = true;
> }
>
> - val = I915_READ(intel_dp->regs.dp_tp_ctl);
> - val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
> - val |= DP_TP_CTL_LINK_TRAIN_PAT1;
> - I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
> + dp_tp_ctl &= ~(DP_TP_CTL_ENABLE |
> DP_TP_CTL_LINK_TRAIN_MASK);
> + dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;
> + I915_WRITE(intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
> POSTING_READ(intel_dp->regs.dp_tp_ctl);
>
> if (wait)
> intel_wait_ddi_buf_idle(dev_priv, port);
> }
>
> - val = DP_TP_CTL_ENABLE |
> - DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
> + dp_tp_ctl = DP_TP_CTL_ENABLE |
> + DP_TP_CTL_LINK_TRAIN_PAT1 |
> DP_TP_CTL_SCRAMBLE_DISABLE;
> if (intel_dp->link_mst)
> - val |= DP_TP_CTL_MODE_MST;
> + dp_tp_ctl |= DP_TP_CTL_MODE_MST;
> else {
> - val |= DP_TP_CTL_MODE_SST;
> + dp_tp_ctl |= DP_TP_CTL_MODE_SST;
> if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> - val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
> + dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
> }
> - I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
> + I915_WRITE(intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
> POSTING_READ(intel_dp->regs.dp_tp_ctl);
>
> intel_dp->DP |= DDI_BUF_CTL_ENABLE;
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Intel-gfx] [PATCH 4/5] drm/i915: avoid reading DP_TP_CTL twice
@ 2019-11-01 0:39 ` Souza, Jose
0 siblings, 0 replies; 28+ messages in thread
From: Souza, Jose @ 2019-11-01 0:39 UTC (permalink / raw)
To: intel-gfx, De Marchi, Lucas
On Tue, 2019-10-29 at 18:24 -0700, Lucas De Marchi wrote:
> Just avoid the additional read in case DP_TP_CTL is enabled:
> read it once and save the value.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 33 ++++++++++++--------
> ----
> 1 file changed, 17 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 2ce998529d08..41b9b9a6772a 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4148,37 +4148,38 @@ static void
> intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
> struct drm_i915_private *dev_priv =
> to_i915(intel_dig_port->base.base.dev);
> enum port port = intel_dig_port->base.port;
> - u32 val;
> + u32 dp_tp_ctl, ddi_buf_ctl;
> bool wait = false;
>
> - if (I915_READ(intel_dp->regs.dp_tp_ctl) & DP_TP_CTL_ENABLE) {
> - val = I915_READ(DDI_BUF_CTL(port));
> - if (val & DDI_BUF_CTL_ENABLE) {
> - val &= ~DDI_BUF_CTL_ENABLE;
> - I915_WRITE(DDI_BUF_CTL(port), val);
> + dp_tp_ctl = I915_READ(intel_dp->regs.dp_tp_ctl);
> +
> + if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
> + ddi_buf_ctl = I915_READ(DDI_BUF_CTL(port));
> + if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) {
> + I915_WRITE(DDI_BUF_CTL(port),
> + ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE);
> wait = true;
> }
>
> - val = I915_READ(intel_dp->regs.dp_tp_ctl);
> - val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
> - val |= DP_TP_CTL_LINK_TRAIN_PAT1;
> - I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
> + dp_tp_ctl &= ~(DP_TP_CTL_ENABLE |
> DP_TP_CTL_LINK_TRAIN_MASK);
> + dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;
> + I915_WRITE(intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
> POSTING_READ(intel_dp->regs.dp_tp_ctl);
>
> if (wait)
> intel_wait_ddi_buf_idle(dev_priv, port);
> }
>
> - val = DP_TP_CTL_ENABLE |
> - DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
> + dp_tp_ctl = DP_TP_CTL_ENABLE |
> + DP_TP_CTL_LINK_TRAIN_PAT1 |
> DP_TP_CTL_SCRAMBLE_DISABLE;
> if (intel_dp->link_mst)
> - val |= DP_TP_CTL_MODE_MST;
> + dp_tp_ctl |= DP_TP_CTL_MODE_MST;
> else {
> - val |= DP_TP_CTL_MODE_SST;
> + dp_tp_ctl |= DP_TP_CTL_MODE_SST;
> if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> - val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
> + dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
> }
> - I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
> + I915_WRITE(intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
> POSTING_READ(intel_dp->regs.dp_tp_ctl);
>
> intel_dp->DP |= DDI_BUF_CTL_ENABLE;
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 0/5] tgl: MST support
@ 2019-11-01 0:43 ` Souza, Jose
0 siblings, 0 replies; 28+ messages in thread
From: Souza, Jose @ 2019-11-01 0:43 UTC (permalink / raw)
To: intel-gfx, De Marchi, Lucas; +Cc: Nikula, Jani
I plan to debug MST with this patches next week but I guess at least
the 4 first patches can be merged. The 5th too if someone else reviews
it, the selection of the master transcoder was tested by me and Lucas
and the problem in not in any of this patches.
On Tue, 2019-10-29 at 18:24 -0700, Lucas De Marchi wrote:
> Additional code to support more than one display when using MST with
> TGL. It's still WIP! From what I could check on my tests we are
> correctly
> tracking the master transcoder and setting it accordingly on
> TRANS_DDI_FUNC_CTL and DP_TP_CTL.
>
> I tried also setting MST mode on the slave's DP_TP_CTL. I could get
> the
> second display to show up some times and we don't get stuck on
> "timeout
> waiting for ACT" error message. This is not according to the spec
> though, and it still doesn't work most of the time. So... I didn't
> add
> it here.
>
> I guess now I need another pair of eyes to check what I'm doing wrong
> since continuing to stare at the spec and code isn't helping. José,
> Imre?
>
> José Roberto de Souza (2):
> drm/i915: Add for_each_new_intel_connector_in_state()
> drm/i915/tgl: Select master transcoder in DP MST
>
> Lucas De Marchi (3):
> drm/i915: add wrappers to get intel connector state
> drm/i915/tgl: do not enable transcoder clock twice on MST
> drm/i915: avoid reading DP_TP_CTL twice
>
> drivers/gpu/drm/i915/display/intel_ddi.c | 54 +++---
> drivers/gpu/drm/i915/display/intel_display.c | 16 ++
> drivers/gpu/drm/i915/display/intel_display.h | 8 +
> .../drm/i915/display/intel_display_types.h | 21 +++
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 159
> +++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_dp_mst.h | 2 +
> 6 files changed, 236 insertions(+), 24 deletions(-)
>
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Intel-gfx] [PATCH 0/5] tgl: MST support
@ 2019-11-01 0:43 ` Souza, Jose
0 siblings, 0 replies; 28+ messages in thread
From: Souza, Jose @ 2019-11-01 0:43 UTC (permalink / raw)
To: intel-gfx, De Marchi, Lucas; +Cc: Nikula, Jani
I plan to debug MST with this patches next week but I guess at least
the 4 first patches can be merged. The 5th too if someone else reviews
it, the selection of the master transcoder was tested by me and Lucas
and the problem in not in any of this patches.
On Tue, 2019-10-29 at 18:24 -0700, Lucas De Marchi wrote:
> Additional code to support more than one display when using MST with
> TGL. It's still WIP! From what I could check on my tests we are
> correctly
> tracking the master transcoder and setting it accordingly on
> TRANS_DDI_FUNC_CTL and DP_TP_CTL.
>
> I tried also setting MST mode on the slave's DP_TP_CTL. I could get
> the
> second display to show up some times and we don't get stuck on
> "timeout
> waiting for ACT" error message. This is not according to the spec
> though, and it still doesn't work most of the time. So... I didn't
> add
> it here.
>
> I guess now I need another pair of eyes to check what I'm doing wrong
> since continuing to stare at the spec and code isn't helping. José,
> Imre?
>
> José Roberto de Souza (2):
> drm/i915: Add for_each_new_intel_connector_in_state()
> drm/i915/tgl: Select master transcoder in DP MST
>
> Lucas De Marchi (3):
> drm/i915: add wrappers to get intel connector state
> drm/i915/tgl: do not enable transcoder clock twice on MST
> drm/i915: avoid reading DP_TP_CTL twice
>
> drivers/gpu/drm/i915/display/intel_ddi.c | 54 +++---
> drivers/gpu/drm/i915/display/intel_display.c | 16 ++
> drivers/gpu/drm/i915/display/intel_display.h | 8 +
> .../drm/i915/display/intel_display_types.h | 21 +++
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 159
> +++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_dp_mst.h | 2 +
> 6 files changed, 236 insertions(+), 24 deletions(-)
>
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^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2019-11-01 0:43 UTC | newest]
Thread overview: 28+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-10-30 1:24 [PATCH 0/5] tgl: MST support Lucas De Marchi
2019-10-30 1:24 ` [Intel-gfx] " Lucas De Marchi
2019-10-30 1:24 ` [PATCH 1/5] drm/i915: Add for_each_new_intel_connector_in_state() Lucas De Marchi
2019-10-30 1:24 ` [Intel-gfx] " Lucas De Marchi
2019-10-30 1:24 ` [PATCH 2/5] drm/i915: add wrappers to get intel connector state Lucas De Marchi
2019-10-30 1:24 ` [Intel-gfx] " Lucas De Marchi
2019-11-01 0:26 ` Souza, Jose
2019-11-01 0:26 ` [Intel-gfx] " Souza, Jose
2019-10-30 1:24 ` [PATCH 3/5] drm/i915/tgl: do not enable transcoder clock twice on MST Lucas De Marchi
2019-10-30 1:24 ` [Intel-gfx] " Lucas De Marchi
2019-11-01 0:37 ` Souza, Jose
2019-11-01 0:37 ` [Intel-gfx] " Souza, Jose
2019-10-30 1:24 ` [PATCH 4/5] drm/i915: avoid reading DP_TP_CTL twice Lucas De Marchi
2019-10-30 1:24 ` [Intel-gfx] " Lucas De Marchi
2019-11-01 0:39 ` Souza, Jose
2019-11-01 0:39 ` [Intel-gfx] " Souza, Jose
2019-10-30 1:24 ` [PATCH 5/5] drm/i915/tgl: Select master transcoder in DP MST Lucas De Marchi
2019-10-30 1:24 ` [Intel-gfx] " Lucas De Marchi
2019-10-30 3:24 ` ✗ Fi.CI.CHECKPATCH: warning for tgl: MST support Patchwork
2019-10-30 3:24 ` [Intel-gfx] " Patchwork
2019-10-30 3:27 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-10-30 3:27 ` [Intel-gfx] " Patchwork
2019-10-30 3:51 ` ✓ Fi.CI.BAT: success " Patchwork
2019-10-30 3:51 ` [Intel-gfx] " Patchwork
2019-10-31 8:00 ` ✓ Fi.CI.IGT: " Patchwork
2019-10-31 8:00 ` [Intel-gfx] " Patchwork
2019-11-01 0:43 ` [PATCH 0/5] " Souza, Jose
2019-11-01 0:43 ` [Intel-gfx] " Souza, Jose
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