* [U-Boot] [RFC PATCH 0/5] WIP Add support for i.MXRT family
@ 2019-10-30 21:09 Giulio Benetti
2019-10-30 21:09 ` [U-Boot] [RFC PATCH 1/5] Add support for the NXP IMXRT10xx SoC family Giulio Benetti
` (5 more replies)
0 siblings, 6 replies; 13+ messages in thread
From: Giulio Benetti @ 2019-10-30 21:09 UTC (permalink / raw)
To: u-boot
This patchset is a WIP for adding i.MXRT family.
It provides:
- soc family entry
- pinctrl driver
- serial driver tweaking
- partial sdram controller driver
- imxrt1050-evk board partial support
To get it working as at least SPL and Falcon mode it still needs sdram
controller driver to be finished and clock driver to be done.
I would like to receive some comment from you all since this is my first
big contribution(at least for me it is).
Giulio Benetti (5):
Add support for the NXP IMXRT10xx SoC family
pinctrl: add i.MXRT driver
serial_lpuart: add support for i.MXRT
ram: add SDRAM driver for i.MXRT SoCs
Add support for the NXP IMXRT1050-EVK board
arch/arm/Kconfig | 10 +
arch/arm/Makefile | 4 +-
arch/arm/dts/Makefile | 2 +
arch/arm/dts/imxrt1050-evk.dts | 124 +++
arch/arm/dts/imxrt1050.dtsi | 73 ++
arch/arm/include/asm/arch-imxrt/clock.h | 10 +
arch/arm/include/asm/arch-imxrt/gpio.h | 10 +
arch/arm/include/asm/arch-imxrt/imx-regs.h | 10 +
arch/arm/include/asm/arch-imxrt/imxrt.h | 11 +
arch/arm/mach-imx/Makefile | 1 +
arch/arm/mach-imx/imxrt/Kconfig | 17 +
arch/arm/mach-imx/imxrt/Makefile | 7 +
arch/arm/mach-imx/imxrt/soc.c | 29 +
board/freescale/imxrt1050-evk/Kconfig | 19 +
board/freescale/imxrt1050-evk/MAINTAINERS | 6 +
board/freescale/imxrt1050-evk/Makefile | 6 +
board/freescale/imxrt1050-evk/imxrt1050-evk.c | 94 ++
configs/imxrt1050-evk_defconfig | 52 +
drivers/pinctrl/nxp/Kconfig | 14 +
drivers/pinctrl/nxp/Makefile | 1 +
drivers/pinctrl/nxp/pinctrl-imxrt.c | 40 +
drivers/ram/Kconfig | 8 +
drivers/ram/Makefile | 2 +
drivers/ram/imxrt_sdram.c | 406 +++++++
drivers/serial/serial_lpuart.c | 15 +-
include/configs/imxrt1050-evk.h | 68 ++
include/dt-bindings/clock/imxrt-clock.h | 272 +++++
include/dt-bindings/memory/imxrt-sdram.h | 168 +++
include/dt-bindings/pinctrl/pins-imxrt1050.h | 993 ++++++++++++++++++
include/fsl_lpuart.h | 3 +-
30 files changed, 2468 insertions(+), 7 deletions(-)
create mode 100644 arch/arm/dts/imxrt1050-evk.dts
create mode 100644 arch/arm/dts/imxrt1050.dtsi
create mode 100644 arch/arm/include/asm/arch-imxrt/clock.h
create mode 100644 arch/arm/include/asm/arch-imxrt/gpio.h
create mode 100644 arch/arm/include/asm/arch-imxrt/imx-regs.h
create mode 100644 arch/arm/include/asm/arch-imxrt/imxrt.h
create mode 100644 arch/arm/mach-imx/imxrt/Kconfig
create mode 100644 arch/arm/mach-imx/imxrt/Makefile
create mode 100644 arch/arm/mach-imx/imxrt/soc.c
create mode 100644 board/freescale/imxrt1050-evk/Kconfig
create mode 100644 board/freescale/imxrt1050-evk/MAINTAINERS
create mode 100644 board/freescale/imxrt1050-evk/Makefile
create mode 100644 board/freescale/imxrt1050-evk/imxrt1050-evk.c
create mode 100644 configs/imxrt1050-evk_defconfig
create mode 100644 drivers/pinctrl/nxp/pinctrl-imxrt.c
create mode 100644 drivers/ram/imxrt_sdram.c
create mode 100644 include/configs/imxrt1050-evk.h
create mode 100644 include/dt-bindings/clock/imxrt-clock.h
create mode 100644 include/dt-bindings/memory/imxrt-sdram.h
create mode 100644 include/dt-bindings/pinctrl/pins-imxrt1050.h
--
2.20.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [RFC PATCH 1/5] Add support for the NXP IMXRT10xx SoC family
2019-10-30 21:09 [U-Boot] [RFC PATCH 0/5] WIP Add support for i.MXRT family Giulio Benetti
@ 2019-10-30 21:09 ` Giulio Benetti
2019-10-30 21:09 ` [U-Boot] [RFC PATCH 2/5] pinctrl: add i.MXRT driver Giulio Benetti
` (4 subsequent siblings)
5 siblings, 0 replies; 13+ messages in thread
From: Giulio Benetti @ 2019-10-30 21:09 UTC (permalink / raw)
To: u-boot
TODO...
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
---
arch/arm/Kconfig | 10 ++++++++
arch/arm/Makefile | 4 +--
arch/arm/include/asm/arch-imxrt/clock.h | 10 ++++++++
arch/arm/include/asm/arch-imxrt/gpio.h | 10 ++++++++
arch/arm/include/asm/arch-imxrt/imx-regs.h | 10 ++++++++
arch/arm/include/asm/arch-imxrt/imxrt.h | 11 ++++++++
arch/arm/mach-imx/Makefile | 1 +
arch/arm/mach-imx/imxrt/Kconfig | 6 +++++
arch/arm/mach-imx/imxrt/Makefile | 7 ++++++
arch/arm/mach-imx/imxrt/soc.c | 29 ++++++++++++++++++++++
10 files changed, 96 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/include/asm/arch-imxrt/clock.h
create mode 100644 arch/arm/include/asm/arch-imxrt/gpio.h
create mode 100644 arch/arm/include/asm/arch-imxrt/imx-regs.h
create mode 100644 arch/arm/include/asm/arch-imxrt/imxrt.h
create mode 100644 arch/arm/mach-imx/imxrt/Kconfig
create mode 100644 arch/arm/mach-imx/imxrt/Makefile
create mode 100644 arch/arm/mach-imx/imxrt/soc.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3b0e315061..672a2a1fe3 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -780,6 +780,14 @@ config ARCH_IMX8M
select SUPPORT_SPL
imply CMD_DM
+config ARCH_IMXRT
+ bool "NXP i.MXRT platform"
+ select CPU_V7M
+ select DM
+ select DM_SERIAL
+ select SUPPORT_SPL
+ imply CMD_DM
+
config ARCH_MX23
bool "NXP i.MX23 family"
select CPU_ARM926EJS
@@ -1694,6 +1702,8 @@ source "arch/arm/mach-imx/imx8/Kconfig"
source "arch/arm/mach-imx/imx8m/Kconfig"
+source "arch/arm/mach-imx/imxrt/Kconfig"
+
source "arch/arm/mach-imx/mxs/Kconfig"
source "arch/arm/mach-omap2/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 5384981c17..5dd9f5b1f6 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -104,11 +104,11 @@ libs-y += arch/arm/cpu/
libs-y += arch/arm/lib/
ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8))
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imxrt))
libs-y += arch/arm/mach-imx/
endif
else
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 vf610))
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 imxrt vf610))
libs-y += arch/arm/mach-imx/
endif
endif
diff --git a/arch/arm/include/asm/arch-imxrt/clock.h b/arch/arm/include/asm/arch-imxrt/clock.h
new file mode 100644
index 0000000000..7409028b9a
--- /dev/null
+++ b/arch/arm/include/asm/arch-imxrt/clock.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-imxrt/gpio.h b/arch/arm/include/asm/arch-imxrt/gpio.h
new file mode 100644
index 0000000000..973ab1da61
--- /dev/null
+++ b/arch/arm/include/asm/arch-imxrt/gpio.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef _GPIO_H_
+#define _GPIO_H_
+
+#endif /* _GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-imxrt/imx-regs.h b/arch/arm/include/asm/arch-imxrt/imx-regs.h
new file mode 100644
index 0000000000..4ca7f6bed3
--- /dev/null
+++ b/arch/arm/include/asm/arch-imxrt/imx-regs.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright(C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef __ASM_ARCH_IMX_REGS_H__
+#define __ASM_ARCH_IMX_REGS_H__
+
+#endif /* __ASM_ARCH_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-imxrt/imxrt.h b/arch/arm/include/asm/arch-imxrt/imxrt.h
new file mode 100644
index 0000000000..1cb2c57d31
--- /dev/null
+++ b/arch/arm/include/asm/arch-imxrt/imxrt.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef _ASM_ARCH_IMXRT_H
+#define _ASM_ARCH_IMXRT_H
+
+#endif /* _ASM_ARCH_IMXRT_H */
+
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 08ee52edbf..4b0e12c1b2 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -208,3 +208,4 @@ obj-$(CONFIG_MX7) += mx7/
obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
obj-$(CONFIG_IMX8M) += imx8m/
obj-$(CONFIG_ARCH_IMX8) += imx8/
+obj-$(CONFIG_ARCH_IMXRT) += imxrt/
diff --git a/arch/arm/mach-imx/imxrt/Kconfig b/arch/arm/mach-imx/imxrt/Kconfig
new file mode 100644
index 0000000000..1da002336b
--- /dev/null
+++ b/arch/arm/mach-imx/imxrt/Kconfig
@@ -0,0 +1,6 @@
+if ARCH_IMXRT
+
+config SYS_SOC
+ default "imxrt"
+
+endif
diff --git a/arch/arm/mach-imx/imxrt/Makefile b/arch/arm/mach-imx/imxrt/Makefile
new file mode 100644
index 0000000000..9621a8335a
--- /dev/null
+++ b/arch/arm/mach-imx/imxrt/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019
+# Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+#
+
+obj-y := soc.o
diff --git a/arch/arm/mach-imx/imxrt/soc.c b/arch/arm/mach-imx/imxrt/soc.c
new file mode 100644
index 0000000000..561f284602
--- /dev/null
+++ b/arch/arm/mach-imx/imxrt/soc.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/armv7_mpu.h>
+
+int arch_cpu_init(void)
+{
+ int i;
+
+ struct mpu_region_config imxrt_region_config[] = {
+ /*
+ * Make SDRAM area cacheable & executable.
+ */
+ { 0x80000000, REGION_1, XN_DIS, PRIV_RW_USR_RW,
+ SHARED_WRITE_BUFFERED, REGION_256MB },
+ };
+
+ disable_mpu();
+ for (i = 0; i < ARRAY_SIZE(imxrt_region_config); i++)
+ mpu_config(&imxrt_region_config[i]);
+ enable_mpu();
+
+ return 0;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [U-Boot] [RFC PATCH 2/5] pinctrl: add i.MXRT driver
2019-10-30 21:09 [U-Boot] [RFC PATCH 0/5] WIP Add support for i.MXRT family Giulio Benetti
2019-10-30 21:09 ` [U-Boot] [RFC PATCH 1/5] Add support for the NXP IMXRT10xx SoC family Giulio Benetti
@ 2019-10-30 21:09 ` Giulio Benetti
2019-10-30 21:09 ` [U-Boot] [RFC PATCH 3/5] serial_lpuart: add support for i.MXRT Giulio Benetti
` (3 subsequent siblings)
5 siblings, 0 replies; 13+ messages in thread
From: Giulio Benetti @ 2019-10-30 21:09 UTC (permalink / raw)
To: u-boot
Add i.MXRT pinctrl driver.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
---
drivers/pinctrl/nxp/Kconfig | 14 +
drivers/pinctrl/nxp/Makefile | 1 +
drivers/pinctrl/nxp/pinctrl-imxrt.c | 40 +
include/dt-bindings/pinctrl/pins-imxrt1050.h | 993 +++++++++++++++++++
4 files changed, 1048 insertions(+)
create mode 100644 drivers/pinctrl/nxp/pinctrl-imxrt.c
create mode 100644 include/dt-bindings/pinctrl/pins-imxrt1050.h
diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig
index f2e67ca231..ec55351e61 100644
--- a/drivers/pinctrl/nxp/Kconfig
+++ b/drivers/pinctrl/nxp/Kconfig
@@ -99,6 +99,20 @@ config PINCTRL_MXS
familiy, e.g. i.MX28. This feature depends on device tree
configuration.
+config PINCTRL_IMXRT
+ bool "IMXRT pinctrl driver"
+ depends on ARCH_IMXRT && PINCTRL_FULL
+ select DEVRES
+ select PINCTRL_IMX
+ help
+ Say Y here to enable the imxrt pinctrl driver
+
+ This provides a simple pinctrl driver for i.MXRT SoC familiy.
+ This feature depends on device tree configuration. This driver
+ is different from the linux one, this is a simple implementation,
+ only parses the 'fsl,pins' property and configure related
+ registers.
+
config PINCTRL_VYBRID
bool "Vybrid (vf610) pinctrl driver"
depends on ARCH_VF610 && PINCTRL_FULL
diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile
index b86448aac9..066ca75b65 100644
--- a/drivers/pinctrl/nxp/Makefile
+++ b/drivers/pinctrl/nxp/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_PINCTRL_IMX8) += pinctrl-imx8.o
obj-$(CONFIG_PINCTRL_IMX8M) += pinctrl-imx8m.o
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
obj-$(CONFIG_PINCTRL_VYBRID) += pinctrl-vf610.o
+obj-$(CONFIG_PINCTRL_IMXRT) += pinctrl-imxrt.o
diff --git a/drivers/pinctrl/nxp/pinctrl-imxrt.c b/drivers/pinctrl/nxp/pinctrl-imxrt.c
new file mode 100644
index 0000000000..4a93941927
--- /dev/null
+++ b/drivers/pinctrl/nxp/pinctrl-imxrt.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+static struct imx_pinctrl_soc_info imxrt_pinctrl_soc_info = {
+ .flags = ZERO_OFFSET_VALID,
+};
+
+static int imxrt_pinctrl_probe(struct udevice *dev)
+{
+ struct imx_pinctrl_soc_info *info =
+ (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev);
+
+ return imx_pinctrl_probe(dev, info);
+}
+
+static const struct udevice_id imxrt_pinctrl_match[] = {
+ { .compatible = "fsl,imxrt-iomuxc",
+ .data = (ulong)&imxrt_pinctrl_soc_info },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(imxrt_pinctrl) = {
+ .name = "imxrt-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(imxrt_pinctrl_match),
+ .probe = imxrt_pinctrl_probe,
+ .remove = imx_pinctrl_remove,
+ .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv),
+ .ops = &imx_pinctrl_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/include/dt-bindings/pinctrl/pins-imxrt1050.h b/include/dt-bindings/pinctrl/pins-imxrt1050.h
new file mode 100644
index 0000000000..e664f977c4
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pins-imxrt1050.h
@@ -0,0 +1,993 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H
+#define _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H
+
+#define IMX_PAD_SION 0x40000000
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+
+#define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_01_XBAR_INOUT3 0x018 0x208 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXIO1_D01 0x018 0x208 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_01_GPIO4_IO01 0x018 0x208 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02 0x01C 0x20C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXPWM4_PWM1_A 0x01C 0x20C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x01C 0x20C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_02_XBAR_INOUT4 0x01C 0x20C 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXIO1_D02 0x01C 0x20C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_02_GPIO4_IO02 0x01C 0x20C 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03 0x020 0x210 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXPWM4_PWM1_B 0x020 0x210 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x020 0x210 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_03_XBAR_INOUT5 0x020 0x210 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXIO1_D03 0x020 0x210 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_03_GPIO4_IO03 0x020 0x210 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04 0x024 0x214 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXPWM4_PWM2_A 0x024 0x214 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_04_SAI2_TX_DATA 0x024 0x214 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_04_XBAR_INOUT6 0x024 0x214 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXIO1_D04 0x024 0x214 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_04_GPIO4_IO04 0x024 0x214 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05 0x028 0x218 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXPWM4_PWM2_B 0x028 0x218 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x028 0x218 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_05_XBAR_INOUT7 0x028 0x218 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXIO1_D05 0x028 0x218 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_05_GPIO4_IO05 0x028 0x218 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06 0x02C 0x21C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXPWM2_PWM0_A 0x02C 0x21C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK 0x02C 0x21C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_06_XBAR_INOUT8 0x02C 0x21C 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXIO1_D06 0x02C 0x21C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_06_GPIO4_IO06 0x02C 0x21C 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07 0x030 0x220 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXPWM2_PWM0_B 0x030 0x220 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_07_SAI2_MCLK 0x030 0x220 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_07_XBAR_INOUT9 0x030 0x220 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXIO1_D07 0x030 0x220 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_07_GPIO4_IO07 0x030 0x220 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00 0x034 0x224 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXPWM2_PWM1_A 0x034 0x224 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x034 0x224 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_08_XBAR_INOUT17 0x034 0x224 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXIO1_D08 0x034 0x224 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_08_GPIO4_IO08 0x034 0x224 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0x038 0x228 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXPWM2_PWM1_B 0x038 0x228 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC 0x038 0x228 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXCAN2_TX 0x038 0x228 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXIO1_D09 0x038 0x228 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_09_GPIO4_IO09 0x038 0x228 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01 0x03C 0x22C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXPWM2_PWM2_A 0x03C 0x22C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK 0x03C 0x22C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXCAN2_RX 0x03C 0x22C 0x450 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXIO1_D10 0x03C 0x22C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_10_GPIO4_IO10 0x03C 0x22C 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02 0x040 0x230 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXPWM2_PWM2_B 0x040 0x230 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_11_LPI2C4_SDA 0x040 0x230 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_11_USDHC2_RESET_B 0x040 0x230 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXIO1_D11 0x040 0x230 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_11_GPIO4_IO11 0x040 0x230 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03 0x044 0x234 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_12_XBAR_INOUT24 0x044 0x234 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_12_LPI2C4_SCL 0x044 0x234 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_12_USDHC2_WP 0x044 0x234 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_12_FLEXPWM1_PWM3_A 0x044 0x234 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_12_GPIO4_IO12 0x044 0x234 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04 0x048 0x238 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_13_XBAR_INOUT25 0x048 0x238 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_13_LPUART3_TXD 0x048 0x238 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_13_MQS_RIGHT 0x048 0x238 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_13_FLEXPWM1_PWM3_B 0x048 0x238 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_13_GPIO4_IO13 0x048 0x238 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05 0x04C 0x23C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_14_XBAR_INOUT19 0x04C 0x23C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_14_LPUART3_RXD 0x04C 0x23C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_14_MQS_LEFT 0x04C 0x23C 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x04C 0x23C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_14_GPIO4_IO14 0x04C 0x23C 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06 0x050 0x240 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_15_XBAR_INOUT20 0x050 0x240 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_15_LPUART3_CTS_B 0x050 0x240 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_15_SPDIF_OUT 0x050 0x240 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_15_TMR3_TIMER0 0x050 0x240 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_15_GPIO4_IO15 0x050 0x240 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07 0x054 0x244 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_16_XBAR_INOUT21 0x054 0x244 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_16_LPUART3_RTS_B 0x054 0x244 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_16_SPDIF_IN 0x054 0x244 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_16_TMR3_TIMER1 0x054 0x244 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_16_GPIO4_IO16 0x054 0x244 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08 0x058 0x248 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXPWM4_PWM3_A 0x058 0x248 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_17_LPUART4_CTS_B 0x058 0x248 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXCAN1_TX 0x058 0x248 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_17_TMR3_TIMER2 0x058 0x248 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_17_GPIO4_IO17 0x058 0x248 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09 0x05C 0x24C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXPWM4_PWM3_B 0x05C 0x24C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_18_LPUART4_RTS_B 0x05C 0x24C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXCAN1_RX 0x05C 0x24C 0x44C 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_18_TMR3_TIMER3 0x05C 0x24C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_18_GPIO4_IO18 0x05C 0x24C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL 0x05C 0x24C 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11 0x060 0x250 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_19_FLEXPWM2_PWM3_A 0x060 0x250 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_19_LPUART4_TXD 0x060 0x250 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_19_ENET_RX_DATA01 0x060 0x250 0x438 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_19_TMR2_TIMER0 0x060 0x250 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_19_GPIO4_IO19 0x060 0x250 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_19_SNVS_VIO_5 0x060 0x250 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12 0x064 0x254 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_20_FLEXPWM2_PWM3_B 0x064 0x254 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_20_LPUART4_RXD 0x064 0x254 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_20_ENET_RX_DATA00 0x064 0x254 0x434 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_20_TMR2_TIMER0 0x064 0x254 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_20_GPIO4_IO20 0x064 0x254 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0 0x068 0x258 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_21_FLEXPWM3_PWM3_A 0x068 0x258 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_21_LPI2C3_SDA 0x068 0x258 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_21_ENET_TX_DATA01 0x068 0x258 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_21_TMR2_TIMER2 0x068 0x258 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_21_GPIO4_IO21 0x068 0x258 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1 0x06C 0x25C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_22_FLEXPWM3_PWM3_B 0x06C 0x25C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_22_LPI2C3_SCL 0x06C 0x25C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_22_ENET_TX_DATA00 0x06C 0x25C 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_22_TMR2_TIMER3 0x06C 0x25C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_22_GPIO4_IO22 0x06C 0x25C 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10 0x070 0x260 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_23_FLEXPWM1_PWM0_A 0x070 0x260 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_23_LPUART5_TXD 0x070 0x260 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_23_ENET_RX_EN 0x070 0x260 0x43C 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 0x070 0x260 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_23_GPIO4_IO23 0x070 0x260 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS 0x074 0x264 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_24_FLEXPWM1_PWM0_B 0x074 0x264 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_24_LPUART5_RXD 0x074 0x264 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_24_ENET_TX_EN 0x074 0x264 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 0x074 0x264 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_24_GPIO4_IO24 0x074 0x264 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS 0x078 0x268 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_25_FLEXPWM1_PWM1_A 0x078 0x268 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_25_LPUART6_TXD 0x078 0x268 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_TX_CLK 0x078 0x268 0x448 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_REF_CLK 0x078 0x268 0x42C 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_25_GPIO4_IO25 0x078 0x268 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK 0x07C 0x26C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXPWM1_PWM1_B 0x07C 0x26C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_26_LPUART6_RXD 0x07C 0x26C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_26_ENET_RX_ER 0x07C 0x26C 0x440 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXIO1_D12 0x07C 0x26C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_26_GPIO4_IO26 0x07C 0x26C 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE 0x080 0x270 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXPWM1_PWM2_A 0x080 0x270 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_27_LPUART5_RTS_B 0x080 0x270 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_27_LPSPI1_SCK 0x080 0x270 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXIO1_D13 0x080 0x270 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_27_GPIO4_IO27 0x080 0x270 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE 0x084 0x274 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXPWM1_PWM2_B 0x084 0x274 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_28_LPUART5_CTS_B 0x084 0x274 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_28_LPSPI1_SDO 0x084 0x274 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXIO1_D14 0x084 0x274 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_28_GPIO4_IO28 0x084 0x274 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0 0x088 0x278 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXPWM3_PWM0_A 0x088 0x278 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_29_LPUART6_RTS_B 0x088 0x278 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_29_LPSPI1_SDI 0x088 0x278 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXIO1_D15 0x088 0x278 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_29_GPIO4_IO29 0x088 0x278 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08 0x08C 0x27C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_30_FLEXPWM3_PWM0_B 0x08C 0x27C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_30_LPUART6_CTS_B 0x08C 0x27C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 0x08C 0x27C 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_30_CSI_DATA23 0x08C 0x27C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_30_GPIO4_IO30 0x08C 0x27C 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09 0x090 0x280 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_31_FLEXPWM3_PWM1_A 0x090 0x280 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_31_LPUART7_TXD 0x090 0x280 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 0x090 0x280 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_31_CSI_DATA22 0x090 0x280 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_31_GPIO4_IO31 0x090 0x280 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10 0x094 0x284 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_32_FLEXPWM3_PWM1_B 0x094 0x284 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_32_LPUART7_RXD 0x094 0x284 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_32_CCM_PMIC_READY 0x094 0x284 0x3FC 0x3 0x4
+#define MXRT1050_IOMUXC_GPIO_EMC_32_CSI_DATA21 0x094 0x284 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_32_GPIO3_IO18 0x094 0x284 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11 0x098 0x288 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_33_FLEXPWM3_PWM2_A 0x098 0x288 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_33_USDHC1_RESET_B 0x098 0x288 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_33_SAI3_RX_DATA 0x098 0x288 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_33_CSI_DATA20 0x098 0x288 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_33_GPIO3_IO19 0x098 0x288 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12 0x09C 0x28C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_34_FLEXPWM3_PWM2_B 0x09C 0x28C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_34_USDHC1_VSELECT 0x09C 0x28C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC 0x09C 0x28C 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_34_CSI_DATA19 0x09C 0x28C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_34_GPIO3_IO20 0x09C 0x28C 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13 0x0A0 0x290 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_35_XBAR_INOUT18 0x0A0 0x290 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 0x0A0 0x290 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK 0x0A0 0x290 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_35_CSI_DATA18 0x0A0 0x290 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_35_GPIO3_IO21 0x0A0 0x290 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_35_USDHC1_CD_B 0x0A0 0x290 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14 0x0A4 0x294 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_36_XBAR_INOUT22 0x0A4 0x294 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 0x0A4 0x294 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_36_SAI3_TX_DATA 0x0A4 0x294 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_36_CSI_DATA17 0x0A4 0x294 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_36_GPIO3_IO22 0x0A4 0x294 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_36_USDHC1_WP 0x0A4 0x294 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15 0x0A8 0x298 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_37_XBAR_INOUT23 0x0A8 0x298 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 0x0A8 0x298 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_37_SAI3_MCLK 0x0A8 0x298 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_37_CSI_DATA16 0x0A8 0x298 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_37_GPIO3_IO23 0x0A8 0x298 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_37_USDHC2_WP 0x0A8 0x298 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01 0x0AC 0x29C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_38_FLEXPWM1_PWM3_A 0x0AC 0x29C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_38_LPUART8_TXD 0x0AC 0x29C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK 0x0AC 0x29C 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_38_CSI_FIELD 0x0AC 0x29C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_38_GPIO3_IO24 0x0AC 0x29C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_38_USDHC2_VSELECT 0x0AC 0x29C 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS 0x0B0 0x2A0 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_39_FLEXPWM1_PWM3_B 0x0B0 0x2A0 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_39_LPUART8_RXD 0x0B0 0x2A0 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC 0x0B0 0x2A0 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_39_WDOG1_B 0x0B0 0x2A0 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_39_GPIO3_IO25 0x0B0 0x2A0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_39_USDHC2_CD_B 0x0B0 0x2A0 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_40_SEMC_RDY 0x0B4 0x2A4 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 0x0B4 0x2A4 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 0x0B4 0x2A4 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_40_USB_OTG2_OC 0x0B4 0x2A4 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_40_ENET_MDC 0x0B4 0x2A4 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_40_GPIO3_IO26 0x0B4 0x2A4 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_40_USDHC2_RESET_B 0x0B4 0x2A4 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_41_SEMC_CSX0 0x0B8 0x2A8 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 0x0B8 0x2A8 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 0x0B8 0x2A8 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_41_USB_OTG2_PWR 0x0B8 0x2A8 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_41_ENET_MDIO 0x0B8 0x2A8 0x430 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_41_GPIO3_IO27 0x0B8 0x2A8 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_41_USDHC2_VSELECT 0x0B8 0x2A8 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWM3_A 0x0BC 0x2AC 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_00_XBAR_INOUT14 0x0BC 0x2AC 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_00_REF_CLK_32K 0x0BC 0x2AC 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID 0x0BC 0x2AC 0x3F8 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS 0x0BC 0x2AC 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x0BC 0x2AC 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B 0x0BC 0x2AC 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK 0x0BC 0x2AC 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWM3_B 0x0C0 0x2B0 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_01_XBAR_INOUT15 0x0C0 0x2B0 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_01_REF_CLK_24M 0x0C0 0x2B0 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID 0x0C0 0x2B0 0x3F4 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS 0x0C0 0x2B0 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x0C0 0x2B0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_01_EWM_OUT_B 0x0C0 0x2B0 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO 0x0C0 0x2B0 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX 0x0C4 0x2B4 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_02_XBAR_INOUT16 0x0C4 0x2B4 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPUART6_TXD 0x0C4 0x2B4 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR 0x0C4 0x2B4 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWM0_X 0x0C4 0x2B4 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0C4 0x2B4 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ 0x0C4 0x2B4 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI 0x0C4 0x2B4 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX 0x0C8 0x2B8 0x450 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_03_XBAR_INOUT17 0x0C8 0x2B8 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPUART6_RXD 0x0C8 0x2B8 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x0C8 0x2B8 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWM1_X 0x0C8 0x2B8 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x0C8 0x2B8 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_03_REF_CLK_24M 0x0C8 0x2B8 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 0x0C8 0x2B8 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00 0x0CC 0x2BC 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_04_MQS_RIGHT 0x0CC 0x2BC 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03 0x0CC 0x2BC 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC 0x0CC 0x2BC 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_04_CSI_DATA09 0x0CC 0x2BC 0x41C 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x0CC 0x2BC 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00 0x0CC 0x2BC 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1 0x0CC 0x2BC 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01 0x0D0 0x2C0 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_05_MQS_LEFT 0x0D0 0x2C0 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02 0x0D0 0x2C0 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK 0x0D0 0x2C0 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_05_CSI_DATA08 0x0D0 0x2C0 0x418 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x0D0 0x2C0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_05_XBAR_INOUT17 0x0D0 0x2C0 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2 0x0D0 0x2C0 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_06_JTAG_TMS 0x0D4 0x2C4 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 0x0D4 0x2C4 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK 0x0D4 0x2C4 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK 0x0D4 0x2C4 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_06_CSI_DATA07 0x0D4 0x2C4 0x414 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x0D4 0x2C4 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_06_XBAR_INOUT18 0x0D4 0x2C4 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3 0x0D4 0x2C4 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_07_JTAG_TCK 0x0D8 0x2C8 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 0x0D8 0x2C8 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_TX_ER 0x0D8 0x2C8 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC 0x0D8 0x2C8 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_07_CSI_DATA06 0x0D8 0x2C8 0x410 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x0D8 0x2C8 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_07_XBAR_INOUT19 0x0D8 0x2C8 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT 0x0D8 0x2C8 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_08_JTAG_MOD 0x0DC 0x2CC 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 0x0DC 0x2CC 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03 0x0DC 0x2CC 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA 0x0DC 0x2CC 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_08_CSI_DATA05 0x0DC 0x2CC 0x40C 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x0DC 0x2CC 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_08_XBAR_INOUT20 0x0DC 0x2CC 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN 0x0DC 0x2CC 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_09_JTAG_TDI 0x0E0 0x2D0 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWM3_A 0x0E0 0x2D0 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02 0x0E0 0x2D0 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA 0x0E0 0x2D0 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_09_CSI_DATA04 0x0E0 0x2D0 0x408 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x0E0 0x2D0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_09_XBAR_INOUT21 0x0E0 0x2D0 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPT2_CLK 0x0E0 0x2D0 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_10_JTAG_TDO 0x0E4 0x2D4 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWM3_A 0x0E4 0x2D4 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_CRS 0x0E4 0x2D4 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_10_SAI2_MCLK 0x0E4 0x2D4 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_10_CSI_DATA03 0x0E4 0x2D4 0x404 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x0E4 0x2D4 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_10_XBAR_INOUT22 0x0E4 0x2D4 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT 0x0E4 0x2D4 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB 0x0E8 0x2D8 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWM3_B 0x0E8 0x2D8 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_COL 0x0E8 0x2D8 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_11_WDOG1_B 0x0E8 0x2D8 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_11_CSI_DATA02 0x0E8 0x2D8 0x400 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x0E8 0x2D8 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_11_XBAR_INOUT23 0x0E8 0x2D8 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN 0x0E8 0x2D8 0x444 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL 0x0EC 0x2DC 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY 0x0EC 0x2DC 0x3FC 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0x0EC 0x2DC 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_12_WDOG2_B 0x0EC 0x2DC 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWM2_X 0x0EC 0x2DC 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x0EC 0x2DC 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT 0x0EC 0x2DC 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_12_NMI 0x0EC 0x2DC 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x0F0 0x2E0 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPT1_CLK 0x0F0 0x2E0 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0x0F0 0x2E0 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_13_EWM_OUT_B 0x0F0 0x2E0 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWM3_X 0x0F0 0x2E0 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x0F0 0x2E0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN 0x0F0 0x2E0 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_13_REF_CLK_24M 0x0F0 0x2E0 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC 0x0F4 0x2E4 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_14_XBAR_INOUT24 0x0F4 0x2E4 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B 0x0F4 0x2E4 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT 0x0F4 0x2E4 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_14_CSI_VSYNC 0x0F4 0x2E4 0x428 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x0F4 0x2E4 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x0F4 0x2E4 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR 0x0F8 0x2E8 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_15_XBAR_INOUT25 0x0F8 0x2E8 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B 0x0F8 0x2E8 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN 0x0F8 0x2E8 0x444 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_15_CSI_HSYNC 0x0F8 0x2E8 0x420 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x0F8 0x2E8 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x0F8 0x2E8 0x450 0x6 0x2
+#define MXRT1050_IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB 0x0F8 0x2E8 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID 0x0FC 0x2EC 0x3F4 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_00_TMR3_TIMER0 0x0FC 0x2EC 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B 0x0FC 0x2EC 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL 0x0FC 0x2EC 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_00_WDOG1_B 0x0FC 0x2EC 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x0FC 0x2EC 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USDHC1_WP 0x0FC 0x2EC 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_00_KPP_ROW07 0x0FC 0x2EC 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR 0x100 0x2F0 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_01_TMR3_TIMER1 0x100 0x2F0 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B 0x100 0x2F0 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA 0x100 0x2F0 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY 0x100 0x2F0 0x3FC 0x4 0x2
+#define MXRT1050_IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x100 0x2F0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT 0x100 0x2F0 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_01_KPP_COL07 0x100 0x2F0 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID 0x104 0x2F4 0x3F4 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_02_TMR3_TIMER2 0x104 0x2F4 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_02_LPUART2_TXD 0x104 0x2F4 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_02_SPDIF_OUT 0x104 0x2F4 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT 0x104 0x2F4 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x104 0x2F4 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B 0x104 0x2F4 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_02_KPP_ROW06 0x104 0x2F4 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC 0x108 0x2F8 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_03_TMR3_TIMER3 0x108 0x2F8 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_03_LPUART2_RXD 0x108 0x2F8 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_03_SPDIF_IN 0x108 0x2F8 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN 0x108 0x2F8 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x108 0x2F8 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B 0x108 0x2F8 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_03_KPP_COL06 0x108 0x2F8 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3 0x10C 0x2FC 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_04_ENET_MDC 0x10C 0x2FC 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B 0x10C 0x2FC 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK 0x10C 0x2FC 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK 0x10C 0x2FC 0x424 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x10C 0x2FC 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 0x10C 0x2FC 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_04_KPP_ROW05 0x10C 0x2FC 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2 0x110 0x300 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_05_ENET_MDIO 0x110 0x300 0x430 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B 0x110 0x300 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_05_SPDIF_OUT 0x110 0x300 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_05_CSI_MCLK 0x110 0x300 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x110 0x300 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 0x110 0x300 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_05_KPP_COL05 0x110 0x300 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1 0x114 0x304 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA 0x114 0x304 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPUART3_TXD 0x114 0x304 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK 0x114 0x304 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_06_CSI_VSYNC 0x114 0x304 0x428 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x114 0x304 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 0x114 0x304 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_06_KPP_ROW04 0x114 0x304 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0 0x118 0x308 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL 0x118 0x308 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPUART3_RXD 0x118 0x308 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK 0x118 0x308 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_07_CSI_HSYNC 0x118 0x308 0x420 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x118 0x308 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 0x118 0x308 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_07_KPP_COL04 0x118 0x308 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXSPI_A_SS1_B 0x11C 0x30C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWM0_A 0x11C 0x30C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX 0x11C 0x30C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY 0x11C 0x30C 0x3FC 0x3 0x3
+#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CSI_DATA09 0x11C 0x30C 0x41C 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x11C 0x30C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_08_USDHC2_CMD 0x11C 0x30C 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_08_KPP_ROW03 0x11C 0x30C 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXSPI_A_DQS 0x120 0x310 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWM1_A 0x120 0x310 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX 0x120 0x310 0x44C 0x2 0x2
+#define MXRT1050_IOMUXC_GPIO_AD_B1_09_SAI1_MCLK 0x120 0x310 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_09_CSI_DATA08 0x120 0x310 0x418 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x120 0x310 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_09_USDHC2_CLK 0x120 0x310 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_09_KPP_COL03 0x120 0x310 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_10_FLEXSPI_A_DATA3 0x124 0x314 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_10_WDOG1_B 0x124 0x314 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_10_LPUART8_TXD 0x124 0x314 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC 0x124 0x314 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_10_CSI_DATA07 0x124 0x314 0x414 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x124 0x314 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_10_USDHC2_WP 0x124 0x314 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_10_KPP_ROW02 0x124 0x314 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_11_FLEXSPI_A_DATA2 0x128 0x318 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_11_EWM_OUT_B 0x128 0x318 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_11_LPUART8_RXD 0x128 0x318 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK 0x128 0x318 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_11_CSI_DATA06 0x128 0x318 0x410 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x128 0x318 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B 0x128 0x318 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_11_KPP_COL02 0x128 0x318 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_12_FLEXSPI_A_DATA1 0x12C 0x31C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_12_ACMP1_OUT 0x12C 0x31C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 0x12C 0x31C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00 0x12C 0x31C 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_12_CSI_DATA05 0x12C 0x31C 0x40C 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x12C 0x31C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4 0x12C 0x31C 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_12_KPP_ROW01 0x12C 0x31C 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_13_FLEXSPI_A_DATA0 0x130 0x320 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_13_ACMP2_OUT 0x130 0x320 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI 0x130 0x320 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00 0x130 0x320 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_13_CSI_DATA04 0x130 0x320 0x408 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x130 0x320 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5 0x130 0x320 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_13_KPP_COL01 0x130 0x320 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_14_FLEXSPI_A_SCLK 0x134 0x324 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_14_ACMP3_OUT 0x134 0x324 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x134 0x324 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK 0x134 0x324 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_14_CSI_DATA03 0x134 0x324 0x404 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x134 0x324 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6 0x134 0x324 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_14_KPP_ROW00 0x134 0x324 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_15_FLEXSPI_A_SS0_B 0x138 0x328 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_15_ACMP4_OUT 0x138 0x328 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK 0x138 0x328 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC 0x138 0x328 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_15_CSI_DATA02 0x138 0x328 0x400 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x138 0x328 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7 0x138 0x328 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_15_KPP_COL00 0x138 0x328 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x13C 0x32C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_00_TMR1_TIMER0 0x13C 0x32C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_00_MQS_RIGHT 0x13C 0x32C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_00_LPSPI4_PCS0 0x13C 0x32C 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_00_FLEXIO2_D00 0x13C 0x32C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_00_GPIO2_IO00 0x13C 0x32C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_00_SEMC_CSX1 0x13C 0x32C 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x140 0x330 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_01_TMR1_TIMER1 0x140 0x330 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_01_MQS_LEFT 0x140 0x330 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_01_LPSPI4_SDI 0x140 0x330 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_01_FLEXIO2_D01 0x140 0x330 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_01_GPIO2_IO01 0x140 0x330 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_01_SEMC_CSX2 0x140 0x330 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x144 0x334 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_02_TMR1_TIMER2 0x144 0x334 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXCAN1_TX 0x144 0x334 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_02_LPSPI4_SDO 0x144 0x334 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXIO2_D02 0x144 0x334 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_02_GPIO2_IO02 0x144 0x334 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_02_SEMC_CSX3 0x144 0x334 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x148 0x338 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_03_TMR2_TIMER0 0x148 0x338 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXCAN1_RX 0x148 0x338 0x44C 0x2 0x3
+#define MXRT1050_IOMUXC_GPIO_B0_03_LPSPI4_SCK 0x148 0x338 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXIO2_D03 0x148 0x338 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_03_GPIO2_IO03 0x148 0x338 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB 0x148 0x338 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x14C 0x33C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_04_TMR2_TIMER1 0x14C 0x33C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_04_LPI2C2_SCL 0x14C 0x33C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_04_ARM_TRACE00 0x14C 0x33C 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_04_FLEXIO2_D04 0x14C 0x33C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_04_GPIO2_IO04 0x14C 0x33C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_04_SRC_BT_CFG00 0x14C 0x33C 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x150 0x340 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_05_TMR2_TIMER2 0x150 0x340 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_05_LPI2C2_SDA 0x150 0x340 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_05_ARM_TRACE01 0x150 0x340 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_05_FLEXIO2_D05 0x150 0x340 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_05_GPIO2_IO05 0x150 0x340 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_05_SRC_BT_CFG01 0x150 0x340 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x154 0x344 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_06_TMR3_TIMER0 0x154 0x344 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXPWM2_PWM0_A 0x154 0x344 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_06_ARM_TRACE02 0x154 0x344 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXIO2_D06 0x154 0x344 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_06_GPIO2_IO06 0x154 0x344 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_06_SRC_BT_CFG02 0x154 0x344 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x158 0x348 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_07_TMR3_TIMER1 0x158 0x348 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXPWM2_PWM0_B 0x158 0x348 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_07_ARM_TRACE03 0x158 0x348 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXIO2_D07 0x158 0x348 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_07_GPIO2_IO07 0x158 0x348 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_07_SRC_BT_CFG03 0x158 0x348 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x15C 0x34C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_08_TMR3_TIMER2 0x15C 0x34C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXPWM2_PWM1_A 0x15C 0x34C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_08_LPUART3_TXD 0x15C 0x34C 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXIO2_D08 0x15C 0x34C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_08_GPIO2_IO08 0x15C 0x34C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_08_SRC_BT_CFG04 0x15C 0x34C 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x160 0x350 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_09_TMR4_TIMER0 0x160 0x350 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXPWM2_PWM1_B 0x160 0x350 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_09_LPUART3_RXD 0x160 0x350 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXIO2_D09 0x160 0x350 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_09_GPIO2_IO09 0x160 0x350 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_09_SRC_BT_CFG05 0x160 0x350 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x164 0x354 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_10_TMR4_TIMER1 0x164 0x354 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXPWM2_PWM2_A 0x164 0x354 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_10_SAI1_TX_DATA03 0x164 0x354 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXIO2_D10 0x164 0x354 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_10_GPIO2_IO10 0x164 0x354 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_10_SRC_BT_CFG06 0x164 0x354 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x168 0x358 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_11_TMR4_TIMER2 0x168 0x358 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXPWM2_PWM2_B 0x168 0x358 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_11_SAI1_TX_DATA02 0x168 0x358 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXIO2_D11 0x168 0x358 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_11_GPIO2_IO11 0x168 0x358 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_11_SRC_BT_CFG07 0x168 0x358 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x16C 0x35C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_12_XBAR_INOUT10 0x16C 0x35C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_12_ARM_TRACE_CLK 0x16C 0x35C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_12_SAI1_TX_DATA01 0x16C 0x35C 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_12_FLEXIO2_D12 0x16C 0x35C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_12_GPIO2_IO12 0x16C 0x35C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_12_SRC_BT_CFG08 0x16C 0x35C 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x170 0x360 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_13_XBAR_INOUT11 0x170 0x360 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_13_ARM_TRACE_SWO 0x170 0x360 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_13_SAI1_MCLK 0x170 0x360 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_13_FLEXIO2_D13 0x170 0x360 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_13_GPIO2_IO13 0x170 0x360 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_13_SRC_BT_CFG09 0x170 0x360 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x174 0x364 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_14_XBAR_INOUT12 0x174 0x364 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_14_ARM_CM7_TXEV 0x174 0x364 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_14_SAI1_RX_SYNC 0x174 0x364 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_14_FLEXIO2_D14 0x174 0x364 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_14_GPIO2_IO14 0x174 0x364 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_14_SRC_BT_CFG10 0x174 0x364 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x178 0x368 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_15_XBAR_INOUT13 0x178 0x368 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_15_ARM_CM7_RXEV 0x178 0x368 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_15_SAI1_RX_BCLK 0x178 0x368 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_15_FLEXIO2_D15 0x178 0x368 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_15_GPIO2_IO15 0x178 0x368 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_15_SRC_BT_CFG11 0x178 0x368 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_00_LCD_DATA12 0x17C 0x36C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_00_XBAR_INOUT14 0x17C 0x36C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_00_LPUART4_TXD 0x17C 0x36C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_00_SAI1_RX_DATA00 0x17C 0x36C 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXIO2_D16 0x17C 0x36C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_00_GPIO2_IO16 0x17C 0x36C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXPWM1_PWM3_A 0x17C 0x36C 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x180 0x370 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_01_XBAR_INOUT15 0x180 0x370 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_01_LPUART4_RXD 0x180 0x370 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_01_SAI1_TX_DATA00 0x180 0x370 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXIO2_D17 0x180 0x370 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_01_GPIO2_IO17 0x180 0x370 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXPWM1_PWM3_B 0x180 0x370 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x184 0x374 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_02_XBAR_INOUT16 0x184 0x374 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_02_LPSPI4_PCS2 0x184 0x374 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_02_SAI1_TX_BCLK 0x184 0x374 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXIO2_D18 0x184 0x374 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_02_GPIO2_IO18 0x184 0x374 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXPWM2_PWM3_A 0x184 0x374 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x188 0x378 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_03_XBAR_INOUT17 0x188 0x378 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_03_LPSPI4_PCS1 0x188 0x378 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_03_SAI1_TX_SYNC 0x188 0x378 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXIO2_D19 0x188 0x378 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_03_GPIO2_IO19 0x188 0x378 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXPWM2_PWM3_B 0x188 0x378 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_04_LCD_DATA16 0x18C 0x37C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_04_LPSPI4_PCS0 0x18C 0x37C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_04_CSI_DATA15 0x18C 0x37C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_04_ENET_RX_DATA00 0x18C 0x37C 0x434 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_04_FLEXIO2_D20 0x18C 0x37C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_04_GPIO2_IO20 0x18C 0x37C 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_05_LCD_DATA17 0x190 0x380 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_05_LPSPI4_SDI 0x190 0x380 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_05_CSI_DATA14 0x190 0x380 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_05_ENET_RX_DATA01 0x190 0x380 0x438 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_05_FLEXIO2_D21 0x190 0x380 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_05_GPIO2_IO21 0x190 0x380 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_06_LCD_DATA18 0x194 0x384 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_06_LPSPI4_SDO 0x194 0x384 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_06_CSI_DATA13 0x194 0x384 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_06_ENET_RX_EN 0x194 0x384 0x43C 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_06_FLEXIO2_D22 0x194 0x384 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_06_GPIO2_IO22 0x194 0x384 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_07_LCD_DATA19 0x198 0x388 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_07_LPSPI4_SCK 0x198 0x388 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_07_CSI_DATA12 0x198 0x388 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_07_ENET_TX_DATA00 0x198 0x388 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_07_FLEXIO2_D23 0x198 0x388 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_07_GPIO2_IO23 0x198 0x388 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_08_LCD_DATA20 0x19C 0x38C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_08_TMR1_TIMER3 0x19C 0x38C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_08_CSI_DATA11 0x19C 0x38C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_08_ENET_TX_DATA01 0x19C 0x38C 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXIO2_D24 0x19C 0x38C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_08_GPIO2_IO24 0x19C 0x38C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXCAN2_TX 0x19C 0x38C 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_09_LCD_DATA21 0x1A0 0x390 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_09_TMR2_TIMER3 0x1A0 0x390 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_09_CSI_DATA10 0x1A0 0x390 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_09_ENET_TX_EN 0x1A0 0x390 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXIO2_D25 0x1A0 0x390 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_09_GPIO2_IO25 0x1A0 0x390 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXCAN2_RX 0x1A0 0x390 0x450 0x6 0x3
+
+#define MXRT1050_IOMUXC_GPIO_B1_10_LCD_DATA22 0x1A4 0x394 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_10_TMR3_TIMER3 0x1A4 0x394 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_10_CSI_DATA00 0x1A4 0x394 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_TX_CLK 0x1A4 0x394 0x448 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_10_FLEXIO2_D26 0x1A4 0x394 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_10_GPIO2_IO26 0x1A4 0x394 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_REF_CLK 0x1A4 0x394 0x42C 0x6 0x1
+
+#define MXRT1050_IOMUXC_GPIO_B1_11_LCD_DATA23 0x1A8 0x398 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_11_TMR4_TIMER3 0x1A8 0x398 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_11_CSI_DATA01 0x1A8 0x398 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_11_ENET_RX_ER 0x1A8 0x398 0x440 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_11_FLEXIO2_D27 0x1A8 0x398 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_11_GPIO2_IO27 0x1A8 0x398 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_11_LPSPI4_PCS3 0x1A8 0x398 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_12_LPUART5_TXD 0x1AC 0x39C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_12_CSI_PIXCLK 0x1AC 0x39C 0x424 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN 0x1AC 0x39C 0x444 0x3 0x2
+#define MXRT1050_IOMUXC_GPIO_B1_12_FLEXIO2_D28 0x1AC 0x39C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_12_GPIO2_IO28 0x1AC 0x39C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1AC 0x39C 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_13_WDOG1_B 0x1B0 0x3A0 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_13_LPUART5_RXD 0x1B0 0x3A0 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_13_CSI_VSYNC 0x1B0 0x3A0 0x428 0x2 0x2
+#define MXRT1050_IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT 0x1B0 0x3A0 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_13_FLEXIO2_D29 0x1B0 0x3A0 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_13_GPIO2_IO29 0x1B0 0x3A0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_13_USDHC1_WP 0x1B0 0x3A0 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_14_ENET_MDC 0x1B4 0x3A4 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXPWM4_PWM2_A 0x1B4 0x3A4 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_14_CSI_HSYNC 0x1B4 0x3A4 0x420 0x2 0x2
+#define MXRT1050_IOMUXC_GPIO_B1_14_XBAR_INOUT02 0x1B4 0x3A4 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXIO2_D30 0x1B4 0x3A4 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_14_GPIO2_IO30 0x1B4 0x3A4 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0x1B4 0x3A4 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_15_ENET_MDIO 0x1B8 0x3A8 0x430 0x0 0x2
+#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXPWM4_PWM3_A 0x1B8 0x3A8 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_15_CSI_MCLK 0x1B8 0x3A8 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_15_XBAR_INOUT03 0x1B8 0x3A8 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXIO2_D31 0x1B8 0x3A8 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x1B8 0x3A8 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_15_USDHC1_RESET_B 0x1B8 0x3A8 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x1BC 0x3AC 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWM0_A 0x1BC 0x3AC 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x1BC 0x3AC 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_00_XBAR_INOUT04 0x1BC 0x3AC 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK 0x1BC 0x3AC 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 0x1BC 0x3AC 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B 0x1BC 0x3AC 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x1C0 0x3B0 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWM0_B 0x1C0 0x3B0 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x1C0 0x3B0 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_01_XBAR_INOUT05 0x1C0 0x3B0 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 0x1C0 0x3B0 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 0x1C0 0x3B0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B 0x1C0 0x3B0 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x1C4 0x3B4 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWM1_A 0x1C4 0x3B4 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B 0x1C4 0x3B4 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_02_XBAR_INOUT06 0x1C4 0x3B4 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO 0x1C4 0x3B4 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 0x1C4 0x3B4 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x1C8 0x3B8 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWM1_B 0x1C8 0x3B8 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B 0x1C8 0x3B8 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_03_XBAR_INOUT07 0x1C8 0x3B8 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI 0x1C8 0x3B8 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 0x1C8 0x3B8 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x1CC 0x3BC 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWM2_A 0x1CC 0x3BC 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_04_LPUART8_TXD 0x1CC 0x3BC 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_04_XBAR_INOUT08 0x1CC 0x3BC 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B 0x1CC 0x3BC 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 0x1CC 0x3BC 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 0x1CC 0x3BC 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x1D0 0x3C0 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWM2_B 0x1D0 0x3C0 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_05_LPUART8_RXD 0x1D0 0x3C0 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_05_XBAR_INOUT09 0x1D0 0x3C0 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS 0x1D0 0x3C0 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 0x1D0 0x3C0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 0x1D0 0x3C0 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 0x1D4 0x3C4 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 0x1D4 0x3C4 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWM3_A 0x1D4 0x3C4 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03 0x1D4 0x3C4 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_00_LPUART4_TXD 0x1D4 0x3C4 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 0x1D4 0x3C4 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 0x1D8 0x3C8 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2 0x1D8 0x3C8 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWM3_B 0x1D8 0x3C8 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02 0x1D8 0x3C8 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_01_LPUART4_RXD 0x1D8 0x3C8 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x1D8 0x3C8 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 0x1DC 0x3CC 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1 0x1DC 0x3CC 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWM3_A 0x1DC 0x3CC 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01 0x1DC 0x3CC 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX 0x1DC 0x3CC 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 0x1DC 0x3CC 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_02_CCM_WAIT 0x1DC 0x3CC 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 0x1E0 0x3D0 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0 0x1E0 0x3D0 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWM3_B 0x1E0 0x3D0 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_03_SAI1_MCLK 0x1E0 0x3D0 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX 0x1E0 0x3D0 0x44C 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 0x1E0 0x3D0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY 0x1E0 0x3D0 0x3FC 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_04_USDHC2_CLK 0x1E4 0x3D4 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK 0x1E4 0x3D4 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL 0x1E4 0x3D4 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC 0x1E4 0x3D4 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXCAN1_A_SS1_B 0x1E4 0x3D4 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 0x1E4 0x3D4 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_04_CCM_STOP 0x1E4 0x3D4 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_05_USDHC2_CMD 0x1E8 0x3D8 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS 0x1E8 0x3D8 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA 0x1E8 0x3D8 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK 0x1E8 0x3D8 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXCAN1_B_SS0_B 0x1E8 0x3D8 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 0x1E8 0x3D8 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B 0x1EC 0x3DC 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B 0x1EC 0x3DC 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B 0x1EC 0x3DC 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00 0x1EC 0x3DC 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x1EC 0x3DC 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 0x1EC 0x3DC 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SEMC_CSX1 0x1F0 0x3E0 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK 0x1F0 0x3E0 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B 0x1F0 0x3E0 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00 0x1F0 0x3E0 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x1F0 0x3E0 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x1F0 0x3E0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_07_CCM_REF_EN_B 0x1F0 0x3E0 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x1F4 0x3E4 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 0x1F4 0x3E4 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPUART7_TXD 0x1F4 0x3E4 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SAI1_TX_BLCK 0x1F4 0x3E4 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO 0x1F4 0x3E4 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 0x1F4 0x3E4 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SEMC_CSX2 0x1F4 0x3E4 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x1F8 0x3E8 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1 0x1F8 0x3E8 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPUART7_RXD 0x1F8 0x3E8 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC 0x1F8 0x3E8 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x1F8 0x3E8 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 0x1F8 0x3E8 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x1FC 0x3EC 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2 0x1FC 0x3EC 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPUART2_RXD 0x1FC 0x3EC 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x1FC 0x3EC 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x1FC 0x3EC 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x1FC 0x3EC 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x200 0x3F0 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3 0x200 0x3F0 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPUART2_TXD 0x200 0x3F0 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x200 0x3F0 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x200 0x3F0 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x200 0x3F0 0x000 0x5 0x0
+
+#endif /* _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H */
--
2.20.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [U-Boot] [RFC PATCH 3/5] serial_lpuart: add support for i.MXRT
2019-10-30 21:09 [U-Boot] [RFC PATCH 0/5] WIP Add support for i.MXRT family Giulio Benetti
2019-10-30 21:09 ` [U-Boot] [RFC PATCH 1/5] Add support for the NXP IMXRT10xx SoC family Giulio Benetti
2019-10-30 21:09 ` [U-Boot] [RFC PATCH 2/5] pinctrl: add i.MXRT driver Giulio Benetti
@ 2019-10-30 21:09 ` Giulio Benetti
2019-10-30 21:09 ` [U-Boot] [RFC PATCH 4/5] ram: add SDRAM driver for i.MXRT SoCs Giulio Benetti
` (2 subsequent siblings)
5 siblings, 0 replies; 13+ messages in thread
From: Giulio Benetti @ 2019-10-30 21:09 UTC (permalink / raw)
To: u-boot
Add i.MXRT compatible string and cpu type support to lpuart driver,
to use little endian 32 bits configurations.
Also according to RM, the Receive RX FIFO Enable (RXFE) field in LPUART
FIFO register is bit 3, so this definition should change to 0x08 as done
for i.MX8. It needs also to set baudrate the same way as i.MX8 does.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
---
drivers/serial/serial_lpuart.c | 15 +++++++++++----
include/fsl_lpuart.h | 3 ++-
2 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index 4b0a964d1b..52b561b627 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -49,7 +49,7 @@
#define FIFO_RXSIZE_MASK 0x7
#define FIFO_RXSIZE_OFF 0
#define FIFO_TXFE 0x80
-#ifdef CONFIG_ARCH_IMX8
+#if defined(CONFIG_ARCH_IMX8) || defined(CONFIG_ARCH_IMXRT)
#define FIFO_RXFE 0x08
#else
#define FIFO_RXFE 0x40
@@ -67,7 +67,8 @@ enum lpuart_devtype {
DEV_VF610 = 1,
DEV_LS1021A,
DEV_MX7ULP,
- DEV_IMX8
+ DEV_IMX8,
+ DEV_IMXRT,
};
struct lpuart_serial_platdata {
@@ -409,7 +410,8 @@ static int _lpuart32_serial_init(struct udevice *dev)
lpuart_write32(plat->flags, &base->match, 0);
- if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8) {
+ if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8 ||
+ plat->devtype == DEV_IMXRT) {
_lpuart32_serial_setbrg_7ulp(dev, gd->baudrate);
} else {
/* provide data bits, parity, stop bit, etc */
@@ -426,7 +428,8 @@ static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
if (is_lpuart32(dev)) {
- if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8)
+ if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8 ||
+ plat->devtype == DEV_IMXRT)
_lpuart32_serial_setbrg_7ulp(dev, baudrate);
else
_lpuart32_serial_setbrg(dev, baudrate);
@@ -514,6 +517,8 @@ static int lpuart_serial_ofdata_to_platdata(struct udevice *dev)
plat->devtype = DEV_VF610;
else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart"))
plat->devtype = DEV_IMX8;
+ else if (!fdt_node_check_compatible(blob, node, "fsl,imxrt-lpuart"))
+ plat->devtype = DEV_IMXRT;
return 0;
}
@@ -533,6 +538,8 @@ static const struct udevice_id lpuart_serial_ids[] = {
{ .compatible = "fsl,vf610-lpuart"},
{ .compatible = "fsl,imx8qm-lpuart",
.data = LPUART_FLAG_REGMAP_32BIT_REG },
+ { .compatible = "fsl,imxrt-lpuart",
+ .data = LPUART_FLAG_REGMAP_32BIT_REG },
{ }
};
diff --git a/include/fsl_lpuart.h b/include/fsl_lpuart.h
index fc517d4b7f..511fb84367 100644
--- a/include/fsl_lpuart.h
+++ b/include/fsl_lpuart.h
@@ -4,7 +4,8 @@
*
*/
-#if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8)
+#if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8) || \
+ defined(CONFIG_ARCH_IMXRT)
struct lpuart_fsl_reg32 {
u32 verid;
u32 param;
--
2.20.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [U-Boot] [RFC PATCH 4/5] ram: add SDRAM driver for i.MXRT SoCs
2019-10-30 21:09 [U-Boot] [RFC PATCH 0/5] WIP Add support for i.MXRT family Giulio Benetti
` (2 preceding siblings ...)
2019-10-30 21:09 ` [U-Boot] [RFC PATCH 3/5] serial_lpuart: add support for i.MXRT Giulio Benetti
@ 2019-10-30 21:09 ` Giulio Benetti
2019-10-31 12:11 ` Giulio Benetti
2019-10-30 21:09 ` [U-Boot] [RFC PATCH 5/5] Add support for the NXP IMXRT1050-EVK board Giulio Benetti
2019-11-01 12:41 ` [U-Boot] [RFC PATCH 0/5] WIP Add support for i.MXRT family Fabio Estevam
5 siblings, 1 reply; 13+ messages in thread
From: Giulio Benetti @ 2019-10-30 21:09 UTC (permalink / raw)
To: u-boot
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
---
drivers/ram/Kconfig | 8 +
drivers/ram/Makefile | 2 +
drivers/ram/imxrt_sdram.c | 406 +++++++++++++++++++++++
include/dt-bindings/memory/imxrt-sdram.h | 168 ++++++++++
4 files changed, 584 insertions(+)
create mode 100644 drivers/ram/imxrt_sdram.c
create mode 100644 include/dt-bindings/memory/imxrt-sdram.h
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 568d8f2c6a..69b0233a48 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -54,5 +54,13 @@ config K3_AM654_DDRSS
config add support for the initialization of the external
SDRAM devices connected to DDR subsystem.
+config IMXRT_SDRAM
+ bool "Enable i.MXRT SDRAM support"
+ depends on RAM
+ help
+ i.MXRT family devices support smart external memory controller(SEMC)
+ to support external memories like sdram, psram & nand.
+ This driver is for the sdram memory interface with the SEMC.
+
source "drivers/ram/rockchip/Kconfig"
source "drivers/ram/stm32mp1/Kconfig"
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index 976ec66df7..d3813e37e4 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -14,3 +14,5 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_K3_AM654_DDRSS) += k3-am654-ddrss.o
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
+
+obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
diff --git a/drivers/ram/imxrt_sdram.c b/drivers/ram/imxrt_sdram.c
new file mode 100644
index 0000000000..7c157f60e2
--- /dev/null
+++ b/drivers/ram/imxrt_sdram.c
@@ -0,0 +1,406 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <ram.h>
+#include <asm/io.h>
+
+/* SDRAM Command Code */
+#define SD_CC_ARD 0x0 /* Master Bus (AXI) command - Read */
+#define SD_CC_AWR 0x1 /* Master Bus (AXI) command - Write */
+#define SD_CC_IRD 0x8 /* IP command - Read */
+#define SD_CC_IWR 0x9 /* IP command - Write */
+#define SD_CC_IMS 0xA /* IP command - Set Mode Register */
+#define SD_CC_IACT 0xB /* IP command - ACTIVE */
+#define SD_CC_IAF 0xC /* IP command - Auto Refresh */
+#define SD_CC_ISF 0xD /* IP Command - Self Refresh */
+#define SD_CC_IPRE 0xE /* IP command - Precharge */
+#define SD_CC_IPREA 0xF /* IP command - Precharge ALL */
+
+#define SEMC_MCR_MDIS BIT(1)
+#define SEMC_MCR_DQSMD BIT(2)
+
+struct imxrt_semc_regs {
+ /* 0x0 */
+ u32 mcr;
+ u32 iocr;
+ u32 bmcr0;
+ u32 bmcr1;
+ u32 br[9];
+
+ /* 0x34 */
+ u32 res1;
+ u32 inten;
+ u32 intr;
+ /* 0x40 */
+ u32 sdramcr0;
+ u32 sdramcr1;
+ u32 sdramcr2;
+ u32 sdramcr3;
+ /* 0x50 */
+ u32 nandcr0;
+ u32 nandcr1;
+ u32 nandcr2;
+ u32 nandcr3;
+ /* 0x60 */
+ u32 norcr0;
+ u32 norcr1;
+ u32 norcr2;
+ u32 norcr3;
+ /* 0x70 */
+ u32 sramcr0;
+ u32 sramcr1;
+ u32 sramcr2;
+ u32 sramcr3;
+ /* 0x80 */
+ u32 dbicr0;
+ u32 dbicr1;
+ u32 res2[2];
+ /* 0x90 */
+ u32 ipcr0;
+ u32 ipcr1;
+ u32 ipcr2;
+ u32 ipcmd;
+ /* 0xA0 */
+ u32 iptxdat;
+ u32 res3[3];
+ /* 0xB0 */
+ u32 iprxdat;
+ u32 res4[3];
+ /* 0xC0 */
+ u32 sts[16];
+};
+
+#define SEMC_IOCR_MUX_A8_SHIFT 0
+#define SEMC_IOCR_MUX_CSX0_SHIFT 1
+#define SEMC_IOCR_MUX_CSX1_SHIFT 2
+#define SEMC_IOCR_MUX_CSX2_SHIFT 3
+#define SEMC_IOCR_MUX_CSX3_SHIFT 4
+#define SEMC_IOCR_MUX_RDY_SHIFT 5
+
+struct imxrt_sdram_mux {
+ u8 a8;
+ u8 csx0;
+ u8 csx1;
+ u8 csx2;
+ u8 csx3;
+ u8 rdy;
+};
+
+#define SEMC_SDRAMCR0_PS_SHIFT 0
+#define SEMC_SDRAMCR0_BL_SHIFT 4
+#define SEMC_SDRAMCR0_COL_SHIFT 8
+#define SEMC_SDRAMCR0_CL_SHIFT 10
+
+struct imxrt_sdram_control {
+ u8 memory_width;
+ u8 burst_len;
+ u8 no_columns;
+ u8 cas_latency;
+};
+
+#define SEMC_SDRAMCR1_PRE2ACT_SHIFT 0
+#define SEMC_SDRAMCR1_ACT2RW_SHIFT 4
+#define SEMC_SDRAMCR1_RFRC_SHIFT 8
+#define SEMC_SDRAMCR1_WRC_SHIFT 12
+
+struct imxrt_sdram_timing {
+ u8 trp;
+ u8 trcd;
+ u8 trfc;
+ u8 twr;
+#if TODO
+ u8 tmrd;
+ u8 txsr;
+ u8 tras;
+ u8 trc;
+#endif
+};
+
+enum imxrt_semc_bank {
+ SDRAM_BANK1,
+ SDRAM_BANK2,
+ SDRAM_BANK3,
+ SDRAM_BANK4,
+ MAX_SDRAM_BANK,
+};
+
+#define SEMC_BR_VLD_MASK 1
+#define SEMC_BR_MS_SHIFT 1
+
+struct bank_params {
+ enum imxrt_semc_bank target_bank;
+ u32 base_address;
+ u32 memory_size;
+};
+
+struct imxrt_sdram_params {
+ struct imxrt_semc_regs *base;
+
+ struct imxrt_sdram_mux *sdram_mux;
+ struct imxrt_sdram_control *sdram_control;
+ struct imxrt_sdram_timing *sdram_timing;
+
+ struct bank_params bank_params[MAX_SDRAM_BANK];
+ u8 no_sdram_banks;
+};
+
+void imxrt_sdram_wait_ipcmd_done(struct imxrt_semc_regs *regs)
+{
+ do {
+ mdelay(50);
+ /* check for IPCMDDONE or IPCMERR */
+ /* TODO: handle error */
+ } while (!(readl(®s->intr) & 0x3));
+}
+
+u32 imxrt_sdram_ipcmd(struct imxrt_semc_regs *regs, u32 mem_addr, u32 ipcmd,
+ u32 wd)
+{
+ u32 rd = 0x0;
+
+ if (ipcmd == SD_CC_IWR || ((ipcmd & 0x0000FFFF) == SD_CC_IMS))
+ writel(wd & 0x0000FFFF, ®s->iptxdat);
+
+ /* set slave address for every command */
+ writel(mem_addr, ®s->ipcr0);
+
+ /* execute command */
+ writel(0xA55A0000 | (ipcmd & 0x0000FFFF), ®s->ipcmd);
+
+ imxrt_sdram_wait_ipcmd_done(regs);
+
+ if (ipcmd == SD_CC_IRD)
+ rd = readl(®s->iprxdat);
+
+ return rd;
+}
+
+int imxrt_sdram_init(struct udevice *dev)
+{
+ struct imxrt_sdram_params *params = dev_get_platdata(dev);
+ struct imxrt_sdram_mux *mux = params->sdram_mux;
+ struct imxrt_sdram_control *ctrl = params->sdram_control;
+ struct imxrt_sdram_timing *time = params->sdram_timing;
+ struct imxrt_semc_regs *regs = params->base;
+ struct bank_params *bank_params = params->bank_params;
+ int i;
+
+ /* enable the SEMC controller */
+ clrbits_le32(®s->mcr, SEMC_MCR_MDIS);
+ /* set DQS mode from DQS pad */
+ setbits_le32(®s->mcr, SEMC_MCR_DQSMD);
+
+ for (i = 0; i < params->no_sdram_banks; bank_params++, i++)
+ writel((bank_params->base_address & 0xfffff000)
+ | bank_params->memory_size << SEMC_BR_MS_SHIFT
+ | SEMC_BR_VLD_MASK,
+ ®s->br[bank_params->target_bank]);
+
+ writel(mux->a8 << SEMC_IOCR_MUX_A8_SHIFT
+ | mux->csx0 << SEMC_IOCR_MUX_CSX0_SHIFT
+ | mux->csx1 << SEMC_IOCR_MUX_CSX1_SHIFT
+ | mux->csx2 << SEMC_IOCR_MUX_CSX2_SHIFT
+ | mux->csx3 << SEMC_IOCR_MUX_CSX3_SHIFT
+ | mux->rdy << SEMC_IOCR_MUX_RDY_SHIFT,
+ ®s->iocr);
+
+ writel(ctrl->memory_width << SEMC_SDRAMCR0_PS_SHIFT
+ | ctrl->burst_len << SEMC_SDRAMCR0_BL_SHIFT
+ | ctrl->no_columns << SEMC_SDRAMCR0_COL_SHIFT
+ | ctrl->cas_latency << SEMC_SDRAMCR0_CL_SHIFT,
+ ®s->sdramcr0);
+
+ writel(time->trp << SEMC_SDRAMCR1_PRE2ACT_SHIFT
+ | time->trcd << SEMC_SDRAMCR1_ACT2RW_SHIFT
+ | time->trfc << SEMC_SDRAMCR1_RFRC_SHIFT
+ | time->twr << SEMC_SDRAMCR1_WRC_SHIFT,
+ ®s->sdramcr1);
+
+ /*
+ * SDRAMCR1:
+ * PRE2ACT => tRP(0x02)
+ * ACT2RW => tRCD(0x02)
+ * RFRC => tRFC(0x09)
+ * WRC => tWR(0x01)
+ * TODO: CKEOFF => CKE Off minimum time(0x05)
+ * TODO: ACT2PRE => ACT to Precharge minimum time(0x06)
+ */
+ writel(0x00010920, ®s->sdramcr2);
+ /*
+ * SDRAMCR2:
+ * SRRC => Self Refresh Recovery Time(0x20)
+ * REF2REF => tRFC(0x09)
+ * ACT2ACT => tRRD(0x01)
+ * ITO => SDRAM idle timeout(0x00)
+ */
+ writel(0x50210A09, ®s->sdramcr3);
+ /*
+ * SDRAMCR3:
+ * REN => Refresh Enable(0x01)
+ * REBL => Refresh Burst Length(0x04)
+ * PRESCALE => Prescaler timer pediod(0x0A)
+ * RT => Refresh timer period(0x21)
+ * UT => Refresh urgent threshold(0x50)
+ */
+
+ mdelay(250);
+ imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IPREA,
+ 0x0000);
+ imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IAF,
+ 0x0000);
+ imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IAF,
+ 0x0000);
+ imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IMS,
+ ctrl->burst_len | (ctrl->cas_latency << 4));
+ mdelay(250);
+
+ return 0;
+}
+
+static int imxrt_semc_ofdata_to_platdata(struct udevice *dev)
+{
+ struct imxrt_sdram_params *params = dev_get_platdata(dev);
+ ofnode bank_node;
+ u8 bank = 0;
+
+ params->sdram_mux =
+ (struct imxrt_sdram_mux *)
+ dev_read_u8_array_ptr(dev,
+ "fsl,sdram-mux",
+ sizeof(struct imxrt_sdram_mux));
+ if (!params->sdram_mux) {
+ pr_err("fsl,sdram-mux not found");
+ return -EINVAL;
+ }
+
+ params->sdram_control =
+ (struct imxrt_sdram_control *)
+ dev_read_u8_array_ptr(dev,
+ "fsl,sdram-control",
+ sizeof(struct imxrt_sdram_control));
+ if (!params->sdram_control) {
+ pr_err("fsl,sdram-control not found");
+ return -EINVAL;
+ }
+
+ params->sdram_timing =
+ (struct imxrt_sdram_timing *)
+ dev_read_u8_array_ptr(dev,
+ "fsl,sdram-timing",
+ sizeof(struct imxrt_sdram_timing));
+ if (!params->sdram_timing) {
+ pr_err("fsl,sdram-timing not found");
+ return -EINVAL;
+ }
+
+ dev_for_each_subnode(bank_node, dev) {
+ struct bank_params *bank_params;
+ char *bank_name;
+ int ret;
+
+ /* extract the bank index from DT */
+ bank_name = (char *)ofnode_get_name(bank_node);
+ strsep(&bank_name, "@");
+ if (!bank_name) {
+ pr_err("missing sdram bank index");
+ return -EINVAL;
+ }
+
+ bank_params = ¶ms->bank_params[bank];
+ strict_strtoul(bank_name, 10,
+ (unsigned long int *)&bank_params->target_bank);
+ if (bank_params->target_bank >= MAX_SDRAM_BANK) {
+ pr_err("Found bank %d , but only bank 0,1,2,3 are supported",
+ bank_params->target_bank);
+ return -EINVAL;
+ }
+
+ ret = ofnode_read_u32(bank_node,
+ "fsl,memory-size",
+ &bank_params->memory_size);
+ if (ret < 0) {
+ pr_err("fsl,memory-size not found");
+ return -EINVAL;
+ }
+
+ ret = ofnode_read_u32(bank_node,
+ "fsl,base-address",
+ &bank_params->base_address);
+ if (ret < 0) {
+ pr_err("fsl,base-address not found");
+ return -EINVAL;
+ }
+
+ debug("Found bank %s %u\n", bank_name,
+ bank_params->target_bank);
+ bank++;
+ }
+
+ params->no_sdram_banks = bank;
+ debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
+
+ return 0;
+}
+
+static int imxrt_semc_probe(struct udevice *dev)
+{
+ struct imxrt_sdram_params *params = dev_get_platdata(dev);
+ int ret;
+ fdt_addr_t addr;
+
+ addr = dev_read_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ params->base = (struct imxrt_semc_regs *)addr;
+
+#ifdef CONFIG_CLK
+ struct clk clk;
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_enable(&clk);
+
+ if (ret) {
+ dev_err(dev, "failed to enable clock\n");
+ return ret;
+ }
+#endif
+ ret = imxrt_sdram_init(dev);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int imxrt_semc_get_info(struct udevice *dev, struct ram_info *info)
+{
+ return 0;
+}
+
+static struct ram_ops imxrt_semc_ops = {
+ .get_info = imxrt_semc_get_info,
+};
+
+static const struct udevice_id imxrt_semc_ids[] = {
+ { .compatible = "fsl,imxrt-semc", .data = 0 },
+ { }
+};
+
+U_BOOT_DRIVER(imxrt_semc) = {
+ .name = "imxrt_semc",
+ .id = UCLASS_RAM,
+ .of_match = imxrt_semc_ids,
+ .ops = &imxrt_semc_ops,
+ .ofdata_to_platdata = imxrt_semc_ofdata_to_platdata,
+ .probe = imxrt_semc_probe,
+ .platdata_auto_alloc_size = sizeof(struct imxrt_sdram_params),
+};
diff --git a/include/dt-bindings/memory/imxrt-sdram.h b/include/dt-bindings/memory/imxrt-sdram.h
new file mode 100644
index 0000000000..dff6d4401e
--- /dev/null
+++ b/include/dt-bindings/memory/imxrt-sdram.h
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef DT_BINDINGS_IMXRT_SDRAM_H
+#define DT_BINDINGS_IMXRT_SDRAM_H
+
+#define MEM_SIZE_4K 0x00
+#define MEM_SIZE_8K 0x01
+#define MEM_SIZE_16K 0x02
+#define MEM_SIZE_32K 0x03
+#define MEM_SIZE_64K 0x04
+#define MEM_SIZE_128K 0x05
+#define MEM_SIZE_256K 0x06
+#define MEM_SIZE_512K 0x07
+#define MEM_SIZE_1M 0x08
+#define MEM_SIZE_2M 0x09
+#define MEM_SIZE_4M 0x0A
+#define MEM_SIZE_8M 0x0B
+#define MEM_SIZE_16M 0x0C
+#define MEM_SIZE_32M 0x0D
+#define MEM_SIZE_64M 0x0E
+#define MEM_SIZE_128M 0x0F
+#define MEM_SIZE_256M 0x10
+#define MEM_SIZE_512M 0x11
+#define MEM_SIZE_1G 0x12
+#define MEM_SIZE_2G 0x13
+#define MEM_SIZE_4G 0x14
+
+#define MUX_A8_SDRAM_A8 0x0
+#define MUX_A8_NAND_CE 0x1
+#define MUX_A8_NOR_CE 0x2
+#define MUX_A8_PSRAM_CE 0x3
+#define MUX_A8_DBI_CSX 0x4
+
+#define MUX_CSX0_NOR_PSRAM_A24 0x0
+#define MUX_CSX0_SDRAM_CS1 0x1
+#define MUX_CSX0_SDRAM_CS2 0x2
+#define MUX_CSX0_SDRAM_CS3 0x3
+#define MUX_CSX0_NAND_CE 0x4
+#define MUX_CSX0_NOR_CE 0x5
+#define MUX_CSX0_PSRAM_CE 0x6
+#define MUX_CSX0_DBI_CSX 0x7
+
+#define MUX_CSX1_NOR_PSRAM_A25 0x0
+#define MUX_CSX1_SDRAM_CS1 0x1
+#define MUX_CSX1_SDRAM_CS2 0x2
+#define MUX_CSX1_SDRAM_CS3 0x3
+#define MUX_CSX1_NAND_CE 0x4
+#define MUX_CSX1_NOR_CE 0x5
+#define MUX_CSX1_PSRAM_CE 0x6
+#define MUX_CSX1_DBI_CSX 0x7
+
+#define MUX_CSX2_NOR_PSRAM_A26 0x0
+#define MUX_CSX2_SDRAM_CS1 0x1
+#define MUX_CSX2_SDRAM_CS2 0x2
+#define MUX_CSX2_SDRAM_CS3 0x3
+#define MUX_CSX2_NAND_CE 0x4
+#define MUX_CSX2_NOR_CE 0x5
+#define MUX_CSX2_PSRAM_CE 0x6
+#define MUX_CSX2_DBI_CSX 0x7
+
+#define MUX_CSX3_NOR_PSRAM_A27 0x0
+#define MUX_CSX3_SDRAM_CS1 0x1
+#define MUX_CSX3_SDRAM_CS2 0x2
+#define MUX_CSX3_SDRAM_CS3 0x3
+#define MUX_CSX3_NAND_CE 0x4
+#define MUX_CSX3_NOR_CE 0x5
+#define MUX_CSX3_PSRAM_CE 0x6
+#define MUX_CSX3_DBI_CSX 0x7
+
+#define MUX_RDY_NAND_RDY_WAIT 0x0
+#define MUX_RDY_SDRAM_CS1 0x1
+#define MUX_RDY_SDRAM_CS2 0x2
+#define MUX_RDY_SDRAM_CS3 0x3
+#define MUX_RDY_NOR_CE 0x4
+#define MUX_RDY_PSRAM_CE 0x5
+#define MUX_RDY_DBI_CSX 0x6
+#define MUX_RDY_NOR_PSRAM_A27 0x7
+
+#define MEM_WIDTH_8BITS 0x0
+#define MEM_WIDTH_16BITS 0x1
+
+#define BL_1 0x0
+#define BL_2 0x1
+#define BL_4 0x2
+#define BL_8 0x3
+
+#define COL_12BITS 0x0
+#define COL_11BITS 0x1
+#define COL_10BITS 0x2
+#define COL_9BITS 0x3
+
+#define CL_1 0x0
+#define CL_2 0x2
+#define CL_3 0x3
+
+#define TRP_1 0x0
+#define TRP_2 0x1
+#define TRP_3 0x2
+#define TRP_4 0x3
+#define TRP_5 0x4
+#define TRP_6 0x5
+#define TRP_7 0x6
+#define TRP_8 0x7
+#define TRP_9 0x8
+#define TRP_10 0x9
+#define TRP_11 0xA
+#define TRP_12 0xB
+#define TRP_13 0xC
+#define TRP_14 0xD
+#define TRP_15 0xE
+#define TRP_16 0xF
+
+#define TRCD_1 0x0
+#define TRCD_2 0x1
+#define TRCD_3 0x2
+#define TRCD_4 0x3
+#define TRCD_5 0x4
+#define TRCD_6 0x5
+#define TRCD_7 0x6
+#define TRCD_8 0x7
+#define TRCD_9 0x8
+#define TRCD_10 0x9
+#define TRCD_11 0xA
+#define TRCD_12 0xB
+#define TRCD_13 0xC
+#define TRCD_14 0xD
+#define TRCD_15 0xE
+#define TRCD_16 0xF
+
+#define TRFC_1 0x0
+#define TRFC_2 0x1
+#define TRFC_3 0x2
+#define TRFC_4 0x3
+#define TRFC_5 0x4
+#define TRFC_6 0x5
+#define TRFC_7 0x6
+#define TRFC_8 0x7
+#define TRFC_9 0x8
+#define TRFC_10 0x9
+#define TRFC_11 0xA
+#define TRFC_12 0xB
+#define TRFC_13 0xC
+#define TRFC_14 0xD
+#define TRFC_15 0xE
+#define TRFC_16 0xF
+
+#define TWR_1 0x0
+#define TWR_2 0x1
+#define TWR_3 0x2
+#define TWR_4 0x3
+#define TWR_5 0x4
+#define TWR_6 0x5
+#define TWR_7 0x6
+#define TWR_8 0x7
+#define TWR_9 0x8
+#define TWR_10 0x9
+#define TWR_11 0xA
+#define TWR_12 0xB
+#define TWR_13 0xC
+#define TWR_14 0xD
+#define TWR_15 0xE
+#define TWR_16 0xF
+
+#endif
--
2.20.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [U-Boot] [RFC PATCH 5/5] Add support for the NXP IMXRT1050-EVK board
2019-10-30 21:09 [U-Boot] [RFC PATCH 0/5] WIP Add support for i.MXRT family Giulio Benetti
` (3 preceding siblings ...)
2019-10-30 21:09 ` [U-Boot] [RFC PATCH 4/5] ram: add SDRAM driver for i.MXRT SoCs Giulio Benetti
@ 2019-10-30 21:09 ` Giulio Benetti
2019-11-01 12:40 ` Fabio Estevam
2019-11-01 12:41 ` [U-Boot] [RFC PATCH 0/5] WIP Add support for i.MXRT family Fabio Estevam
5 siblings, 1 reply; 13+ messages in thread
From: Giulio Benetti @ 2019-10-30 21:09 UTC (permalink / raw)
To: u-boot
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/imxrt1050-evk.dts | 124 ++++++++
arch/arm/dts/imxrt1050.dtsi | 73 +++++
arch/arm/mach-imx/imxrt/Kconfig | 11 +
board/freescale/imxrt1050-evk/Kconfig | 19 ++
board/freescale/imxrt1050-evk/MAINTAINERS | 6 +
board/freescale/imxrt1050-evk/Makefile | 6 +
board/freescale/imxrt1050-evk/imxrt1050-evk.c | 94 ++++++
configs/imxrt1050-evk_defconfig | 52 ++++
include/configs/imxrt1050-evk.h | 68 +++++
include/dt-bindings/clock/imxrt-clock.h | 272 ++++++++++++++++++
11 files changed, 727 insertions(+)
create mode 100644 arch/arm/dts/imxrt1050-evk.dts
create mode 100644 arch/arm/dts/imxrt1050.dtsi
create mode 100644 board/freescale/imxrt1050-evk/Kconfig
create mode 100644 board/freescale/imxrt1050-evk/MAINTAINERS
create mode 100644 board/freescale/imxrt1050-evk/Makefile
create mode 100644 board/freescale/imxrt1050-evk/imxrt1050-evk.c
create mode 100644 configs/imxrt1050-evk_defconfig
create mode 100644 include/configs/imxrt1050-evk.h
create mode 100644 include/dt-bindings/clock/imxrt-clock.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 62da168ef8..5ac490fa5e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -631,6 +631,8 @@ dtb-$(CONFIG_ARCH_IMX8) += \
dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb
+dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb
+
dtb-$(CONFIG_RCAR_GEN2) += \
r8a7790-lager-u-boot.dtb \
r8a7790-stout-u-boot.dtb \
diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts
new file mode 100644
index 0000000000..8b5ec7fe9f
--- /dev/null
+++ b/arch/arm/dts/imxrt1050-evk.dts
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+/dts-v1/;
+#include "imxrt1050.dtsi"
+#include <dt-bindings/pinctrl/pins-imxrt1050.h>
+
+/ {
+ model = "NXP IMXRT1050-evk board";
+ compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
+
+ chosen {
+ u-boot,dm-spl;
+ bootargs = "root=/dev/ram";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0x80000000 0x2000000>;
+ };
+
+ aliases {
+ serial0 = &lpuart1;
+ };
+};
+
+&lpuart1 { /* console */
+ u-boot,dm-spl;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart1>;
+ status = "okay";
+};
+
+&semc {
+ /*
+ * Memory configuration from sdram datasheet IS42S32800G-6BLI
+ */
+ fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
+ MUX_CSX0_SDRAM_CS1
+ 0
+ 0
+ 0
+ 0>;
+ fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
+ BL_8
+ COL_9BITS
+ CL_3>;
+ fsl,sdram-timing = /bits/ 8 <TRP_3
+ TRCD_3
+ TRFC_10
+ TWR_3>;
+
+ bank1: bank at 0 {
+ u-boot,dm-spl;
+ fsl,base-address = <0x80000000>;
+ fsl,memory-size = <MEM_SIZE_32M>;
+ };
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart1>;
+
+ imxrt1050-evk {
+ u-boot,dm-spl;
+ pinctrl_lpuart1: lpuart1grp {
+ u-boot,dm-spl;
+ fsl,pins = <
+ MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0xf1
+ MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0xf1
+ >;
+ };
+
+ pinctrl_semc: semcgrp {
+ u-boot,dm-spl;
+ fsl,pins = <
+ MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0xf1 /* SEMC_D0 */
+ MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0xf1 /* SEMC_D1 */
+ MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02 0xf1 /* SEMC_D2 */
+ MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03 0xf1 /* SEMC_D3 */
+ MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04 0xf1 /* SEMC_D4 */
+ MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05 0xf1 /* SEMC_D5 */
+ MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06 0xf1 /* SEMC_D6 */
+ MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07 0xf1 /* SEMC_D7 */
+ MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00 0xf1 /* SEMC_DM0 */
+ MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0xf1 /* SEMC_A0 */
+ MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01 0xf1 /* SEMC_A1 */
+ MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02 0xf1 /* SEMC_A2 */
+ MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03 0xf1 /* SEMC_A3 */
+ MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04 0xf1 /* SEMC_A4 */
+ MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05 0xf1 /* SEMC_A5 */
+ MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06 0xf1 /* SEMC_A6 */
+ MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07 0xf1 /* SEMC_A7 */
+ MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08 0xf1 /* SEMC_A8 */
+ MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09 0xf1 /* SEMC_A9 */
+ MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11 0xf1 /* SEMC_A11 */
+ MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12 0xf1 /* SEMC_A12 */
+ MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0 0xf1 /* SEMC_BA0 */
+ MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1 0xf1 /* SEMC_BA1 */
+ MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10 0xf1 /* SEMC_A10 */
+ MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS 0xf1 /* SEMC_CAS */
+ MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS 0xf1 /* SEMC_RAS */
+ MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK 0xf1 /* SEMC_CLK */
+ MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE 0xf1 /* SEMC_CKE */
+ MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE 0xf1 /* SEMC_WE */
+ MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0 0xf1 /* SEMC_CS0 */
+ MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08 0xf1 /* SEMC_D8 */
+ MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09 0xf1 /* SEMC_D9 */
+ MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10 0xf1 /* SEMC_D10 */
+ MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11 0xf1 /* SEMC_D11 */
+ MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12 0xf1 /* SEMC_D12 */
+ MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13 0xf1 /* SEMC_D13 */
+ MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14 0xf1 /* SEMC_D14 */
+ MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15 0xf1 /* SEMC_D15 */
+ MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01 0xf1 /* SEMC_DM1 */
+ MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS (IMX_PAD_SION | 0xf1) /* SEMC_DQS */
+ >;
+ };
+ };
+};
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
new file mode 100644
index 0000000000..a6416477f5
--- /dev/null
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include "skeleton.dtsi"
+#include "armv7-m.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/imxrt-clock.h>
+#include <dt-bindings/memory/imxrt-sdram.h>
+
+/ {
+ clocks {
+ ckil {
+ compatible = "fsl,imx-ckil", "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ ckih1 {
+ compatible = "fsl,imx-ckih1", "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ osc {
+ compatible = "fsl,imx-osc", "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+ };
+
+ soc {
+ u-boot,dm-spl;
+
+ semc: semc at 402f0000 {
+ u-boot,dm-spl;
+ compatible = "fsl,imxrt-semc";
+ reg = <0x402f0000 0x4000>;
+ /*clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;*/
+ pinctrl-0 = <&pinctrl_semc>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ lpuart1: serial at 40184000 {
+ compatible = "fsl,imxrt-lpuart";
+ reg = <0x40184000 0x4000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMXRT_CLK_UART_SERIAL>,
+ <&clks IMXRT_CLK_UART_IPG>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clks IMXRT_CLK_UART_SERIAL>;
+ assigned-clock-rates = <80000000>;
+ status = "disabled";
+ };
+
+ iomuxc: iomuxc at 401f8000 {
+ compatible = "fsl,imxrt-iomuxc";
+ reg = <0x401f8000 0x4000>;
+ fsl,mux_mask = <0x7>;
+ };
+
+ clks: ccm at 400fc000 {
+ compatible = "fsl,imxrt-ccm";
+ reg = <0x400fc000 0x4000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ #clock-cells = <1>;
+ };
+ };
+};
diff --git a/arch/arm/mach-imx/imxrt/Kconfig b/arch/arm/mach-imx/imxrt/Kconfig
index 1da002336b..45dd8fcd76 100644
--- a/arch/arm/mach-imx/imxrt/Kconfig
+++ b/arch/arm/mach-imx/imxrt/Kconfig
@@ -3,4 +3,15 @@ if ARCH_IMXRT
config SYS_SOC
default "imxrt"
+choice
+ prompt "IMXRT board select"
+ optional
+
+config TARGET_IMXRT1050_EVK
+ bool "Support imxrt1050 EVK board"
+
+endchoice
+
+source "board/freescale/imxrt1050-evk/Kconfig"
+
endif
diff --git a/board/freescale/imxrt1050-evk/Kconfig b/board/freescale/imxrt1050-evk/Kconfig
new file mode 100644
index 0000000000..0c07c0c5e0
--- /dev/null
+++ b/board/freescale/imxrt1050-evk/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_IMXRT1050_EVK
+
+config SYS_BOARD
+ string
+ default "imxrt1050-evk"
+
+config SYS_VENDOR
+ string
+ default "freescale"
+
+config SYS_SOC
+ string
+ default "imxrt"
+
+config SYS_CONFIG_NAME
+ string
+ default "imxrt1050-evk"
+
+endif
diff --git a/board/freescale/imxrt1050-evk/MAINTAINERS b/board/freescale/imxrt1050-evk/MAINTAINERS
new file mode 100644
index 0000000000..a872855452
--- /dev/null
+++ b/board/freescale/imxrt1050-evk/MAINTAINERS
@@ -0,0 +1,6 @@
+IMXRT1050 EVALUATION KIT
+M: Giulio Benetti <giulio.benetti@benettiengineering.com>
+S: Maintained
+F: board/freescale/imxrt1050-evk
+F: include/configs/imxrt1050-evk.h
+F: configs/imxrt1050-evk_defconfig
diff --git a/board/freescale/imxrt1050-evk/Makefile b/board/freescale/imxrt1050-evk/Makefile
new file mode 100644
index 0000000000..0e984d1d7a
--- /dev/null
+++ b/board/freescale/imxrt1050-evk/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019
+# Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+
+obj-y := imxrt1050-evk.o
diff --git a/board/freescale/imxrt1050-evk/imxrt1050-evk.c b/board/freescale/imxrt1050-evk/imxrt1050-evk.c
new file mode 100644
index 0000000000..94fddbbc2f
--- /dev/null
+++ b/board/freescale/imxrt1050-evk/imxrt1050-evk.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ram.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/armv7m.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+#ifndef CONFIG_SUPPORT_SPL
+ int rv;
+ struct udevice *dev;
+
+ rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (rv) {
+ debug("DRAM init failed: %d\n", rv);
+ return rv;
+ }
+
+#endif
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ debug("SPL: booting kernel\n");
+ /* break into full u-boot on 'c' */
+ return serial_tstc() && serial_getc() == 'c';
+}
+#endif
+
+int spl_dram_init(void)
+{
+ struct udevice *dev;
+ int rv;
+
+ rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (rv)
+ debug("DRAM init failed: %d\n", rv);
+ return rv;
+}
+
+void spl_board_init(void)
+{
+ spl_dram_init();
+ preloader_console_init();
+ arch_cpu_init(); /* to configure mpu for sdram rw permissions */
+}
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_XIP;
+}
+
+u32 get_lpuart_clk(void)
+{
+ /* On startup lpuart is clocked by bypassed PLL3(OSC) that is
+ * 24Mhz, and its clock source is divided by 6 as referenced in RM
+ */
+ return 4000000;
+}
+#endif
+
+u32 get_board_rev(void)
+{
+ return 0;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+
+ return 0;
+}
diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig
new file mode 100644
index 0000000000..355f0f6250
--- /dev/null
+++ b/configs/imxrt1050-evk_defconfig
@@ -0,0 +1,52 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMXRT=y
+CONFIG_SYS_TEXT_BASE=0x80000000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_IMXRT1050_EVK=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x20200000
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_CONSOLE_MUX=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_CMD_BOOTEFI is not set
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_NVEDIT_EFI is not set
+# CONFIG_CMD_MII is not set
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imxrt1050-evk"
+CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent interrupts"
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+# CONFIG_OF_TRANSLATE is not set
+# CONFIG_INPUT is not set
+CONFIG_DM_MMC=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMXRT=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_IMXRT_SDRAM=y
+CONFIG_FSL_LPUART=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_SHA1=y
+CONFIG_SHA256=y
+CONFIG_HEXDUMP=y
+# CONFIG_GENERATE_SMBIOS_TABLE is not set
diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h
new file mode 100644
index 0000000000..4627a7b06e
--- /dev/null
+++ b/include/configs/imxrt1050-evk.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_INIT_SP_ADDR 0x20280000
+
+#ifdef CONFIG_SUPPORT_SPL
+#define CONFIG_SYS_LOAD_ADDR 0x20200000
+#else
+#define CONFIG_SYS_LOAD_ADDR 0x80000000
+#define CONFIG_LOADADDR 0x80000000
+#endif
+
+/*
+ * Configuration of the external SDRAM memory
+ */
+#define CONFIG_ENV_SIZE (8 << 10)
+
+#define CONFIG_SYS_HZ_CLOCK 24000000 /* Timer is clocked at 24MHz */
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_SYS_CBSIZE 1024
+
+#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0)
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_BOARD_LATE_INIT
+
+/* For SPL */
+#ifdef CONFIG_SUPPORT_SPL
+#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_SPL_LEN 0x00008000
+#define CONFIG_SYS_UBOOT_START 0x080083FD
+#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \
+ CONFIG_SYS_SPL_LEN)
+
+/* DT blob (fdt) address */
+#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \
+ 0x1C0000)
+#endif
+/* For SPL ends */
+
+/* For splashcreen */
+#ifdef CONFIG_DM_VIDEO
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_BMP_16BPP
+#define CONFIG_BMP_24BPP
+#define CONFIG_BMP_32BPP
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/dt-bindings/clock/imxrt-clock.h b/include/dt-bindings/clock/imxrt-clock.h
new file mode 100644
index 0000000000..2eb9eb8a67
--- /dev/null
+++ b/include/dt-bindings/clock/imxrt-clock.h
@@ -0,0 +1,272 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright(C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMXRT_H
+#define __DT_BINDINGS_CLOCK_IMXRT_H
+
+#define IMXRT_CLK_DUMMY 0
+#define IMXRT_CLK_CKIL 1
+#define IMXRT_CLK_CKIH 2
+#define IMXRT_CLK_OSC 3
+#define IMXRT_CLK_PLL2_PFD0_352M 4
+#define IMXRT_CLK_PLL2_PFD1_594M 5
+#define IMXRT_CLK_PLL2_PFD2_396M 6
+#define IMXRT_CLK_PLL3_PFD0_720M 7
+#define IMXRT_CLK_PLL3_PFD1_540M 8
+#define IMXRT_CLK_PLL3_PFD2_508M 9
+#define IMXRT_CLK_PLL3_PFD3_454M 10
+#define IMXRT_CLK_PLL2_198M 11
+#define IMXRT_CLK_PLL3_120M 12
+#define IMXRT_CLK_PLL3_80M 13
+#define IMXRT_CLK_PLL3_60M 14
+#define IMXRT_CLK_TWD 15
+#define IMXRT_CLK_STEP 16
+#define IMXRT_CLK_PLL1_SW 17
+#define IMXRT_CLK_PERIPH_PRE 18
+#define IMXRT_CLK_PERIPH2_PRE 19
+#define IMXRT_CLK_PERIPH_CLK2_SEL 20
+#define IMXRT_CLK_PERIPH2_CLK2_SEL 21
+#define IMXRT_CLK_AXI_SEL 22
+#define IMXRT_CLK_ESAI_SEL 23
+#define IMXRT_CLK_ASRC_SEL 24
+#define IMXRT_CLK_SPDIF_SEL 25
+#define IMXRT_CLK_GPU2D_AXI 26
+#define IMXRT_CLK_GPU3D_AXI 27
+#define IMXRT_CLK_GPU2D_CORE_SEL 28
+#define IMXRT_CLK_GPU3D_CORE_SEL 29
+#define IMXRT_CLK_GPU3D_SHADER_SEL 30
+#define IMXRT_CLK_IPU1_SEL 31
+#define IMXRT_CLK_IPU2_SEL 32
+#define IMXRT_CLK_LDB_DI0_SEL 33
+#define IMXRT_CLK_LDB_DI1_SEL 34
+#define IMXRT_CLK_IPU1_DI0_PRE_SEL 35
+#define IMXRT_CLK_IPU1_DI1_PRE_SEL 36
+#define IMXRT_CLK_IPU2_DI0_PRE_SEL 37
+#define IMXRT_CLK_IPU2_DI1_PRE_SEL 38
+#define IMXRT_CLK_IPU1_DI0_SEL 39
+#define IMXRT_CLK_IPU1_DI1_SEL 40
+#define IMXRT_CLK_IPU2_DI0_SEL 41
+#define IMXRT_CLK_IPU2_DI1_SEL 42
+#define IMXRT_CLK_HSI_TX_SEL 43
+#define IMXRT_CLK_PCIE_AXI_SEL 44
+#define IMXRT_CLK_SSI1_SEL 45
+#define IMXRT_CLK_SSI2_SEL 46
+#define IMXRT_CLK_SSI3_SEL 47
+#define IMXRT_CLK_USDHC1_SEL 48
+#define IMXRT_CLK_USDHC2_SEL 49
+#define IMXRT_CLK_USDHC3_SEL 50
+#define IMXRT_CLK_USDHC4_SEL 51
+#define IMXRT_CLK_ENFC_SEL 52
+#define IMXRT_CLK_EIM_SEL 53
+#define IMXRT_CLK_EIM_SLOW_SEL 54
+#define IMXRT_CLK_VDO_AXI_SEL 55
+#define IMXRT_CLK_VPU_AXI_SEL 56
+#define IMXRT_CLK_CKO1_SEL 57
+#define IMXRT_CLK_PERIPH 58
+#define IMXRT_CLK_PERIPH2 59
+#define IMXRT_CLK_PERIPH_CLK2 60
+#define IMXRT_CLK_PERIPH2_CLK2 61
+#define IMXRT_CLK_IPG 62
+#define IMXRT_CLK_IPG_PER 63
+#define IMXRT_CLK_ESAI_PRED 64
+#define IMXRT_CLK_ESAI_PODF 65
+#define IMXRT_CLK_ASRC_PRED 66
+#define IMXRT_CLK_ASRC_PODF 67
+#define IMXRT_CLK_SPDIF_PRED 68
+#define IMXRT_CLK_SPDIF_PODF 69
+#define IMXRT_CLK_CAN_ROOT 70
+#define IMXRT_CLK_ECSPI_ROOT 71
+#define IMXRT_CLK_GPU2D_CORE_PODF 72
+#define IMXRT_CLK_GPU3D_CORE_PODF 73
+#define IMXRT_CLK_GPU3D_SHADER 74
+#define IMXRT_CLK_IPU1_PODF 75
+#define IMXRT_CLK_IPU2_PODF 76
+#define IMXRT_CLK_LDB_DI0_PODF 77
+#define IMXRT_CLK_LDB_DI1_PODF 78
+#define IMXRT_CLK_IPU1_DI0_PRE 79
+#define IMXRT_CLK_IPU1_DI1_PRE 80
+#define IMXRT_CLK_IPU2_DI0_PRE 81
+#define IMXRT_CLK_IPU2_DI1_PRE 82
+#define IMXRT_CLK_HSI_TX_PODF 83
+#define IMXRT_CLK_SSI1_PRED 84
+#define IMXRT_CLK_SSI1_PODF 85
+#define IMXRT_CLK_SSI2_PRED 86
+#define IMXRT_CLK_SSI2_PODF 87
+#define IMXRT_CLK_SSI3_PRED 88
+#define IMXRT_CLK_SSI3_PODF 89
+#define IMXRT_CLK_UART_SERIAL_PODF 90
+#define IMXRT_CLK_USDHC1_PODF 91
+#define IMXRT_CLK_USDHC2_PODF 92
+#define IMXRT_CLK_USDHC3_PODF 93
+#define IMXRT_CLK_USDHC4_PODF 94
+#define IMXRT_CLK_ENFC_PRED 95
+#define IMXRT_CLK_ENFC_PODF 96
+#define IMXRT_CLK_EIM_PODF 97
+#define IMXRT_CLK_EIM_SLOW_PODF 98
+#define IMXRT_CLK_VPU_AXI_PODF 99
+#define IMXRT_CLK_CKO1_PODF 100
+#define IMXRT_CLK_AXI 101
+#define IMXRT_CLK_MMDC_CH0_AXI_PODF 102
+#define IMXRT_CLK_MMDC_CH1_AXI_PODF 103
+#define IMXRT_CLK_ARM 104
+#define IMXRT_CLK_AHB 105
+#define IMXRT_CLK_APBH_DMA 106
+#define IMXRT_CLK_ASRC 107
+#define IMXRT_CLK_CAN1_IPG 108
+#define IMXRT_CLK_CAN1_SERIAL 109
+#define IMXRT_CLK_CAN2_IPG 110
+#define IMXRT_CLK_CAN2_SERIAL 111
+#define IMXRT_CLK_ECSPI1 112
+#define IMXRT_CLK_ECSPI2 113
+#define IMXRT_CLK_ECSPI3 114
+#define IMXRT_CLK_ECSPI4 115
+#define IMX6Q_CLK_ECSPI5 116
+#define IMX6DL_CLK_I2C4 116
+#define IMXRT_CLK_ENET 117
+#define IMXRT_CLK_ESAI_EXTAL 118
+#define IMXRT_CLK_GPT_IPG 119
+#define IMXRT_CLK_GPT_IPG_PER 120
+#define IMXRT_CLK_GPU2D_CORE 121
+#define IMXRT_CLK_GPU3D_CORE 122
+#define IMXRT_CLK_HDMI_IAHB 123
+#define IMXRT_CLK_HDMI_ISFR 124
+#define IMXRT_CLK_I2C1 125
+#define IMXRT_CLK_I2C2 126
+#define IMXRT_CLK_I2C3 127
+#define IMXRT_CLK_IIM 128
+#define IMXRT_CLK_ENFC 129
+#define IMXRT_CLK_IPU1 130
+#define IMXRT_CLK_IPU1_DI0 131
+#define IMXRT_CLK_IPU1_DI1 132
+#define IMXRT_CLK_IPU2 133
+#define IMXRT_CLK_IPU2_DI0 134
+#define IMXRT_CLK_LDB_DI0 135
+#define IMXRT_CLK_LDB_DI1 136
+#define IMXRT_CLK_IPU2_DI1 137
+#define IMXRT_CLK_HSI_TX 138
+#define IMXRT_CLK_MLB 139
+#define IMXRT_CLK_MMDC_CH0_AXI 140
+#define IMXRT_CLK_MMDC_CH1_AXI 141
+#define IMXRT_CLK_OCRAM 142
+#define IMXRT_CLK_OPENVG_AXI 143
+#define IMXRT_CLK_PCIE_AXI 144
+#define IMXRT_CLK_PWM1 145
+#define IMXRT_CLK_PWM2 146
+#define IMXRT_CLK_PWM3 147
+#define IMXRT_CLK_PWM4 148
+#define IMXRT_CLK_PER1_BCH 149
+#define IMXRT_CLK_GPMI_BCH_APB 150
+#define IMXRT_CLK_GPMI_BCH 151
+#define IMXRT_CLK_GPMI_IO 152
+#define IMXRT_CLK_GPMI_APB 153
+#define IMXRT_CLK_SATA 154
+#define IMXRT_CLK_SDMA 155
+#define IMXRT_CLK_SPBA 156
+#define IMXRT_CLK_SSI1 157
+#define IMXRT_CLK_SSI2 158
+#define IMXRT_CLK_SSI3 159
+#define IMXRT_CLK_UART_IPG 160
+#define IMXRT_CLK_UART_SERIAL 161
+#define IMXRT_CLK_USBOH3 162
+#define IMXRT_CLK_USDHC1 163
+#define IMXRT_CLK_USDHC2 164
+#define IMXRT_CLK_USDHC3 165
+#define IMXRT_CLK_USDHC4 166
+#define IMXRT_CLK_VDO_AXI 167
+#define IMXRT_CLK_VPU_AXI 168
+#define IMXRT_CLK_CKO1 169
+#define IMXRT_CLK_PLL1_SYS 170
+#define IMXRT_CLK_PLL2_BUS 171
+#define IMXRT_CLK_PLL3_USB_OTG 172
+#define IMXRT_CLK_PLL4_AUDIO 173
+#define IMXRT_CLK_PLL5_VIDEO 174
+#define IMXRT_CLK_PLL8_MLB 175
+#define IMXRT_CLK_PLL7_USB_HOST 176
+#define IMXRT_CLK_PLL6_ENET 177
+#define IMXRT_CLK_SSI1_IPG 178
+#define IMXRT_CLK_SSI2_IPG 179
+#define IMXRT_CLK_SSI3_IPG 180
+#define IMXRT_CLK_ROM 181
+#define IMXRT_CLK_USBPHY1 182
+#define IMXRT_CLK_USBPHY2 183
+#define IMXRT_CLK_LDB_DI0_DIV_3_5 184
+#define IMXRT_CLK_LDB_DI1_DIV_3_5 185
+#define IMXRT_CLK_SATA_REF 186
+#define IMXRT_CLK_SATA_REF_100M 187
+#define IMXRT_CLK_PCIE_REF 188
+#define IMXRT_CLK_PCIE_REF_125M 189
+#define IMXRT_CLK_ENET_REF 190
+#define IMXRT_CLK_USBPHY1_GATE 191
+#define IMXRT_CLK_USBPHY2_GATE 192
+#define IMXRT_CLK_PLL4_POST_DIV 193
+#define IMXRT_CLK_PLL5_POST_DIV 194
+#define IMXRT_CLK_PLL5_VIDEO_DIV 195
+#define IMXRT_CLK_EIM_SLOW 196
+#define IMXRT_CLK_SPDIF 197
+#define IMXRT_CLK_CKO2_SEL 198
+#define IMXRT_CLK_CKO2_PODF 199
+#define IMXRT_CLK_CKO2 200
+#define IMXRT_CLK_CKO 201
+#define IMXRT_CLK_VDOA 202
+#define IMXRT_CLK_PLL4_AUDIO_DIV 203
+#define IMXRT_CLK_LVDS1_SEL 204
+#define IMXRT_CLK_LVDS2_SEL 205
+#define IMXRT_CLK_LVDS1_GATE 206
+#define IMXRT_CLK_LVDS2_GATE 207
+#define IMXRT_CLK_ESAI_IPG 208
+#define IMXRT_CLK_ESAI_MEM 209
+#define IMXRT_CLK_ASRC_IPG 210
+#define IMXRT_CLK_ASRC_MEM 211
+#define IMXRT_CLK_LVDS1_IN 212
+#define IMXRT_CLK_LVDS2_IN 213
+#define IMXRT_CLK_ANACLK1 214
+#define IMXRT_CLK_ANACLK2 215
+#define IMXRT_PLL1_BYPASS_SRC 216
+#define IMXRT_PLL2_BYPASS_SRC 217
+#define IMXRT_PLL3_BYPASS_SRC 218
+#define IMXRT_PLL4_BYPASS_SRC 219
+#define IMXRT_PLL5_BYPASS_SRC 220
+#define IMXRT_PLL6_BYPASS_SRC 221
+#define IMXRT_PLL7_BYPASS_SRC 222
+#define IMXRT_CLK_PLL1 223
+#define IMXRT_CLK_PLL2 224
+#define IMXRT_CLK_PLL3 225
+#define IMXRT_CLK_PLL4 226
+#define IMXRT_CLK_PLL5 227
+#define IMXRT_CLK_PLL6 228
+#define IMXRT_CLK_PLL7 229
+#define IMXRT_PLL1_BYPASS 230
+#define IMXRT_PLL2_BYPASS 231
+#define IMXRT_PLL3_BYPASS 232
+#define IMXRT_PLL4_BYPASS 233
+#define IMXRT_PLL5_BYPASS 234
+#define IMXRT_PLL6_BYPASS 235
+#define IMXRT_PLL7_BYPASS 236
+#define IMXRT_CLK_GPT_3M 237
+#define IMXRT_CLK_VIDEO_27M 238
+#define IMXRT_CLK_MIPI_CORE_CFG 239
+#define IMXRT_CLK_MIPI_IPG 240
+#define IMXRT_CLK_CAAM_MEM 241
+#define IMXRT_CLK_CAAM_ACLK 242
+#define IMXRT_CLK_CAAM_IPG 243
+#define IMXRT_CLK_SPDIF_GCLK 244
+#define IMXRT_CLK_UART_SEL 245
+#define IMXRT_CLK_IPG_PER_SEL 246
+#define IMXRT_CLK_ECSPI_SEL 247
+#define IMXRT_CLK_CAN_SEL 248
+#define IMXRT_CLK_MMDC_CH1_AXI_CG 249
+#define IMXRT_CLK_PRE0 250
+#define IMXRT_CLK_PRE1 251
+#define IMXRT_CLK_PRE2 252
+#define IMXRT_CLK_PRE3 253
+#define IMXRT_CLK_PRG0_AXI 254
+#define IMXRT_CLK_PRG1_AXI 255
+#define IMXRT_CLK_PRG0_APB 256
+#define IMXRT_CLK_PRG1_APB 257
+#define IMXRT_CLK_PRE_AXI 258
+#define IMXRT_CLK_END 259
+
+#endif /* __DT_BINDINGS_CLOCK_IMXRT_H */
--
2.20.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [U-Boot] [RFC PATCH 4/5] ram: add SDRAM driver for i.MXRT SoCs
2019-10-30 21:09 ` [U-Boot] [RFC PATCH 4/5] ram: add SDRAM driver for i.MXRT SoCs Giulio Benetti
@ 2019-10-31 12:11 ` Giulio Benetti
2019-11-04 16:33 ` Fabio Estevam
0 siblings, 1 reply; 13+ messages in thread
From: Giulio Benetti @ 2019-10-31 12:11 UTC (permalink / raw)
To: u-boot
Hi Stefano, Fabio and All,
I have some question below:
On 10/30/19 10:09 PM, Giulio Benetti wrote:
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> ---
> drivers/ram/Kconfig | 8 +
> drivers/ram/Makefile | 2 +
> drivers/ram/imxrt_sdram.c | 406 +++++++++++++++++++++++
> include/dt-bindings/memory/imxrt-sdram.h | 168 ++++++++++
> 4 files changed, 584 insertions(+)
> create mode 100644 drivers/ram/imxrt_sdram.c
> create mode 100644 include/dt-bindings/memory/imxrt-sdram.h
>
> diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
> index 568d8f2c6a..69b0233a48 100644
> --- a/drivers/ram/Kconfig
> +++ b/drivers/ram/Kconfig
> @@ -54,5 +54,13 @@ config K3_AM654_DDRSS
> config add support for the initialization of the external
> SDRAM devices connected to DDR subsystem.
>
> +config IMXRT_SDRAM
> + bool "Enable i.MXRT SDRAM support"
> + depends on RAM
> + help
> + i.MXRT family devices support smart external memory controller(SEMC)
> + to support external memories like sdram, psram & nand.
> + This driver is for the sdram memory interface with the SEMC.
> +
> source "drivers/ram/rockchip/Kconfig"
> source "drivers/ram/stm32mp1/Kconfig"
> diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
> index 976ec66df7..d3813e37e4 100644
> --- a/drivers/ram/Makefile
> +++ b/drivers/ram/Makefile
> @@ -14,3 +14,5 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
>
> obj-$(CONFIG_K3_AM654_DDRSS) += k3-am654-ddrss.o
> obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
> +
> +obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
> diff --git a/drivers/ram/imxrt_sdram.c b/drivers/ram/imxrt_sdram.c
> new file mode 100644
> index 0000000000..7c157f60e2
> --- /dev/null
> +++ b/drivers/ram/imxrt_sdram.c
> @@ -0,0 +1,406 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019
> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> + */
> +
> +#include <common.h>
> +#include <clk.h>
> +#include <dm.h>
> +#include <ram.h>
> +#include <asm/io.h>
> +
> +/* SDRAM Command Code */
> +#define SD_CC_ARD 0x0 /* Master Bus (AXI) command - Read */
> +#define SD_CC_AWR 0x1 /* Master Bus (AXI) command - Write */
> +#define SD_CC_IRD 0x8 /* IP command - Read */
> +#define SD_CC_IWR 0x9 /* IP command - Write */
> +#define SD_CC_IMS 0xA /* IP command - Set Mode Register */
> +#define SD_CC_IACT 0xB /* IP command - ACTIVE */
> +#define SD_CC_IAF 0xC /* IP command - Auto Refresh */
> +#define SD_CC_ISF 0xD /* IP Command - Self Refresh */
> +#define SD_CC_IPRE 0xE /* IP command - Precharge */
> +#define SD_CC_IPREA 0xF /* IP command - Precharge ALL */
> +
> +#define SEMC_MCR_MDIS BIT(1)
> +#define SEMC_MCR_DQSMD BIT(2)
> +
> +struct imxrt_semc_regs {
> + /* 0x0 */
> + u32 mcr;
> + u32 iocr;
> + u32 bmcr0;
> + u32 bmcr1;
> + u32 br[9];
> +
> + /* 0x34 */
> + u32 res1;
> + u32 inten;
> + u32 intr;
> + /* 0x40 */
> + u32 sdramcr0;
> + u32 sdramcr1;
> + u32 sdramcr2;
> + u32 sdramcr3;
> + /* 0x50 */
> + u32 nandcr0;
> + u32 nandcr1;
> + u32 nandcr2;
> + u32 nandcr3;
> + /* 0x60 */
> + u32 norcr0;
> + u32 norcr1;
> + u32 norcr2;
> + u32 norcr3;
> + /* 0x70 */
> + u32 sramcr0;
> + u32 sramcr1;
> + u32 sramcr2;
> + u32 sramcr3;
> + /* 0x80 */
> + u32 dbicr0;
> + u32 dbicr1;
> + u32 res2[2];
> + /* 0x90 */
> + u32 ipcr0;
> + u32 ipcr1;
> + u32 ipcr2;
> + u32 ipcmd;
> + /* 0xA0 */
> + u32 iptxdat;
> + u32 res3[3];
> + /* 0xB0 */
> + u32 iprxdat;
> + u32 res4[3];
> + /* 0xC0 */
> + u32 sts[16];
> +};
> +
> +#define SEMC_IOCR_MUX_A8_SHIFT 0
> +#define SEMC_IOCR_MUX_CSX0_SHIFT 1
> +#define SEMC_IOCR_MUX_CSX1_SHIFT 2
> +#define SEMC_IOCR_MUX_CSX2_SHIFT 3
> +#define SEMC_IOCR_MUX_CSX3_SHIFT 4
> +#define SEMC_IOCR_MUX_RDY_SHIFT 5
> +
> +struct imxrt_sdram_mux {
> + u8 a8;
> + u8 csx0;
> + u8 csx1;
> + u8 csx2;
> + u8 csx3;
> + u8 rdy;
> +};
> +
> +#define SEMC_SDRAMCR0_PS_SHIFT 0
> +#define SEMC_SDRAMCR0_BL_SHIFT 4
> +#define SEMC_SDRAMCR0_COL_SHIFT 8
> +#define SEMC_SDRAMCR0_CL_SHIFT 10
> +
> +struct imxrt_sdram_control {
> + u8 memory_width;
> + u8 burst_len;
> + u8 no_columns;
> + u8 cas_latency;
> +};
> +
> +#define SEMC_SDRAMCR1_PRE2ACT_SHIFT 0
> +#define SEMC_SDRAMCR1_ACT2RW_SHIFT 4
> +#define SEMC_SDRAMCR1_RFRC_SHIFT 8
> +#define SEMC_SDRAMCR1_WRC_SHIFT 12
> +
> +struct imxrt_sdram_timing {
> + u8 trp;
> + u8 trcd;
> + u8 trfc;
> + u8 twr;
> +#if TODO
> + u8 tmrd;
> + u8 txsr;
> + u8 tras;
> + u8 trc;
> +#endif
> +};
> +
> +enum imxrt_semc_bank {
> + SDRAM_BANK1,
> + SDRAM_BANK2,
> + SDRAM_BANK3,
> + SDRAM_BANK4,
> + MAX_SDRAM_BANK,
> +};
> +
> +#define SEMC_BR_VLD_MASK 1
> +#define SEMC_BR_MS_SHIFT 1
> +
> +struct bank_params {
> + enum imxrt_semc_bank target_bank;
> + u32 base_address;
> + u32 memory_size;
> +};
> +
> +struct imxrt_sdram_params {
> + struct imxrt_semc_regs *base;
> +
> + struct imxrt_sdram_mux *sdram_mux;
> + struct imxrt_sdram_control *sdram_control;
> + struct imxrt_sdram_timing *sdram_timing;
> +
> + struct bank_params bank_params[MAX_SDRAM_BANK];
> + u8 no_sdram_banks;
> +};
> +
> +void imxrt_sdram_wait_ipcmd_done(struct imxrt_semc_regs *regs)
> +{
> + do {
> + mdelay(50);
> + /* check for IPCMDDONE or IPCMERR */
> + /* TODO: handle error */
> + } while (!(readl(®s->intr) & 0x3));
> +}
> +
> +u32 imxrt_sdram_ipcmd(struct imxrt_semc_regs *regs, u32 mem_addr, u32 ipcmd,
> + u32 wd)
> +{
> + u32 rd = 0x0;
> +
> + if (ipcmd == SD_CC_IWR || ((ipcmd & 0x0000FFFF) == SD_CC_IMS))
> + writel(wd & 0x0000FFFF, ®s->iptxdat);
> +
> + /* set slave address for every command */
> + writel(mem_addr, ®s->ipcr0);
> +
> + /* execute command */
> + writel(0xA55A0000 | (ipcmd & 0x0000FFFF), ®s->ipcmd);
> +
> + imxrt_sdram_wait_ipcmd_done(regs);
> +
> + if (ipcmd == SD_CC_IRD)
> + rd = readl(®s->iprxdat);
> +
> + return rd;
> +}
> +
> +int imxrt_sdram_init(struct udevice *dev)
> +{
> + struct imxrt_sdram_params *params = dev_get_platdata(dev);
> + struct imxrt_sdram_mux *mux = params->sdram_mux;
> + struct imxrt_sdram_control *ctrl = params->sdram_control;
> + struct imxrt_sdram_timing *time = params->sdram_timing;
> + struct imxrt_semc_regs *regs = params->base;
> + struct bank_params *bank_params = params->bank_params;
> + int i;
> +
> + /* enable the SEMC controller */
> + clrbits_le32(®s->mcr, SEMC_MCR_MDIS);
> + /* set DQS mode from DQS pad */
> + setbits_le32(®s->mcr, SEMC_MCR_DQSMD);
> +
> + for (i = 0; i < params->no_sdram_banks; bank_params++, i++)
> + writel((bank_params->base_address & 0xfffff000)
> + | bank_params->memory_size << SEMC_BR_MS_SHIFT
> + | SEMC_BR_VLD_MASK,
> + ®s->br[bank_params->target_bank]);
> +
> + writel(mux->a8 << SEMC_IOCR_MUX_A8_SHIFT
> + | mux->csx0 << SEMC_IOCR_MUX_CSX0_SHIFT
> + | mux->csx1 << SEMC_IOCR_MUX_CSX1_SHIFT
> + | mux->csx2 << SEMC_IOCR_MUX_CSX2_SHIFT
> + | mux->csx3 << SEMC_IOCR_MUX_CSX3_SHIFT
> + | mux->rdy << SEMC_IOCR_MUX_RDY_SHIFT,
> + ®s->iocr);
> +
> + writel(ctrl->memory_width << SEMC_SDRAMCR0_PS_SHIFT
> + | ctrl->burst_len << SEMC_SDRAMCR0_BL_SHIFT
> + | ctrl->no_columns << SEMC_SDRAMCR0_COL_SHIFT
> + | ctrl->cas_latency << SEMC_SDRAMCR0_CL_SHIFT,
> + ®s->sdramcr0);
> +
> + writel(time->trp << SEMC_SDRAMCR1_PRE2ACT_SHIFT
> + | time->trcd << SEMC_SDRAMCR1_ACT2RW_SHIFT
> + | time->trfc << SEMC_SDRAMCR1_RFRC_SHIFT
> + | time->twr << SEMC_SDRAMCR1_WRC_SHIFT,
> + ®s->sdramcr1);
Here I've tried to use classic sdram timing as parameters but...
> + /*
> + * SDRAMCR1:
> + * PRE2ACT => tRP(0x02)
> + * ACT2RW => tRCD(0x02)
> + * RFRC => tRFC(0x09)
> + * WRC => tWR(0x01)
> + * TODO: CKEOFF => CKE Off minimum time(0x05)
> + * TODO: ACT2PRE => ACT to Precharge minimum time(0x06)
> + */
> + writel(0x00010920, ®s->sdramcr2);
...in this register and the next one there are parameters like CKEOFF
and ACT2PRE impossible to lead to classic tXXX sdram timing parameters.
I've done this way inspired by stm32-sdram, but maybe U should go back
using i.MXRT names(i.e. PRE2ACT instead of tRP) and list all possible
useful registers in DM as I've done for tRP etc.
What do you think?
And...
> + /*
> + * SDRAMCR2:
> + * SRRC => Self Refresh Recovery Time(0x20)
> + * REF2REF => tRFC(0x09)
> + * ACT2ACT => tRRD(0x01)
> + * ITO => SDRAM idle timeout(0x00)
> + */
> + writel(0x50210A09, ®s->sdramcr3);
> + /*
> + * SDRAMCR3:
> + * REN => Refresh Enable(0x01)
> + * REBL => Refresh Burst Length(0x04)
> + * PRESCALE => Prescaler timer pediod(0x0A)
> + * RT => Refresh timer period(0x21)
> + * UT => Refresh urgent threshold(0x50)
> + */ > + mdelay(250);
> + imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IPREA,
> + 0x0000);
> + imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IAF,
> + 0x0000);
> + imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IAF,
> + 0x0000);
> + imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IMS,
> + ctrl->burst_len | (ctrl->cas_latency << 4));
> + mdelay(250);
> +
> + return 0;
> +}
> +
> +static int imxrt_semc_ofdata_to_platdata(struct udevice *dev)
> +{
> + struct imxrt_sdram_params *params = dev_get_platdata(dev);
> + ofnode bank_node;
> + u8 bank = 0;
> +
> + params->sdram_mux =
> + (struct imxrt_sdram_mux *)
> + dev_read_u8_array_ptr(dev,
> + "fsl,sdram-mux",
> + sizeof(struct imxrt_sdram_mux));
> + if (!params->sdram_mux) {
> + pr_err("fsl,sdram-mux not found");
> + return -EINVAL;
> + }
> +
> + params->sdram_control =
> + (struct imxrt_sdram_control *)
> + dev_read_u8_array_ptr(dev,
> + "fsl,sdram-control",
> + sizeof(struct imxrt_sdram_control));
> + if (!params->sdram_control) {
> + pr_err("fsl,sdram-control not found");
> + return -EINVAL;
> + }
> +
> + params->sdram_timing =
> + (struct imxrt_sdram_timing *)
> + dev_read_u8_array_ptr(dev,
> + "fsl,sdram-timing",
> + sizeof(struct imxrt_sdram_timing));
> + if (!params->sdram_timing) {
> + pr_err("fsl,sdram-timing not found");
> + return -EINVAL;
> + }
> +
> + dev_for_each_subnode(bank_node, dev) {
> + struct bank_params *bank_params;
> + char *bank_name;
> + int ret;
> +
> + /* extract the bank index from DT */
> + bank_name = (char *)ofnode_get_name(bank_node);
> + strsep(&bank_name, "@");
> + if (!bank_name) {
> + pr_err("missing sdram bank index");
> + return -EINVAL;
> + }
> +
> + bank_params = ¶ms->bank_params[bank];
> + strict_strtoul(bank_name, 10,
> + (unsigned long int *)&bank_params->target_bank);
> + if (bank_params->target_bank >= MAX_SDRAM_BANK) {
> + pr_err("Found bank %d , but only bank 0,1,2,3 are supported",
> + bank_params->target_bank);
> + return -EINVAL;
> + }
> +
> + ret = ofnode_read_u32(bank_node,
> + "fsl,memory-size",
> + &bank_params->memory_size);
> + if (ret < 0) {
> + pr_err("fsl,memory-size not found");
> + return -EINVAL;
> + }
> +
> + ret = ofnode_read_u32(bank_node,
> + "fsl,base-address",
> + &bank_params->base_address);
> + if (ret < 0) {
> + pr_err("fsl,base-address not found");
> + return -EINVAL;
> + }
> +
> + debug("Found bank %s %u\n", bank_name,
> + bank_params->target_bank);
> + bank++;
> + }
> +
> + params->no_sdram_banks = bank;
> + debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
> +
> + return 0;
> +}
> +
> +static int imxrt_semc_probe(struct udevice *dev)
> +{
> + struct imxrt_sdram_params *params = dev_get_platdata(dev);
> + int ret;
> + fdt_addr_t addr;
> +
> + addr = dev_read_addr(dev);
> + if (addr == FDT_ADDR_T_NONE)
> + return -EINVAL;
> +
> + params->base = (struct imxrt_semc_regs *)addr;
> +
> +#ifdef CONFIG_CLK
> + struct clk clk;
> +
> + ret = clk_get_by_index(dev, 0, &clk);
> + if (ret < 0)
> + return ret;
> +
> + ret = clk_enable(&clk);
> +
> + if (ret) {
> + dev_err(dev, "failed to enable clock\n");
> + return ret;
> + }
> +#endif
> + ret = imxrt_sdram_init(dev);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +
> +static int imxrt_semc_get_info(struct udevice *dev, struct ram_info *info)
> +{
> + return 0;
> +}
> +
> +static struct ram_ops imxrt_semc_ops = {
> + .get_info = imxrt_semc_get_info,
> +};
> +
> +static const struct udevice_id imxrt_semc_ids[] = {
> + { .compatible = "fsl,imxrt-semc", .data = 0 },
> + { }
> +};
> +
> +U_BOOT_DRIVER(imxrt_semc) = {
> + .name = "imxrt_semc",
> + .id = UCLASS_RAM,
> + .of_match = imxrt_semc_ids,
> + .ops = &imxrt_semc_ops,
> + .ofdata_to_platdata = imxrt_semc_ofdata_to_platdata,
> + .probe = imxrt_semc_probe,
> + .platdata_auto_alloc_size = sizeof(struct imxrt_sdram_params),
> +};
> diff --git a/include/dt-bindings/memory/imxrt-sdram.h b/include/dt-bindings/memory/imxrt-sdram.h
> new file mode 100644
> index 0000000000..dff6d4401e
> --- /dev/null
> +++ b/include/dt-bindings/memory/imxrt-sdram.h
> @@ -0,0 +1,168 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019
> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> + */
> +
> +#ifndef DT_BINDINGS_IMXRT_SDRAM_H
> +#define DT_BINDINGS_IMXRT_SDRAM_H
> +
> +#define MEM_SIZE_4K 0x00
> +#define MEM_SIZE_8K 0x01
> +#define MEM_SIZE_16K 0x02
> +#define MEM_SIZE_32K 0x03
> +#define MEM_SIZE_64K 0x04
> +#define MEM_SIZE_128K 0x05
> +#define MEM_SIZE_256K 0x06
> +#define MEM_SIZE_512K 0x07
> +#define MEM_SIZE_1M 0x08
> +#define MEM_SIZE_2M 0x09
> +#define MEM_SIZE_4M 0x0A
> +#define MEM_SIZE_8M 0x0B
> +#define MEM_SIZE_16M 0x0C
> +#define MEM_SIZE_32M 0x0D
> +#define MEM_SIZE_64M 0x0E
> +#define MEM_SIZE_128M 0x0F
> +#define MEM_SIZE_256M 0x10
> +#define MEM_SIZE_512M 0x11
> +#define MEM_SIZE_1G 0x12
> +#define MEM_SIZE_2G 0x13
> +#define MEM_SIZE_4G 0x14
> +
> +#define MUX_A8_SDRAM_A8 0x0
> +#define MUX_A8_NAND_CE 0x1
> +#define MUX_A8_NOR_CE 0x2
> +#define MUX_A8_PSRAM_CE 0x3
> +#define MUX_A8_DBI_CSX 0x4
> +
> +#define MUX_CSX0_NOR_PSRAM_A24 0x0
> +#define MUX_CSX0_SDRAM_CS1 0x1
> +#define MUX_CSX0_SDRAM_CS2 0x2
> +#define MUX_CSX0_SDRAM_CS3 0x3
> +#define MUX_CSX0_NAND_CE 0x4
> +#define MUX_CSX0_NOR_CE 0x5
> +#define MUX_CSX0_PSRAM_CE 0x6
> +#define MUX_CSX0_DBI_CSX 0x7
> +
> +#define MUX_CSX1_NOR_PSRAM_A25 0x0
> +#define MUX_CSX1_SDRAM_CS1 0x1
> +#define MUX_CSX1_SDRAM_CS2 0x2
> +#define MUX_CSX1_SDRAM_CS3 0x3
> +#define MUX_CSX1_NAND_CE 0x4
> +#define MUX_CSX1_NOR_CE 0x5
> +#define MUX_CSX1_PSRAM_CE 0x6
> +#define MUX_CSX1_DBI_CSX 0x7
> +
> +#define MUX_CSX2_NOR_PSRAM_A26 0x0
> +#define MUX_CSX2_SDRAM_CS1 0x1
> +#define MUX_CSX2_SDRAM_CS2 0x2
> +#define MUX_CSX2_SDRAM_CS3 0x3
> +#define MUX_CSX2_NAND_CE 0x4
> +#define MUX_CSX2_NOR_CE 0x5
> +#define MUX_CSX2_PSRAM_CE 0x6
> +#define MUX_CSX2_DBI_CSX 0x7
> +
> +#define MUX_CSX3_NOR_PSRAM_A27 0x0
> +#define MUX_CSX3_SDRAM_CS1 0x1
> +#define MUX_CSX3_SDRAM_CS2 0x2
> +#define MUX_CSX3_SDRAM_CS3 0x3
> +#define MUX_CSX3_NAND_CE 0x4
> +#define MUX_CSX3_NOR_CE 0x5
> +#define MUX_CSX3_PSRAM_CE 0x6
> +#define MUX_CSX3_DBI_CSX 0x7
> +
> +#define MUX_RDY_NAND_RDY_WAIT 0x0
> +#define MUX_RDY_SDRAM_CS1 0x1
> +#define MUX_RDY_SDRAM_CS2 0x2
> +#define MUX_RDY_SDRAM_CS3 0x3
> +#define MUX_RDY_NOR_CE 0x4
> +#define MUX_RDY_PSRAM_CE 0x5
> +#define MUX_RDY_DBI_CSX 0x6
> +#define MUX_RDY_NOR_PSRAM_A27 0x7
> +
> +#define MEM_WIDTH_8BITS 0x0
> +#define MEM_WIDTH_16BITS 0x1
> +
> +#define BL_1 0x0
> +#define BL_2 0x1
> +#define BL_4 0x2
> +#define BL_8 0x3
> +
> +#define COL_12BITS 0x0
> +#define COL_11BITS 0x1
> +#define COL_10BITS 0x2
> +#define COL_9BITS 0x3
> +
> +#define CL_1 0x0
> +#define CL_2 0x2
> +#define CL_3 0x3
> +
> +#define TRP_1 0x0
> +#define TRP_2 0x1
> +#define TRP_3 0x2
> +#define TRP_4 0x3
> +#define TRP_5 0x4
> +#define TRP_6 0x5
> +#define TRP_7 0x6
> +#define TRP_8 0x7
> +#define TRP_9 0x8
> +#define TRP_10 0x9
> +#define TRP_11 0xA
> +#define TRP_12 0xB
> +#define TRP_13 0xC
> +#define TRP_14 0xD
> +#define TRP_15 0xE
> +#define TRP_16 0xF
> +
> +#define TRCD_1 0x0
> +#define TRCD_2 0x1
> +#define TRCD_3 0x2
> +#define TRCD_4 0x3
> +#define TRCD_5 0x4
> +#define TRCD_6 0x5
> +#define TRCD_7 0x6
> +#define TRCD_8 0x7
> +#define TRCD_9 0x8
> +#define TRCD_10 0x9
> +#define TRCD_11 0xA
> +#define TRCD_12 0xB
> +#define TRCD_13 0xC
> +#define TRCD_14 0xD
> +#define TRCD_15 0xE
> +#define TRCD_16 0xF
> +
> +#define TRFC_1 0x0
> +#define TRFC_2 0x1
> +#define TRFC_3 0x2
> +#define TRFC_4 0x3
> +#define TRFC_5 0x4
> +#define TRFC_6 0x5
> +#define TRFC_7 0x6
> +#define TRFC_8 0x7
> +#define TRFC_9 0x8
> +#define TRFC_10 0x9
> +#define TRFC_11 0xA
> +#define TRFC_12 0xB
> +#define TRFC_13 0xC
> +#define TRFC_14 0xD
> +#define TRFC_15 0xE
> +#define TRFC_16 0xF
> +
> +#define TWR_1 0x0
> +#define TWR_2 0x1
> +#define TWR_3 0x2
> +#define TWR_4 0x3
> +#define TWR_5 0x4
> +#define TWR_6 0x5
> +#define TWR_7 0x6
> +#define TWR_8 0x7
> +#define TWR_9 0x8
> +#define TWR_10 0x9
> +#define TWR_11 0xA
> +#define TWR_12 0xB
> +#define TWR_13 0xC
> +#define TWR_14 0xD
> +#define TWR_15 0xE
> +#define TWR_16 0xF
> +
> +#endif
>
...is it ok listing every possible value for DM parameter?
I mean, some of them would be 8-bit, this would mean having 256 cases,
that sound very ugly to me.
Thanks in advance
Kind regards
--
Giulio Benetti
Benetti Engineering sas
^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [RFC PATCH 5/5] Add support for the NXP IMXRT1050-EVK board
2019-10-30 21:09 ` [U-Boot] [RFC PATCH 5/5] Add support for the NXP IMXRT1050-EVK board Giulio Benetti
@ 2019-11-01 12:40 ` Fabio Estevam
2019-11-04 16:28 ` Giulio Benetti
0 siblings, 1 reply; 13+ messages in thread
From: Fabio Estevam @ 2019-11-01 12:40 UTC (permalink / raw)
To: u-boot
Hi Giulio,
On Wed, Oct 30, 2019 at 6:09 PM Giulio Benetti
<giulio.benetti@benettiengineering.com> wrote:
Please add a commit log that briefly describes the board.
>
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> ---
> arch/arm/dts/Makefile | 2 +
> arch/arm/dts/imxrt1050-evk.dts | 124 ++++++++
> arch/arm/dts/imxrt1050.dtsi | 73 +++++
> arch/arm/mach-imx/imxrt/Kconfig | 11 +
> board/freescale/imxrt1050-evk/Kconfig | 19 ++
> board/freescale/imxrt1050-evk/MAINTAINERS | 6 +
> board/freescale/imxrt1050-evk/Makefile | 6 +
Please add a board/freescale/imxrt1050-evk/README that explains how to
build, flash the U-Boot binary and boot.
> board/freescale/imxrt1050-evk/imxrt1050-evk.c | 94 ++++++
> configs/imxrt1050-evk_defconfig | 52 ++++
> include/configs/imxrt1050-evk.h | 68 +++++
> include/dt-bindings/clock/imxrt-clock.h | 272 ++++++++++++++++++
> 11 files changed, 727 insertions(+)
> create mode 100644 arch/arm/dts/imxrt1050-evk.dts
> create mode 100644 arch/arm/dts/imxrt1050.dtsi
> create mode 100644 board/freescale/imxrt1050-evk/Kconfig
> create mode 100644 board/freescale/imxrt1050-evk/MAINTAINERS
> create mode 100644 board/freescale/imxrt1050-evk/Makefile
> create mode 100644 board/freescale/imxrt1050-evk/imxrt1050-evk.c
> create mode 100644 configs/imxrt1050-evk_defconfig
> create mode 100644 include/configs/imxrt1050-evk.h
> create mode 100644 include/dt-bindings/clock/imxrt-clock.h
This imxrt-clock.h header and the arch/arm/dts/imxrt1050.dts is
common imxrt code and not related to the evk board, so better put them
on a separate patch.
^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [RFC PATCH 0/5] WIP Add support for i.MXRT family
2019-10-30 21:09 [U-Boot] [RFC PATCH 0/5] WIP Add support for i.MXRT family Giulio Benetti
` (4 preceding siblings ...)
2019-10-30 21:09 ` [U-Boot] [RFC PATCH 5/5] Add support for the NXP IMXRT1050-EVK board Giulio Benetti
@ 2019-11-01 12:41 ` Fabio Estevam
2019-11-04 16:25 ` Giulio Benetti
5 siblings, 1 reply; 13+ messages in thread
From: Fabio Estevam @ 2019-11-01 12:41 UTC (permalink / raw)
To: u-boot
Hi Giulio,
On Wed, Oct 30, 2019 at 6:09 PM Giulio Benetti
<giulio.benetti@benettiengineering.com> wrote:
>
> This patchset is a WIP for adding i.MXRT family.
> It provides:
> - soc family entry
> - pinctrl driver
> - serial driver tweaking
> - partial sdram controller driver
> - imxrt1050-evk board partial support
Where do you store the U-Boot environment? Is there a eSDHC driver for
it, for example?
^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [RFC PATCH 0/5] WIP Add support for i.MXRT family
2019-11-01 12:41 ` [U-Boot] [RFC PATCH 0/5] WIP Add support for i.MXRT family Fabio Estevam
@ 2019-11-04 16:25 ` Giulio Benetti
0 siblings, 0 replies; 13+ messages in thread
From: Giulio Benetti @ 2019-11-04 16:25 UTC (permalink / raw)
To: u-boot
Hi Fabio,
On 11/1/19 1:41 PM, Fabio Estevam wrote:
> Hi Giulio,
>
> On Wed, Oct 30, 2019 at 6:09 PM Giulio Benetti
> <giulio.benetti@benettiengineering.com> wrote:
>>
>> This patchset is a WIP for adding i.MXRT family.
>> It provides:
>> - soc family entry
>> - pinctrl driver
>> - serial driver tweaking
>> - partial sdram controller driver
>> - imxrt1050-evk board partial support
>
> Where do you store the U-Boot environment?Is there a eSDHC driver for
> it, for example?
Yes, I want to use eSDHC to store there u-boot environment and I'm still
working on it.
--
Giulio Benetti
Benetti Engineering sas
^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [RFC PATCH 5/5] Add support for the NXP IMXRT1050-EVK board
2019-11-01 12:40 ` Fabio Estevam
@ 2019-11-04 16:28 ` Giulio Benetti
0 siblings, 0 replies; 13+ messages in thread
From: Giulio Benetti @ 2019-11-04 16:28 UTC (permalink / raw)
To: u-boot
Hi Fabio,
On 11/1/19 1:40 PM, Fabio Estevam wrote:
> Hi Giulio,
>
> On Wed, Oct 30, 2019 at 6:09 PM Giulio Benetti
> <giulio.benetti@benettiengineering.com> wrote:
>
> Please add a commit log that briefly describes the board.
Yes.
>>
>> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
>> ---
>> arch/arm/dts/Makefile | 2 +
>> arch/arm/dts/imxrt1050-evk.dts | 124 ++++++++
>> arch/arm/dts/imxrt1050.dtsi | 73 +++++
>> arch/arm/mach-imx/imxrt/Kconfig | 11 +
>> board/freescale/imxrt1050-evk/Kconfig | 19 ++
>> board/freescale/imxrt1050-evk/MAINTAINERS | 6 +
>> board/freescale/imxrt1050-evk/Makefile | 6 +
>
> Please add a board/freescale/imxrt1050-evk/README that explains how to
> build, flash the U-Boot binary and boot.
Right.
>> board/freescale/imxrt1050-evk/imxrt1050-evk.c | 94 ++++++
>> configs/imxrt1050-evk_defconfig | 52 ++++
>> include/configs/imxrt1050-evk.h | 68 +++++
>> include/dt-bindings/clock/imxrt-clock.h | 272 ++++++++++++++++++
>> 11 files changed, 727 insertions(+)
>> create mode 100644 arch/arm/dts/imxrt1050-evk.dts
>> create mode 100644 arch/arm/dts/imxrt1050.dtsi
>> create mode 100644 board/freescale/imxrt1050-evk/Kconfig
>> create mode 100644 board/freescale/imxrt1050-evk/MAINTAINERS
>> create mode 100644 board/freescale/imxrt1050-evk/Makefile
>> create mode 100644 board/freescale/imxrt1050-evk/imxrt1050-evk.c
>> create mode 100644 configs/imxrt1050-evk_defconfig
>> create mode 100644 include/configs/imxrt1050-evk.h
>> create mode 100644 include/dt-bindings/clock/imxrt-clock.h
>
> This imxrt-clock.h header and the arch/arm/dts/imxrt1050.dts is
> common imxrt code and not related to the evk board, so better put them
> on a separate patch.
Ok, already done since I'm working right on clock driver now.
Thanks for reviewing my patches, can you also take a look at this [1]?
Because I don't know how to proceed with sdram driver.
Thanks in advance
[1]: https://lists.denx.de/pipermail/u-boot/2019-October/388905.html
Best regards
--
Giulio Benetti
Benetti Engineering sas
^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [RFC PATCH 4/5] ram: add SDRAM driver for i.MXRT SoCs
2019-10-31 12:11 ` Giulio Benetti
@ 2019-11-04 16:33 ` Fabio Estevam
2019-11-04 16:53 ` Giulio Benetti
0 siblings, 1 reply; 13+ messages in thread
From: Fabio Estevam @ 2019-11-04 16:33 UTC (permalink / raw)
To: u-boot
Hi Giulio,
On Thu, Oct 31, 2019 at 9:11 AM Giulio Benetti
<giulio.benetti@benettiengineering.com> wrote:
> ...in this register and the next one there are parameters like CKEOFF
> and ACT2PRE impossible to lead to classic tXXX sdram timing parameters.
> I've done this way inspired by stm32-sdram, but maybe U should go back
> using i.MXRT names(i.e. PRE2ACT instead of tRP) and list all possible
> useful registers in DM as I've done for tRP etc.
> What do you think?
I think it is OK to use the i.MXRT names.
#define TWR_1 0x0
> > +#define TWR_2 0x1
> > +#define TWR_3 0x2
> > +#define TWR_4 0x3
> > +#define TWR_5 0x4
> > +#define TWR_6 0x5
> > +#define TWR_7 0x6
> > +#define TWR_8 0x7
> > +#define TWR_9 0x8
> > +#define TWR_10 0x9
> > +#define TWR_11 0xA
> > +#define TWR_12 0xB
> > +#define TWR_13 0xC
> > +#define TWR_14 0xD
> > +#define TWR_15 0xE
> > +#define TWR_16 0xF
> > +
> > +#endif
> >
>
> ...is it ok listing every possible value for DM parameter?
> I mean, some of them would be 8-bit, this would mean having 256 cases,
> that sound very ugly to me.
It doesn't seem necessary to write all 256 cases. I would suggest to
write the direct hex number.
^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [RFC PATCH 4/5] ram: add SDRAM driver for i.MXRT SoCs
2019-11-04 16:33 ` Fabio Estevam
@ 2019-11-04 16:53 ` Giulio Benetti
0 siblings, 0 replies; 13+ messages in thread
From: Giulio Benetti @ 2019-11-04 16:53 UTC (permalink / raw)
To: u-boot
On 11/4/19 5:33 PM, Fabio Estevam wrote:
> Hi Giulio,
>
> On Thu, Oct 31, 2019 at 9:11 AM Giulio Benetti
> <giulio.benetti@benettiengineering.com> wrote:
>
>> ...in this register and the next one there are parameters like CKEOFF
>> and ACT2PRE impossible to lead to classic tXXX sdram timing parameters.
>> I've done this way inspired by stm32-sdram, but maybe U should go back
>> using i.MXRT names(i.e. PRE2ACT instead of tRP) and list all possible
>> useful registers in DM as I've done for tRP etc.
>> What do you think?
>
> I think it is OK to use the i.MXRT names.
Ok
> #define TWR_1 0x0
>>> +#define TWR_2 0x1
>>> +#define TWR_3 0x2
>>> +#define TWR_4 0x3
>>> +#define TWR_5 0x4
>>> +#define TWR_6 0x5
>>> +#define TWR_7 0x6
>>> +#define TWR_8 0x7
>>> +#define TWR_9 0x8
>>> +#define TWR_10 0x9
>>> +#define TWR_11 0xA
>>> +#define TWR_12 0xB
>>> +#define TWR_13 0xC
>>> +#define TWR_14 0xD
>>> +#define TWR_15 0xE
>>> +#define TWR_16 0xF
>>> +
>>> +#endif
>>>
>>
>> ...is it ok listing every possible value for DM parameter?
>> I mean, some of them would be 8-bit, this would mean having 256 cases,
>> that sound very ugly to me.
>
> It doesn't seem necessary to write all 256 cases. I would suggest to
> write the direct hex number.
>
Well, thanks a lot!
Best regards
--
Giulio Benetti
Benetti Engineering sas
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2019-11-04 16:53 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-10-30 21:09 [U-Boot] [RFC PATCH 0/5] WIP Add support for i.MXRT family Giulio Benetti
2019-10-30 21:09 ` [U-Boot] [RFC PATCH 1/5] Add support for the NXP IMXRT10xx SoC family Giulio Benetti
2019-10-30 21:09 ` [U-Boot] [RFC PATCH 2/5] pinctrl: add i.MXRT driver Giulio Benetti
2019-10-30 21:09 ` [U-Boot] [RFC PATCH 3/5] serial_lpuart: add support for i.MXRT Giulio Benetti
2019-10-30 21:09 ` [U-Boot] [RFC PATCH 4/5] ram: add SDRAM driver for i.MXRT SoCs Giulio Benetti
2019-10-31 12:11 ` Giulio Benetti
2019-11-04 16:33 ` Fabio Estevam
2019-11-04 16:53 ` Giulio Benetti
2019-10-30 21:09 ` [U-Boot] [RFC PATCH 5/5] Add support for the NXP IMXRT1050-EVK board Giulio Benetti
2019-11-01 12:40 ` Fabio Estevam
2019-11-04 16:28 ` Giulio Benetti
2019-11-01 12:41 ` [U-Boot] [RFC PATCH 0/5] WIP Add support for i.MXRT family Fabio Estevam
2019-11-04 16:25 ` Giulio Benetti
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