* [PATCH] drm/i915/selftests: Perform some basic cycle counting of MI ops
@ 2019-10-31 14:03 ` Chris Wilson
0 siblings, 0 replies; 8+ messages in thread
From: Chris Wilson @ 2019-10-31 14:03 UTC (permalink / raw)
To: intel-gfx; +Cc: Anna Karas
Some basic information that is useful to know, such as how many cycles
is a MI_NOOP.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Anna Karas <anna.karas@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 324 +++++++++++++++++-
.../drm/i915/selftests/i915_live_selftests.h | 1 +
2 files changed, 324 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
index 3880f07c29b8..f8697b784955 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
@@ -4,7 +4,329 @@
* Copyright © 2018 Intel Corporation
*/
-#include "../i915_selftest.h"
+#include <linux/sort.h>
+
+#include "i915_selftest.h"
+#include "selftests/igt_flush_test.h"
+
+#define COUNT 5
+
+static int cmp_u32(const void *A, const void *B)
+{
+ const u32 *a = A, *b = B;
+
+ if (*a < *b)
+ return -1;
+ else if (*a > *b)
+ return 1;
+ else
+ return 0;
+}
+
+static int write_timestamp(struct i915_request *rq, int slot)
+{
+ u32 cmd;
+ u32 *cs;
+
+ cs = intel_ring_begin(rq, 4);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
+ if (INTEL_GEN(rq->i915) >= 8)
+ cmd++;
+ *cs++ = cmd;
+ *cs++ = rq->engine->mmio_base + 0x358;
+ *cs++ = i915_request_active_timeline(rq)->hwsp_offset +
+ slot * sizeof(u32);
+ *cs++ = 0;
+
+ intel_ring_advance(rq, cs);
+
+ return 0;
+}
+
+static struct i915_vma *create_empty_batch(struct intel_context *ce)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ u32 *cs;
+ int err;
+
+ obj = i915_gem_object_create_internal(ce->engine->i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ cs = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(cs)) {
+ i915_gem_object_put(obj);
+ return ERR_CAST(cs);
+ }
+
+ cs[0] = MI_BATCH_BUFFER_END;
+
+ i915_gem_object_flush_map(obj);
+ i915_gem_object_unpin_map(obj);
+
+ vma = i915_vma_instance(obj, ce->vm, NULL);
+ if (IS_ERR(vma)) {
+ i915_gem_object_put(obj);
+ return vma;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err) {
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+ }
+
+ return vma;
+}
+
+static u32 trifilter(u32 *a)
+{
+ u64 sum;
+
+ sort(a, COUNT, sizeof(*a), cmp_u32, NULL);
+
+ sum += mul_u32_u32(a[2], 2);
+ sum += a[1];
+ sum += a[3];
+
+ return sum >> 2;
+}
+
+static int perf_mi_bb_start(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
+ return 0;
+
+ for_each_engine(engine, gt, id) {
+ struct intel_context *ce = engine->kernel_context;
+ struct i915_vma *batch;
+ u32 cycles[COUNT];
+ int i;
+
+ batch = create_empty_batch(ce);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ break;
+ }
+
+ err = i915_vma_sync(batch);
+ if (err) {
+ i915_vma_put(batch);
+ break;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(cycles); i++) {
+ struct i915_request *rq;
+
+ rq = i915_request_create(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ break;
+ }
+
+ err = write_timestamp(rq, 2);
+ if (err)
+ goto out;
+
+ err = rq->engine->emit_bb_start(rq,
+ batch->node.start, 8,
+ 0);
+ if (err)
+ goto out;
+
+ err = write_timestamp(rq, 3);
+ if (err)
+ goto out;
+
+out:
+ i915_request_get(rq);
+ i915_request_add(rq);
+
+ if (i915_request_wait(rq, 0, HZ / 5) < 0)
+ err = -EIO;
+ i915_request_put(rq);
+ if (err)
+ break;
+
+ cycles[i] = rq->hwsp_seqno[3] - rq->hwsp_seqno[2];
+ }
+ i915_vma_put(batch);
+ if (err)
+ break;
+
+ pr_info("%s: MI_BB_START cycles: %u\n",
+ engine->name, trifilter(cycles));
+ }
+
+ if (igt_flush_test(gt->i915))
+ err = -EIO;
+
+ return err;
+}
+
+static struct i915_vma *create_nop_batch(struct intel_context *ce)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ u32 *cs;
+ int err;
+
+ obj = i915_gem_object_create_internal(ce->engine->i915, SZ_64K);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ cs = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(cs)) {
+ i915_gem_object_put(obj);
+ return ERR_CAST(cs);
+ }
+
+ memset(cs, 0, SZ_64K);
+ cs[SZ_64K / sizeof(*cs) - 1] = MI_BATCH_BUFFER_END;
+
+ i915_gem_object_flush_map(obj);
+ i915_gem_object_unpin_map(obj);
+
+ vma = i915_vma_instance(obj, ce->vm, NULL);
+ if (IS_ERR(vma)) {
+ i915_gem_object_put(obj);
+ return vma;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err) {
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+ }
+
+ return vma;
+}
+
+static int perf_mi_noop(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
+ return 0;
+
+ for_each_engine(engine, gt, id) {
+ struct intel_context *ce = engine->kernel_context;
+ struct i915_vma *base, *nop;
+ u32 cycles[COUNT];
+ int i;
+
+ base = create_empty_batch(ce);
+ if (IS_ERR(base)) {
+ err = PTR_ERR(base);
+ break;
+ }
+
+ err = i915_vma_sync(base);
+ if (err) {
+ i915_vma_put(base);
+ break;
+ }
+
+ nop = create_nop_batch(ce);
+ if (IS_ERR(nop)) {
+ err = PTR_ERR(nop);
+ i915_vma_put(base);
+ break;
+ }
+
+ err = i915_vma_sync(nop);
+ if (err) {
+ i915_vma_put(nop);
+ i915_vma_put(base);
+ break;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(cycles); i++) {
+ struct i915_request *rq;
+
+ rq = i915_request_create(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ break;
+ }
+
+ err = write_timestamp(rq, 2);
+ if (err)
+ goto out;
+
+ err = rq->engine->emit_bb_start(rq,
+ base->node.start, 8,
+ 0);
+ if (err)
+ goto out;
+
+ err = write_timestamp(rq, 3);
+ if (err)
+ goto out;
+
+ err = rq->engine->emit_bb_start(rq,
+ nop->node.start, 4096,
+ 0);
+ if (err)
+ goto out;
+
+ err = write_timestamp(rq, 4);
+ if (err)
+ goto out;
+
+out:
+ i915_request_get(rq);
+ i915_request_add(rq);
+
+ if (i915_request_wait(rq, 0, HZ / 5) < 0)
+ err = -EIO;
+ i915_request_put(rq);
+ if (err)
+ break;
+
+ cycles[i] =
+ (rq->hwsp_seqno[4] - rq->hwsp_seqno[3]) -
+ (rq->hwsp_seqno[3] - rq->hwsp_seqno[2]);
+ }
+ i915_vma_put(nop);
+ i915_vma_put(base);
+ if (err)
+ break;
+
+ pr_info("%s: 16K MI_NOOP cycles: %u\n",
+ engine->name, trifilter(cycles));
+ }
+
+ if (igt_flush_test(gt->i915))
+ err = -EIO;
+
+ return err;
+}
+
+int intel_engine_cs_live_selftests(struct drm_i915_private *i915)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(perf_mi_bb_start),
+ SUBTEST(perf_mi_noop),
+ };
+
+ if (intel_gt_is_wedged(&i915->gt))
+ return 0;
+
+ return intel_gt_live_subtests(tests, &i915->gt);
+}
static int intel_mmio_bases_check(void *arg)
{
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index 4b3cac73e291..cc44e288a3c5 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -13,6 +13,7 @@ selftest(sanitycheck, i915_live_sanitycheck) /* keep first (igt selfcheck) */
selftest(uncore, intel_uncore_live_selftests)
selftest(workarounds, intel_workarounds_live_selftests)
selftest(gt_engines, intel_engine_live_selftests)
+selftest(gt_engine_cs, intel_engine_cs_live_selftests)
selftest(gt_timelines, intel_timeline_live_selftests)
selftest(gt_contexts, intel_context_live_selftests)
selftest(gt_lrc, intel_lrc_live_selftests)
--
2.24.0.rc1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/selftests: Perform some basic cycle counting of MI ops
@ 2019-10-31 14:03 ` Chris Wilson
0 siblings, 0 replies; 8+ messages in thread
From: Chris Wilson @ 2019-10-31 14:03 UTC (permalink / raw)
To: intel-gfx; +Cc: Anna Karas
Some basic information that is useful to know, such as how many cycles
is a MI_NOOP.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Anna Karas <anna.karas@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 324 +++++++++++++++++-
.../drm/i915/selftests/i915_live_selftests.h | 1 +
2 files changed, 324 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
index 3880f07c29b8..f8697b784955 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
@@ -4,7 +4,329 @@
* Copyright © 2018 Intel Corporation
*/
-#include "../i915_selftest.h"
+#include <linux/sort.h>
+
+#include "i915_selftest.h"
+#include "selftests/igt_flush_test.h"
+
+#define COUNT 5
+
+static int cmp_u32(const void *A, const void *B)
+{
+ const u32 *a = A, *b = B;
+
+ if (*a < *b)
+ return -1;
+ else if (*a > *b)
+ return 1;
+ else
+ return 0;
+}
+
+static int write_timestamp(struct i915_request *rq, int slot)
+{
+ u32 cmd;
+ u32 *cs;
+
+ cs = intel_ring_begin(rq, 4);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
+ if (INTEL_GEN(rq->i915) >= 8)
+ cmd++;
+ *cs++ = cmd;
+ *cs++ = rq->engine->mmio_base + 0x358;
+ *cs++ = i915_request_active_timeline(rq)->hwsp_offset +
+ slot * sizeof(u32);
+ *cs++ = 0;
+
+ intel_ring_advance(rq, cs);
+
+ return 0;
+}
+
+static struct i915_vma *create_empty_batch(struct intel_context *ce)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ u32 *cs;
+ int err;
+
+ obj = i915_gem_object_create_internal(ce->engine->i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ cs = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(cs)) {
+ i915_gem_object_put(obj);
+ return ERR_CAST(cs);
+ }
+
+ cs[0] = MI_BATCH_BUFFER_END;
+
+ i915_gem_object_flush_map(obj);
+ i915_gem_object_unpin_map(obj);
+
+ vma = i915_vma_instance(obj, ce->vm, NULL);
+ if (IS_ERR(vma)) {
+ i915_gem_object_put(obj);
+ return vma;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err) {
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+ }
+
+ return vma;
+}
+
+static u32 trifilter(u32 *a)
+{
+ u64 sum;
+
+ sort(a, COUNT, sizeof(*a), cmp_u32, NULL);
+
+ sum += mul_u32_u32(a[2], 2);
+ sum += a[1];
+ sum += a[3];
+
+ return sum >> 2;
+}
+
+static int perf_mi_bb_start(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
+ return 0;
+
+ for_each_engine(engine, gt, id) {
+ struct intel_context *ce = engine->kernel_context;
+ struct i915_vma *batch;
+ u32 cycles[COUNT];
+ int i;
+
+ batch = create_empty_batch(ce);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ break;
+ }
+
+ err = i915_vma_sync(batch);
+ if (err) {
+ i915_vma_put(batch);
+ break;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(cycles); i++) {
+ struct i915_request *rq;
+
+ rq = i915_request_create(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ break;
+ }
+
+ err = write_timestamp(rq, 2);
+ if (err)
+ goto out;
+
+ err = rq->engine->emit_bb_start(rq,
+ batch->node.start, 8,
+ 0);
+ if (err)
+ goto out;
+
+ err = write_timestamp(rq, 3);
+ if (err)
+ goto out;
+
+out:
+ i915_request_get(rq);
+ i915_request_add(rq);
+
+ if (i915_request_wait(rq, 0, HZ / 5) < 0)
+ err = -EIO;
+ i915_request_put(rq);
+ if (err)
+ break;
+
+ cycles[i] = rq->hwsp_seqno[3] - rq->hwsp_seqno[2];
+ }
+ i915_vma_put(batch);
+ if (err)
+ break;
+
+ pr_info("%s: MI_BB_START cycles: %u\n",
+ engine->name, trifilter(cycles));
+ }
+
+ if (igt_flush_test(gt->i915))
+ err = -EIO;
+
+ return err;
+}
+
+static struct i915_vma *create_nop_batch(struct intel_context *ce)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ u32 *cs;
+ int err;
+
+ obj = i915_gem_object_create_internal(ce->engine->i915, SZ_64K);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ cs = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(cs)) {
+ i915_gem_object_put(obj);
+ return ERR_CAST(cs);
+ }
+
+ memset(cs, 0, SZ_64K);
+ cs[SZ_64K / sizeof(*cs) - 1] = MI_BATCH_BUFFER_END;
+
+ i915_gem_object_flush_map(obj);
+ i915_gem_object_unpin_map(obj);
+
+ vma = i915_vma_instance(obj, ce->vm, NULL);
+ if (IS_ERR(vma)) {
+ i915_gem_object_put(obj);
+ return vma;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err) {
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+ }
+
+ return vma;
+}
+
+static int perf_mi_noop(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
+ return 0;
+
+ for_each_engine(engine, gt, id) {
+ struct intel_context *ce = engine->kernel_context;
+ struct i915_vma *base, *nop;
+ u32 cycles[COUNT];
+ int i;
+
+ base = create_empty_batch(ce);
+ if (IS_ERR(base)) {
+ err = PTR_ERR(base);
+ break;
+ }
+
+ err = i915_vma_sync(base);
+ if (err) {
+ i915_vma_put(base);
+ break;
+ }
+
+ nop = create_nop_batch(ce);
+ if (IS_ERR(nop)) {
+ err = PTR_ERR(nop);
+ i915_vma_put(base);
+ break;
+ }
+
+ err = i915_vma_sync(nop);
+ if (err) {
+ i915_vma_put(nop);
+ i915_vma_put(base);
+ break;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(cycles); i++) {
+ struct i915_request *rq;
+
+ rq = i915_request_create(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ break;
+ }
+
+ err = write_timestamp(rq, 2);
+ if (err)
+ goto out;
+
+ err = rq->engine->emit_bb_start(rq,
+ base->node.start, 8,
+ 0);
+ if (err)
+ goto out;
+
+ err = write_timestamp(rq, 3);
+ if (err)
+ goto out;
+
+ err = rq->engine->emit_bb_start(rq,
+ nop->node.start, 4096,
+ 0);
+ if (err)
+ goto out;
+
+ err = write_timestamp(rq, 4);
+ if (err)
+ goto out;
+
+out:
+ i915_request_get(rq);
+ i915_request_add(rq);
+
+ if (i915_request_wait(rq, 0, HZ / 5) < 0)
+ err = -EIO;
+ i915_request_put(rq);
+ if (err)
+ break;
+
+ cycles[i] =
+ (rq->hwsp_seqno[4] - rq->hwsp_seqno[3]) -
+ (rq->hwsp_seqno[3] - rq->hwsp_seqno[2]);
+ }
+ i915_vma_put(nop);
+ i915_vma_put(base);
+ if (err)
+ break;
+
+ pr_info("%s: 16K MI_NOOP cycles: %u\n",
+ engine->name, trifilter(cycles));
+ }
+
+ if (igt_flush_test(gt->i915))
+ err = -EIO;
+
+ return err;
+}
+
+int intel_engine_cs_live_selftests(struct drm_i915_private *i915)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(perf_mi_bb_start),
+ SUBTEST(perf_mi_noop),
+ };
+
+ if (intel_gt_is_wedged(&i915->gt))
+ return 0;
+
+ return intel_gt_live_subtests(tests, &i915->gt);
+}
static int intel_mmio_bases_check(void *arg)
{
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index 4b3cac73e291..cc44e288a3c5 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -13,6 +13,7 @@ selftest(sanitycheck, i915_live_sanitycheck) /* keep first (igt selfcheck) */
selftest(uncore, intel_uncore_live_selftests)
selftest(workarounds, intel_workarounds_live_selftests)
selftest(gt_engines, intel_engine_live_selftests)
+selftest(gt_engine_cs, intel_engine_cs_live_selftests)
selftest(gt_timelines, intel_timeline_live_selftests)
selftest(gt_contexts, intel_context_live_selftests)
selftest(gt_lrc, intel_lrc_live_selftests)
--
2.24.0.rc1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2] drm/i915/selftests: Perform some basic cycle counting of MI ops
@ 2019-10-31 14:44 ` Chris Wilson
0 siblings, 0 replies; 8+ messages in thread
From: Chris Wilson @ 2019-10-31 14:44 UTC (permalink / raw)
To: intel-gfx; +Cc: Anna Karas
Some basic information that is useful to know, such as how many cycles
is a MI_NOOP.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Anna Karas <anna.karas@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
Having remember to ask for a fixed frequency!
---
drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 339 +++++++++++++++++-
.../drm/i915/selftests/i915_live_selftests.h | 1 +
2 files changed, 339 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
index 3880f07c29b8..bdd82d142602 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
@@ -4,7 +4,344 @@
* Copyright © 2018 Intel Corporation
*/
-#include "../i915_selftest.h"
+#include <linux/sort.h>
+
+#include "intel_gt_pm.h"
+#include "intel_rps.h"
+
+#include "i915_selftest.h"
+#include "selftests/igt_flush_test.h"
+
+#define COUNT 5
+
+static int cmp_u32(const void *A, const void *B)
+{
+ const u32 *a = A, *b = B;
+
+ return *a - *b;
+}
+
+static void perf_begin(struct intel_gt *gt)
+{
+ intel_gt_pm_get(gt);
+
+ /* Boost gpufreq to max [waitboost] and keep it fixed */
+ atomic_inc(>->rps.num_waiters);
+ schedule_work(>->rps.work);
+ flush_work(>->rps.work);
+}
+
+static int perf_end(struct intel_gt *gt)
+{
+ atomic_dec(>->rps.num_waiters);
+ intel_gt_pm_put(gt);
+
+ return igt_flush_test(gt->i915);
+}
+
+static int write_timestamp(struct i915_request *rq, int slot)
+{
+ u32 cmd;
+ u32 *cs;
+
+ cs = intel_ring_begin(rq, 4);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
+ if (INTEL_GEN(rq->i915) >= 8)
+ cmd++;
+ *cs++ = cmd;
+ *cs++ = rq->engine->mmio_base + 0x358;
+ *cs++ = i915_request_timeline(rq)->hwsp_offset + slot * sizeof(u32);
+ *cs++ = 0;
+
+ intel_ring_advance(rq, cs);
+
+ return 0;
+}
+
+static struct i915_vma *create_empty_batch(struct intel_context *ce)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ u32 *cs;
+ int err;
+
+ obj = i915_gem_object_create_internal(ce->engine->i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ cs = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(cs)) {
+ i915_gem_object_put(obj);
+ return ERR_CAST(cs);
+ }
+
+ cs[0] = MI_BATCH_BUFFER_END;
+
+ i915_gem_object_flush_map(obj);
+ i915_gem_object_unpin_map(obj);
+
+ vma = i915_vma_instance(obj, ce->vm, NULL);
+ if (IS_ERR(vma)) {
+ i915_gem_object_put(obj);
+ return vma;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err) {
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+ }
+
+ return vma;
+}
+
+static u32 trifilter(u32 *a)
+{
+ u64 sum;
+
+ sort(a, COUNT, sizeof(*a), cmp_u32, NULL);
+
+ sum += mul_u32_u32(a[2], 2);
+ sum += a[1];
+ sum += a[3];
+
+ return sum >> 2;
+}
+
+static int perf_mi_bb_start(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
+ return 0;
+
+ perf_begin(gt);
+ for_each_engine(engine, gt, id) {
+ struct intel_context *ce = engine->kernel_context;
+ struct i915_vma *batch;
+ u32 cycles[COUNT];
+ int i;
+
+ batch = create_empty_batch(ce);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ break;
+ }
+
+ err = i915_vma_sync(batch);
+ if (err) {
+ i915_vma_put(batch);
+ break;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(cycles); i++) {
+ struct i915_request *rq;
+
+ rq = i915_request_create(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ break;
+ }
+
+ err = write_timestamp(rq, 2);
+ if (err)
+ goto out;
+
+ err = rq->engine->emit_bb_start(rq,
+ batch->node.start, 8,
+ 0);
+ if (err)
+ goto out;
+
+ err = write_timestamp(rq, 3);
+ if (err)
+ goto out;
+
+out:
+ i915_request_get(rq);
+ i915_request_add(rq);
+
+ if (i915_request_wait(rq, 0, HZ / 5) < 0)
+ err = -EIO;
+ i915_request_put(rq);
+ if (err)
+ break;
+
+ cycles[i] = rq->hwsp_seqno[3] - rq->hwsp_seqno[2];
+ }
+ i915_vma_put(batch);
+ if (err)
+ break;
+
+ pr_info("%s: MI_BB_START cycles: %u\n",
+ engine->name, trifilter(cycles));
+ }
+ if (perf_end(gt))
+ err = -EIO;
+
+ return err;
+}
+
+static struct i915_vma *create_nop_batch(struct intel_context *ce)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ u32 *cs;
+ int err;
+
+ obj = i915_gem_object_create_internal(ce->engine->i915, SZ_64K);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ cs = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(cs)) {
+ i915_gem_object_put(obj);
+ return ERR_CAST(cs);
+ }
+
+ memset(cs, 0, SZ_64K);
+ cs[SZ_64K / sizeof(*cs) - 1] = MI_BATCH_BUFFER_END;
+
+ i915_gem_object_flush_map(obj);
+ i915_gem_object_unpin_map(obj);
+
+ vma = i915_vma_instance(obj, ce->vm, NULL);
+ if (IS_ERR(vma)) {
+ i915_gem_object_put(obj);
+ return vma;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err) {
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+ }
+
+ return vma;
+}
+
+static int perf_mi_noop(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
+ return 0;
+
+ perf_begin(gt);
+ for_each_engine(engine, gt, id) {
+ struct intel_context *ce = engine->kernel_context;
+ struct i915_vma *base, *nop;
+ u32 cycles[COUNT];
+ int i;
+
+ base = create_empty_batch(ce);
+ if (IS_ERR(base)) {
+ err = PTR_ERR(base);
+ break;
+ }
+
+ err = i915_vma_sync(base);
+ if (err) {
+ i915_vma_put(base);
+ break;
+ }
+
+ nop = create_nop_batch(ce);
+ if (IS_ERR(nop)) {
+ err = PTR_ERR(nop);
+ i915_vma_put(base);
+ break;
+ }
+
+ err = i915_vma_sync(nop);
+ if (err) {
+ i915_vma_put(nop);
+ i915_vma_put(base);
+ break;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(cycles); i++) {
+ struct i915_request *rq;
+
+ rq = i915_request_create(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ break;
+ }
+
+ err = write_timestamp(rq, 2);
+ if (err)
+ goto out;
+
+ err = rq->engine->emit_bb_start(rq,
+ base->node.start, 8,
+ 0);
+ if (err)
+ goto out;
+
+ err = write_timestamp(rq, 3);
+ if (err)
+ goto out;
+
+ err = rq->engine->emit_bb_start(rq,
+ nop->node.start, 4096,
+ 0);
+ if (err)
+ goto out;
+
+ err = write_timestamp(rq, 4);
+ if (err)
+ goto out;
+
+out:
+ i915_request_get(rq);
+ i915_request_add(rq);
+
+ if (i915_request_wait(rq, 0, HZ / 5) < 0)
+ err = -EIO;
+ i915_request_put(rq);
+ if (err)
+ break;
+
+ cycles[i] =
+ (rq->hwsp_seqno[4] - rq->hwsp_seqno[3]) -
+ (rq->hwsp_seqno[3] - rq->hwsp_seqno[2]);
+ }
+ i915_vma_put(nop);
+ i915_vma_put(base);
+ if (err)
+ break;
+
+ pr_info("%s: 16K MI_NOOP cycles: %u\n",
+ engine->name, trifilter(cycles));
+ }
+ if (perf_end(gt))
+ err = -EIO;
+
+ return err;
+}
+
+int intel_engine_cs_live_selftests(struct drm_i915_private *i915)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(perf_mi_bb_start),
+ SUBTEST(perf_mi_noop),
+ };
+
+ if (intel_gt_is_wedged(&i915->gt))
+ return 0;
+
+ return intel_gt_live_subtests(tests, &i915->gt);
+}
static int intel_mmio_bases_check(void *arg)
{
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index 4b3cac73e291..cc44e288a3c5 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -13,6 +13,7 @@ selftest(sanitycheck, i915_live_sanitycheck) /* keep first (igt selfcheck) */
selftest(uncore, intel_uncore_live_selftests)
selftest(workarounds, intel_workarounds_live_selftests)
selftest(gt_engines, intel_engine_live_selftests)
+selftest(gt_engine_cs, intel_engine_cs_live_selftests)
selftest(gt_timelines, intel_timeline_live_selftests)
selftest(gt_contexts, intel_context_live_selftests)
selftest(gt_lrc, intel_lrc_live_selftests)
--
2.24.0.rc1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] [PATCH v2] drm/i915/selftests: Perform some basic cycle counting of MI ops
@ 2019-10-31 14:44 ` Chris Wilson
0 siblings, 0 replies; 8+ messages in thread
From: Chris Wilson @ 2019-10-31 14:44 UTC (permalink / raw)
To: intel-gfx; +Cc: Anna Karas
Some basic information that is useful to know, such as how many cycles
is a MI_NOOP.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Anna Karas <anna.karas@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
Having remember to ask for a fixed frequency!
---
drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 339 +++++++++++++++++-
.../drm/i915/selftests/i915_live_selftests.h | 1 +
2 files changed, 339 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
index 3880f07c29b8..bdd82d142602 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
@@ -4,7 +4,344 @@
* Copyright © 2018 Intel Corporation
*/
-#include "../i915_selftest.h"
+#include <linux/sort.h>
+
+#include "intel_gt_pm.h"
+#include "intel_rps.h"
+
+#include "i915_selftest.h"
+#include "selftests/igt_flush_test.h"
+
+#define COUNT 5
+
+static int cmp_u32(const void *A, const void *B)
+{
+ const u32 *a = A, *b = B;
+
+ return *a - *b;
+}
+
+static void perf_begin(struct intel_gt *gt)
+{
+ intel_gt_pm_get(gt);
+
+ /* Boost gpufreq to max [waitboost] and keep it fixed */
+ atomic_inc(>->rps.num_waiters);
+ schedule_work(>->rps.work);
+ flush_work(>->rps.work);
+}
+
+static int perf_end(struct intel_gt *gt)
+{
+ atomic_dec(>->rps.num_waiters);
+ intel_gt_pm_put(gt);
+
+ return igt_flush_test(gt->i915);
+}
+
+static int write_timestamp(struct i915_request *rq, int slot)
+{
+ u32 cmd;
+ u32 *cs;
+
+ cs = intel_ring_begin(rq, 4);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
+ if (INTEL_GEN(rq->i915) >= 8)
+ cmd++;
+ *cs++ = cmd;
+ *cs++ = rq->engine->mmio_base + 0x358;
+ *cs++ = i915_request_timeline(rq)->hwsp_offset + slot * sizeof(u32);
+ *cs++ = 0;
+
+ intel_ring_advance(rq, cs);
+
+ return 0;
+}
+
+static struct i915_vma *create_empty_batch(struct intel_context *ce)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ u32 *cs;
+ int err;
+
+ obj = i915_gem_object_create_internal(ce->engine->i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ cs = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(cs)) {
+ i915_gem_object_put(obj);
+ return ERR_CAST(cs);
+ }
+
+ cs[0] = MI_BATCH_BUFFER_END;
+
+ i915_gem_object_flush_map(obj);
+ i915_gem_object_unpin_map(obj);
+
+ vma = i915_vma_instance(obj, ce->vm, NULL);
+ if (IS_ERR(vma)) {
+ i915_gem_object_put(obj);
+ return vma;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err) {
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+ }
+
+ return vma;
+}
+
+static u32 trifilter(u32 *a)
+{
+ u64 sum;
+
+ sort(a, COUNT, sizeof(*a), cmp_u32, NULL);
+
+ sum += mul_u32_u32(a[2], 2);
+ sum += a[1];
+ sum += a[3];
+
+ return sum >> 2;
+}
+
+static int perf_mi_bb_start(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
+ return 0;
+
+ perf_begin(gt);
+ for_each_engine(engine, gt, id) {
+ struct intel_context *ce = engine->kernel_context;
+ struct i915_vma *batch;
+ u32 cycles[COUNT];
+ int i;
+
+ batch = create_empty_batch(ce);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ break;
+ }
+
+ err = i915_vma_sync(batch);
+ if (err) {
+ i915_vma_put(batch);
+ break;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(cycles); i++) {
+ struct i915_request *rq;
+
+ rq = i915_request_create(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ break;
+ }
+
+ err = write_timestamp(rq, 2);
+ if (err)
+ goto out;
+
+ err = rq->engine->emit_bb_start(rq,
+ batch->node.start, 8,
+ 0);
+ if (err)
+ goto out;
+
+ err = write_timestamp(rq, 3);
+ if (err)
+ goto out;
+
+out:
+ i915_request_get(rq);
+ i915_request_add(rq);
+
+ if (i915_request_wait(rq, 0, HZ / 5) < 0)
+ err = -EIO;
+ i915_request_put(rq);
+ if (err)
+ break;
+
+ cycles[i] = rq->hwsp_seqno[3] - rq->hwsp_seqno[2];
+ }
+ i915_vma_put(batch);
+ if (err)
+ break;
+
+ pr_info("%s: MI_BB_START cycles: %u\n",
+ engine->name, trifilter(cycles));
+ }
+ if (perf_end(gt))
+ err = -EIO;
+
+ return err;
+}
+
+static struct i915_vma *create_nop_batch(struct intel_context *ce)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ u32 *cs;
+ int err;
+
+ obj = i915_gem_object_create_internal(ce->engine->i915, SZ_64K);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ cs = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(cs)) {
+ i915_gem_object_put(obj);
+ return ERR_CAST(cs);
+ }
+
+ memset(cs, 0, SZ_64K);
+ cs[SZ_64K / sizeof(*cs) - 1] = MI_BATCH_BUFFER_END;
+
+ i915_gem_object_flush_map(obj);
+ i915_gem_object_unpin_map(obj);
+
+ vma = i915_vma_instance(obj, ce->vm, NULL);
+ if (IS_ERR(vma)) {
+ i915_gem_object_put(obj);
+ return vma;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err) {
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+ }
+
+ return vma;
+}
+
+static int perf_mi_noop(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
+ return 0;
+
+ perf_begin(gt);
+ for_each_engine(engine, gt, id) {
+ struct intel_context *ce = engine->kernel_context;
+ struct i915_vma *base, *nop;
+ u32 cycles[COUNT];
+ int i;
+
+ base = create_empty_batch(ce);
+ if (IS_ERR(base)) {
+ err = PTR_ERR(base);
+ break;
+ }
+
+ err = i915_vma_sync(base);
+ if (err) {
+ i915_vma_put(base);
+ break;
+ }
+
+ nop = create_nop_batch(ce);
+ if (IS_ERR(nop)) {
+ err = PTR_ERR(nop);
+ i915_vma_put(base);
+ break;
+ }
+
+ err = i915_vma_sync(nop);
+ if (err) {
+ i915_vma_put(nop);
+ i915_vma_put(base);
+ break;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(cycles); i++) {
+ struct i915_request *rq;
+
+ rq = i915_request_create(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ break;
+ }
+
+ err = write_timestamp(rq, 2);
+ if (err)
+ goto out;
+
+ err = rq->engine->emit_bb_start(rq,
+ base->node.start, 8,
+ 0);
+ if (err)
+ goto out;
+
+ err = write_timestamp(rq, 3);
+ if (err)
+ goto out;
+
+ err = rq->engine->emit_bb_start(rq,
+ nop->node.start, 4096,
+ 0);
+ if (err)
+ goto out;
+
+ err = write_timestamp(rq, 4);
+ if (err)
+ goto out;
+
+out:
+ i915_request_get(rq);
+ i915_request_add(rq);
+
+ if (i915_request_wait(rq, 0, HZ / 5) < 0)
+ err = -EIO;
+ i915_request_put(rq);
+ if (err)
+ break;
+
+ cycles[i] =
+ (rq->hwsp_seqno[4] - rq->hwsp_seqno[3]) -
+ (rq->hwsp_seqno[3] - rq->hwsp_seqno[2]);
+ }
+ i915_vma_put(nop);
+ i915_vma_put(base);
+ if (err)
+ break;
+
+ pr_info("%s: 16K MI_NOOP cycles: %u\n",
+ engine->name, trifilter(cycles));
+ }
+ if (perf_end(gt))
+ err = -EIO;
+
+ return err;
+}
+
+int intel_engine_cs_live_selftests(struct drm_i915_private *i915)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(perf_mi_bb_start),
+ SUBTEST(perf_mi_noop),
+ };
+
+ if (intel_gt_is_wedged(&i915->gt))
+ return 0;
+
+ return intel_gt_live_subtests(tests, &i915->gt);
+}
static int intel_mmio_bases_check(void *arg)
{
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index 4b3cac73e291..cc44e288a3c5 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -13,6 +13,7 @@ selftest(sanitycheck, i915_live_sanitycheck) /* keep first (igt selfcheck) */
selftest(uncore, intel_uncore_live_selftests)
selftest(workarounds, intel_workarounds_live_selftests)
selftest(gt_engines, intel_engine_live_selftests)
+selftest(gt_engine_cs, intel_engine_cs_live_selftests)
selftest(gt_timelines, intel_timeline_live_selftests)
selftest(gt_contexts, intel_context_live_selftests)
selftest(gt_lrc, intel_lrc_live_selftests)
--
2.24.0.rc1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/selftests: Perform some basic cycle counting of MI ops (rev2)
@ 2019-10-31 16:57 ` Patchwork
0 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2019-10-31 16:57 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/selftests: Perform some basic cycle counting of MI ops (rev2)
URL : https://patchwork.freedesktop.org/series/68824/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7231 -> Patchwork_15090
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_15090 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15090, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15090:
### IGT changes ###
#### Warnings ####
* igt@i915_pm_rpm@basic-rte:
- fi-kbl-guc: [SKIP][1] ([fdo#109271]) -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
New tests
---------
New tests have been introduced between CI_DRM_7231 and Patchwork_15090:
### New IGT tests (1) ###
* igt@i915_selftest@live_gt_engine_cs:
- Statuses : 43 pass(s)
- Exec time: [0.40, 1.43] s
Known issues
------------
Here are the changes found in Patchwork_15090 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_render_linear_blits@basic:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/fi-icl-u3/igt@gem_render_linear_blits@basic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/fi-icl-u3/igt@gem_render_linear_blits@basic.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/fi-icl-u3/igt@gem_exec_suspend@basic-s4-devices.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/fi-icl-u3/igt@gem_exec_suspend@basic-s4-devices.html
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
Participating hosts (52 -> 45)
------------------------------
Additional (1): fi-tgl-u
Missing (8): fi-ilk-m540 fi-hsw-4200u fi-tgl-u2 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7231 -> Patchwork_15090
CI-20190529: 20190529
CI_DRM_7231: 9c304eaf3dae009ccb96d56eca58a81837303fc6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5255: b21b6a7aaa0db2159f22ee4427804e5a16fe2261 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15090: c08fccd51739d9ca8ca7adaccad4054c0052f744 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c08fccd51739 drm/i915/selftests: Perform some basic cycle counting of MI ops
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Perform some basic cycle counting of MI ops (rev2)
@ 2019-10-31 16:57 ` Patchwork
0 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2019-10-31 16:57 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/selftests: Perform some basic cycle counting of MI ops (rev2)
URL : https://patchwork.freedesktop.org/series/68824/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7231 -> Patchwork_15090
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_15090 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15090, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15090:
### IGT changes ###
#### Warnings ####
* igt@i915_pm_rpm@basic-rte:
- fi-kbl-guc: [SKIP][1] ([fdo#109271]) -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
New tests
---------
New tests have been introduced between CI_DRM_7231 and Patchwork_15090:
### New IGT tests (1) ###
* igt@i915_selftest@live_gt_engine_cs:
- Statuses : 43 pass(s)
- Exec time: [0.40, 1.43] s
Known issues
------------
Here are the changes found in Patchwork_15090 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_render_linear_blits@basic:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/fi-icl-u3/igt@gem_render_linear_blits@basic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/fi-icl-u3/igt@gem_render_linear_blits@basic.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/fi-icl-u3/igt@gem_exec_suspend@basic-s4-devices.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/fi-icl-u3/igt@gem_exec_suspend@basic-s4-devices.html
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
Participating hosts (52 -> 45)
------------------------------
Additional (1): fi-tgl-u
Missing (8): fi-ilk-m540 fi-hsw-4200u fi-tgl-u2 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7231 -> Patchwork_15090
CI-20190529: 20190529
CI_DRM_7231: 9c304eaf3dae009ccb96d56eca58a81837303fc6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5255: b21b6a7aaa0db2159f22ee4427804e5a16fe2261 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15090: c08fccd51739d9ca8ca7adaccad4054c0052f744 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c08fccd51739 drm/i915/selftests: Perform some basic cycle counting of MI ops
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* ✗ Fi.CI.IGT: failure for drm/i915/selftests: Perform some basic cycle counting of MI ops (rev2)
@ 2019-11-01 20:09 ` Patchwork
0 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2019-11-01 20:09 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/selftests: Perform some basic cycle counting of MI ops (rev2)
URL : https://patchwork.freedesktop.org/series/68824/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7231_full -> Patchwork_15090_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15090_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15090_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15090_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@mock_requests:
- shard-glk: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-glk6/igt@i915_selftest@mock_requests.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-glk9/igt@i915_selftest@mock_requests.html
New tests
---------
New tests have been introduced between CI_DRM_7231_full and Patchwork_15090_full:
### New IGT tests (1) ###
* igt@i915_selftest@live_gt_engine_cs:
- Statuses : 7 pass(s)
- Exec time: [0.32, 2.25] s
Known issues
------------
Here are the changes found in Patchwork_15090_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@vcs1-reset:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb2/igt@gem_ctx_isolation@vcs1-reset.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb7/igt@gem_ctx_isolation@vcs1-reset.html
* igt@gem_ctx_switch@vcs1:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#112080]) +7 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb2/igt@gem_ctx_switch@vcs1.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb8/igt@gem_ctx_switch@vcs1.html
* igt@gem_exec_schedule@independent-bsd:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#112146])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb3/igt@gem_exec_schedule@independent-bsd.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb2/igt@gem_exec_schedule@independent-bsd.html
* igt@gem_exec_schedule@independent-bsd2:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +9 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb2/igt@gem_exec_schedule@independent-bsd2.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb8/igt@gem_exec_schedule@independent-bsd2.html
* igt@gem_persistent_relocs@forked-thrashing:
- shard-iclb: [PASS][11] -> [INCOMPLETE][12] ([fdo#107713] / [fdo#109100] / [fdo#112068 ])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb4/igt@gem_persistent_relocs@forked-thrashing.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb3/igt@gem_persistent_relocs@forked-thrashing.html
* igt@gem_softpin@noreloc-s3:
- shard-skl: [PASS][13] -> [INCOMPLETE][14] ([fdo#104108])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-skl10/igt@gem_softpin@noreloc-s3.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-skl2/igt@gem_softpin@noreloc-s3.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-snb: [PASS][15] -> [DMESG-WARN][16] ([fdo#110789] / [fdo#111870])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-snb7/igt@gem_userptr_blits@dmabuf-unsync.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-snb1/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-hsw: [PASS][17] -> [DMESG-WARN][18] ([fdo#111870])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-hsw5/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-hsw8/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
* igt@gem_userptr_blits@sync-unmap:
- shard-snb: [PASS][19] -> [DMESG-WARN][20] ([fdo#111870])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-snb4/igt@gem_userptr_blits@sync-unmap.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-snb6/igt@gem_userptr_blits@sync-unmap.html
* igt@i915_selftest@live_hangcheck:
- shard-iclb: [PASS][21] -> [INCOMPLETE][22] ([fdo#107713] / [fdo#108569])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb7/igt@i915_selftest@live_hangcheck.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb1/igt@i915_selftest@live_hangcheck.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-apl: [PASS][23] -> [DMESG-WARN][24] ([fdo#108566])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-apl2/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-apl6/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-iclb: [PASS][25] -> [INCOMPLETE][26] ([fdo#107713])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: [PASS][27] -> [FAIL][28] ([fdo#105363])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-glk9/igt@kms_flip@flip-vs-expired-vblank.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-glk2/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [PASS][29] -> [DMESG-WARN][30] ([fdo#108566]) +5 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [PASS][31] -> [FAIL][32] ([fdo#103167]) +3 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc:
- shard-skl: [PASS][33] -> [FAIL][34] ([fdo#103167])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-skl8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][35] -> [FAIL][36] ([fdo#108145])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_cursor@pipe-a-viewport-size-64:
- shard-apl: [PASS][37] -> [INCOMPLETE][38] ([fdo#103927])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-apl6/igt@kms_plane_cursor@pipe-a-viewport-size-64.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-apl1/igt@kms_plane_cursor@pipe-a-viewport-size-64.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: [PASS][39] -> [FAIL][40] ([fdo#103166])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb4/igt@kms_plane_lowres@pipe-a-tiling-x.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb4/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-skl: [PASS][41] -> [DMESG-WARN][42] ([fdo#106885])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-skl1/igt@kms_plane_multiple@atomic-pipe-a-tiling-y.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-skl4/igt@kms_plane_multiple@atomic-pipe-a-tiling-y.html
* igt@kms_psr@psr2_basic:
- shard-iclb: [PASS][43] -> [SKIP][44] ([fdo#109441]) +2 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb2/igt@kms_psr@psr2_basic.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb1/igt@kms_psr@psr2_basic.html
* igt@kms_setmode@basic:
- shard-hsw: [PASS][45] -> [FAIL][46] ([fdo#99912])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-hsw1/igt@kms_setmode@basic.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-hsw8/igt@kms_setmode@basic.html
#### Possible fixes ####
* igt@gem_ctx_isolation@vcs1-none:
- shard-iclb: [SKIP][47] ([fdo#109276] / [fdo#112080]) -> [PASS][48] +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb6/igt@gem_ctx_isolation@vcs1-none.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb2/igt@gem_ctx_isolation@vcs1-none.html
* {igt@gem_ctx_persistence@vcs0-mixed-process}:
- shard-skl: [FAIL][49] -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-skl5/igt@gem_ctx_persistence@vcs0-mixed-process.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-skl6/igt@gem_ctx_persistence@vcs0-mixed-process.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [SKIP][51] ([fdo#110841]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb2/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb8/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_ctx_shared@q-smoketest-all:
- {shard-tglb}: [INCOMPLETE][53] ([fdo#111735]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-tglb4/igt@gem_ctx_shared@q-smoketest-all.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-tglb7/igt@gem_ctx_shared@q-smoketest-all.html
* igt@gem_eio@unwedge-stress:
- shard-snb: [FAIL][55] ([fdo#109661]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-snb1/igt@gem_eio@unwedge-stress.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-snb2/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_schedule@preempt-queue-contexts-chain-render:
- {shard-tglb}: [INCOMPLETE][57] ([fdo#111677]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-tglb6/igt@gem_exec_schedule@preempt-queue-contexts-chain-render.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-tglb3/igt@gem_exec_schedule@preempt-queue-contexts-chain-render.html
* igt@gem_exec_schedule@wide-bsd:
- shard-iclb: [SKIP][59] ([fdo#112146]) -> [PASS][60] +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb2/igt@gem_exec_schedule@wide-bsd.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb7/igt@gem_exec_schedule@wide-bsd.html
* igt@gem_softpin@noreloc-s3:
- shard-apl: [DMESG-WARN][61] ([fdo#108566]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-apl6/igt@gem_softpin@noreloc-s3.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-apl4/igt@gem_softpin@noreloc-s3.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
- shard-apl: [INCOMPLETE][63] ([fdo#103927]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-apl3/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-apl7/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-snb: [DMESG-WARN][65] ([fdo#111870]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
- shard-hsw: [DMESG-WARN][67] ([fdo#111870]) -> [PASS][68] +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-hsw1/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* igt@gem_workarounds@suspend-resume:
- {shard-tglb}: [INCOMPLETE][69] ([fdo#111832] / [fdo#111850]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-tglb7/igt@gem_workarounds@suspend-resume.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-tglb8/igt@gem_workarounds@suspend-resume.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [DMESG-WARN][71] ([fdo#108566]) -> [PASS][72] +2 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-kbl4/igt@gem_workarounds@suspend-resume-fd.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-kbl3/igt@gem_workarounds@suspend-resume-fd.html
* igt@i915_pm_rpm@modeset-stress-extra-wait:
- shard-glk: [DMESG-WARN][73] ([fdo#105763] / [fdo#106538]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-glk8/igt@i915_pm_rpm@modeset-stress-extra-wait.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-glk9/igt@i915_pm_rpm@modeset-stress-extra-wait.html
* {igt@i915_selftest@live_gt_timelines}:
- {shard-tglb}: [INCOMPLETE][75] ([fdo#111831]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-tglb6/igt@i915_selftest@live_gt_timelines.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-tglb8/igt@i915_selftest@live_gt_timelines.html
* igt@kms_color@pipe-b-ctm-0-25:
- shard-skl: [DMESG-WARN][77] ([fdo#106107]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-skl6/igt@kms_color@pipe-b-ctm-0-25.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-skl5/igt@kms_color@pipe-b-ctm-0-25.html
* igt@kms_cursor_crc@pipe-a-cursor-128x128-random:
- shard-hsw: [INCOMPLETE][79] ([fdo#103540]) -> [PASS][80] +1 similar issue
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-hsw4/igt@kms_cursor_crc@pipe-a-cursor-128x128-random.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-hsw1/igt@kms_cursor_crc@pipe-a-cursor-128x128-random.html
* igt@kms_cursor_crc@pipe-a-cursor-dpms:
- shard-kbl: [FAIL][81] ([fdo#103232]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-dpms.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-dpms.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-skl: [INCOMPLETE][83] ([fdo#110741]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-skl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-skl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [FAIL][85] ([fdo#104873]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-glk5/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-glk6/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-skl: [INCOMPLETE][87] ([fdo#109507]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-skl10/igt@kms_flip@flip-vs-suspend-interruptible.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-skl4/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [FAIL][89] ([fdo#103167]) -> [PASS][90] +5 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-cpu:
- {shard-tglb}: [INCOMPLETE][91] ([fdo#111884]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-cpu.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt:
- {shard-tglb}: [FAIL][93] ([fdo#103167]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][95] ([fdo#108145]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][97] ([fdo#109441]) -> [PASS][98] +3 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb6/igt@kms_psr@psr2_primary_mmap_cpu.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@perf_pmu@busy-no-semaphores-vcs1:
- shard-iclb: [SKIP][99] ([fdo#112080]) -> [PASS][100] +11 similar issues
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb8/igt@perf_pmu@busy-no-semaphores-vcs1.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb4/igt@perf_pmu@busy-no-semaphores-vcs1.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [SKIP][101] ([fdo#109276]) -> [PASS][102] +16 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb7/igt@prime_busy@hang-bsd2.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb4/igt@prime_busy@hang-bsd2.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-isolation-bsd2:
- shard-iclb: [SKIP][103] ([fdo#109276]) -> [FAIL][104] ([fdo#111330])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/sha
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftests: Perform some basic cycle counting of MI ops (rev2)
@ 2019-11-01 20:09 ` Patchwork
0 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2019-11-01 20:09 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/selftests: Perform some basic cycle counting of MI ops (rev2)
URL : https://patchwork.freedesktop.org/series/68824/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7231_full -> Patchwork_15090_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15090_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15090_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15090_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@mock_requests:
- shard-glk: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-glk6/igt@i915_selftest@mock_requests.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-glk9/igt@i915_selftest@mock_requests.html
New tests
---------
New tests have been introduced between CI_DRM_7231_full and Patchwork_15090_full:
### New IGT tests (1) ###
* igt@i915_selftest@live_gt_engine_cs:
- Statuses : 7 pass(s)
- Exec time: [0.32, 2.25] s
Known issues
------------
Here are the changes found in Patchwork_15090_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@vcs1-reset:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb2/igt@gem_ctx_isolation@vcs1-reset.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb7/igt@gem_ctx_isolation@vcs1-reset.html
* igt@gem_ctx_switch@vcs1:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#112080]) +7 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb2/igt@gem_ctx_switch@vcs1.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb8/igt@gem_ctx_switch@vcs1.html
* igt@gem_exec_schedule@independent-bsd:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#112146])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb3/igt@gem_exec_schedule@independent-bsd.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb2/igt@gem_exec_schedule@independent-bsd.html
* igt@gem_exec_schedule@independent-bsd2:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +9 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb2/igt@gem_exec_schedule@independent-bsd2.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb8/igt@gem_exec_schedule@independent-bsd2.html
* igt@gem_persistent_relocs@forked-thrashing:
- shard-iclb: [PASS][11] -> [INCOMPLETE][12] ([fdo#107713] / [fdo#109100] / [fdo#112068 ])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb4/igt@gem_persistent_relocs@forked-thrashing.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb3/igt@gem_persistent_relocs@forked-thrashing.html
* igt@gem_softpin@noreloc-s3:
- shard-skl: [PASS][13] -> [INCOMPLETE][14] ([fdo#104108])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-skl10/igt@gem_softpin@noreloc-s3.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-skl2/igt@gem_softpin@noreloc-s3.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-snb: [PASS][15] -> [DMESG-WARN][16] ([fdo#110789] / [fdo#111870])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-snb7/igt@gem_userptr_blits@dmabuf-unsync.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-snb1/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-hsw: [PASS][17] -> [DMESG-WARN][18] ([fdo#111870])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-hsw5/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-hsw8/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
* igt@gem_userptr_blits@sync-unmap:
- shard-snb: [PASS][19] -> [DMESG-WARN][20] ([fdo#111870])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-snb4/igt@gem_userptr_blits@sync-unmap.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-snb6/igt@gem_userptr_blits@sync-unmap.html
* igt@i915_selftest@live_hangcheck:
- shard-iclb: [PASS][21] -> [INCOMPLETE][22] ([fdo#107713] / [fdo#108569])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb7/igt@i915_selftest@live_hangcheck.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb1/igt@i915_selftest@live_hangcheck.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-apl: [PASS][23] -> [DMESG-WARN][24] ([fdo#108566])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-apl2/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-apl6/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-iclb: [PASS][25] -> [INCOMPLETE][26] ([fdo#107713])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: [PASS][27] -> [FAIL][28] ([fdo#105363])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-glk9/igt@kms_flip@flip-vs-expired-vblank.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-glk2/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [PASS][29] -> [DMESG-WARN][30] ([fdo#108566]) +5 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [PASS][31] -> [FAIL][32] ([fdo#103167]) +3 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc:
- shard-skl: [PASS][33] -> [FAIL][34] ([fdo#103167])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-skl8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][35] -> [FAIL][36] ([fdo#108145])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_cursor@pipe-a-viewport-size-64:
- shard-apl: [PASS][37] -> [INCOMPLETE][38] ([fdo#103927])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-apl6/igt@kms_plane_cursor@pipe-a-viewport-size-64.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-apl1/igt@kms_plane_cursor@pipe-a-viewport-size-64.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: [PASS][39] -> [FAIL][40] ([fdo#103166])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb4/igt@kms_plane_lowres@pipe-a-tiling-x.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb4/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-skl: [PASS][41] -> [DMESG-WARN][42] ([fdo#106885])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-skl1/igt@kms_plane_multiple@atomic-pipe-a-tiling-y.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-skl4/igt@kms_plane_multiple@atomic-pipe-a-tiling-y.html
* igt@kms_psr@psr2_basic:
- shard-iclb: [PASS][43] -> [SKIP][44] ([fdo#109441]) +2 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb2/igt@kms_psr@psr2_basic.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb1/igt@kms_psr@psr2_basic.html
* igt@kms_setmode@basic:
- shard-hsw: [PASS][45] -> [FAIL][46] ([fdo#99912])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-hsw1/igt@kms_setmode@basic.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-hsw8/igt@kms_setmode@basic.html
#### Possible fixes ####
* igt@gem_ctx_isolation@vcs1-none:
- shard-iclb: [SKIP][47] ([fdo#109276] / [fdo#112080]) -> [PASS][48] +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb6/igt@gem_ctx_isolation@vcs1-none.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb2/igt@gem_ctx_isolation@vcs1-none.html
* {igt@gem_ctx_persistence@vcs0-mixed-process}:
- shard-skl: [FAIL][49] -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-skl5/igt@gem_ctx_persistence@vcs0-mixed-process.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-skl6/igt@gem_ctx_persistence@vcs0-mixed-process.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [SKIP][51] ([fdo#110841]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb2/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb8/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_ctx_shared@q-smoketest-all:
- {shard-tglb}: [INCOMPLETE][53] ([fdo#111735]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-tglb4/igt@gem_ctx_shared@q-smoketest-all.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-tglb7/igt@gem_ctx_shared@q-smoketest-all.html
* igt@gem_eio@unwedge-stress:
- shard-snb: [FAIL][55] ([fdo#109661]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-snb1/igt@gem_eio@unwedge-stress.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-snb2/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_schedule@preempt-queue-contexts-chain-render:
- {shard-tglb}: [INCOMPLETE][57] ([fdo#111677]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-tglb6/igt@gem_exec_schedule@preempt-queue-contexts-chain-render.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-tglb3/igt@gem_exec_schedule@preempt-queue-contexts-chain-render.html
* igt@gem_exec_schedule@wide-bsd:
- shard-iclb: [SKIP][59] ([fdo#112146]) -> [PASS][60] +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb2/igt@gem_exec_schedule@wide-bsd.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb7/igt@gem_exec_schedule@wide-bsd.html
* igt@gem_softpin@noreloc-s3:
- shard-apl: [DMESG-WARN][61] ([fdo#108566]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-apl6/igt@gem_softpin@noreloc-s3.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-apl4/igt@gem_softpin@noreloc-s3.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
- shard-apl: [INCOMPLETE][63] ([fdo#103927]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-apl3/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-apl7/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-snb: [DMESG-WARN][65] ([fdo#111870]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
- shard-hsw: [DMESG-WARN][67] ([fdo#111870]) -> [PASS][68] +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-hsw1/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* igt@gem_workarounds@suspend-resume:
- {shard-tglb}: [INCOMPLETE][69] ([fdo#111832] / [fdo#111850]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-tglb7/igt@gem_workarounds@suspend-resume.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-tglb8/igt@gem_workarounds@suspend-resume.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [DMESG-WARN][71] ([fdo#108566]) -> [PASS][72] +2 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-kbl4/igt@gem_workarounds@suspend-resume-fd.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-kbl3/igt@gem_workarounds@suspend-resume-fd.html
* igt@i915_pm_rpm@modeset-stress-extra-wait:
- shard-glk: [DMESG-WARN][73] ([fdo#105763] / [fdo#106538]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-glk8/igt@i915_pm_rpm@modeset-stress-extra-wait.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-glk9/igt@i915_pm_rpm@modeset-stress-extra-wait.html
* {igt@i915_selftest@live_gt_timelines}:
- {shard-tglb}: [INCOMPLETE][75] ([fdo#111831]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-tglb6/igt@i915_selftest@live_gt_timelines.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-tglb8/igt@i915_selftest@live_gt_timelines.html
* igt@kms_color@pipe-b-ctm-0-25:
- shard-skl: [DMESG-WARN][77] ([fdo#106107]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-skl6/igt@kms_color@pipe-b-ctm-0-25.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-skl5/igt@kms_color@pipe-b-ctm-0-25.html
* igt@kms_cursor_crc@pipe-a-cursor-128x128-random:
- shard-hsw: [INCOMPLETE][79] ([fdo#103540]) -> [PASS][80] +1 similar issue
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-hsw4/igt@kms_cursor_crc@pipe-a-cursor-128x128-random.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-hsw1/igt@kms_cursor_crc@pipe-a-cursor-128x128-random.html
* igt@kms_cursor_crc@pipe-a-cursor-dpms:
- shard-kbl: [FAIL][81] ([fdo#103232]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-dpms.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-dpms.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-skl: [INCOMPLETE][83] ([fdo#110741]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-skl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-skl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [FAIL][85] ([fdo#104873]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-glk5/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-glk6/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-skl: [INCOMPLETE][87] ([fdo#109507]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-skl10/igt@kms_flip@flip-vs-suspend-interruptible.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-skl4/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [FAIL][89] ([fdo#103167]) -> [PASS][90] +5 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-cpu:
- {shard-tglb}: [INCOMPLETE][91] ([fdo#111884]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-cpu.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt:
- {shard-tglb}: [FAIL][93] ([fdo#103167]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][95] ([fdo#108145]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][97] ([fdo#109441]) -> [PASS][98] +3 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb6/igt@kms_psr@psr2_primary_mmap_cpu.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@perf_pmu@busy-no-semaphores-vcs1:
- shard-iclb: [SKIP][99] ([fdo#112080]) -> [PASS][100] +11 similar issues
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb8/igt@perf_pmu@busy-no-semaphores-vcs1.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb4/igt@perf_pmu@busy-no-semaphores-vcs1.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [SKIP][101] ([fdo#109276]) -> [PASS][102] +16 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/shard-iclb7/igt@prime_busy@hang-bsd2.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/shard-iclb4/igt@prime_busy@hang-bsd2.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-isolation-bsd2:
- shard-iclb: [SKIP][103] ([fdo#109276]) -> [FAIL][104] ([fdo#111330])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/sha
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/index.html
_______________________________________________
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^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2019-11-01 20:09 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-10-31 14:03 [PATCH] drm/i915/selftests: Perform some basic cycle counting of MI ops Chris Wilson
2019-10-31 14:03 ` [Intel-gfx] " Chris Wilson
2019-10-31 14:44 ` [PATCH v2] " Chris Wilson
2019-10-31 14:44 ` [Intel-gfx] " Chris Wilson
2019-10-31 16:57 ` ✓ Fi.CI.BAT: success for drm/i915/selftests: Perform some basic cycle counting of MI ops (rev2) Patchwork
2019-10-31 16:57 ` [Intel-gfx] " Patchwork
2019-11-01 20:09 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-11-01 20:09 ` [Intel-gfx] " Patchwork
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