[PATCH v2 0/5] MSM8976/56 Sony Xperia Loire (X/XCompact) smartphones

[PATCH v2 0/5] MSM8976/56 Sony Xperia Loire (X/XCompact) smartphones

[kholk11]

From: AngeloGioacchino Del Regno <kholk11@gmail.com>

Here it all comes together.

This patch series enables support for MSM8976 and MSM8956 with all
the extra functionality that has been tested and sent upstream and
also adds support for the Sony Xperia Loire platform, including two
devices in the Loire project: the Xperia X (Suzu) and the Xperia
X Compact (Kugo).

That's only a subset of what I actually have in my hat.. I didn't
feel like sending the entire thing because the rest is not perfectly
clean yet (even if working, and we all know that "works != clean").

As for my entire local stuff, here I can successfully boot Android 10
with nice display and 3d on both smartphones.

So, this is composed of:
- A main device-tree for the MSM8976/56 SoC (*)
- Standard configuration for the PM/PMI8950 and PM8004, which are
  found on all (from what I know) MSM8976 and 8956 boards, since
  that seems to be the recommended hardware configuration from qcom
- A main device-tree for the Sony Xperia Loire project (**)
- Device specific device-trees for Loire Kugo and Loire Suzu. (***)

(*) The MSM8956 SoC is a "broken" MSM8976. It has got two *disabled*
    BIG cores and you can't preventively know which ones are enabled
    and which ones are not: there you only know that you've got two.
    So, you can get any combination of disabled cores (relative to
    cluster 1, it can be 0,1 or 1,2 or 2,3 or 0,3 or 1,3.. etc) on
    the chip that you own.
    After many trials on (various) downstream kernels and a number of
    devices, I have concluded that the only way to get both the enabled
    big cores up is to actually declare all four and let Linux error
    out on the disabled cores (and - of course - never use them), mostly
    because there doesn't seem to be any register that can be read for
    that purpose... may sound stupid, but ... eh :)

(**) The Sony Xperia Loire platform is composed of 3 devices with their
     specific region variants, specifically, two MSM8956 smartphones
     (Suzu, Kugo) and one APQ8056 smart projector (Blanc). All these
     devices reuse the same base board design, so I thought that it is
     just better to create a common DT for all of them, hence avoiding
     a whole lot of code duplication.
     P.S.: I don't know if I'll ever try to upstream the SmartLoire
           APQ8056 Xperia Touch projector. I hope to have time to do
           it as it's a great device and I really want to but, as of
           now, I can't make any promise about that specific device.

(***) These DTs are now very light, but they will contain some
      more nodes as I get more components upstreamed. For example, the
      X Compact (Kugo) smartphone has Type-C through the FUSB301 chip,
      which resides on i2c, a RGBC-IR sensor and a VL53L0 ToF, while X
      (Suzu) has just MicroUSB and none of these sensors.
      These devices also are of a different form factor, so they've got
      different displays but connected to the same power rails anyway.


Changes in v2 (all changes requested by Bjorn):
- Reordered DT nodes by address and padded them to 8 digits
- Dropped useless inner subnodes for pinctrl configurations
- Removed the forgotten useless "qcom,init-voltage" property
- Moved BLSP2 UART2 node to main DT, declared as disabled
- Refactored SDC related pinctrl nodes as suggested
- Deleted msm8976-pins DT, moved stripped-to-the-bone pinctrl
  in msm8976.dtsi, plus remaining board-specific nodes in the
  loire board dtsi
- Removed the split mux/config in pinctrl nodes
- Added explicit "qcom,scm-msm8976" to the scm node
- Removed PM8950 regulators configuration skeleton from msm8976.dtsi
  and moved the entire thing to board specific files (in this
  case, msm8956-sony-xperia-loire.dtsi)
- Moved non-mmio nodes from /soc to /
- Removed the remoteproc/hexagon configuration completely, as it
  was just a forgotten node from various tests that I did on the
  platform (sorry guys -- plan is now to enable modem and hexagon
  in a future patch series)
- Fixed trailing whitespace issues in xperia-loire DT.

AngeloGioacchino Del Regno (5):
  dt-bindings: iio: spmi-vadc: Add definitions for USB DP/DM VADCs
  arm64: dts: pm8004: Add SPMI regulator and add phandles to lsids
  arm64: dts: qcom: Add configuration for PM8950 and PMI8950 peripherals
  arm64: dts: qcom: Add MSM8976 SoC support dts files
  arm64: dts: qcom: Add Sony Xperia (Loire) X and X Compact support

 arch/arm64/boot/dts/qcom/Makefile             |    2 +
 .../qcom/msm8956-sony-xperia-loire-kugo.dts   |   56 +
 .../qcom/msm8956-sony-xperia-loire-suzu.dts   |   17 +
 .../dts/qcom/msm8956-sony-xperia-loire.dtsi   |  744 +++++++
 arch/arm64/boot/dts/qcom/msm8976.dtsi         | 1705 +++++++++++++++++
 arch/arm64/boot/dts/qcom/pm8004.dtsi          |   10 +-
 arch/arm64/boot/dts/qcom/pm8950.dtsi          |  187 ++
 arch/arm64/boot/dts/qcom/pmi8950.dtsi         |   98 +
 include/dt-bindings/iio/qcom,spmi-vadc.h      |    3 +
 9 files changed, 2820 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-kugo.dts
 create mode 100644 arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-suzu.dts
 create mode 100644 arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/msm8976.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/pm8950.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/pmi8950.dtsi

-- 
2.21.0

[PATCH v2 1/5] dt-bindings: iio: spmi-vadc: Add definitions for USB DP/DM VADCs

[kholk11]

From: AngeloGioacchino Del Regno <kholk11@gmail.com>

Some PMICs, like PMI8950, feature two ADCs, at 0x43 and 0x44,
respectively used for USB D+ and USB D- (DP/DM): add the definition
for them as VADC_USB_DP and VADC_USB_DM.

Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
---
 include/dt-bindings/iio/qcom,spmi-vadc.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/dt-bindings/iio/qcom,spmi-vadc.h b/include/dt-bindings/iio/qcom,spmi-vadc.h
index 61d556db1542..c4c3914d831c 100644
--- a/include/dt-bindings/iio/qcom,spmi-vadc.h
+++ b/include/dt-bindings/iio/qcom,spmi-vadc.h
@@ -72,6 +72,9 @@
 #define VADC_AMUX_PU2				0x3b
 #define VADC_LR_MUX3_BUF_XO_THERM		0x3c
 
+#define VADC_USB_DP				0x43
+#define VADC_USB_DM				0x44
+
 #define VADC_LR_MUX1_PU1_BAT_THERM		0x70
 #define VADC_LR_MUX2_PU1_BAT_ID			0x71
 #define VADC_LR_MUX3_PU1_XO_THERM		0x72
-- 
2.21.0

Re: [PATCH v2 1/5] dt-bindings: iio: spmi-vadc: Add definitions for USB DP/DM VADCs

[Rob Herring]

On Thu, 31 Oct 2019 12:16:41 +0100, kholk11@gmail.com wrote:
> From: AngeloGioacchino Del Regno <kholk11@gmail.com>
> 
> Some PMICs, like PMI8950, feature two ADCs, at 0x43 and 0x44,
> respectively used for USB D+ and USB D- (DP/DM): add the definition
> for them as VADC_USB_DP and VADC_USB_DM.
> 
> Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
> ---
>  include/dt-bindings/iio/qcom,spmi-vadc.h | 3 +++
>  1 file changed, 3 insertions(+)
> 

Please add Acked-by/Reviewed-by tags when posting new versions. However,
there's no need to repost patches *only* to add the tags. The upstream
maintainer will do that for acks received on the version they apply.

If a tag was not added on purpose, please state why and what changed.

Re: [PATCH v2 1/5] dt-bindings: iio: spmi-vadc: Add definitions for USB DP/DM VADCs

[AngeloGioacchino Del Regno]

Il giorno mar 5 nov 2019 alle ore 19:42 Rob Herring <robh@kernel.org>
ha scritto:
>
> On Thu, 31 Oct 2019 12:16:41 +0100, kholk11@gmail.com wrote:
> > From: AngeloGioacchino Del Regno <kholk11@gmail.com>
> >
> > Some PMICs, like PMI8950, feature two ADCs, at 0x43 and 0x44,
> > respectively used for USB D+ and USB D- (DP/DM): add the definition
> > for them as VADC_USB_DP and VADC_USB_DM.
> >
> > Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
> > ---
> >  include/dt-bindings/iio/qcom,spmi-vadc.h | 3 +++
> >  1 file changed, 3 insertions(+)
> >
>
> Please add Acked-by/Reviewed-by tags when posting new versions. However,
> there's no need to repost patches *only* to add the tags. The upstream
> maintainer will do that for acks received on the version they apply.
>
> If a tag was not added on purpose, please state why and what changed.

I'm sorry, that wasn't intentional. Nothing changed in this patch.

[PATCH v2 2/5] arm64: dts: pm8004: Add SPMI regulator and add phandles to lsids

[kholk11]

From: AngeloGioacchino Del Regno <kholk11@gmail.com>

Add the SPMI regulator node in the PM8004 LSID5 (as there is where
it resides basically 99% of the times) and set the nodes to be
disabled by default, as not all boards have both or one of the
lsids specified in this generic pm8004 DT.

While at it, also add nice phandles to the lsids specified in this
DT to allow configuration in specific board dts in a more human
readable fashion.

Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
---
 arch/arm64/boot/dts/qcom/pm8004.dtsi | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/pm8004.dtsi b/arch/arm64/boot/dts/qcom/pm8004.dtsi
index 297b57bfa87a..0abd1abe12fc 100644
--- a/arch/arm64/boot/dts/qcom/pm8004.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8004.dtsi
@@ -4,17 +4,23 @@
 
 &spmi_bus {
 
-	pmic@4 {
+	pm8004_lsid4: pmic@4 {
 		compatible = "qcom,pm8004", "qcom,spmi-pmic";
 		reg = <0x4 SPMI_USID>;
 		#address-cells = <1>;
 		#size-cells = <0>;
+		status = "disabled";
 	};
 
-	pmic@5 {
+	pm8004_lsid5: pmic@5 {
 		compatible = "qcom,pm8004", "qcom,spmi-pmic";
 		reg = <0x5 SPMI_USID>;
 		#address-cells = <1>;
 		#size-cells = <0>;
+		status = "disabled";
+
+		pm8004_spmi_regulators: regulators {
+			compatible = "qcom,pm8004-regulators";
+		};
 	};
 };
-- 
2.21.0

[PATCH v2 3/5] arm64: dts: qcom: Add configuration for PM8950 and PMI8950 peripherals

[kholk11]

From: AngeloGioacchino Del Regno <kholk11@gmail.com>

The PM(I)8950 feature integrated peripherals like ADC, GPIO
controller, MPPs, PON keys and others.
Add them to DT files that will be imported on boards having
this PMIC combo (or one of them, anyways).

Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
---
 arch/arm64/boot/dts/qcom/pm8950.dtsi  | 187 ++++++++++++++++++++++++++
 arch/arm64/boot/dts/qcom/pmi8950.dtsi |  98 ++++++++++++++
 2 files changed, 285 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/pm8950.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/pmi8950.dtsi

diff --git a/arch/arm64/boot/dts/qcom/pm8950.dtsi b/arch/arm64/boot/dts/qcom/pm8950.dtsi
new file mode 100644
index 000000000000..a349a8dd867e
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pm8950.dtsi
@@ -0,0 +1,187 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2019, AngeloGioacchino Del Regno <kholk11@gmail.com>
+
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+	pm8950_lsid0: pm8950@0 {
+		compatible = "qcom,pm8950", "qcom,spmi-pmic";
+		reg = <0x0 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pon@800 {
+			compatible = "qcom,pm8916-pon";
+			reg = <0x0800>;
+			mode-bootloader = <0x2>;
+			mode-recovery = <0x1>;
+
+			pwrkey {
+				compatible = "qcom,pm8941-pwrkey";
+				interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
+				debounce = <15625>;
+				bias-pull-up;
+				linux,code = <KEY_POWER>;
+			};
+		};
+
+		pm8950_mpps: mpps@a000 {
+			compatible = "qcom,pm8950-mpp", "qcom,spmi-mpp";
+			reg = <0xa000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupts = <0 0xa0 0 IRQ_TYPE_NONE>,
+				     <0 0xa1 0 IRQ_TYPE_NONE>,
+				     <0 0xa2 0 IRQ_TYPE_NONE>,
+				     <0 0xa3 0 IRQ_TYPE_NONE>;
+
+			/* MPP_2: PA_THERM1 */
+			pa_therm {
+				pm8950_mpp2_def: pa_therm1_default {
+					pins = "mpp2";
+					function = "analog";
+					input-enable;
+					qcom,amux-route =
+						<PMIC_MPP_AMUX_ROUTE_CH6>;
+				};
+			};
+
+			/* MPP_4: QUIET_THERM */
+			case_therm {
+				pm8950_mpp4_def: case_therm_default {
+					pins = "mpp4";
+					function = "analog";
+					input-enable;
+					qcom,amux-route =
+						<PMIC_MPP_AMUX_ROUTE_CH8>;
+				};
+			};
+		};
+
+		pm8950_gpios: gpio@c000 {
+			compatible = "qcom,pm8950-gpio", "qcom,spmi-gpio";
+			reg = <0xc000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupts = <0 0xc0 0 IRQ_TYPE_NONE>,
+				<0 0xc1 0 IRQ_TYPE_NONE>,
+				<0 0xc3 0 IRQ_TYPE_NONE>,
+				<0 0xc4 0 IRQ_TYPE_NONE>,
+				<0 0xc5 0 IRQ_TYPE_NONE>,
+				<0 0xc6 0 IRQ_TYPE_NONE>,
+				<0 0xc7 0 IRQ_TYPE_NONE>;
+		};
+
+		pm8950_temp: temp-alarm@2400 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0x2400>;
+			interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>;
+			io-channels = <&pm8950_adc VADC_DIE_TEMP>;
+			io-channel-names = "thermal";
+			#thermal-sensor-cells = <0>;
+		};
+
+		pm8950_adc: adc@3100 {
+			compatible = "qcom,spmi-vadc";
+			reg = <0x3100>;
+			interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#io-channel-cells = <1>;
+
+			vcoin {
+				label = "vcoin";
+				reg = <VADC_VCOIN>;
+				qcom,pre-scaling = <1 1>;
+			};
+			vph_pwr {
+				label = "vph_pwr";
+				reg = <VADC_VSYS>;
+				qcom,pre-scaling = <1 1>;
+			};
+			die_temp {
+				label = "die_temp";
+				reg = <VADC_DIE_TEMP>;
+				qcom,pre-scaling = <1 1>;
+			};
+			ref_625mv {
+				label = "ref_625mv";
+				reg = <VADC_REF_625MV>;
+				qcom,pre-scaling = <1 1>;
+			};
+			ref_1250v {
+				label = "ref_1250v";
+				reg = <VADC_REF_1250MV>;
+				qcom,pre-scaling = <1 1>;
+			};
+			ref_buf_625mv {
+				label = "ref_buf_625mv";
+				reg = <VADC_SPARE1>;
+				qcom,pre-scaling = <1 1>;
+			};
+			ref_gnd {
+				reg = <VADC_GND_REF>;
+			};
+			ref_vdd {
+				reg = <VADC_VDD_VADC>;
+			};
+			pa_therm0 {
+				label = "pa_therm0";
+				reg = <VADC_LR_MUX7_HW_ID>;
+				qcom,pre-scaling = <1 1>;
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+			};
+			pa_therm1 {
+				label = "pa_therm1";
+				reg = <VADC_P_MUX2_1_1>;
+				qcom,pre-scaling = <1 1>;
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+			};
+			xo_therm {
+				label = "xo_therm";
+				reg = <VADC_LR_MUX3_XO_THERM>;
+				qcom,pre-scaling = <1 1>;
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+			};
+			xo_therm_buf {
+				label = "xo_therm_buf";
+				reg = <VADC_LR_MUX3_BUF_XO_THERM>;
+				qcom,pre-scaling = <1 1>;
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+			};
+			case_therm {
+				label = "case_therm";
+				reg = <VADC_P_MUX4_1_1>;
+				qcom,pre-scaling = <1 1>;
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+			};
+		};
+
+		rtc@6000 {
+			compatible = "qcom,pm8941-rtc";
+			reg = <0x6000>;
+			reg-names = "rtc", "alarm";
+			interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
+		};
+	};
+
+	pm8950_lsid1: pm8950@1 {
+		compatible = "qcom,pm8950", "qcom,spmi-pmic";
+		reg = <0x1 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm8950_spmi_regulators: regulators {
+			compatible = "qcom,pm8950-regulators";
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/qcom/pmi8950.dtsi b/arch/arm64/boot/dts/qcom/pmi8950.dtsi
new file mode 100644
index 000000000000..73afdfca27c1
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pmi8950.dtsi
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2019, AngeloGioacchino Del Regno <kholk11@gmail.com>
+
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+	pmi8950_lsid0: pmic@2 {
+		compatible = "qcom,pmi8950", "qcom,spmi-pmic";
+		reg = <0x2 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pmi8950_mpp: mpps@a000 {
+			compatible = "qcom,pmi8950-mpp", "qcom,spmi-mpp";
+			reg = <0xa000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupts = <0x2 0xa0 0 IRQ_TYPE_NONE>,
+				<0x2 0xa1 0 IRQ_TYPE_NONE>,
+				<0x2 0xa2 0 IRQ_TYPE_NONE>,
+				<0x2 0xa3 0 IRQ_TYPE_NONE>;
+		};
+
+		pmi8950_gpio: gpios@c000 {
+			compatible = "qcom,pmi8950-gpio", "qcom,spmi-gpio";
+			reg = <0xc000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupts = <0 0xc0 0 IRQ_TYPE_NONE>,
+				<0 0xc1 0 IRQ_TYPE_NONE>;
+		};
+
+		pmi8950_adc: adc@3100 {
+			compatible = "qcom,spmi-vadc";
+			reg = <0x3100>;
+			interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#io-channel-cells = <1>;
+
+			usbin {
+				label = "usbin";
+				reg = <VADC_USBIN>;
+				qcom,pre-scaling = <1 4>;
+			};
+			dcin {
+				label = "dcin";
+				reg = <VADC_DCIN>;
+				qcom,pre-scaling = <1 4>;
+			};
+			vchg_sns {
+				label = "vchg_sns";
+				reg = <VADC_VCHG_SNS>;
+				qcom,pre-scaling = <1 1>;
+			};
+			ref_625mv {
+				label = "ref_625mv";
+				reg = <VADC_REF_625MV>;
+				qcom,pre-scaling = <1 1>;
+			};
+			ref_1250v {
+				label = "ref_1250v";
+				reg = <VADC_REF_1250MV>;
+				qcom,pre-scaling = <1 1>;
+			};
+			ref_gnd {
+				reg = <VADC_GND_REF>;
+			};
+			ref_vdd {
+				reg = <VADC_VDD_VADC>;
+			};
+			chg_temp {
+				label = "chg_temp";
+				reg = <VADC_SPARE2>;
+				qcom,pre-scaling = <1 1>;
+			};
+			usb_dp {
+				label = "usb_dp";
+				reg = <VADC_USB_DP>;
+				qcom,pre-scaling = <1 1>;
+			};
+			usb_dm {
+				label = "usb_dm";
+				reg = <VADC_USB_DM>;
+				qcom,pre-scaling = <1 1>;
+			};
+		};
+	};
+
+	pmi8950_lsid1: pmic@3 {
+		compatible = "qcom,pmi8950", "qcom,spmi-pmic";
+		reg = <0x3 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+};
-- 
2.21.0

Re: [PATCH v2 3/5] arm64: dts: qcom: Add configuration for PM8950 and PMI8950 peripherals

[Brian Masney]

Thanks for the patches. Good to see the progress!

On Thu, Oct 31, 2019 at 12:16:43PM +0100, kholk11@gmail.com wrote:
> From: AngeloGioacchino Del Regno <kholk11@gmail.com>
> 
> The PM(I)8950 feature integrated peripherals like ADC, GPIO
> controller, MPPs, PON keys and others.
> Add them to DT files that will be imported on boards having
> this PMIC combo (or one of them, anyways).
> 
> Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
> ---
>  arch/arm64/boot/dts/qcom/pm8950.dtsi  | 187 ++++++++++++++++++++++++++
>  arch/arm64/boot/dts/qcom/pmi8950.dtsi |  98 ++++++++++++++
>  2 files changed, 285 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/qcom/pm8950.dtsi
>  create mode 100644 arch/arm64/boot/dts/qcom/pmi8950.dtsi
> 
> diff --git a/arch/arm64/boot/dts/qcom/pm8950.dtsi b/arch/arm64/boot/dts/qcom/pm8950.dtsi
> new file mode 100644
> index 000000000000..a349a8dd867e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/pm8950.dtsi
> @@ -0,0 +1,187 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2019, AngeloGioacchino Del Regno <kholk11@gmail.com>
> +
> +#include <dt-bindings/iio/qcom,spmi-vadc.h>
> +#include <dt-bindings/input/linux-event-codes.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
> +#include <dt-bindings/spmi/spmi.h>
> +
> +&spmi_bus {
> +	pm8950_lsid0: pm8950@0 {
> +		compatible = "qcom,pm8950", "qcom,spmi-pmic";
> +		reg = <0x0 SPMI_USID>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		pon@800 {
> +			compatible = "qcom,pm8916-pon";
> +			reg = <0x0800>;
> +			mode-bootloader = <0x2>;
> +			mode-recovery = <0x1>;
> +
> +			pwrkey {
> +				compatible = "qcom,pm8941-pwrkey";
> +				interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
> +				debounce = <15625>;
> +				bias-pull-up;
> +				linux,code = <KEY_POWER>;
> +			};
> +		};
> +
> +		pm8950_mpps: mpps@a000 {
> +			compatible = "qcom,pm8950-mpp", "qcom,spmi-mpp";
> +			reg = <0xa000>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupts = <0 0xa0 0 IRQ_TYPE_NONE>,
> +				     <0 0xa1 0 IRQ_TYPE_NONE>,
> +				     <0 0xa2 0 IRQ_TYPE_NONE>,
> +				     <0 0xa3 0 IRQ_TYPE_NONE>;
> +
> +			/* MPP_2: PA_THERM1 */
> +			pa_therm {
> +				pm8950_mpp2_def: pa_therm1_default {
> +					pins = "mpp2";
> +					function = "analog";
> +					input-enable;
> +					qcom,amux-route =
> +						<PMIC_MPP_AMUX_ROUTE_CH6>;
> +				};
> +			};
> +
> +			/* MPP_4: QUIET_THERM */
> +			case_therm {
> +				pm8950_mpp4_def: case_therm_default {
> +					pins = "mpp4";
> +					function = "analog";
> +					input-enable;
> +					qcom,amux-route =
> +						<PMIC_MPP_AMUX_ROUTE_CH8>;
> +				};
> +			};
> +		};
> +
> +		pm8950_gpios: gpio@c000 {
> +			compatible = "qcom,pm8950-gpio", "qcom,spmi-gpio";
> +			reg = <0xc000>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupts = <0 0xc0 0 IRQ_TYPE_NONE>,
> +				<0 0xc1 0 IRQ_TYPE_NONE>,
> +				<0 0xc3 0 IRQ_TYPE_NONE>,
> +				<0 0xc4 0 IRQ_TYPE_NONE>,
> +				<0 0xc5 0 IRQ_TYPE_NONE>,
> +				<0 0xc6 0 IRQ_TYPE_NONE>,
> +				<0 0xc7 0 IRQ_TYPE_NONE>;
> +		};

Please add gpio-ranges so that gpio-hogging will work properly. See
commits for pm8941 and spmi-gpio that describes the problem and how
to fix it:

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=149a96047237574b756d872007c006acd0cc6687
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=cdd3d64d843a2a4c658a182b744bfefbd021d542

Please drop the interrupts property and configure this to be a
hierarchical IRQ chip. See these two commits for more details:

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=ca69e2d165eb3d060cc9ad70a745e27a2cf4310b
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=5f540fb4821a5444350ab3311fff60013d755d8f

There is some kind of mask that you'll need to add to omit 0xc2 that
Linus Walleij told me about before. I don't have the property handy
right now, but can look it up later if needed.

Brian

Re: [PATCH v2 3/5] arm64: dts: qcom: Add configuration for PM8950 and PMI8950 peripherals

[AngeloGioacchino Del Regno]

Il giorno gio 31 ott 2019 alle ore 20:58 Brian Masney
<masneyb@onstation.org> ha scritto:
>
> Thanks for the patches. Good to see the progress!
>
> On Thu, Oct 31, 2019 at 12:16:43PM +0100, kholk11@gmail.com wrote:
> > From: AngeloGioacchino Del Regno <kholk11@gmail.com>
> >
> > The PM(I)8950 feature integrated peripherals like ADC, GPIO
> > controller, MPPs, PON keys and others.
> > Add them to DT files that will be imported on boards having
> > this PMIC combo (or one of them, anyways).
> >
> > Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
> > ---
> >  arch/arm64/boot/dts/qcom/pm8950.dtsi  | 187 ++++++++++++++++++++++++++
> >  arch/arm64/boot/dts/qcom/pmi8950.dtsi |  98 ++++++++++++++
> >  2 files changed, 285 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/qcom/pm8950.dtsi
> >  create mode 100644 arch/arm64/boot/dts/qcom/pmi8950.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/qcom/pm8950.dtsi b/arch/arm64/boot/dts/qcom/pm8950.dtsi
> > new file mode 100644
> > index 000000000000..a349a8dd867e
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/qcom/pm8950.dtsi
> > @@ -0,0 +1,187 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +// Copyright (c) 2019, AngeloGioacchino Del Regno <kholk11@gmail.com>
> > +
> > +#include <dt-bindings/iio/qcom,spmi-vadc.h>
> > +#include <dt-bindings/input/linux-event-codes.h>
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
> > +#include <dt-bindings/spmi/spmi.h>
> > +
> > +&spmi_bus {
> > +     pm8950_lsid0: pm8950@0 {
> > +             compatible = "qcom,pm8950", "qcom,spmi-pmic";
> > +             reg = <0x0 SPMI_USID>;
> > +             #address-cells = <1>;
> > +             #size-cells = <0>;
> > +
> > +             pon@800 {
> > +                     compatible = "qcom,pm8916-pon";
> > +                     reg = <0x0800>;
> > +                     mode-bootloader = <0x2>;
> > +                     mode-recovery = <0x1>;
> > +
> > +                     pwrkey {
> > +                             compatible = "qcom,pm8941-pwrkey";
> > +                             interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
> > +                             debounce = <15625>;
> > +                             bias-pull-up;
> > +                             linux,code = <KEY_POWER>;
> > +                     };
> > +             };
> > +
> > +             pm8950_mpps: mpps@a000 {
> > +                     compatible = "qcom,pm8950-mpp", "qcom,spmi-mpp";
> > +                     reg = <0xa000>;
> > +                     gpio-controller;
> > +                     #gpio-cells = <2>;
> > +                     interrupts = <0 0xa0 0 IRQ_TYPE_NONE>,
> > +                                  <0 0xa1 0 IRQ_TYPE_NONE>,
> > +                                  <0 0xa2 0 IRQ_TYPE_NONE>,
> > +                                  <0 0xa3 0 IRQ_TYPE_NONE>;
> > +
> > +                     /* MPP_2: PA_THERM1 */
> > +                     pa_therm {
> > +                             pm8950_mpp2_def: pa_therm1_default {
> > +                                     pins = "mpp2";
> > +                                     function = "analog";
> > +                                     input-enable;
> > +                                     qcom,amux-route =
> > +                                             <PMIC_MPP_AMUX_ROUTE_CH6>;
> > +                             };
> > +                     };
> > +
> > +                     /* MPP_4: QUIET_THERM */
> > +                     case_therm {
> > +                             pm8950_mpp4_def: case_therm_default {
> > +                                     pins = "mpp4";
> > +                                     function = "analog";
> > +                                     input-enable;
> > +                                     qcom,amux-route =
> > +                                             <PMIC_MPP_AMUX_ROUTE_CH8>;
> > +                             };
> > +                     };
> > +             };
> > +
> > +             pm8950_gpios: gpio@c000 {
> > +                     compatible = "qcom,pm8950-gpio", "qcom,spmi-gpio";
> > +                     reg = <0xc000>;
> > +                     gpio-controller;
> > +                     #gpio-cells = <2>;
> > +                     interrupts = <0 0xc0 0 IRQ_TYPE_NONE>,
> > +                             <0 0xc1 0 IRQ_TYPE_NONE>,
> > +                             <0 0xc3 0 IRQ_TYPE_NONE>,
> > +                             <0 0xc4 0 IRQ_TYPE_NONE>,
> > +                             <0 0xc5 0 IRQ_TYPE_NONE>,
> > +                             <0 0xc6 0 IRQ_TYPE_NONE>,
> > +                             <0 0xc7 0 IRQ_TYPE_NONE>;
> > +             };
>
> Please add gpio-ranges so that gpio-hogging will work properly. See
> commits for pm8941 and spmi-gpio that describes the problem and how
> to fix it:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=149a96047237574b756d872007c006acd0cc6687
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=cdd3d64d843a2a4c658a182b744bfefbd021d542
>
> Please drop the interrupts property and configure this to be a
> hierarchical IRQ chip. See these two commits for more details:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=ca69e2d165eb3d060cc9ad70a745e27a2cf4310b
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=5f540fb4821a5444350ab3311fff60013d755d8f
>
> There is some kind of mask that you'll need to add to omit 0xc2 that
> Linus Walleij told me about before. I don't have the property handy
> right now, but can look it up later if needed.
>
> Brian

That looks cleaner! Didn't know about it... Anyway, the only way that I know
to exclude the 0xc2 is something like

gpio-ranges = <&pm8950_gpios 0 0 8>;
gpio-reserved-ranges = <2 1>;

...but you're talking about a mask? Is there a different way of doing it, or
were you referring to the gpio-reserved-ranges property?

Angelo

Re: [PATCH v2 3/5] arm64: dts: qcom: Add configuration for PM8950 and PMI8950 peripherals

[Brian Masney]

On Tue, Nov 05, 2019 at 12:18:45PM +0100, AngeloGioacchino Del Regno wrote:
> Il giorno gio 31 ott 2019 alle ore 20:58 Brian Masney
> <masneyb@onstation.org> ha scritto:
> >
> > Thanks for the patches. Good to see the progress!
> >
> > On Thu, Oct 31, 2019 at 12:16:43PM +0100, kholk11@gmail.com wrote:
> > > From: AngeloGioacchino Del Regno <kholk11@gmail.com>
> > >
> > > The PM(I)8950 feature integrated peripherals like ADC, GPIO
> > > controller, MPPs, PON keys and others.
> > > Add them to DT files that will be imported on boards having
> > > this PMIC combo (or one of them, anyways).
> > >
> > > Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
> > > ---
> > >  arch/arm64/boot/dts/qcom/pm8950.dtsi  | 187 ++++++++++++++++++++++++++
> > >  arch/arm64/boot/dts/qcom/pmi8950.dtsi |  98 ++++++++++++++
> > >  2 files changed, 285 insertions(+)
> > >  create mode 100644 arch/arm64/boot/dts/qcom/pm8950.dtsi
> > >  create mode 100644 arch/arm64/boot/dts/qcom/pmi8950.dtsi
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/pm8950.dtsi b/arch/arm64/boot/dts/qcom/pm8950.dtsi
> > > new file mode 100644
> > > index 000000000000..a349a8dd867e
> > > --- /dev/null
> > > +++ b/arch/arm64/boot/dts/qcom/pm8950.dtsi
> > > @@ -0,0 +1,187 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +// Copyright (c) 2019, AngeloGioacchino Del Regno <kholk11@gmail.com>
> > > +
> > > +#include <dt-bindings/iio/qcom,spmi-vadc.h>
> > > +#include <dt-bindings/input/linux-event-codes.h>
> > > +#include <dt-bindings/interrupt-controller/irq.h>
> > > +#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
> > > +#include <dt-bindings/spmi/spmi.h>
> > > +
> > > +&spmi_bus {
> > > +     pm8950_lsid0: pm8950@0 {
> > > +             compatible = "qcom,pm8950", "qcom,spmi-pmic";
> > > +             reg = <0x0 SPMI_USID>;
> > > +             #address-cells = <1>;
> > > +             #size-cells = <0>;
> > > +
> > > +             pon@800 {
> > > +                     compatible = "qcom,pm8916-pon";
> > > +                     reg = <0x0800>;
> > > +                     mode-bootloader = <0x2>;
> > > +                     mode-recovery = <0x1>;
> > > +
> > > +                     pwrkey {
> > > +                             compatible = "qcom,pm8941-pwrkey";
> > > +                             interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
> > > +                             debounce = <15625>;
> > > +                             bias-pull-up;
> > > +                             linux,code = <KEY_POWER>;
> > > +                     };
> > > +             };
> > > +
> > > +             pm8950_mpps: mpps@a000 {
> > > +                     compatible = "qcom,pm8950-mpp", "qcom,spmi-mpp";
> > > +                     reg = <0xa000>;
> > > +                     gpio-controller;
> > > +                     #gpio-cells = <2>;
> > > +                     interrupts = <0 0xa0 0 IRQ_TYPE_NONE>,
> > > +                                  <0 0xa1 0 IRQ_TYPE_NONE>,
> > > +                                  <0 0xa2 0 IRQ_TYPE_NONE>,
> > > +                                  <0 0xa3 0 IRQ_TYPE_NONE>;
> > > +
> > > +                     /* MPP_2: PA_THERM1 */
> > > +                     pa_therm {
> > > +                             pm8950_mpp2_def: pa_therm1_default {
> > > +                                     pins = "mpp2";
> > > +                                     function = "analog";
> > > +                                     input-enable;
> > > +                                     qcom,amux-route =
> > > +                                             <PMIC_MPP_AMUX_ROUTE_CH6>;
> > > +                             };
> > > +                     };
> > > +
> > > +                     /* MPP_4: QUIET_THERM */
> > > +                     case_therm {
> > > +                             pm8950_mpp4_def: case_therm_default {
> > > +                                     pins = "mpp4";
> > > +                                     function = "analog";
> > > +                                     input-enable;
> > > +                                     qcom,amux-route =
> > > +                                             <PMIC_MPP_AMUX_ROUTE_CH8>;
> > > +                             };
> > > +                     };
> > > +             };
> > > +
> > > +             pm8950_gpios: gpio@c000 {
> > > +                     compatible = "qcom,pm8950-gpio", "qcom,spmi-gpio";
> > > +                     reg = <0xc000>;
> > > +                     gpio-controller;
> > > +                     #gpio-cells = <2>;
> > > +                     interrupts = <0 0xc0 0 IRQ_TYPE_NONE>,
> > > +                             <0 0xc1 0 IRQ_TYPE_NONE>,
> > > +                             <0 0xc3 0 IRQ_TYPE_NONE>,
> > > +                             <0 0xc4 0 IRQ_TYPE_NONE>,
> > > +                             <0 0xc5 0 IRQ_TYPE_NONE>,
> > > +                             <0 0xc6 0 IRQ_TYPE_NONE>,
> > > +                             <0 0xc7 0 IRQ_TYPE_NONE>;
> > > +             };
> >
> > Please add gpio-ranges so that gpio-hogging will work properly. See
> > commits for pm8941 and spmi-gpio that describes the problem and how
> > to fix it:
> >
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=149a96047237574b756d872007c006acd0cc6687
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=cdd3d64d843a2a4c658a182b744bfefbd021d542
> >
> > Please drop the interrupts property and configure this to be a
> > hierarchical IRQ chip. See these two commits for more details:
> >
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=ca69e2d165eb3d060cc9ad70a745e27a2cf4310b
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=5f540fb4821a5444350ab3311fff60013d755d8f
> >
> > There is some kind of mask that you'll need to add to omit 0xc2 that
> > Linus Walleij told me about before. I don't have the property handy
> > right now, but can look it up later if needed.
> >
> > Brian
> 
> That looks cleaner! Didn't know about it... Anyway, the only way that I know
> to exclude the 0xc2 is something like
> 
> gpio-ranges = <&pm8950_gpios 0 0 8>;
> gpio-reserved-ranges = <2 1>;
> 
> ...but you're talking about a mask? Is there a different way of doing it, or
> were you referring to the gpio-reserved-ranges property?

Yes, it looks like gpio-reserved-ranges property is what you need.

Brian

[PATCH v2 4/5] arm64: dts: qcom: Add MSM8976 SoC support dts files

[kholk11]

From: AngeloGioacchino Del Regno <kholk11@gmail.com>

These are the DTs to support the MSM8976 SoC and, with very small
overrides in future ones, also MSM8956 and their APQ variants.

This configuration includes firmware, cpu, psci, idle states,
clocks, smem, rpm and power domains, i2c, spi, thermal sensors,
smsm, smp2p, sdhci, spmi, iommus, gpu, mdss/mdp, hexagon.

Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
---
 arch/arm64/boot/dts/qcom/msm8976.dtsi | 1705 +++++++++++++++++++++++++
 1 file changed, 1705 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/msm8976.dtsi

diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi
new file mode 100644
index 000000000000..6fb917cd48fc
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi
@@ -0,0 +1,1705 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2019 AngeloGioacchino Del Regno <kholk11@gmail.com>
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-msm8976.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+
+/ {
+	interrupt-parent = <&intc>;
+
+	qcom,msm-id = <278 0x10001>; /* MSM8976 */
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
+		sdhc2 = &sdhc_2; /* SDC2 SD card slot */
+		sdhc3 = &sdhc_3; /* SDC3 SDIO card slot */
+		i2c2  = &blsp_i2c2;
+		i2c4  = &blsp_i2c4;
+		i2c6  = &blsp_i2c6;
+		i2c8  = &blsp_i2c8;
+		spi0  = &blsp1_spi0;
+	};
+
+	chosen { };
+
+	memory {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the reg */
+		reg = <0 0 0 0>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cont_splash_mem: memory@83000000 {
+			reg = <0x0 0x83000000 0x0 0x2800000>;
+		};
+
+		ext-region@85b00000 {
+			reg = <0x0 0x85b00000 0x0 0x500000>;
+			no-map;
+		};
+
+		msm_imem: memory@86000000 {
+			reg = <0x0 0x86000000 0x0 0x300000>;
+			no-map;
+		};
+
+		smem_mem: memory@86300000 {
+			reg = <0x0 0x86300000 0x0 0x100000>;
+			no-map;
+		};
+
+		reserved@86400000 {
+			reg = <0x0 0x86400000 0x0 0x800000>;
+			no-map;
+		};
+
+		mpss_mem: memory@86c00000 {
+			reg = <0x0 0x86c00000 0x0 0x5600000>;
+			no-map;
+		};
+
+		lpass_mem: memory@8c200000 {
+			reg = <0x0 0x8c200000 0x0 0x1800000>;
+			no-map;
+		};
+
+		venus_mem: memory@8da00000 {
+			reg = <0x0 0x8DA00000 0x0 0x2600000>;
+			no-map;
+		};
+
+		tz_apps: memory@8dd00000 {
+			reg = <0x0 0x8dd00000 0x0 0x1400000>;
+			no-map;
+		};
+
+		rmtfs_mem: memory@dc400000 {
+			compatible = "qcom,rmtfs-mem";
+
+			size = <0x0 0x200000>;
+			alloc-ranges = <0x0 0xdc400000 0x0 0x2000000>;
+			no-map;
+
+			qcom,client-id = <1>;
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0>;
+			enable-method = "psci";
+			cpu-idle-states = <&LITTLE_CPU_SLEEP_0>;
+			capacity-dmips-mhz = <1024>;
+			next-level-cache = <&L2_0>;
+			#cooling-cells = <2>;
+			L2_0: l2-cache {
+				compatible = "arm,arch-cache";
+				cache-level = <2>;
+			};
+			L1_I_0: l1-icache {
+				compatible = "arm,arch-cache";
+			};
+			L1_D_0: l1-dcache {
+				compatible = "arm,arch-cache";
+			};
+		};
+
+		CPU1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x1>;
+			enable-method = "psci";
+			cpu-idle-states = <&LITTLE_CPU_SLEEP_0>;
+			capacity-dmips-mhz = <1024>;
+			next-level-cache = <&L2_0>;
+			#cooling-cells = <2>;
+			L1_I_1: l1-icache {
+				compatible = "arm,arch-cache";
+			};
+			L1_D_1: l1-dcache {
+				compatible = "arm,arch-cache";
+			};
+		};
+
+		CPU2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x2>;
+			enable-method = "psci";
+			cpu-idle-states = <&LITTLE_CPU_SLEEP_0>;
+			capacity-dmips-mhz = <1024>;
+			next-level-cache = <&L2_0>;
+			#cooling-cells = <2>;
+			L1_I_2: l1-icache {
+				compatible = "arm,arch-cache";
+			};
+			L1_D_2: l1-dcache {
+				compatible = "arm,arch-cache";
+			};
+		};
+
+		CPU3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x3>;
+			enable-method = "psci";
+			cpu-idle-states = <&LITTLE_CPU_SLEEP_0>;
+			capacity-dmips-mhz = <1024>;
+			next-level-cache = <&L2_0>;
+			#cooling-cells = <2>;
+			L1_I_3: l1-icache {
+				compatible = "arm,arch-cache";
+			};
+			L1_D_3: l1-dcache {
+				compatible = "arm,arch-cache";
+			};
+		};
+
+		CPU4: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x100>;
+			enable-method = "psci";
+			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
+			capacity-dmips-mhz = <1830>;
+			next-level-cache = <&L2_1>;
+			#cooling-cells = <2>;
+			L2_1: l2-cache {
+				compatible = "arm,arch-cache";
+				cache-level = <2>;
+			};
+			L1_I_100: l1-icache {
+				compatible = "arm,arch-cache";
+			};
+			L1_D_100: l1-dcache {
+				compatible = "arm,arch-cache";
+			};
+		};
+
+		CPU5: cpu@101 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x101>;
+			enable-method = "psci";
+			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
+			capacity-dmips-mhz = <1830>;
+			next-level-cache = <&L2_1>;
+			#cooling-cells = <2>;
+			L1_I_101: l1-icache {
+				compatible = "arm,arch-cache";
+			};
+			L1_D_101: l1-dcache {
+				compatible = "arm,arch-cache";
+			};
+		};
+
+		CPU6: cpu@102 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x102>;
+			enable-method = "psci";
+			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
+			capacity-dmips-mhz = <1830>;
+			next-level-cache = <&L2_1>;
+			#cooling-cells = <2>;
+			L1_I_102: l1-icache {
+				compatible = "arm,arch-cache";
+			};
+			L1_D_102: l1-dcache {
+				compatible = "arm,arch-cache";
+			};
+		};
+
+		CPU7: cpu@103 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x103>;
+			enable-method = "psci";
+			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
+			capacity-dmips-mhz = <1830>;
+			next-level-cache = <&L2_1>;
+			#cooling-cells = <2>;
+			L1_I_103: l1-icache {
+				compatible = "arm,arch-cache";
+			};
+			L1_D_103: l1-dcache {
+				compatible = "arm,arch-cache";
+			};
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&CPU0>;
+				};
+
+				core1 {
+					cpu = <&CPU1>;
+				};
+
+				core2 {
+					cpu = <&CPU2>;
+				};
+
+				core3 {
+					cpu = <&CPU3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&CPU4>;
+				};
+
+				core1 {
+					cpu = <&CPU5>;
+				};
+
+				core2 {
+					cpu = <&CPU6>;
+				};
+
+				core3 {
+					cpu = <&CPU7>;
+				};
+			};
+		};
+
+		idle-states {
+			entry-method = "psci";
+
+			LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
+				compatible = "arm,idle-state";
+				idle-state-name = "little-power-collapse";
+				arm,psci-suspend-param = <0x40000003>;
+				entry-latency-us = <181>;
+				exit-latency-us = <149>;
+				min-residency-us = <703>;
+				local-timer-stop;
+			};
+
+			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
+				compatible = "arm,idle-state";
+				idle-state-name = "big-retention";
+				arm,psci-suspend-param = <0x00000002>;
+				entry-latency-us = <142>;
+				exit-latency-us = <99>;
+				min-residency-us = <242>;
+			};
+
+			BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
+				compatible = "arm,idle-state";
+				idle-state-name = "big-power-collapse";
+				arm,psci-suspend-param = <0x40000003>;
+				entry-latency-us = <158>;
+				exit-latency-us = <144>;
+				min-residency-us = <863>;
+				local-timer-stop;
+			};
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+		clock-frequency = <19200000>;
+	};
+
+	clocks {
+		xo_board: xo_board {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <19200000>;
+			clock-output-names = "xo_board";
+		};
+
+		cxo: cxo {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <19200000>;
+			clock-output-names = "cxo";
+		};
+
+		sleep_clk: sleep_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32764>;
+			clock-output-names = "sleep_clk";
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	firmware {
+		scm: scm {
+			compatible = "qcom,scm-msm8976", "qcom,scm";
+			clocks = <&gcc GCC_CRYPTO_CLK>,
+				 <&gcc GCC_CRYPTO_AXI_CLK>,
+				 <&gcc GCC_CRYPTO_AHB_CLK>;
+			clock-names = "core", "bus", "iface";
+			#reset-cells = <1>;
+
+			qcom,dload-mode = <&tcsr 0x6100>;
+		};
+	};
+
+	smem {
+		compatible = "qcom,smem";
+
+		memory-region = <&smem_mem>;
+		qcom,rpm-msg-ram = <&rpm_msg_ram>;
+
+		hwlocks = <&tcsr_mutex 3>;
+	};
+
+	rpmpd_opp_table: opp-table {
+		compatible = "operating-points-v2";
+
+		rpmpd_opp_ret: opp1 {
+			opp-level = <RPM_SMD_LEVEL_RETENTION>;
+		};
+
+		rpmpd_opp_ret_plus: opp2 {
+			opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
+		};
+
+		rpmpd_opp_min_svs: opp3 {
+			opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
+		};
+
+		rpmpd_opp_low_svs: opp4 {
+			opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
+		};
+
+		rpmpd_opp_svs: opp5 {
+			opp-level = <RPM_SMD_LEVEL_SVS>;
+		};
+
+		rpmpd_opp_svs_plus: opp6 {
+			opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
+		};
+
+		rpmpd_opp_nom: opp7 {
+			opp-level = <RPM_SMD_LEVEL_NOM>;
+		};
+
+		rpmpd_opp_nom_plus: opp8 {
+			opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
+		};
+
+		rpmpd_opp_turbo: opp9 {
+			opp-level = <RPM_SMD_LEVEL_TURBO>;
+		};
+
+		rpmpd_opp_turbo_no_cpr: opp10 {
+			opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
+		};
+
+		rpmpd_opp_turbo_high: opp111 {
+			opp-level = <RPM_SMD_LEVEL_TURBO_HIGH>;
+		};
+	};
+
+	smd {
+		compatible = "qcom,smd";
+
+		rpm {
+			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+			qcom,ipc = <&apcs 8 0>;
+			qcom,smd-edge = <15>;
+
+			rpm_requests: smd-channel {
+				compatible = "qcom,rpm-msm8976";
+				qcom,smd-channels = "rpm_requests";
+
+				rpmcc: clock-controller {
+					compatible = "qcom,rpmcc-msm8976";
+					#clock-cells = <1>;
+				};
+
+				rpmpd: power-controller {
+					compatible = "qcom,msm8976-rpmpd";
+					#power-domain-cells = <1>;
+					operating-points-v2 = <&rpmpd_opp_table>;
+				};
+			};
+		};
+	};
+
+	tcsr_mutex: hwlock {
+		compatible = "qcom,tcsr-mutex";
+		syscon = <&tcsr_mutex_regs 0 0x1000>;
+		#hwlock-cells = <1>;
+	};
+
+	soc: soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0 0 0xffffffff>;
+		compatible = "simple-bus";
+
+		rng@22000 {
+			compatible = "qcom,prng";
+			reg = <0x00022000 0x140>;
+			clocks = <&gcc GCC_PRNG_AHB_CLK>;
+			clock-names = "core";
+		};
+
+		rpm_msg_ram: memory@60000 {
+			compatible = "qcom,rpm-msg-ram";
+			reg = <0x00060000 0x8000>;
+		};
+
+		qfprom@a4000 {
+			compatible = "qcom,qfprom";
+			reg = <0x000a4000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			tsens_caldata: caldata@218 {
+				reg = <0x218 0x18>;
+			};
+		};
+
+		tsens0: thermal-sensor@4a9000 {
+			compatible = "qcom,msm8976-tsens";
+			reg = <0x004a9000 0x1000>, /* TM */
+			      <0x004a8000 0x1000>; /* SROT */
+			nvmem-cells = <&tsens_caldata>;
+			nvmem-cell-names = "calib";
+			#qcom,sensors = <11>;
+			#thermal-sensor-cells = <1>;
+		};
+
+		tlmm: pinctrl@1000000 {
+			compatible = "qcom,msm8976-pinctrl";
+			reg = <0x01000000 0x300000>;
+			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+
+			blsp1_uart1_default: blsp1_uart1_default {
+				pins = "gpio0", "gpio1", "gpio2", "gpio3";
+				function = "blsp_uart1";
+
+				drive-strength = <16>;
+				bias-disable;
+			};
+
+			blsp1_uart2_default: blsp1_uart2_default {
+				pins = "gpio4", "gpio5", "gpio6", "gpio7";
+				function = "blsp_uart2";
+
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp2_uart2_default: blsp2_uart2_default {
+				pins = "gpio20", "gpio21";
+				function = "blsp_uart6";
+
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			spi0_default: spi0_default {
+				bus {
+					/* MOSI, MISO, CLK */
+					pins = "gpio0", "gpio1", "gpio3";
+					function = "blsp_spi1";
+
+					drive-strength = <12>;
+				};
+
+				cs0 {
+					pins = "gpio2";
+					function = "blsp_spi1";
+
+					drive-strength = <2>;
+				};
+			};
+
+			i2c2_default: i2c2_default {
+				pins = "gpio6", "gpio7";
+				function = "blsp_i2c2";
+
+				drive-strength = <2>;
+			};
+
+			i2c4_default: i2c4_default {
+				pins = "gpio14", "gpio15";
+				function = "blsp_i2c4";
+
+				drive-strength = <2>;
+			};
+
+			i2c6_default: i2c6_default {
+				pins = "gpio22", "gpio23";
+				function = "blsp_i2c6";
+
+				drive-strength = <2>;
+			};
+
+			i2c8_default: i2c8_default {
+				pins = "gpio18", "gpio19";
+				function = "blsp_i2c8";
+
+				drive-strength = <2>;
+			};
+
+			cci0_i2c_default: cci0_i2c_default {
+				pins = "gpio29", "gpio30";
+				function = "cci0_i2c";
+
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			cci1_i2c_default: cci1_i2c_default {
+				pins = "gpio103", "gpio104";
+				function = "cci0_i2c";
+
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		gcc: clock-controller@1800000 {
+			compatible = "qcom,gcc-msm8976";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+			reg = <0x01800000 0x80000>;
+		};
+
+		tcsr_mutex_regs: syscon@1905000 {
+			compatible = "syscon";
+			reg = <0x01905000 0x20000>;
+		};
+
+		tcsr: syscon@1937000 {
+			compatible = "qcom,tcsr-msm8916", "syscon";
+			reg = <0x01937000 0x30000>;
+		};
+
+		mdss: mdss@1a00000 {
+			compatible = "qcom,mdss";
+			reg = <0x01a00000 0x1000>,
+			      <0x01ac8000 0x3000>;
+			reg-names = "mdss_phys", "vbif_phys";
+
+			power-domains = <&gcc MDSS_GDSC>;
+
+			clocks = <&gcc GCC_MDSS_AHB_CLK>,
+				 <&gcc GCC_MDSS_AXI_CLK>,
+				 <&gcc GCC_MDSS_VSYNC_CLK>;
+			clock-names = "iface",
+				      "bus",
+				      "vsync";
+
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+
+			interrupt-controller;
+			#interrupt-cells = <1>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			mdp: mdp@1a01000 {
+				compatible = "qcom,mdp5";
+				reg = <0x01a01000 0x89000>;
+				reg-names = "mdp_phys";
+
+				interrupt-parent = <&mdss>;
+				interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_MDSS_AHB_CLK>,
+					 <&gcc GCC_MDSS_AXI_CLK>,
+					 <&gcc GCC_MDSS_MDP_CLK>,
+					 <&gcc GCC_MDSS_VSYNC_CLK>,
+					 <&gcc GCC_MDP_TBU_CLK>,
+					 <&gcc GCC_MDP_RT_TBU_CLK>;
+				clock-names = "iface",
+					      "bus",
+					      "core",
+					      "vsync",
+					      "tbu",
+					      "tbu_rt";
+
+				iommus = <&apps_iommu 22>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						mdp5_intf1_out: endpoint {
+							remote-endpoint = <&dsi0_in>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						mdp5_intf2_out: endpoint {
+							remote-endpoint = <&dsi1_in>;
+						};
+					};
+				};
+			};
+
+			dsi0: dsi@1a94000 {
+				compatible = "qcom,mdss-dsi-ctrl";
+				reg = <0x01a94000 0x25c>;
+				reg-names = "dsi_ctrl";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				interrupt-parent = <&mdss>;
+				interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+
+				assigned-clocks =
+					<&gcc GCC_MDSS_BYTE0_CLK_SRC>,
+					<&gcc GCC_MDSS_PCLK0_CLK_SRC>;
+				assigned-clock-parents = <&dsi_phy0 0>;
+
+				clocks = <&gcc GCC_MDSS_MDP_CLK>,
+					 <&gcc GCC_MDSS_AHB_CLK>,
+					 <&gcc GCC_MDSS_AXI_CLK>,
+					 <&gcc GCC_MDSS_BYTE0_CLK>,
+					 <&gcc GCC_MDSS_PCLK0_CLK>,
+					 <&gcc GCC_MDSS_ESC0_CLK>;
+				clock-names = "mdp_core",
+					      "iface",
+					      "bus",
+					      "byte",
+					      "pixel",
+					      "core";
+				phys = <&dsi_phy0>;
+				phy-names = "dsi-phy";
+
+				qcom,mdss-mdp-transfer-time-us = <12000>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						dsi0_in: endpoint {
+							remote-endpoint = <&mdp5_intf1_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						dsi0_out: endpoint {
+						};
+					};
+				};
+			};
+
+			dsi_phy0: dsi-phy@1a94a00 {
+				compatible = "qcom,dsi-phy-28nm-hpm-8976";
+				reg = <0x01a94a00 0xd4>,
+				      <0x01a94400 0x280>,
+				      <0x01a94b80 0x30>;
+				reg-names = "dsi_pll",
+					    "dsi_phy",
+					    "dsi_phy_regulator";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				clocks = <&gcc GCC_MDSS_AHB_CLK>,
+					 <&xo_board>;
+				clock-names = "iface", "ref";
+			};
+
+			dsi1: dsi@1a96000 {
+				compatible = "qcom,mdss-dsi-ctrl";
+				reg = <0x01a96000 0x300>;
+				reg-names = "dsi_ctrl";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				interrupt-parent = <&mdss>;
+				interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
+
+				assigned-clocks =
+					<&gcc GCC_MDSS_BYTE1_CLK_SRC>,
+					<&gcc GCC_MDSS_PCLK1_CLK_SRC>;
+				assigned-clock-parents = <&dsi_phy1 0>,
+							 <&dsi_phy1 1>;
+
+				clocks = <&gcc GCC_MDSS_MDP_CLK>,
+					 <&gcc GCC_MDSS_AHB_CLK>,
+					 <&gcc GCC_MDSS_AXI_CLK>,
+					 <&gcc GCC_MDSS_BYTE1_CLK>,
+					 <&gcc GCC_MDSS_PCLK1_CLK>,
+					 <&gcc GCC_MDSS_ESC1_CLK>;
+				clock-names = "mdp_core",
+					      "iface",
+					      "bus",
+					      "byte",
+					      "pixel",
+					      "core";
+				phys = <&dsi_phy1>;
+				phy-names = "dsi-phy";
+
+				qcom,mdss-mdp-transfer-time-us = <12000>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						dsi1_in: endpoint {
+							remote-endpoint = <&mdp5_intf2_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						dsi1_out: endpoint {
+						};
+					};
+				};
+			};
+
+			dsi_phy1: dsi-phy@1a96a00 {
+				compatible = "qcom,dsi-phy-28nm-hpm-8976";
+				reg = <0x01a96a00 0xd4>,
+				      <0x01a96400 0x280>,
+				      <0x01a96b80 0x30>;
+				reg-names = "dsi_pll",
+					    "dsi_phy",
+					    "dsi_phy_regulator";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				clocks = <&gcc GCC_MDSS_AHB_CLK>,
+					 <&xo_board>;
+				clock-names = "iface", "ref";
+			};
+		};
+
+		adreno_gpu: gpu@1c00000 {
+			compatible = "qcom,adreno-510.0", "qcom,adreno";
+			#stream-id-cells = <16>;
+
+			reg = <0x01c00000 0x40000>;
+			reg-names = "kgsl_3d0_reg_memory";
+
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "kgsl_3d0_irq";
+
+			clock-names =
+			    "core",
+			    "iface",
+			    "mem",
+			    "rbbmtimer",
+			    "gtcu",
+			    "gtbu",
+			    "alwayson";
+
+			clocks =
+			    <&gcc GCC_GFX3D_OXILI_CLK>,
+			    <&gcc GCC_GFX3D_OXILI_AHB_CLK>,
+			    <&gcc GCC_GFX3D_BIMC_CLK>,
+			    <&gcc GCC_GFX3D_OXILI_TIMER_CLK>,
+			    <&gcc GCC_GFX3D_GTCU_AHB_CLK>,
+			    <&gcc GCC_GFX3D_TBU1_CLK>,
+			    <&gcc GCC_GFX3D_OXILI_AON_CLK>;
+
+			power-domains = <&gcc OXILI_GX_GDSC>;
+			operating-points-v2 = <&gpu_opp_table>;
+			iommus = <&gpu_iommu 0>;
+
+			gpu_opp_table: opp_table {
+				compatible = "operating-points-v2";
+
+				opp-200000000 {
+					opp-hz = /bits/ 64 <200000000>;
+				};
+
+				opp-160000000 {
+					opp-hz = /bits/ 64 <160000000>;
+				};
+			};
+		};
+
+		apps_iommu: iommu@1e1f000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			#iommu-cells = <1>;
+			compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v1";
+			ranges = <0 0x01e1f000 0x21000>;
+			clocks = <&gcc GCC_SMMU_CFG_CLK>,
+				 <&gcc GCC_APSS_TCU_CLK>;
+			clock-names = "iface", "bus";
+			qcom,iommu-secure-id = <17>;
+			status = "ok";
+
+			// adsp_elf:
+			iommu-ctx@1000 {
+				compatible = "qcom,msm-iommu-v2-sec";
+				reg = <0x1000 0x1000>;
+				qcom,ctx-num = <1>;
+				interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			// adsp_sec_pixel:
+			iommu-ctx@2000 {
+				compatible = "qcom,msm-iommu-v2-sec";
+				reg = <0x2000 0x1000>;
+				qcom,ctx-num = <2>;
+				interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			// adsp_sec_bitstream:
+			iommu-ctx@3000 {
+				compatible = "qcom,msm-iommu-v2-sec";
+				reg = <0x3000 0x1000>;
+				qcom,ctx-num = <3>;
+				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			// venus_fw:
+			iommu-ctx@4000 {
+				compatible = "qcom,msm-iommu-v2-sec";
+				reg = <0x4000 0x1000>;
+				qcom,ctx-num = <4>;
+				interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			// venus_sec_non_pixel:
+			iommu-ctx@5000 {
+				compatible = "qcom,msm-iommu-v2-sec";
+				reg = <0x5000 0x1000>;
+				qcom,ctx-num = <5>;
+				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			// venus_sec_bitstream:
+			iommu-ctx@6000 {
+				compatible = "qcom,msm-iommu-v2-sec";
+				reg = <0x6000 0x1000>;
+				qcom,ctx-num = <6>;
+				interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			// venus_sec_pixel:
+			iommu-ctx@7000 {
+				compatible = "qcom,msm-iommu-v2-sec";
+				reg = <0x7000 0x1000>;
+				qcom,ctx-num = <7>;
+				interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			// venus_enc:
+			iommu-ctx@8000 {
+				compatible = "qcom,msm-iommu-v2-sec";
+				reg = <0x8000 0x1000>;
+				qcom,ctx-num = <8>;
+				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			// mdp_1:
+			iommu-ctx@9000 {
+				compatible = "qcom,msm-iommu-v2-sec";
+				reg = <0x9000 0x1000>;
+				qcom,ctx-num = <9>;
+				interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			// adsp_io:
+			iommu-ctx@10000 {
+				compatible = "qcom,msm-iommu-v2-ns";
+				reg = <0x10000 0x1000>;
+				interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+				qcom,ctx-num = <14>;
+			};
+
+			// adsp_opendsp:
+			iommu-ctx@11000 {
+				compatible = "qcom,msm-iommu-v2-ns";
+				reg = <0x11000 0x1000>;
+				interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+				qcom,ctx-num = <15>;
+			};
+
+			// adsp_shared:
+			iommu-ctx@12000 {
+				compatible = "qcom,msm-iommu-v2-ns";
+				reg = <0x12000 0x1000>;
+				interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+				qcom,ctx-num = <16>;
+			};
+
+			// lpass_stream:
+			iommu-ctx@13000 {
+				compatible = "qcom,msm-iommu-v2-ns";
+				reg = <0x13000 0x1000>;
+				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+				qcom,ctx-num = <17>;
+			};
+
+			// cpp:
+			iommu-ctx@14000 {
+				compatible = "qcom,msm-iommu-v2-ns";
+				reg = <0x14000 0x1000>;
+				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+				qcom,ctx-num = <18>;
+			};
+
+			// jpeg_enc0:
+			iommu-ctx@15000 {
+				compatible = "qcom,msm-iommu-v2-ns";
+				reg = <0x15000 0x1000>;
+				interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+				qcom,ctx-num = <19>;
+			};
+
+			// vfe:
+			iommu-ctx@16000 {
+				compatible = "qcom,msm-iommu-v2-ns";
+				reg = <0x16000 0x1000>;
+				interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+				qcom,ctx-num = <20>;
+			};
+
+			// venus_ns:
+			iommu-ctx@17000 {
+				compatible = "qcom,msm-iommu-v2-ns";
+				reg = <0x17000 0x1000>;
+				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+				qcom,ctx-num = <21>;
+			};
+
+			// mdp_0:
+			iommu-ctx@18000 {
+				compatible = "qcom,msm-iommu-v2-ns";
+				reg = <0x18000 0x1000>;
+				interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+				qcom,ctx-num = <22>;
+			};
+
+			// pronto_buf:
+			iommu-ctx@19000 {
+				compatible = "qcom,msm-iommu-v2-ns";
+				reg = <0x19000 0x1000>;
+				interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+				qcom,ctx-num = <23>;
+			};
+
+			// mss_nav:
+			iommu-ctx@1a000 {
+				compatible = "qcom,msm-iommu-v2-ns";
+				reg = <0x1a000 0x1000>;
+				interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+				qcom,ctx-num = <24>;
+			};
+
+			// ipa_shared:
+			iommu-ctx@1b000 {
+				compatible = "qcom,msm-iommu-v2-ns";
+				reg = <0x1b000 0x1000>;
+				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+				qcom,ctx-num = <25>;
+			};
+
+			// ipa_wlan:
+			iommu-ctx@1c000 {
+				compatible = "qcom,msm-iommu-v2-ns";
+				reg = <0x1c000 0x1000>;
+				interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+				qcom,ctx-num = <26>;
+			};
+
+			// ipa_uc:
+			iommu-ctx@1d000 {
+				compatible = "qcom,msm-iommu-v2-ns";
+				reg = <0x1d000 0x1000>;
+				interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+				qcom,ctx-num = <27>;
+			};
+		};
+
+		gpu_iommu: iommu@1f08000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			#iommu-cells = <1>;
+			compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v1";
+			ranges = <0 0x01f08000 0x8000>;
+			clocks = <&gcc GCC_SMMU_CFG_CLK>,
+				 <&gcc GCC_GFX3D_TCU_CLK>;
+			clock-names = "iface", "bus";
+			qcom,iommu-secure-id = <18>;
+			power-domains = <&gcc OXILI_CX_GDSC>;
+
+			// gfx3d_user:
+			iommu-ctx@0 {
+				compatible = "qcom,msm-iommu-v1-ns";
+				reg = <0x0 0x1000>;
+				qcom,ctx-num = <0>;
+				interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			// gfx3d_sec:
+			iommu-ctx@2000 {
+				compatible = "qcom,msm-iommu-v2-sec";
+				reg = <0x1000 0x1000>;
+				qcom,ctx-num = <2>;
+				interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			// gfx3d_priv:
+			iommu-ctx@3000 {
+				compatible = "qcom,msm-iommu-v2-sec";
+				reg = <0x2000 0x1000>;
+				qcom,ctx-num = <1>;
+				interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+		};
+
+		spmi_bus: qcom,spmi@200f000 {
+			compatible = "qcom,spmi-pmic-arb";
+			reg = <0x0200f000 0x1000>,
+				<0x02400000 0x800000>,
+				<0x02c00000 0x800000>,
+				<0x03800000 0x200000>,
+				<0x0200a000 0x2100>;
+			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "periph_irq";
+			qcom,channel = <0>;
+			qcom,ee = <0>;
+
+			#address-cells = <2>;
+			#size-cells = <0>;
+			interrupt-controller;
+			#interrupt-cells = <4>;
+			cell-index = <0>;
+		};
+
+		sdhc_1: mmc@7824000 {
+			compatible = "qcom,sdhci-msm-v4";
+			reg = <0x07824900 0x500>, <0x07824000 0x800>;
+			reg-names = "hc_mem", "core_mem";
+
+			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq", "pwr_irq";
+
+			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
+				 <&gcc GCC_SDCC1_AHB_CLK>,
+				 <&xo_board>;
+			clock-names = "core", "iface", "xo";
+
+			mmc-hs400-1_8v;
+			bus-width = <8>;
+			non-removable;
+			status = "disabled";
+		};
+
+		sdhc_2: sdhci@7864000 {
+			compatible = "qcom,sdhci-msm-v4";
+			reg = <0x07864900 0x11c>, <0x07864000 0x800>;
+			reg-names = "hc_mem", "core_mem";
+
+			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq", "pwr_irq";
+
+			clocks = <&gcc GCC_SDCC2_APPS_CLK>,
+				 <&gcc GCC_SDCC2_AHB_CLK>,
+				 <&xo_board>;
+			clock-names = "core", "iface", "xo";
+
+			bus-width = <4>;
+			status = "disabled";
+		};
+
+		blsp_dma: dma@7884000 {
+			compatible = "qcom,bam-v1.7.0";
+			reg = <0x07884000 0x1f000>;
+			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "bam_clk";
+			#dma-cells = <1>;
+			qcom,ee = <0>;
+			status = "disabled";
+		};
+
+		blsp1_uart1: serial@78af000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0x078af000 0x200>;
+			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp_dma 1>, <&blsp_dma 0>;
+			dma-names = "rx", "tx";
+			pinctrl-names = "default";
+			pinctrl-0 = <&blsp1_uart1_default>;
+			status = "disabled";
+		};
+
+		blsp1_uart2: serial@78b0000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0x078b0000 0x200>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp_dma 3>, <&blsp_dma 2>;
+			dma-names = "rx", "tx";
+			pinctrl-names = "default";
+			pinctrl-0 = <&blsp1_uart2_default>;
+			status = "disabled";
+		};
+
+		blsp2_uart2: serial@7af0000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0x07af0000 0x200>;
+			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
+				 <&gcc GCC_BLSP2_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp2_dma 1>, <&blsp2_dma 0>;
+			dma-names = "rx", "tx";
+			pinctrl-names = "default";
+			pinctrl-0 = <&blsp2_uart2_default>;
+			status = "disabled";
+		};
+
+		blsp1_spi0: spi@78b5000 {
+			compatible = "qcom,spi-qup-v2.2.1";
+			reg = <0x078b5000 0x500>;
+			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp_dma 5>, <&blsp_dma 4>;
+			dma-names = "rx", "tx";
+			pinctrl-names = "default";
+			pinctrl-0 = <&spi0_default>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp_i2c2: i2c@78b6000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x078b6000 0x500>;
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+				 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+			clock-names = "iface", "core";
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c2_default>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp_i2c4: i2c@78b8000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x078b8000 0x500>;
+			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+				 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
+			clock-names = "iface", "core";
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c4_default>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		otg: usb@78d9000 {
+			compatible = "qcom,ci-hdrc";
+			reg = <0x078db000 0x200>,
+			      <0x078db200 0x200>;
+			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_USB_HS_AHB_CLK>,
+				 <&gcc GCC_USB_HS_SYSTEM_CLK>;
+			clock-names = "iface", "core";
+			assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
+			assigned-clock-rates = <80000000>;
+			resets = <&gcc RST_USB_HS_BCR>;
+			reset-names = "core";
+			phy_type = "ulpi";
+			dr_mode = "peripheral";
+			ahb-burst-config = <0>;
+			status = "disabled";
+			#reset-cells = <1>;
+		};
+
+		sdhc_3: sdhci@7a24000 {
+			compatible = "qcom,sdhci-msm-v4";
+			reg = <0x07a24900 0x11c>, <0x07a24000 0x800>;
+			reg-names = "hc_mem", "core_mem";
+
+			interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq", "pwr_irq";
+
+			clocks = <&gcc GCC_SDCC3_APPS_CLK>,
+				 <&gcc GCC_SDCC3_AHB_CLK>,
+				 <&xo_board>;
+			clock-names = "core", "iface", "xo";
+
+			bus-width = <4>;
+			status = "disabled";
+		};
+
+		blsp2_dma: dma@7ac4000 {
+			compatible = "qcom,bam-v1.7.0";
+			reg = <0x07ac4000 0x1f000>;
+			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP2_AHB_CLK>;
+			clock-names = "bam_clk";
+			#dma-cells = <1>;
+			qcom,ee = <0>;
+			status = "disabled";
+		};
+
+		blsp_i2c6: i2c@7af6000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x07af6000 0x600>;
+			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
+				 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
+			clock-names = "iface", "core";
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c6_default>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp_i2c8: i2c@7af8000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x07af8000 0x600>;
+			interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
+				 <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>;
+			clock-names = "iface", "core";
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c8_default>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		intc: interrupt-controller@b000000 {
+			compatible = "qcom,msm-qgic2";
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			reg = <0x0b000000 0x1000>,
+			      <0x0b002000 0x1000>;
+		};
+
+		apcs: syscon@b011000 {
+			compatible = "syscon";
+			reg = <0x0b011000 0x1000>;
+		};
+
+		timer@b120000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			compatible = "arm,armv7-timer-mem";
+			reg = <0x0b120000 0x1000>;
+			clock-frequency = <19200000>;
+
+			frame@b121000 {
+				frame-number = <0>;
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0b121000 0x1000>,
+				      <0x0b122000 0x1000>;
+			};
+
+			frame@b123000 {
+				frame-number = <1>;
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0b123000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@b124000 {
+				frame-number = <2>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0b124000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@b125000 {
+				frame-number = <3>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0b125000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@b126000 {
+				frame-number = <4>;
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0b126000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@b127000 {
+				frame-number = <5>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0b127000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@b128000 {
+				frame-number = <6>;
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0b128000 0x1000>;
+				status = "disabled";
+			};
+		};
+	};
+
+	smsm {
+		compatible = "qcom,smsm";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		qcom,ipc-1 = <&apcs 8 12>;
+		qcom,ipc-2 = <&apcs 8 9>;
+		qcom,ipc-3 = <&apcs 8 18>;
+
+		apps_smsm: apps@0 {
+			reg = <0>;
+			#qcom,smem-state-cells = <1>;
+		};
+
+		hexagon_smsm: hexagon@1 {
+			reg = <1>;
+			interrupts = <0 290 IRQ_TYPE_EDGE_RISING>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		wcnss_smsm: wcnss@6 {
+			reg = <6>;
+			interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	modem-smp2p {
+		compatible = "qcom,smp2p";
+		qcom,smem = <435>, <428>;
+
+		interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
+
+		qcom,ipc = <&apcs 8 13>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <1>;
+
+		modem_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+
+			#qcom,smem-state-cells = <1>;
+		};
+
+		modem_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	wcnss-smp2p {
+		compatible = "qcom,smp2p";
+		qcom,smem = <451>, <431>;
+
+		interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
+
+		qcom,ipc = <&apcs 8 17>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <4>;
+
+		wcnss_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+
+			#qcom,smem-state-cells = <1>;
+		};
+
+		wcnss_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	hexagon-smp2p {
+		compatible = "qcom,smp2p";
+		qcom,smem = <443>, <429>;
+
+		interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
+
+		qcom,ipc = <&apcs 8 10>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <2>;
+
+		adsp_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+
+			#qcom,smem-state-cells = <1>;
+		};
+
+		adsp_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	thermal_zones: thermal-zones {
+		aoss0-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens0 0>;
+			trips {
+				aoss0_alert: trip-point@0 {
+					temperature = <105000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		mdm-core-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens0 1>;
+			trips {
+				modem_alert: trip-point@0 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		qdsp-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens0 2>;
+			trips {
+				qdsp_alert: trip-point@0 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		cam-isp-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens0 3>;
+			trips {
+				cam_isp_alert: trip-point@0 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		apc1-cpu0-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+			thermal-sensors = <&tsens0 4>;
+
+			trips {
+				cpu4_alert0: trip-point@0 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+				cpu4_alert1: trip-point@1 {
+					temperature = <105000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu4_crit: trip-point@2 {
+					temperature = <120000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		apc1-cpu1-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+			thermal-sensors = <&tsens0 5>;
+
+			trips {
+				cpu5_alert0: trip-point@0 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+				cpu5_alert1: trip-point@1 {
+					temperature = <105000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu5_crit: trip-point@2 {
+					temperature = <120000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		apc1-cpu2-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+			thermal-sensors = <&tsens0 6>;
+
+			trips {
+				cpu6_alert0: trip-point@0 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+				cpu6_alert1: trip-point@1 {
+					temperature = <105000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu6_crit: trip-point@2 {
+					temperature = <120000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		apc1-cpu3-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+			thermal-sensors = <&tsens0 7>;
+
+			trips {
+				cpu7_alert0: trip-point@0 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+				cpu7_alert1: trip-point@1 {
+					temperature = <105000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu7_crit: trip-point@2 {
+					temperature = <120000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		apc1-l2-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+			thermal-sensors = <&tsens0 8>;
+
+			trips {
+				l2_alert0: trip-point@0 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+				l2_alert1: trip-point@1 {
+					temperature = <105000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				l2_crit: trip-point@2 {
+					temperature = <120000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		apc0-cpu0-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+			thermal-sensors = <&tsens0 9>;
+
+			trips {
+				cpu0_alert0: trip-point@0 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+				cpu0_alert1: trip-point@1 {
+					temperature = <105000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu0_crit: trip-point@2 {
+					temperature = <120000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+	};
+};
-- 
2.21.0

Re: [PATCH v2 4/5] arm64: dts: qcom: Add MSM8976 SoC support dts files

[Amit Kucheria]

On Thu, Oct 31, 2019 at 4:46 PM <kholk11@gmail.com> wrote:
>
> From: AngeloGioacchino Del Regno <kholk11@gmail.com>
>
> These are the DTs to support the MSM8976 SoC and, with very small
> overrides in future ones, also MSM8956 and their APQ variants.
>
> This configuration includes firmware, cpu, psci, idle states,
> clocks, smem, rpm and power domains, i2c, spi, thermal sensors,
> smsm, smp2p, sdhci, spmi, iommus, gpu, mdss/mdp, hexagon.
>
> Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
> ---
>  arch/arm64/boot/dts/qcom/msm8976.dtsi | 1705 +++++++++++++++++++++++++
>  1 file changed, 1705 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/qcom/msm8976.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi
> new file mode 100644
> index 000000000000..6fb917cd48fc
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi
> @@ -0,0 +1,1705 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2016-2019 AngeloGioacchino Del Regno <kholk11@gmail.com>
> + */
> +

<snip>

> +
> +       cpus {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               CPU0: cpu@0 {
> +                       device_type = "cpu";
> +                       compatible = "arm,armv8";
> +                       reg = <0x0>;
> +                       enable-method = "psci";
> +                       cpu-idle-states = <&LITTLE_CPU_SLEEP_0>;
> +                       capacity-dmips-mhz = <1024>;
> +                       next-level-cache = <&L2_0>;
> +                       #cooling-cells = <2>;
> +                       L2_0: l2-cache {
> +                               compatible = "arm,arch-cache";
> +                               cache-level = <2>;
> +                       };
> +                       L1_I_0: l1-icache {
> +                               compatible = "arm,arch-cache";
> +                       };
> +                       L1_D_0: l1-dcache {
> +                               compatible = "arm,arch-cache";
> +                       };
> +               };
> +
> +               CPU1: cpu@1 {
> +                       device_type = "cpu";
> +                       compatible = "arm,armv8";
> +                       reg = <0x1>;
> +                       enable-method = "psci";
> +                       cpu-idle-states = <&LITTLE_CPU_SLEEP_0>;
> +                       capacity-dmips-mhz = <1024>;
> +                       next-level-cache = <&L2_0>;
> +                       #cooling-cells = <2>;
> +                       L1_I_1: l1-icache {
> +                               compatible = "arm,arch-cache";
> +                       };
> +                       L1_D_1: l1-dcache {
> +                               compatible = "arm,arch-cache";
> +                       };
> +               };
> +
> +               CPU2: cpu@2 {
> +                       device_type = "cpu";
> +                       compatible = "arm,armv8";
> +                       reg = <0x2>;
> +                       enable-method = "psci";
> +                       cpu-idle-states = <&LITTLE_CPU_SLEEP_0>;
> +                       capacity-dmips-mhz = <1024>;
> +                       next-level-cache = <&L2_0>;
> +                       #cooling-cells = <2>;
> +                       L1_I_2: l1-icache {
> +                               compatible = "arm,arch-cache";
> +                       };
> +                       L1_D_2: l1-dcache {
> +                               compatible = "arm,arch-cache";
> +                       };
> +               };
> +
> +               CPU3: cpu@3 {
> +                       device_type = "cpu";
> +                       compatible = "arm,armv8";
> +                       reg = <0x3>;
> +                       enable-method = "psci";
> +                       cpu-idle-states = <&LITTLE_CPU_SLEEP_0>;
> +                       capacity-dmips-mhz = <1024>;
> +                       next-level-cache = <&L2_0>;
> +                       #cooling-cells = <2>;
> +                       L1_I_3: l1-icache {
> +                               compatible = "arm,arch-cache";
> +                       };
> +                       L1_D_3: l1-dcache {
> +                               compatible = "arm,arch-cache";
> +                       };
> +               };
> +
> +               CPU4: cpu@100 {
> +                       device_type = "cpu";
> +                       compatible = "arm,armv8";
> +                       reg = <0x100>;
> +                       enable-method = "psci";
> +                       cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
> +                       capacity-dmips-mhz = <1830>;

The convention has been to use 1024 as the capacity-dmips-mhz value
for the big core and scale down the capacity for the LITTLE core
accordingly.

> +                       next-level-cache = <&L2_1>;
> +                       #cooling-cells = <2>;
> +                       L2_1: l2-cache {
> +                               compatible = "arm,arch-cache";
> +                               cache-level = <2>;
> +                       };
> +                       L1_I_100: l1-icache {
> +                               compatible = "arm,arch-cache";
> +                       };
> +                       L1_D_100: l1-dcache {
> +                               compatible = "arm,arch-cache";
> +                       };
> +               };
> +
> +               CPU5: cpu@101 {
> +                       device_type = "cpu";
> +                       compatible = "arm,armv8";
> +                       reg = <0x101>;
> +                       enable-method = "psci";
> +                       cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
> +                       capacity-dmips-mhz = <1830>;
> +                       next-level-cache = <&L2_1>;
> +                       #cooling-cells = <2>;
> +                       L1_I_101: l1-icache {
> +                               compatible = "arm,arch-cache";
> +                       };
> +                       L1_D_101: l1-dcache {
> +                               compatible = "arm,arch-cache";
> +                       };
> +               };
> +
> +               CPU6: cpu@102 {
> +                       device_type = "cpu";
> +                       compatible = "arm,armv8";
> +                       reg = <0x102>;
> +                       enable-method = "psci";
> +                       cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
> +                       capacity-dmips-mhz = <1830>;
> +                       next-level-cache = <&L2_1>;
> +                       #cooling-cells = <2>;
> +                       L1_I_102: l1-icache {
> +                               compatible = "arm,arch-cache";
> +                       };
> +                       L1_D_102: l1-dcache {
> +                               compatible = "arm,arch-cache";
> +                       };
> +               };
> +
> +               CPU7: cpu@103 {
> +                       device_type = "cpu";
> +                       compatible = "arm,armv8";
> +                       reg = <0x103>;
> +                       enable-method = "psci";
> +                       cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
> +                       capacity-dmips-mhz = <1830>;
> +                       next-level-cache = <&L2_1>;
> +                       #cooling-cells = <2>;
> +                       L1_I_103: l1-icache {
> +                               compatible = "arm,arch-cache";
> +                       };
> +                       L1_D_103: l1-dcache {
> +                               compatible = "arm,arch-cache";


<snip>

> +
> +               tsens0: thermal-sensor@4a9000 {
> +                       compatible = "qcom,msm8976-tsens";
> +                       reg = <0x004a9000 0x1000>, /* TM */
> +                             <0x004a8000 0x1000>; /* SROT */
> +                       nvmem-cells = <&tsens_caldata>;
> +                       nvmem-cell-names = "calib";
> +                       #qcom,sensors = <11>;
> +                       #thermal-sensor-cells = <1>;

Now that interrupt support for tsens has landed in 5.5-rc1, please add that too.

<snip>


> +                                       temperature = <95000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                       };
> +               };
> +
> +               cam-isp-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +
> +                       thermal-sensors = <&tsens0 3>;
> +                       trips {
> +                               cam_isp_alert: trip-point@0 {

Lose the @. Just use trip-point0 else the DT compiler will complain.
Please replace for all thermal zones.

> +                                       temperature = <95000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                       };
> +               };
> +
> +               apc1-cpu0-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +                       thermal-sensors = <&tsens0 4>;
> +
> +                       trips {
> +                               cpu4_alert0: trip-point@0 {
> +                                       temperature = <95000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                               cpu4_alert1: trip-point@1 {
> +                                       temperature = <105000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +                               cpu4_crit: trip-point@2 {
> +                                       temperature = <120000>;
> +                                       hysteresis = <2000>;
> +                                       type = "critical";
> +                               };

Since you don't have cpufreq support from what I can tell, there are
no cooling maps for the cpus. So there is no point in having these
passive trip points. Just have the hot and critical trips for now.

Once we get the cpuidle cooling governor merged or you add cpufreq
support, you can re-add the passive trip point along with the cooling
maps.


> +                       };
> +               };
> +
> +               apc1-cpu1-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +                       thermal-sensors = <&tsens0 5>;
> +
> +                       trips {
> +                               cpu5_alert0: trip-point@0 {
> +                                       temperature = <95000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                               cpu5_alert1: trip-point@1 {
> +                                       temperature = <105000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +                               cpu5_crit: trip-point@2 {
> +                                       temperature = <120000>;
> +                                       hysteresis = <2000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +               };
> +
> +               apc1-cpu2-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +                       thermal-sensors = <&tsens0 6>;
> +
> +                       trips {
> +                               cpu6_alert0: trip-point@0 {
> +                                       temperature = <95000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                               cpu6_alert1: trip-point@1 {
> +                                       temperature = <105000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +                               cpu6_crit: trip-point@2 {
> +                                       temperature = <120000>;
> +                                       hysteresis = <2000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +               };
> +
> +               apc1-cpu3-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +                       thermal-sensors = <&tsens0 7>;
> +
> +                       trips {
> +                               cpu7_alert0: trip-point@0 {
> +                                       temperature = <95000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                               cpu7_alert1: trip-point@1 {
> +                                       temperature = <105000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +                               cpu7_crit: trip-point@2 {
> +                                       temperature = <120000>;
> +                                       hysteresis = <2000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +               };
> +
> +               apc1-l2-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +                       thermal-sensors = <&tsens0 8>;
> +
> +                       trips {
> +                               l2_alert0: trip-point@0 {
> +                                       temperature = <95000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                               l2_alert1: trip-point@1 {
> +                                       temperature = <105000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +                               l2_crit: trip-point@2 {
> +                                       temperature = <120000>;
> +                                       hysteresis = <2000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +               };
> +
> +               apc0-cpu0-thermal {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <1000>;
> +                       thermal-sensors = <&tsens0 9>;
> +
> +                       trips {
> +                               cpu0_alert0: trip-point@0 {
> +                                       temperature = <95000>;
> +                                       hysteresis = <2000>;
> +                                       type = "hot";
> +                               };
> +                               cpu0_alert1: trip-point@1 {
> +                                       temperature = <105000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +                               cpu0_crit: trip-point@2 {
> +                                       temperature = <120000>;
> +                                       hysteresis = <2000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +               };
> +       };
> +};
> --
> 2.21.0
>

[PATCH v2 5/5] arm64: dts: qcom: Add Sony Xperia (Loire) X and X Compact support

[kholk11]

From: AngeloGioacchino Del Regno <kholk11@gmail.com>

This adds support for the Sony Xperia Loire/SmartLoire platform
with a base configuration that is common across all of the
devices that are based on this project.

Also adds a base DT configuration for the Xperia X and Xperia
X Compact (respectively, Suzu and Kugo) which is valid for both
their RoW (single-sim), DSDS (dual-sim) and other regional
variants of these two smartphones, that makes us able to boot
to a UART console.

This configuration also enables the use of the Broadcom SDIO
WiFi solution (BCM43455), vibrator, GPIO Keys, eMMC, MicroSD
card slot, Synaptics touchscreen (i2c) and configures all of
the needed regulators and GPIOs present on all Loire boards.

Please note that, currently, the APC0/1 (cluster 0/1) vregs
are set to a safe voltage in order to ensure boot stability
until a proper solution for CPU DVFS scaling lands.

Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
---
 arch/arm64/boot/dts/qcom/Makefile             |   2 +
 .../qcom/msm8956-sony-xperia-loire-kugo.dts   |  56 ++
 .../qcom/msm8956-sony-xperia-loire-suzu.dts   |  17 +
 .../dts/qcom/msm8956-sony-xperia-loire.dtsi   | 744 ++++++++++++++++++
 4 files changed, 819 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-kugo.dts
 create mode 100644 arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-suzu.dts
 create mode 100644 arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire.dtsi

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 6498a1ec893f..a6fdd97de83e 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -6,6 +6,8 @@ dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-mtp.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-longcheer-l8150.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-samsung-a3u-eur.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-samsung-a5u-eur.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= msm8956-sony-xperia-loire-kugo.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= msm8956-sony-xperia-loire-suzu.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= msm8992-bullhead-rev-101.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= msm8994-angler-rev-101.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= msm8996-mtp.dtb
diff --git a/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-kugo.dts b/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-kugo.dts
new file mode 100644
index 000000000000..f77cfd5424f0
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-kugo.dts
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (C) 2014 Sony Mobile Communications Inc.
+ * Copyright (c) 2016-2019 AngeloGioacchino Del Regno <kholk11@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "msm8956-sony-xperia-loire.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Sony Xperia X Compact (Loire Kugo)";
+	compatible = "sony,xperia-kugo", "qcom,msm8956";
+
+	qcom,msm-id = <266 0x10001>; /* MSM8956 PM/PMI8956 */
+	qcom,board-id = <8 0>;
+};
+
+&blsp_i2c6 {
+	status = "ok";
+};
+
+&pm8950_l1 {
+	regulator-min-microvolt = <1100000>;
+	regulator-max-microvolt = <1300000>;
+};
+
+/* Machine specific pins */
+&tlmm {
+	usb_cable_det_n_gpio: usb_cable_det_n {
+		pins = "gpio107";
+		function = "gpio";
+
+		drive-strength = <2>;
+		bias-pull-up;
+		input-enable;
+	};
+
+	usb_cable_sense_en_gpio: usb_cable_sense_en {
+		pins = "gpio116";
+		function = "gpio";
+
+		drive-strength = <2>;
+		bias-disable;
+		output-low;
+	};
+
+	usb_cc_int_n_gpio: usb_cc_int_n {
+		pins = "gpio131";
+		function = "gpio";
+
+		drive-strength = <2>;
+		bias-pull-up;
+		input-enable;
+	};
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-suzu.dts b/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-suzu.dts
new file mode 100644
index 000000000000..14d65e68f300
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-suzu.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (C) 2014 Sony Mobile Communications Inc.
+ * Copyright (c) 2016-2019 AngeloGioacchino Del Regno <kholk11@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "msm8956-sony-xperia-loire.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Sony Xperia X (Loire Suzu)";
+	compatible = "sony,xperia-suzu", "qcom,msm8956";
+
+	qcom,msm-id = <266 0x10001>; /* MSM8956 PM/PMI8956 */
+	qcom,board-id = <8 0>;
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire.dtsi b/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire.dtsi
new file mode 100644
index 000000000000..8da88bb24e7d
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire.dtsi
@@ -0,0 +1,744 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Sony Xperia Loire/SmartLoire platform (MSM8956/APQ8056) configuration
+ * This configuration is common across a range of Xperia devices
+ * based on the Loire and SmartLoire projects.
+ *
+ * Copyright (C) 2014 Sony Mobile Communications Inc.
+ * Copyright (c) 2016-2019 AngeloGioacchino Del Regno <kholk11@gmail.com>
+ */
+
+#include "msm8976.dtsi"
+#include "pmi8950.dtsi"
+#include "pm8950.dtsi"
+#include "pm8004.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/gpio-keys.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+
+/ {
+	aliases {
+		serial0 = &blsp2_uart2;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	reserved-memory {
+		ramoops {
+			compatible = "ramoops";
+			reg = <0 0x57f00000 0 0x00100000>;
+			record-size = <0x20000>;
+			console-size = <0x40000>;
+			ftrace-size = <0x20000>;
+			pmsg-size = <0x20000>;
+			ecc-size = <16>;
+			status = "ok";
+		};
+	};
+
+	vph_pwr: vph-pwr-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vph_pwr";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	tp_vddio_vreg: tp-vddio-regulator {
+		compatible = "regulator-fixed";
+
+		regulator-name = "tp-vddio";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+
+		gpio = <&tlmm 126 GPIO_ACTIVE_HIGH>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&tp_vddio_en_gpio>;
+	};
+
+	bcm43455_pwr_vreg: wlan-regulator {
+		compatible = "regulator-fixed";
+
+		regulator-name = "wlan-vreg";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 48 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&wl_vreg_on_gpio>;
+	};
+
+	bcm43455_pwrseq: wlan-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&pm8950_gpios 2 GPIO_ACTIVE_LOW>;
+	};
+
+	vibrator {
+		compatible = "gpio-vibrator";
+		enable-gpios = <&pmi8950_gpio 2 GPIO_ACTIVE_HIGH>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&vibrator_ldo_en>;
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		input-name = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		autorepeat;
+
+		button@0 {
+			label = "Volume Up";
+			gpios = <&tlmm 130 GPIO_ACTIVE_LOW>;
+			linux,input-type = <EV_KEY>;
+			linux,code = <KEY_VOLUMEUP>;
+			wakeup-source;
+			debounce-interval = <15>;
+		};
+
+		button@1 {
+			label = "Volume Down";
+			gpios = <&tlmm 113 GPIO_ACTIVE_LOW>;
+			linux,input-type = <EV_KEY>;
+			linux,code = <KEY_VOLUMEDOWN>;
+			wakeup-source;
+			debounce-interval = <15>;
+		};
+
+		button@2 {
+			label = "Camera Focus";
+			gpios = <&tlmm 114 GPIO_ACTIVE_LOW>;
+			linux,input-type = <EV_KEY>;
+			linux,code = <KEY_CAMERA_FOCUS>;
+			wakeup-source;
+			debounce-interval = <15>;
+		};
+
+		button@3 {
+			label = "Camera Snapshot";
+			gpios = <&tlmm 115 GPIO_ACTIVE_LOW>;
+			linux,input-type = <EV_KEY>;
+			linux,code = <KEY_CAMERA>;
+			wakeup-source;
+			wakeup-event-action = <EV_ACT_ASSERTED>;
+			debounce-interval = <15>;
+		};
+	};
+};
+
+&blsp_dma {
+	status = "ok";
+};
+
+&blsp2_dma {
+	status = "ok";
+};
+
+&blsp1_uart1 {
+	status = "disabled";
+};
+
+&blsp1_uart2 {
+	status = "disabled";
+};
+
+&blsp2_uart2 {
+	status = "ok";
+};
+
+/* eMMC */
+&sdhc_1 {
+	vmmc-supply = <&pm8950_l8>;
+	vqmmc-supply = <&pm8950_l5>;
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc1_on>;
+	pinctrl-1 = <&sdc1_off>;
+
+	status = "ok";
+};
+
+/* MicroSD card slot */
+&sdhc_2 {
+	vmmc-supply = <&pm8950_l11>;
+	vqmmc-supply = <&pm8950_l12>;
+	cd-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>;
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc2_on &tray_det_n_gpio>;
+	pinctrl-1 = <&sdc2_off &tray_det_n_gpio>;
+
+	status = "ok";
+};
+
+/* SDIO (internal) to BCM WiFi */
+&sdhc_3 {
+	status = "ok";
+	no-sd;
+	no-mmc;
+
+	bus-width = <4>;
+	max-frequency = <100000000>;
+	keep-power-in-suspend;
+
+	non-removable;
+	wakeup-source;
+	vmmc-supply = <&bcm43455_pwr_vreg>;
+	mmc-pwrseq = <&bcm43455_pwrseq>;
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc3_on &wlan_sleep_pin &wl_host_wake_n_gpio>;
+	pinctrl-1 = <&sdc3_off &wlan_sleep_pin &wl_host_wake_n_gpio>;
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	brcmf: brcmf@1 {
+		reg = <1>;
+		compatible = "brcm,bcm4329-fmac";
+		interrupt-parent = <&tlmm>;
+		interrupts = <45 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-names = "host-wake";
+	};
+};
+
+&blsp_i2c4 {
+	status = "ok";
+
+	rmi4-i2c-dev@2c {
+		compatible = "syna,rmi4-i2c";
+		reg = <0x2c>;
+
+		interrupt-parent = <&tlmm>;
+		interrupts = <65 IRQ_TYPE_EDGE_FALLING>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdd-supply = <&tp_vddio_vreg>;
+
+		syna,reset-delay-ms = <220>;
+		syna,startup-delay-ms = <220>;
+
+		rmi4-f01@1 {
+			reg = <0x1>;
+			syna,nosleep-mode = <1>;
+		};
+
+		rmi4-f12@12 {
+			reg = <0x12>;
+			syna,sensor-type = <1>;
+		};
+	};
+};
+
+&blsp_i2c8 {
+	status = "ok";
+};
+
+&tlmm {
+	gpio-reserved-ranges = <0 4>;
+
+	mdp_vsync_p_gpio: mdp_sync_p_gpio {
+		pins = "gpio24";
+		function = "mdp_vsync";
+
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+
+	disp_reset_n_gpio: disp_reset_n_gpio {
+		pins = "gpio25";
+		function = "gpio";
+
+		drive-strength = <2>;
+		output-high;
+	};
+
+	wl_host_wake_n_gpio: wl_host_wake_n_gpio {
+		pins = "gpio45";
+		function = "gpio";
+
+		drive-strength = <2>;
+		bias-pull-down;
+		input-enable;
+	};
+
+	wl_vreg_on_gpio: wl_vreg_on_gpio {
+		pins = "gpio48";
+		function = "gpio";
+
+		drive-strength = <2>;
+		bias-disable;
+		output-high;
+	};
+
+	tp_reset_n_gpio: tp_reset_n_gpio {
+		pins = "gpio64";
+		function = "gpio";
+
+		drive-strength = <2>;
+	};
+
+	tp_int_n_gpio: tp_int_n_gpio {
+		pins = "gpio65";
+		function = "gpio";
+
+		drive-strength = <2>;
+		bias-pull-up;
+		input-enable;
+	};
+
+	tray_det_n_gpio: tray_det_n_gpio {
+		pins = "gpio100";
+		function = "gpio";
+
+		drive-strength = <2>;
+		bias-disable;
+		input-enable;
+	};
+
+	tp_vddio_en_gpio: tp_vddio_en_gpio {
+		pins = "gpio126";
+		function = "gpio";
+
+		drive-strength = <2>;
+		bias-disable;
+		output-low;
+	};
+
+	sdc1_on: sdc1-on {
+		clk {
+			pins = "sdc1_clk";
+			bias-disable;
+			drive-strength = <16>;
+		};
+
+		cmd {
+			pins = "sdc1_cmd";
+			bias-pull-up;
+			drive-strength = <10>;
+		};
+
+		data {
+			pins = "sdc1_data";
+			bias-pull-up;
+			drive-strength = <10>;
+		};
+
+		rclk {
+			pins = "sdc1_rclk";
+			bias-pull-down;
+		};
+	};
+
+	sdc1_off: sdc1-off {
+		clk {
+			pins = "sdc1_clk";
+			bias-disable;
+			drive-strength = <2>;
+		};
+
+		cmd {
+			pins = "sdc1_cmd";
+			bias-pull-up;
+			drive-strength = <2>;
+		};
+
+		data {
+			pins = "sdc1_data";
+			bias-pull-up;
+			drive-strength = <2>;
+		};
+
+		rclk {
+			pins = "sdc1_rclk";
+			bias-pull-down;
+		};
+	};
+
+	sdc2_on: sdc2-on {
+		clk {
+			pins = "sdc2_clk";
+			bias-disable;
+			drive-strength = <16>;
+		};
+
+		cmd {
+			pins = "sdc2_cmd";
+			bias-pull-up;
+			drive-strength = <10>;
+		};
+
+		data {
+			pins = "sdc2_data";
+			bias-pull-up;
+			drive-strength = <10>;
+		};
+	};
+
+	sdc2_off: sdc2-off {
+		clk {
+			pins = "sdc2_clk";
+			bias-disable;
+			drive-strength = <2>;
+		};
+
+		cmd {
+			pins = "sdc2_cmd";
+			bias-pull-up;
+			drive-strength = <2>;
+		};
+
+		data {
+			pins = "sdc2_data";
+			bias-pull-up;
+			drive-strength = <2>;
+		};
+	};
+
+	sdc3_on: sdc3-on {
+		clk {
+			pins = "gpio44";
+			function = "sdc3";
+			bias-disable;
+			drive-strength = <10>;
+		};
+
+		cmd {
+			pins = "gpio43";
+			function = "sdc3";
+			bias-pull-up;
+			drive-strength = <10>;
+		};
+
+		data {
+			pins = "gpio39", "gpio40", "gpio41", "gpio42";
+			function = "sdc3";
+			bias-pull-up;
+			drive-strength = <10>;
+		};
+	};
+
+	sdc3_off: sdc3-off {
+		clk {
+			pins = "gpio44";
+			function = "sdc3";
+			bias-disable;
+			drive-strength = <2>;
+		};
+
+		cmd {
+			pins = "gpio43";
+			function = "sdc3";
+			bias-pull-up;
+			drive-strength = <2>;
+		};
+
+		data {
+			pins = "gpio39", "gpio40", "gpio41", "gpio42";
+			function = "sdc3";
+			bias-pull-up;
+			drive-strength = <2>;
+		};
+	};
+};
+
+&mdss {
+	vdd-supply = <&pm8950_l17>;
+};
+
+&dsi0 {
+	vdda-supply = <&pm8950_l1>;
+	vddio-supply = <&pm8950_l6>;
+};
+
+&dsi1 {
+	vdda-supply = <&pm8950_l1>;
+	vddio-supply = <&pm8950_l6>;
+};
+
+&dsi_phy0 {
+	vddio-supply = <&pm8950_l6>;
+};
+
+&dsi_phy1 {
+	vddio-supply = <&pm8950_l6>;
+};
+
+&pm8004_lsid5 {
+	status = "ok";
+};
+
+&pm8004_spmi_regulators {
+	vdd_s2-supply = <&vph_pwr>;
+	vdd_s5-supply = <&vph_pwr>;
+
+	/* Cluster 1 supply */
+	pm8004_s2: s2 {
+		/* Set APC1 always-on and raise min voltage to .95V
+		 * until a proper CPU scaling solution lands
+		 */
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-name = "vdd_apc1";
+		regulator-min-microvolt = <950000>; /* 500000 */
+		regulator-max-microvolt = <1165000>;
+	};
+
+	pm8004_s5: s5 {
+		/* Put GFX VDD up at boot until a proper solution lands */
+		regulator-boot-on;
+
+		regulator-name = "vdd_gfx";
+		regulator-min-microvolt = <950000>;
+		regulator-max-microvolt = <1165000>;
+		regulator-enable-ramp-delay = <500>;
+	};
+};
+
+&adreno_gpu {
+	vdd-supply = <&pm8004_s5>;
+};
+
+&pm8950_spmi_regulators {
+	vdd_s5-supply = <&vph_pwr>;
+
+	/* Cluster 0 supply */
+	pm8950_spmi_s5: s5 {
+		/* Set APC0 always-on and raise min voltage to .95V
+		 * until a proper CPU scaling solution lands
+		 */
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-name = "vdd_apc0";
+		regulator-min-microvolt = <950000>; /* 790000 */
+		regulator-max-microvolt = <1165000>;
+	};
+};
+
+&rpm_requests {
+	smd_rpm_regulators: pm8950-rpm-regulators {
+		compatible = "qcom,rpm-pm8950-regulators";
+
+		vdd_s1-supply = <&vph_pwr>;
+		vdd_s2-supply = <&vph_pwr>;
+		vdd_s3-supply = <&vph_pwr>;
+		vdd_s4-supply = <&vph_pwr>;
+		vdd_s5-supply = <&vph_pwr>;
+		vdd_s6-supply = <&vph_pwr>;
+		vdd_l1_l19-supply = <&pm8950_s3>;
+		vdd_l2_l23-supply = <&pm8950_s3>;
+		vdd_l3-supply = <&pm8950_s3>;
+		vdd_l4_l5_l6_l7_l16-supply = <&pm8950_s4>;
+		vdd_l8_l11_l12_l17_l22-supply = <&vph_pwr>;
+		vdd_l20-supply = <&pm8950_s4>;
+		vdd_l21-supply = <&pm8950_s4>;
+
+		pm8950_s1: s1 {
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1162500>;
+		};
+
+		pm8950_s3: s3 {
+			regulator-min-microvolt = <1325000>;
+			regulator-max-microvolt = <1325000>;
+			regulator-always-on;
+		};
+
+		pm8950_s4: s4 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-always-on;
+		};
+
+		pm8950_s5: s5 {};
+
+		pm8950_s6: s6 {};
+
+		pm8950_l1: l1 {
+			regulator-min-microvolt = <900000>;
+			regulator-max-microvolt = <1100000>;
+			regulator-min-microamp = <100>;
+			regulator-max-microamp = <100000>;
+			regulator-enable-ramp-delay = <10>;
+
+			regulator-system-load = <100000>;
+			regulator-allow-set-load;
+		};
+
+		pm8950_l2: l2 {
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+		};
+
+		pm8950_l3: l3 {
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1200000>;
+		};
+
+		pm8950_l5: l5 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+
+			regulator-system-load = <300000>;
+			regulator-allow-set-load;
+		};
+
+		pm8950_l6: l6 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-min-microamp = <100>;
+			regulator-max-microamp = <100000>;
+
+			regulator-system-load = <100000>;
+			regulator-allow-set-load;
+		};
+
+		pm8950_l7: l7 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+
+		pm8950_l8: l8 {
+			regulator-min-microvolt = <2900000>;
+			regulator-max-microvolt = <2900000>;
+
+			regulator-system-load = <550000>;
+			regulator-allow-set-load;
+		};
+
+		pm8950_l9: l9 {
+			regulator-min-microvolt = <2000000>;
+			regulator-max-microvolt = <2400000>;
+		};
+
+		pm8950_l10: l10 {
+			regulator-min-microvolt = <2500000>;
+			regulator-max-microvolt = <2900000>;
+		};
+
+		pm8950_l11: l11 {
+			regulator-min-microvolt = <2950000>;
+			regulator-max-microvolt = <2950000>;
+
+			regulator-system-load = <550000>;
+			regulator-allow-set-load;
+		};
+
+		pm8950_l12: l12 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <2950000>;
+
+			regulator-system-load = <22000>;
+			regulator-allow-set-load;
+		};
+
+		pm8950_l13: l13 {
+			regulator-min-microvolt = <3075000>;
+			regulator-max-microvolt = <3075000>;
+		};
+
+		pm8950_l14: l14 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3300000>;
+		};
+
+		pm8950_l15: l15 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3300000>;
+		};
+
+		pm8950_l16: l16 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+
+		pm8950_l17: l17 {
+			regulator-min-microvolt = <2500000>;
+			regulator-max-microvolt = <2900000>;
+		};
+
+		pm8950_l19: l19 {
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1350000>;
+		};
+
+		pm8950_l22: l22 {
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			regulator-min-microamp = <100>;
+			regulator-max-microamp = <100000>;
+
+			regulator-system-load = <100000>;
+			regulator-allow-set-load;
+		};
+
+		pm8950_l23: l23 {
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-min-microamp = <100>;
+			regulator-max-microamp = <100000>;
+
+			regulator-system-load = <100000>;
+			regulator-allow-set-load;
+		};
+	};
+};
+
+&pm8950_gpios {
+	cdc_pm_mclk_pin: cdc_pm_mclk {
+		pins = "gpio1";
+		function = PMIC_GPIO_FUNC_FUNC1; /* SF1 */
+		output-low;
+		bias-disable;
+		qcom,drive-strength = <PMIC_GPIO_STRENGTH_MED>;
+		power-source = <2>; /* VIN 2 */
+	};
+
+	wlan_sleep_pin: wl_sleep_clk {
+		pins = "gpio2";
+		function = PMIC_GPIO_FUNC_FUNC1; /* SF1 SLEEP_CLK2 */
+		output-high;
+		bias-disable;
+		drive-push-pull;
+		qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+		power-source = <0>; /* VPH_PWR */
+	};
+
+	wcd_eldo_pin: wcd_eldo_en {
+		pins = "gpio7";
+		function = "gpio";
+		output-low;
+		bias-disable;
+		power-source = <0>; /* VPH_PWR */
+	};
+};
+
+&pmi8950_gpio {
+	usb_switch_sel_gpio: usb_switch_sel {
+		pins = "gpio1";
+		function = PMIC_GPIO_FUNC_NORMAL;
+		output-low;
+		drive-push-pull;
+		qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+		power-source = <0>;
+	};
+
+	vibrator_ldo_en: vib_ldo_en {
+		pins = "gpio2";
+		function = PMIC_GPIO_FUNC_NORMAL;
+		output-low;
+		drive-push-pull;
+		qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+		power-source = <0>;
+	};
+};
-- 
2.21.0