* [Intel-gfx] [PATCH] drm/i915: update rawclk also on resume
@ 2019-10-31 11:14 ` Jani Nikula
0 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2019-10-31 11:14 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Since CNP it's possible for rawclk to have two different values, 19.2
and 24 MHz. If the value indicated by SFUSE_STRAP register is different
from the power on default for PCH_RAWCLK_FREQ, we'll end up having a
mismatch between the rawclk hardware and software states after
suspend/resume. On previous platforms this used to work by accident,
because the power on defaults worked just fine.
Update the rawclk also on resume. The natural place to do this is
intel_modeset_init_hw(), however VLV/CHV need it done before
intel_power_domains_init_hw(). Split the update accordingly, even if
that's slighly ugly. This means moving the update later for non-VLV/CHV
platforms in probe.
Reported-by: Shawn Lee <shawn.c.lee@intel.com>
Cc: Shawn Lee <shawn.c.lee@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +++++
drivers/gpu/drm/i915/display/intel_display_power.c | 7 +++++++
drivers/gpu/drm/i915/i915_drv.c | 3 ---
3 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e56a75c07043..e31697fdffd3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -16610,6 +16610,11 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
void intel_modeset_init_hw(struct drm_i915_private *i915)
{
+ /*
+ * VLV/CHV update rawclk earlier in intel_power_domains_init_hw().
+ */
+ if (!IS_VALLEYVIEW(i915) && !IS_CHERRYVIEW(i915))
+ intel_update_rawclk(i915);
intel_update_cdclk(i915);
intel_dump_cdclk_state(&i915->cdclk.hw, "Current CDCLK");
i915->cdclk.logical = i915->cdclk.actual = i915->cdclk.hw;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 707ac110e271..999133d1f088 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5015,6 +5015,13 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
power_domains->initializing = true;
+ /*
+ * Must happen before power domain init on VLV/CHV, the rest update
+ * rawclk later in intel_modeset_init_hw().
+ */
+ if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+ intel_update_rawclk(i915);
+
if (INTEL_GEN(i915) >= 11) {
icl_display_core_init(i915, resume);
} else if (IS_CANNONLAKE(i915)) {
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 21273b516dbe..62906336298a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -296,9 +296,6 @@ static int i915_driver_modeset_probe(struct drm_i915_private *i915)
if (ret)
goto cleanup_vga_client;
- /* must happen before intel_power_domains_init_hw() on VLV/CHV */
- intel_update_rawclk(i915);
-
intel_power_domains_init_hw(i915, false);
intel_csr_ucode_init(i915);
--
2.20.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915: update rawclk also on resume
@ 2019-10-31 13:53 ` Patchwork
0 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-10-31 13:53 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: update rawclk also on resume
URL : https://patchwork.freedesktop.org/series/68817/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7228 -> Patchwork_15088
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/index.html
Known issues
------------
Here are the changes found in Patchwork_15088 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_basic@bad-close:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/fi-icl-u3/igt@gem_basic@bad-close.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/fi-icl-u3/igt@gem_basic@bad-close.html
* igt@gem_ctx_switch@rcs0:
- fi-bxt-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/fi-bxt-dsi/igt@gem_ctx_switch@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/fi-bxt-dsi/igt@gem_ctx_switch@rcs0.html
#### Possible fixes ####
* igt@gem_ctx_create@basic-files:
- fi-icl-u3: [INCOMPLETE][5] ([fdo#107713] / [fdo#109100]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/fi-icl-u3/igt@gem_ctx_create@basic-files.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/fi-icl-u3/igt@gem_ctx_create@basic-files.html
* igt@i915_selftest@live_hangcheck:
- {fi-icl-u4}: [INCOMPLETE][7] ([fdo#107713] / [fdo#108569]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-kbl-7500u: [FAIL][9] ([fdo#109483]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/fi-kbl-7500u/igt@kms_chamelium@hdmi-edid-read.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/fi-kbl-7500u/igt@kms_chamelium@hdmi-edid-read.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][11] ([fdo#111045] / [fdo#111096]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
Participating hosts (50 -> 41)
------------------------------
Additional (1): fi-kbl-soraka
Missing (10): fi-ilk-m540 fi-tgl-u fi-hsw-4200u fi-bsw-n3050 fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-icl-y fi-bsw-kefka fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7228 -> Patchwork_15088
CI-20190529: 20190529
CI_DRM_7228: 5efc505498d2612451f6230a6347f4e0e1960e50 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5253: d46ccb32cf693e8d8253543e9a4fbe5eaef4aa41 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15088: 853a8863d3fe4157cb8f50dafab5b471c3fef978 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
853a8863d3fe drm/i915: update rawclk also on resume
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH] drm/i915: update rawclk also on resume
@ 2019-10-31 13:56 ` Ville Syrjälä
0 siblings, 0 replies; 22+ messages in thread
From: Ville Syrjälä @ 2019-10-31 13:56 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Oct 31, 2019 at 01:14:07PM +0200, Jani Nikula wrote:
> Since CNP it's possible for rawclk to have two different values, 19.2
> and 24 MHz. If the value indicated by SFUSE_STRAP register is different
> from the power on default for PCH_RAWCLK_FREQ, we'll end up having a
> mismatch between the rawclk hardware and software states after
> suspend/resume. On previous platforms this used to work by accident,
> because the power on defaults worked just fine.
>
> Update the rawclk also on resume. The natural place to do this is
> intel_modeset_init_hw(), however VLV/CHV need it done before
> intel_power_domains_init_hw(). Split the update accordingly, even if
> that's slighly ugly. This means moving the update later for non-VLV/CHV
> platforms in probe.
>
> Reported-by: Shawn Lee <shawn.c.lee@intel.com>
> Cc: Shawn Lee <shawn.c.lee@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 5 +++++
> drivers/gpu/drm/i915/display/intel_display_power.c | 7 +++++++
> drivers/gpu/drm/i915/i915_drv.c | 3 ---
> 3 files changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index e56a75c07043..e31697fdffd3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -16610,6 +16610,11 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
>
> void intel_modeset_init_hw(struct drm_i915_private *i915)
> {
> + /*
> + * VLV/CHV update rawclk earlier in intel_power_domains_init_hw().
> + */
> + if (!IS_VALLEYVIEW(i915) && !IS_CHERRYVIEW(i915))
> + intel_update_rawclk(i915);
> intel_update_cdclk(i915);
> intel_dump_cdclk_state(&i915->cdclk.hw, "Current CDCLK");
> i915->cdclk.logical = i915->cdclk.actual = i915->cdclk.hw;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 707ac110e271..999133d1f088 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5015,6 +5015,13 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
>
> power_domains->initializing = true;
>
> + /*
> + * Must happen before power domain init on VLV/CHV, the rest update
> + * rawclk later in intel_modeset_init_hw().
> + */
> + if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> + intel_update_rawclk(i915);
Can't we just do it here unconditionally? I think this gets called on
the resume path as well.
> +
> if (INTEL_GEN(i915) >= 11) {
> icl_display_core_init(i915, resume);
> } else if (IS_CANNONLAKE(i915)) {
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 21273b516dbe..62906336298a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -296,9 +296,6 @@ static int i915_driver_modeset_probe(struct drm_i915_private *i915)
> if (ret)
> goto cleanup_vga_client;
>
> - /* must happen before intel_power_domains_init_hw() on VLV/CHV */
> - intel_update_rawclk(i915);
> -
> intel_power_domains_init_hw(i915, false);
>
> intel_csr_ucode_init(i915);
> --
> 2.20.1
--
Ville Syrjälä
Intel
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [Intel-gfx] [PATCH] drm/i915: update rawclk also on resume
@ 2019-10-31 13:56 ` Ville Syrjälä
0 siblings, 0 replies; 22+ messages in thread
From: Ville Syrjälä @ 2019-10-31 13:56 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Oct 31, 2019 at 01:14:07PM +0200, Jani Nikula wrote:
> Since CNP it's possible for rawclk to have two different values, 19.2
> and 24 MHz. If the value indicated by SFUSE_STRAP register is different
> from the power on default for PCH_RAWCLK_FREQ, we'll end up having a
> mismatch between the rawclk hardware and software states after
> suspend/resume. On previous platforms this used to work by accident,
> because the power on defaults worked just fine.
>
> Update the rawclk also on resume. The natural place to do this is
> intel_modeset_init_hw(), however VLV/CHV need it done before
> intel_power_domains_init_hw(). Split the update accordingly, even if
> that's slighly ugly. This means moving the update later for non-VLV/CHV
> platforms in probe.
>
> Reported-by: Shawn Lee <shawn.c.lee@intel.com>
> Cc: Shawn Lee <shawn.c.lee@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 5 +++++
> drivers/gpu/drm/i915/display/intel_display_power.c | 7 +++++++
> drivers/gpu/drm/i915/i915_drv.c | 3 ---
> 3 files changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index e56a75c07043..e31697fdffd3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -16610,6 +16610,11 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
>
> void intel_modeset_init_hw(struct drm_i915_private *i915)
> {
> + /*
> + * VLV/CHV update rawclk earlier in intel_power_domains_init_hw().
> + */
> + if (!IS_VALLEYVIEW(i915) && !IS_CHERRYVIEW(i915))
> + intel_update_rawclk(i915);
> intel_update_cdclk(i915);
> intel_dump_cdclk_state(&i915->cdclk.hw, "Current CDCLK");
> i915->cdclk.logical = i915->cdclk.actual = i915->cdclk.hw;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 707ac110e271..999133d1f088 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5015,6 +5015,13 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
>
> power_domains->initializing = true;
>
> + /*
> + * Must happen before power domain init on VLV/CHV, the rest update
> + * rawclk later in intel_modeset_init_hw().
> + */
> + if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> + intel_update_rawclk(i915);
Can't we just do it here unconditionally? I think this gets called on
the resume path as well.
> +
> if (INTEL_GEN(i915) >= 11) {
> icl_display_core_init(i915, resume);
> } else if (IS_CANNONLAKE(i915)) {
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 21273b516dbe..62906336298a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -296,9 +296,6 @@ static int i915_driver_modeset_probe(struct drm_i915_private *i915)
> if (ret)
> goto cleanup_vga_client;
>
> - /* must happen before intel_power_domains_init_hw() on VLV/CHV */
> - intel_update_rawclk(i915);
> -
> intel_power_domains_init_hw(i915, false);
>
> intel_csr_ucode_init(i915);
> --
> 2.20.1
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH] drm/i915: update rawclk also on resume
@ 2019-11-01 3:17 ` Lee, Shawn C
0 siblings, 0 replies; 22+ messages in thread
From: Lee, Shawn C @ 2019-11-01 3:17 UTC (permalink / raw)
To: Ville Syrjälä, Nikula, Jani; +Cc: intel-gfx
On Thu, Oct 31, 2019, Ville Syrjala wrote:
>On Thu, Oct 31, 2019 at 01:14:07PM +0200, Jani Nikula wrote:
>> Since CNP it's possible for rawclk to have two different values, 19.2
>> and 24 MHz. If the value indicated by SFUSE_STRAP register is
>> different from the power on default for PCH_RAWCLK_FREQ, we'll end up
>> having a mismatch between the rawclk hardware and software states
>> after suspend/resume. On previous platforms this used to work by
>> accident, because the power on defaults worked just fine.
>>
>> Update the rawclk also on resume. The natural place to do this is
>> intel_modeset_init_hw(), however VLV/CHV need it done before
>> intel_power_domains_init_hw(). Split the update accordingly, even if
>> that's slighly ugly. This means moving the update later for
>> non-VLV/CHV platforms in probe.
>>
>> Reported-by: Shawn Lee <shawn.c.lee@intel.com>
>> Cc: Shawn Lee <shawn.c.lee@intel.com>
>> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_display.c | 5 +++++
>> drivers/gpu/drm/i915/display/intel_display_power.c | 7 +++++++
>> drivers/gpu/drm/i915/i915_drv.c | 3 ---
>> 3 files changed, 12 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> b/drivers/gpu/drm/i915/display/intel_display.c
>> index e56a75c07043..e31697fdffd3 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -16610,6 +16610,11 @@ void intel_init_display_hooks(struct
>> drm_i915_private *dev_priv)
>>
>> void intel_modeset_init_hw(struct drm_i915_private *i915) {
>> + /*
>> + * VLV/CHV update rawclk earlier in intel_power_domains_init_hw().
>> + */
>> + if (!IS_VALLEYVIEW(i915) && !IS_CHERRYVIEW(i915))
>> + intel_update_rawclk(i915);
>> intel_update_cdclk(i915);
>> intel_dump_cdclk_state(&i915->cdclk.hw, "Current CDCLK");
>> i915->cdclk.logical = i915->cdclk.actual = i915->cdclk.hw; diff
>> --git a/drivers/gpu/drm/i915/display/intel_display_power.c
>> b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index 707ac110e271..999133d1f088 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -5015,6 +5015,13 @@ void intel_power_domains_init_hw(struct
>> drm_i915_private *i915, bool resume)
>>
>> power_domains->initializing = true;
>>
>> + /*
>> + * Must happen before power domain init on VLV/CHV, the rest update
>> + * rawclk later in intel_modeset_init_hw().
>> + */
>> + if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
>> + intel_update_rawclk(i915);
>
>Can't we just do it here unconditionally? I think this gets called on the resume path as well.
>
Try to do intel_update_rawclk() here and remove it at intel_modeset_init_hw() and i915_driver_modeset_probe().
Here will be executed before intel_modeset_init_hw(). So it looks good to me just do it here.
Best regards,
Shawn
>> +
>> if (INTEL_GEN(i915) >= 11) {
>> icl_display_core_init(i915, resume);
>> } else if (IS_CANNONLAKE(i915)) {
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c
>> b/drivers/gpu/drm/i915/i915_drv.c index 21273b516dbe..62906336298a
>> 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -296,9 +296,6 @@ static int i915_driver_modeset_probe(struct drm_i915_private *i915)
>> if (ret)
>> goto cleanup_vga_client;
>>
>> - /* must happen before intel_power_domains_init_hw() on VLV/CHV */
>> - intel_update_rawclk(i915);
>> -
>> intel_power_domains_init_hw(i915, false);
>>
>> intel_csr_ucode_init(i915);
>> --
>> 2.20.1
>
>--
>Ville Syrjälä
>Intel
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [Intel-gfx] [PATCH] drm/i915: update rawclk also on resume
@ 2019-11-01 3:17 ` Lee, Shawn C
0 siblings, 0 replies; 22+ messages in thread
From: Lee, Shawn C @ 2019-11-01 3:17 UTC (permalink / raw)
To: Ville Syrjälä, Nikula, Jani; +Cc: intel-gfx
On Thu, Oct 31, 2019, Ville Syrjala wrote:
>On Thu, Oct 31, 2019 at 01:14:07PM +0200, Jani Nikula wrote:
>> Since CNP it's possible for rawclk to have two different values, 19.2
>> and 24 MHz. If the value indicated by SFUSE_STRAP register is
>> different from the power on default for PCH_RAWCLK_FREQ, we'll end up
>> having a mismatch between the rawclk hardware and software states
>> after suspend/resume. On previous platforms this used to work by
>> accident, because the power on defaults worked just fine.
>>
>> Update the rawclk also on resume. The natural place to do this is
>> intel_modeset_init_hw(), however VLV/CHV need it done before
>> intel_power_domains_init_hw(). Split the update accordingly, even if
>> that's slighly ugly. This means moving the update later for
>> non-VLV/CHV platforms in probe.
>>
>> Reported-by: Shawn Lee <shawn.c.lee@intel.com>
>> Cc: Shawn Lee <shawn.c.lee@intel.com>
>> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_display.c | 5 +++++
>> drivers/gpu/drm/i915/display/intel_display_power.c | 7 +++++++
>> drivers/gpu/drm/i915/i915_drv.c | 3 ---
>> 3 files changed, 12 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> b/drivers/gpu/drm/i915/display/intel_display.c
>> index e56a75c07043..e31697fdffd3 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -16610,6 +16610,11 @@ void intel_init_display_hooks(struct
>> drm_i915_private *dev_priv)
>>
>> void intel_modeset_init_hw(struct drm_i915_private *i915) {
>> + /*
>> + * VLV/CHV update rawclk earlier in intel_power_domains_init_hw().
>> + */
>> + if (!IS_VALLEYVIEW(i915) && !IS_CHERRYVIEW(i915))
>> + intel_update_rawclk(i915);
>> intel_update_cdclk(i915);
>> intel_dump_cdclk_state(&i915->cdclk.hw, "Current CDCLK");
>> i915->cdclk.logical = i915->cdclk.actual = i915->cdclk.hw; diff
>> --git a/drivers/gpu/drm/i915/display/intel_display_power.c
>> b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index 707ac110e271..999133d1f088 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -5015,6 +5015,13 @@ void intel_power_domains_init_hw(struct
>> drm_i915_private *i915, bool resume)
>>
>> power_domains->initializing = true;
>>
>> + /*
>> + * Must happen before power domain init on VLV/CHV, the rest update
>> + * rawclk later in intel_modeset_init_hw().
>> + */
>> + if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
>> + intel_update_rawclk(i915);
>
>Can't we just do it here unconditionally? I think this gets called on the resume path as well.
>
Try to do intel_update_rawclk() here and remove it at intel_modeset_init_hw() and i915_driver_modeset_probe().
Here will be executed before intel_modeset_init_hw(). So it looks good to me just do it here.
Best regards,
Shawn
>> +
>> if (INTEL_GEN(i915) >= 11) {
>> icl_display_core_init(i915, resume);
>> } else if (IS_CANNONLAKE(i915)) {
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c
>> b/drivers/gpu/drm/i915/i915_drv.c index 21273b516dbe..62906336298a
>> 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -296,9 +296,6 @@ static int i915_driver_modeset_probe(struct drm_i915_private *i915)
>> if (ret)
>> goto cleanup_vga_client;
>>
>> - /* must happen before intel_power_domains_init_hw() on VLV/CHV */
>> - intel_update_rawclk(i915);
>> -
>> intel_power_domains_init_hw(i915, false);
>>
>> intel_csr_ucode_init(i915);
>> --
>> 2.20.1
>
>--
>Ville Syrjälä
>Intel
>
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^ permalink raw reply [flat|nested] 22+ messages in thread
* ✗ Fi.CI.BUILD: failure for drm/i915: update rawclk also on resume (rev2)
@ 2019-11-01 6:56 ` Patchwork
0 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-11-01 6:56 UTC (permalink / raw)
To: Lee Shawn C; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: update rawclk also on resume (rev2)
URL : https://patchwork.freedesktop.org/series/68817/
State : failure
== Summary ==
Applying: drm/i915: update rawclk also on resume
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/display/intel_display_power.c
M drivers/gpu/drm/i915/i915_drv.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/i915_drv.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_drv.c
Auto-merging drivers/gpu/drm/i915/display/intel_display_power.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch' to see the failed patch
Patch failed at 0001 drm/i915: update rawclk also on resume
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: update rawclk also on resume (rev2)
@ 2019-11-01 6:56 ` Patchwork
0 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-11-01 6:56 UTC (permalink / raw)
To: Lee Shawn C; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: update rawclk also on resume (rev2)
URL : https://patchwork.freedesktop.org/series/68817/
State : failure
== Summary ==
Applying: drm/i915: update rawclk also on resume
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/display/intel_display_power.c
M drivers/gpu/drm/i915/i915_drv.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/i915_drv.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_drv.c
Auto-merging drivers/gpu/drm/i915/display/intel_display_power.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch' to see the failed patch
Patch failed at 0001 drm/i915: update rawclk also on resume
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: update rawclk also on resume (rev3)
@ 2019-11-01 9:03 ` Patchwork
0 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-11-01 9:03 UTC (permalink / raw)
To: Lee Shawn C; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: update rawclk also on resume (rev3)
URL : https://patchwork.freedesktop.org/series/68817/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
16aa0cf9fc99 drm/i915: update rawclk also on resume
-:20: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#20:
be configured with proper setting and executed before intel_modeset_init_hw().
total: 0 errors, 1 warnings, 0 checks, 21 lines checked
_______________________________________________
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^ permalink raw reply [flat|nested] 22+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: update rawclk also on resume (rev3)
@ 2019-11-01 9:33 ` Patchwork
0 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-11-01 9:33 UTC (permalink / raw)
To: Lee Shawn C; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: update rawclk also on resume (rev3)
URL : https://patchwork.freedesktop.org/series/68817/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7236 -> Patchwork_15100
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15100/index.html
Known issues
------------
Here are the changes found in Patchwork_15100 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_switch@legacy-render:
- fi-icl-u2: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7236/fi-icl-u2/igt@gem_ctx_switch@legacy-render.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15100/fi-icl-u2/igt@gem_ctx_switch@legacy-render.html
* igt@gem_exec_reloc@basic-cpu-active:
- fi-kbl-soraka: [PASS][3] -> [DMESG-WARN][4] ([fdo#106107])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7236/fi-kbl-soraka/igt@gem_exec_reloc@basic-cpu-active.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15100/fi-kbl-soraka/igt@gem_exec_reloc@basic-cpu-active.html
* igt@gem_mmap_gtt@basic-read-write-distinct:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7236/fi-icl-u3/igt@gem_mmap_gtt@basic-read-write-distinct.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15100/fi-icl-u3/igt@gem_mmap_gtt@basic-read-write-distinct.html
#### Possible fixes ####
* igt@gem_mmap@basic-small-bo:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7236/fi-icl-u3/igt@gem_mmap@basic-small-bo.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15100/fi-icl-u3/igt@gem_mmap@basic-small-bo.html
* igt@gem_mmap_gtt@basic-write-cpu-read-gtt:
- {fi-icl-dsi}: [DMESG-WARN][9] ([fdo#106107]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7236/fi-icl-dsi/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15100/fi-icl-dsi/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html
* igt@i915_selftest@live_blt:
- fi-bsw-n3050: [DMESG-FAIL][11] ([fdo#112176]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7236/fi-bsw-n3050/igt@i915_selftest@live_blt.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15100/fi-bsw-n3050/igt@i915_selftest@live_blt.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][13] ([fdo#111407]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7236/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15100/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [DMESG-WARN][15] ([fdo#102614]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7236/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15100/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#112176]: https://bugs.freedesktop.org/show_bug.cgi?id=112176
Participating hosts (51 -> 46)
------------------------------
Additional (3): fi-tgl-u fi-tgl-y fi-tgl-u2
Missing (8): fi-icl-u4 fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7236 -> Patchwork_15100
CI-20190529: 20190529
CI_DRM_7236: 98f73fdd2c8b82607cdc155c338293f9cce1aec2 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5257: 57efd81037861a68e2f04186fec7a4f2a3a2cf6f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15100: 16aa0cf9fc99c90367e96062f252d8e25add2ad7 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
16aa0cf9fc99 drm/i915: update rawclk also on resume
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15100/index.html
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* ✓ Fi.CI.IGT: success for drm/i915: update rawclk also on resume
@ 2019-11-01 13:18 ` Patchwork
0 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-11-01 13:18 UTC (permalink / raw)
To: Lee Shawn C; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: update rawclk also on resume
URL : https://patchwork.freedesktop.org/series/68817/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7228_full -> Patchwork_15088_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_15088_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@bcs0-s3:
- shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-apl2/igt@gem_ctx_isolation@bcs0-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-apl6/igt@gem_ctx_isolation@bcs0-s3.html
* igt@gem_ctx_isolation@rcs0-s3:
- shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +8 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-kbl2/igt@gem_ctx_isolation@rcs0-s3.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-kbl4/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_ctx_isolation@vcs1-dirty-switch:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276] / [fdo#112080])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-iclb2/igt@gem_ctx_isolation@vcs1-dirty-switch.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-iclb5/igt@gem_ctx_isolation@vcs1-dirty-switch.html
* igt@gem_exec_parallel@vcs1-fds:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#112080]) +10 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-iclb4/igt@gem_exec_parallel@vcs1-fds.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-iclb8/igt@gem_exec_parallel@vcs1-fds.html
* igt@gem_exec_schedule@independent-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#112146]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-iclb7/igt@gem_exec_schedule@independent-bsd.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-iclb4/igt@gem_exec_schedule@independent-bsd.html
* igt@gem_exec_schedule@preempt-contexts-bsd2:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276]) +14 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-iclb4/igt@gem_exec_schedule@preempt-contexts-bsd2.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-iclb6/igt@gem_exec_schedule@preempt-contexts-bsd2.html
* igt@gem_partial_pwrite_pread@writes-after-reads-snoop:
- shard-apl: [PASS][13] -> [INCOMPLETE][14] ([fdo#103927]) +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-apl4/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-apl6/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html
* igt@gem_userptr_blits@sync-unmap:
- shard-hsw: [PASS][15] -> [DMESG-WARN][16] ([fdo#111870])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-hsw1/igt@gem_userptr_blits@sync-unmap.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-hsw5/igt@gem_userptr_blits@sync-unmap.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-snb: [PASS][17] -> [DMESG-WARN][18] ([fdo#111870]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-snb4/igt@gem_userptr_blits@sync-unmap-cycles.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-snb4/igt@gem_userptr_blits@sync-unmap-cycles.html
* igt@kms_cursor_legacy@all-pipes-torture-move:
- shard-glk: [PASS][19] -> [DMESG-WARN][20] ([fdo#105763] / [fdo#106538])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-glk4/igt@kms_cursor_legacy@all-pipes-torture-move.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-glk5/igt@kms_cursor_legacy@all-pipes-torture-move.html
* igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible:
- shard-hsw: [PASS][21] -> [INCOMPLETE][22] ([fdo#103540])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-hsw4/igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-hsw8/igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [PASS][23] -> [FAIL][24] ([fdo#103167]) +7 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_psr@psr2_sprite_plane_onoff:
- shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109441])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-iclb2/igt@kms_psr@psr2_sprite_plane_onoff.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-iclb7/igt@kms_psr@psr2_sprite_plane_onoff.html
#### Possible fixes ####
* igt@gem_ctx_isolation@vcs1-clean:
- shard-iclb: [SKIP][27] ([fdo#109276] / [fdo#112080]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-iclb6/igt@gem_ctx_isolation@vcs1-clean.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-iclb2/igt@gem_ctx_isolation@vcs1-clean.html
* {igt@gem_ctx_persistence@bcs0-queued}:
- {shard-tglb}: [FAIL][29] ([fdo#112180]) -> [PASS][30] +2 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-tglb8/igt@gem_ctx_persistence@bcs0-queued.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-tglb7/igt@gem_ctx_persistence@bcs0-queued.html
* igt@gem_ctx_switch@vcs1-heavy-queue:
- shard-iclb: [SKIP][31] ([fdo#112080]) -> [PASS][32] +6 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-iclb6/igt@gem_ctx_switch@vcs1-heavy-queue.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-iclb2/igt@gem_ctx_switch@vcs1-heavy-queue.html
* igt@gem_exec_params@invalid-bsd-ring:
- shard-iclb: [SKIP][33] ([fdo#109276]) -> [PASS][34] +3 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-iclb8/igt@gem_exec_params@invalid-bsd-ring.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-iclb4/igt@gem_exec_params@invalid-bsd-ring.html
* igt@gem_exec_schedule@reorder-wide-blt:
- {shard-tglb}: [INCOMPLETE][35] ([fdo#111747]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-tglb2/igt@gem_exec_schedule@reorder-wide-blt.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-tglb4/igt@gem_exec_schedule@reorder-wide-blt.html
* igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [SKIP][37] ([fdo#112146]) -> [PASS][38] +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-iclb4/igt@gem_exec_schedule@reorder-wide-bsd.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-iclb5/igt@gem_exec_schedule@reorder-wide-bsd.html
* igt@gem_exec_suspend@basic-s3-devices:
- {shard-tglb}: [INCOMPLETE][39] ([fdo#111832] / [fdo#111850]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-tglb5/igt@gem_exec_suspend@basic-s3-devices.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-tglb2/igt@gem_exec_suspend@basic-s3-devices.html
* igt@gem_mocs_settings@mocs-rc6-bsd2:
- {shard-tglb}: [TIMEOUT][41] ([fdo#112126]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-tglb7/igt@gem_mocs_settings@mocs-rc6-bsd2.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-tglb3/igt@gem_mocs_settings@mocs-rc6-bsd2.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
- shard-hsw: [DMESG-WARN][43] ([fdo#111870]) -> [PASS][44] +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-hsw8/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-hsw5/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-snb: [DMESG-WARN][45] ([fdo#111870]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* {igt@i915_pm_dc@dc6-psr}:
- shard-iclb: [FAIL][47] ([fdo#110548]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-iclb8/igt@i915_pm_dc@dc6-psr.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [DMESG-WARN][49] ([fdo#108566]) -> [PASS][50] +4 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-apl4/igt@i915_suspend@sysfs-reader.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-apl2/igt@i915_suspend@sysfs-reader.html
* igt@kms_color@pipe-b-ctm-0-75:
- shard-skl: [DMESG-WARN][51] ([fdo#106107]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-skl7/igt@kms_color@pipe-b-ctm-0-75.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-skl10/igt@kms_color@pipe-b-ctm-0-75.html
* igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen:
- shard-hsw: [INCOMPLETE][53] ([fdo#103540]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-hsw7/igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-hsw8/igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen.html
* igt@kms_cursor_edge_walk@pipe-b-64x64-bottom-edge:
- {shard-tglb}: [INCOMPLETE][55] ([fdo#112035 ]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-tglb8/igt@kms_cursor_edge_walk@pipe-b-64x64-bottom-edge.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-tglb4/igt@kms_cursor_edge_walk@pipe-b-64x64-bottom-edge.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
- {shard-tglb}: [TIMEOUT][57] ([fdo#112168]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-tglb7/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-tglb3/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
* igt@kms_flip@flip-vs-suspend:
- shard-skl: [INCOMPLETE][59] ([fdo#109507]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-skl4/igt@kms_flip@flip-vs-suspend.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-skl2/igt@kms_flip@flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [DMESG-WARN][61] ([fdo#108566]) -> [PASS][62] +4 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-suspend.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
- shard-iclb: [FAIL][63] ([fdo#103167]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary:
- {shard-tglb}: [FAIL][65] ([fdo#103167]) -> [PASS][66] +3 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- {shard-tglb}: [DMESG-WARN][67] ([fdo#111600]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-tglb1/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-tglb2/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [SKIP][69] ([fdo#109441]) -> [PASS][70] +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-iclb1/igt@kms_psr@psr2_cursor_blt.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-apl: [INCOMPLETE][71] ([fdo#103927]) -> [PASS][72] +1 similar issue
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-apl1/igt@kms_rotation_crc@multiplane-rotation-cropping-bottom.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-apl8/igt@kms_rotation_crc@multiplane-rotation-cropping-bottom.html
* igt@kms_setmode@basic:
- shard-glk: [FAIL][73] ([fdo#99912]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-glk8/igt@kms_setmode@basic.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-glk4/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- {shard-tglb}: [INCOMPLETE][75] ([fdo#111850]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-tglb2/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-tglb4/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-settings-bsd2:
- shard-iclb: [FAIL][77] ([fdo#111330]) -> [SKIP][78] ([fdo#109276]) +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-iclb2/igt@gem_mocs_settings@mocs-settings-bsd2.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-iclb7/igt@gem_mocs_settings@mocs-settings-bsd2.html
* igt@kms_flip@flip-vs-suspend:
- shard-kbl: [INCOMPLETE][79] ([fdo#103665]) -> [DMESG-WARN][80] ([fdo#108566])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/shard-kbl7/igt@kms_flip@flip-vs-suspend.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/shard-kbl2/igt@kms_flip@flip-vs-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo# 112000 ]: https://bugs.freedesktop.org/show_bug.cgi?id= 112000
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108838]: https://bugs.freedesktop.org/show_bug.cgi?id=108838
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#110548]: https://bugs.freedesktop.org/show_bug.cgi?id=110548
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
[fdo#111606]: https://bugs.freedesktop.org/show_bug.cgi?id=111606
[fdo#111646]: https://bugs.freedesktop.org/show_bug.cgi?id=111646
[fdo#111671]: https://bugs.freedesktop.org/show_bug.cgi?id=111671
[fdo#111677]: https://bugs.freedesktop.org/show_bug.cgi?id=111677
[fdo#111703]: https://bugs.freedesktop.org/show_bug.cgi?id=111703
[fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
[fdo#111781]: https://bugs.freedesktop.org/show_bug.cgi?id=111781
[fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832
[fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
[fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
[fdo#111884]: https://bugs.freedesktop.org/show_bug.cgi?id=111884
[fdo#112035 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112035
[fdo#112068 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112068
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112126]: https://bugs.freedesktop.org/show_bug.cgi?id=112126
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[fdo#112168]: https://bugs.freedesktop.org/show_bug.cgi?id=112168
[fdo#112180]: https://bugs.freedesktop.org/show_bug.cgi?id=112180
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7228 -> Patchwork_15088
CI-20190529: 20190529
CI_DRM_7228: 5efc505498d2612451f6230a6347f4e0e1960e50 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5253: d46ccb32cf693e8d8253543e9a4fbe5eaef4aa41 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15088: 853a8863d3fe4157cb8f50dafab5b471c3fef978 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH v2] drm/i915: update rawclk also on resume
@ 2019-11-01 14:45 ` Lee Shawn C
0 siblings, 0 replies; 22+ messages in thread
From: Lee Shawn C @ 2019-11-01 14:45 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Since CNP it's possible for rawclk to have two different values, 19.2
and 24 MHz. If the value indicated by SFUSE_STRAP register is different
from the power on default for PCH_RAWCLK_FREQ, we'll end up having a
mismatch between the rawclk hardware and software states after
suspend/resume. On previous platforms this used to work by accident,
because the power on defaults worked just fine.
Update the rawclk also on resume. The natural place to do this is
intel_modeset_init_hw(), however VLV/CHV need it done before
intel_power_domains_init_hw(). Split the update accordingly, even if
that's slighly ugly. This means moving the update later for non-VLV/CHV
platforms in probe.
v2: Do intel_update_rawclk() at intel_power_domains_init_hw(). Rawclk will
be configured with proper setting and executed before intel_modeset_init_hw().
Reported-by: Shawn Lee <shawn.c.lee@intel.com>
Cc: Shawn Lee <shawn.c.lee@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 6 ++++++
drivers/gpu/drm/i915/i915_drv.c | 3 ---
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index dd2a50b8ba0a..089ba6cbb348 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4914,6 +4914,12 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
power_domains->initializing = true;
+ /*
+ * Must happen before power domain init on VLV/CHV, the rest update
+ * rawclk can be done here as well.
+ */
+ intel_update_rawclk(i915);
+
if (INTEL_GEN(i915) >= 11) {
icl_display_core_init(i915, resume);
} else if (IS_CANNONLAKE(i915)) {
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f2d3d754af37..1f36e3c3f967 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -716,9 +716,6 @@ static int i915_driver_modeset_probe(struct drm_device *dev)
if (ret)
goto cleanup_vga_client;
- /* must happen before intel_power_domains_init_hw() on VLV/CHV */
- intel_update_rawclk(dev_priv);
-
intel_power_domains_init_hw(dev_priv, false);
intel_csr_ucode_init(dev_priv);
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* [Intel-gfx] [PATCH v2] drm/i915: update rawclk also on resume
@ 2019-11-01 14:45 ` Lee Shawn C
0 siblings, 0 replies; 22+ messages in thread
From: Lee Shawn C @ 2019-11-01 14:45 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Since CNP it's possible for rawclk to have two different values, 19.2
and 24 MHz. If the value indicated by SFUSE_STRAP register is different
from the power on default for PCH_RAWCLK_FREQ, we'll end up having a
mismatch between the rawclk hardware and software states after
suspend/resume. On previous platforms this used to work by accident,
because the power on defaults worked just fine.
Update the rawclk also on resume. The natural place to do this is
intel_modeset_init_hw(), however VLV/CHV need it done before
intel_power_domains_init_hw(). Split the update accordingly, even if
that's slighly ugly. This means moving the update later for non-VLV/CHV
platforms in probe.
v2: Do intel_update_rawclk() at intel_power_domains_init_hw(). Rawclk will
be configured with proper setting and executed before intel_modeset_init_hw().
Reported-by: Shawn Lee <shawn.c.lee@intel.com>
Cc: Shawn Lee <shawn.c.lee@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 6 ++++++
drivers/gpu/drm/i915/i915_drv.c | 3 ---
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index dd2a50b8ba0a..089ba6cbb348 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4914,6 +4914,12 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
power_domains->initializing = true;
+ /*
+ * Must happen before power domain init on VLV/CHV, the rest update
+ * rawclk can be done here as well.
+ */
+ intel_update_rawclk(i915);
+
if (INTEL_GEN(i915) >= 11) {
icl_display_core_init(i915, resume);
} else if (IS_CANNONLAKE(i915)) {
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f2d3d754af37..1f36e3c3f967 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -716,9 +716,6 @@ static int i915_driver_modeset_probe(struct drm_device *dev)
if (ret)
goto cleanup_vga_client;
- /* must happen before intel_power_domains_init_hw() on VLV/CHV */
- intel_update_rawclk(dev_priv);
-
intel_power_domains_init_hw(dev_priv, false);
intel_csr_ucode_init(dev_priv);
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v3] drm/i915: update rawclk also on resume
@ 2019-11-01 16:29 ` Lee Shawn C
0 siblings, 0 replies; 22+ messages in thread
From: Lee Shawn C @ 2019-11-01 16:29 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Since CNP it's possible for rawclk to have two different values, 19.2
and 24 MHz. If the value indicated by SFUSE_STRAP register is different
from the power on default for PCH_RAWCLK_FREQ, we'll end up having a
mismatch between the rawclk hardware and software states after
suspend/resume. On previous platforms this used to work by accident,
because the power on defaults worked just fine.
Update the rawclk also on resume. The natural place to do this is
intel_modeset_init_hw(), however VLV/CHV need it done before
intel_power_domains_init_hw(). Split the update accordingly, even if
that's slighly ugly. This means moving the update later for non-VLV/CHV
platforms in probe.
v2: Do intel_update_rawclk() at intel_power_domains_init_hw(). Rawclk will
be configured with proper setting and executed before intel_modeset_init_hw().
v3: Update code base to latest to fix git merge failed.
Reported-by: Shawn Lee <shawn.c.lee@intel.com>
Cc: Shawn Lee <shawn.c.lee@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 6 ++++++
drivers/gpu/drm/i915/i915_drv.c | 3 ---
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 707ac110e271..21a95d181a20 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5015,6 +5015,12 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
power_domains->initializing = true;
+ /*
+ * Must happen before power domain init on VLV/CHV, the rest update
+ * rawclk can be done here as well.
+ */
+ intel_update_rawclk(i915);
+
if (INTEL_GEN(i915) >= 11) {
icl_display_core_init(i915, resume);
} else if (IS_CANNONLAKE(i915)) {
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 480e2054f628..b26b4457339c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -296,9 +296,6 @@ static int i915_driver_modeset_probe(struct drm_i915_private *i915)
if (ret)
goto cleanup_vga_client;
- /* must happen before intel_power_domains_init_hw() on VLV/CHV */
- intel_update_rawclk(i915);
-
intel_power_domains_init_hw(i915, false);
intel_csr_ucode_init(i915);
--
2.17.1
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [Intel-gfx] [PATCH v3] drm/i915: update rawclk also on resume
@ 2019-11-01 16:29 ` Lee Shawn C
0 siblings, 0 replies; 22+ messages in thread
From: Lee Shawn C @ 2019-11-01 16:29 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Since CNP it's possible for rawclk to have two different values, 19.2
and 24 MHz. If the value indicated by SFUSE_STRAP register is different
from the power on default for PCH_RAWCLK_FREQ, we'll end up having a
mismatch between the rawclk hardware and software states after
suspend/resume. On previous platforms this used to work by accident,
because the power on defaults worked just fine.
Update the rawclk also on resume. The natural place to do this is
intel_modeset_init_hw(), however VLV/CHV need it done before
intel_power_domains_init_hw(). Split the update accordingly, even if
that's slighly ugly. This means moving the update later for non-VLV/CHV
platforms in probe.
v2: Do intel_update_rawclk() at intel_power_domains_init_hw(). Rawclk will
be configured with proper setting and executed before intel_modeset_init_hw().
v3: Update code base to latest to fix git merge failed.
Reported-by: Shawn Lee <shawn.c.lee@intel.com>
Cc: Shawn Lee <shawn.c.lee@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 6 ++++++
drivers/gpu/drm/i915/i915_drv.c | 3 ---
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 707ac110e271..21a95d181a20 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5015,6 +5015,12 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
power_domains->initializing = true;
+ /*
+ * Must happen before power domain init on VLV/CHV, the rest update
+ * rawclk can be done here as well.
+ */
+ intel_update_rawclk(i915);
+
if (INTEL_GEN(i915) >= 11) {
icl_display_core_init(i915, resume);
} else if (IS_CANNONLAKE(i915)) {
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 480e2054f628..b26b4457339c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -296,9 +296,6 @@ static int i915_driver_modeset_probe(struct drm_i915_private *i915)
if (ret)
goto cleanup_vga_client;
- /* must happen before intel_power_domains_init_hw() on VLV/CHV */
- intel_update_rawclk(i915);
-
intel_power_domains_init_hw(i915, false);
intel_csr_ucode_init(i915);
--
2.17.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3] drm/i915: update rawclk also on resume
@ 2019-11-01 14:24 ` Jani Nikula
0 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2019-11-01 14:24 UTC (permalink / raw)
To: Lee Shawn C, intel-gfx
On Sat, 02 Nov 2019, Lee Shawn C <shawn.c.lee@intel.com> wrote:
> Since CNP it's possible for rawclk to have two different values, 19.2
> and 24 MHz. If the value indicated by SFUSE_STRAP register is different
> from the power on default for PCH_RAWCLK_FREQ, we'll end up having a
> mismatch between the rawclk hardware and software states after
> suspend/resume. On previous platforms this used to work by accident,
> because the power on defaults worked just fine.
>
> Update the rawclk also on resume. The natural place to do this is
> intel_modeset_init_hw(), however VLV/CHV need it done before
> intel_power_domains_init_hw(). Split the update accordingly, even if
> that's slighly ugly. This means moving the update later for non-VLV/CHV
> platforms in probe.
>
> v2: Do intel_update_rawclk() at intel_power_domains_init_hw(). Rawclk will
> be configured with proper setting and executed before intel_modeset_init_hw().
> v3: Update code base to latest to fix git merge failed.
>
> Reported-by: Shawn Lee <shawn.c.lee@intel.com>
> Cc: Shawn Lee <shawn.c.lee@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
Please don't change the authorship of patches when you make new versions
of them, especially so if the changes are neglible. 90% of the work in
the original was writing the commit message, and here the commit message
no longer matches the actual change.
My v2 of the patch is [1].
BR,
Jani.
[1] http://patchwork.freedesktop.org/patch/msgid/20191101142024.13877-1-jani.nikula@intel.com
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 6 ++++++
> drivers/gpu/drm/i915/i915_drv.c | 3 ---
> 2 files changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 707ac110e271..21a95d181a20 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5015,6 +5015,12 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
>
> power_domains->initializing = true;
>
> + /*
> + * Must happen before power domain init on VLV/CHV, the rest update
> + * rawclk can be done here as well.
> + */
> + intel_update_rawclk(i915);
> +
> if (INTEL_GEN(i915) >= 11) {
> icl_display_core_init(i915, resume);
> } else if (IS_CANNONLAKE(i915)) {
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 480e2054f628..b26b4457339c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -296,9 +296,6 @@ static int i915_driver_modeset_probe(struct drm_i915_private *i915)
> if (ret)
> goto cleanup_vga_client;
>
> - /* must happen before intel_power_domains_init_hw() on VLV/CHV */
> - intel_update_rawclk(i915);
> -
> intel_power_domains_init_hw(i915, false);
>
> intel_csr_ucode_init(i915);
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [Intel-gfx] [PATCH v3] drm/i915: update rawclk also on resume
@ 2019-11-01 14:24 ` Jani Nikula
0 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2019-11-01 14:24 UTC (permalink / raw)
To: Lee Shawn C, intel-gfx
On Sat, 02 Nov 2019, Lee Shawn C <shawn.c.lee@intel.com> wrote:
> Since CNP it's possible for rawclk to have two different values, 19.2
> and 24 MHz. If the value indicated by SFUSE_STRAP register is different
> from the power on default for PCH_RAWCLK_FREQ, we'll end up having a
> mismatch between the rawclk hardware and software states after
> suspend/resume. On previous platforms this used to work by accident,
> because the power on defaults worked just fine.
>
> Update the rawclk also on resume. The natural place to do this is
> intel_modeset_init_hw(), however VLV/CHV need it done before
> intel_power_domains_init_hw(). Split the update accordingly, even if
> that's slighly ugly. This means moving the update later for non-VLV/CHV
> platforms in probe.
>
> v2: Do intel_update_rawclk() at intel_power_domains_init_hw(). Rawclk will
> be configured with proper setting and executed before intel_modeset_init_hw().
> v3: Update code base to latest to fix git merge failed.
>
> Reported-by: Shawn Lee <shawn.c.lee@intel.com>
> Cc: Shawn Lee <shawn.c.lee@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
Please don't change the authorship of patches when you make new versions
of them, especially so if the changes are neglible. 90% of the work in
the original was writing the commit message, and here the commit message
no longer matches the actual change.
My v2 of the patch is [1].
BR,
Jani.
[1] http://patchwork.freedesktop.org/patch/msgid/20191101142024.13877-1-jani.nikula@intel.com
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 6 ++++++
> drivers/gpu/drm/i915/i915_drv.c | 3 ---
> 2 files changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 707ac110e271..21a95d181a20 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5015,6 +5015,12 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
>
> power_domains->initializing = true;
>
> + /*
> + * Must happen before power domain init on VLV/CHV, the rest update
> + * rawclk can be done here as well.
> + */
> + intel_update_rawclk(i915);
> +
> if (INTEL_GEN(i915) >= 11) {
> icl_display_core_init(i915, resume);
> } else if (IS_CANNONLAKE(i915)) {
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 480e2054f628..b26b4457339c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -296,9 +296,6 @@ static int i915_driver_modeset_probe(struct drm_i915_private *i915)
> if (ret)
> goto cleanup_vga_client;
>
> - /* must happen before intel_power_domains_init_hw() on VLV/CHV */
> - intel_update_rawclk(i915);
> -
> intel_power_domains_init_hw(i915, false);
>
> intel_csr_ucode_init(i915);
--
Jani Nikula, Intel Open Source Graphics Center
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread