From: Thierry Reding <thierry.reding@gmail.com> Cc: Sowjanya Komatineni <skomatineni@nvidia.com>, jonathanh@nvidia.com, tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, linus.walleij@linaro.org, stefan@agner.ch, mark.rutland@arm.com, pdeschrijver@nvidia.com, pgaikwad@nvidia.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, jckuo@nvidia.com, josephl@nvidia.com, talho@nvidia.com, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, mperttunen@nvidia.com, spatra@nvidia.com, robh+dt@kernel.org, digetx@gmail.com, devicetree@vger.kernel.org, rjw@rjwysocki.net, viresh.kumar@linaro.org, linux-pm@vger.kernel.org Subject: Re: [PATCH v9 12/22] cpufreq: tegra124: Add suspend and resume support Date: Sat, 2 Nov 2019 15:42:35 +0100 [thread overview] Message-ID: <20191102144235.GA3862867@ulmo> (raw) In-Reply-To: <1565984527-5272-13-git-send-email-skomatineni@nvidia.com> [-- Attachment #1: Type: text/plain, Size: 3659 bytes --] On Fri, Aug 16, 2019 at 12:41:57PM -0700, Sowjanya Komatineni wrote: > This patch adds suspend and resume pm ops for cpufreq driver. > > PLLP is the safe clock source for CPU during system suspend and > resume as PLLP rate is below the CPU Fmax at Vmin. > > CPUFreq driver suspend switches the CPU clock source to PLLP and > disables the DFLL clock. > > During system resume, warmboot code powers up the CPU with PLLP > clock source. So CPUFreq driver resume enabled DFLL clock and > switches CPU back to DFLL clock source. > > Acked-by: Thierry Reding <treding@nvidia.com> > Acked-by: Viresh Kumar <viresh.kumar@linaro.org> > Reviewed-by: Dmitry Osipenko <digetx@gmail.com> > Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> > --- > drivers/cpufreq/tegra124-cpufreq.c | 59 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 59 insertions(+) Hi Rafael, I was originally planning to pick this up into the Tegra tree with your and Viresh's Acked-by, but I now realize that there aren't any dependencies between this and the rest of the series, so this can also go through your tree. Do you have any preference on how to merge it? I've already Acked this from the Tegra side, so feel free to pick it up if that's what you prefer. Thierry > diff --git a/drivers/cpufreq/tegra124-cpufreq.c b/drivers/cpufreq/tegra124-cpufreq.c > index 4f0c637b3b49..7a1ea6fdcab6 100644 > --- a/drivers/cpufreq/tegra124-cpufreq.c > +++ b/drivers/cpufreq/tegra124-cpufreq.c > @@ -6,6 +6,7 @@ > #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt > > #include <linux/clk.h> > +#include <linux/cpufreq.h> > #include <linux/err.h> > #include <linux/init.h> > #include <linux/kernel.h> > @@ -128,8 +129,66 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev) > return ret; > } > > +static int __maybe_unused tegra124_cpufreq_suspend(struct device *dev) > +{ > + struct tegra124_cpufreq_priv *priv = dev_get_drvdata(dev); > + int err; > + > + /* > + * PLLP rate 408Mhz is below the CPU Fmax at Vmin and is safe to > + * use during suspend and resume. So, switch the CPU clock source > + * to PLLP and disable DFLL. > + */ > + err = clk_set_parent(priv->cpu_clk, priv->pllp_clk); > + if (err < 0) { > + dev_err(dev, "failed to reparent to PLLP: %d\n", err); > + return err; > + } > + > + clk_disable_unprepare(priv->dfll_clk); > + > + return 0; > +} > + > +static int __maybe_unused tegra124_cpufreq_resume(struct device *dev) > +{ > + struct tegra124_cpufreq_priv *priv = dev_get_drvdata(dev); > + int err; > + > + /* > + * Warmboot code powers up the CPU with PLLP clock source. > + * Enable DFLL clock and switch CPU clock source back to DFLL. > + */ > + err = clk_prepare_enable(priv->dfll_clk); > + if (err < 0) { > + dev_err(dev, "failed to enable DFLL clock for CPU: %d\n", err); > + goto disable_cpufreq; > + } > + > + err = clk_set_parent(priv->cpu_clk, priv->dfll_clk); > + if (err < 0) { > + dev_err(dev, "failed to reparent to DFLL clock: %d\n", err); > + goto disable_dfll; > + } > + > + return 0; > + > +disable_dfll: > + clk_disable_unprepare(priv->dfll_clk); > +disable_cpufreq: > + disable_cpufreq(); > + > + return err; > +} > + > +static const struct dev_pm_ops tegra124_cpufreq_pm_ops = { > + SET_SYSTEM_SLEEP_PM_OPS(tegra124_cpufreq_suspend, > + tegra124_cpufreq_resume) > +}; > + > static struct platform_driver tegra124_cpufreq_platdrv = { > .driver.name = "cpufreq-tegra124", > + .driver.pm = &tegra124_cpufreq_pm_ops, > .probe = tegra124_cpufreq_probe, > }; > > -- > 2.7.4 > [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 833 bytes --]
WARNING: multiple messages have this Message-ID (diff)
From: Thierry Reding <thierry.reding@gmail.com> To: "Rafael J. Wysocki" <rjw@rjwysocki.net> Cc: Sowjanya Komatineni <skomatineni@nvidia.com>, jonathanh@nvidia.com, tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, linus.walleij@linaro.org, stefan@agner.ch, mark.rutland@arm.com, pdeschrijver@nvidia.com, pgaikwad@nvidia.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, jckuo@nvidia.com, josephl@nvidia.com, talho@nvidia.com, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, mperttunen@nvidia.com, spatra@nvidia.com, robh+dt@kernel.org, digetx@gmail.com, devicetree@vger.kernel.org, rjw@rjwysocki.net, viresh.kumar@linaro.org, linux-pm@vger.kernel.org Subject: Re: [PATCH v9 12/22] cpufreq: tegra124: Add suspend and resume support Date: Sat, 2 Nov 2019 15:42:35 +0100 [thread overview] Message-ID: <20191102144235.GA3862867@ulmo> (raw) In-Reply-To: <1565984527-5272-13-git-send-email-skomatineni@nvidia.com> [-- Attachment #1: Type: text/plain, Size: 3659 bytes --] On Fri, Aug 16, 2019 at 12:41:57PM -0700, Sowjanya Komatineni wrote: > This patch adds suspend and resume pm ops for cpufreq driver. > > PLLP is the safe clock source for CPU during system suspend and > resume as PLLP rate is below the CPU Fmax at Vmin. > > CPUFreq driver suspend switches the CPU clock source to PLLP and > disables the DFLL clock. > > During system resume, warmboot code powers up the CPU with PLLP > clock source. So CPUFreq driver resume enabled DFLL clock and > switches CPU back to DFLL clock source. > > Acked-by: Thierry Reding <treding@nvidia.com> > Acked-by: Viresh Kumar <viresh.kumar@linaro.org> > Reviewed-by: Dmitry Osipenko <digetx@gmail.com> > Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> > --- > drivers/cpufreq/tegra124-cpufreq.c | 59 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 59 insertions(+) Hi Rafael, I was originally planning to pick this up into the Tegra tree with your and Viresh's Acked-by, but I now realize that there aren't any dependencies between this and the rest of the series, so this can also go through your tree. Do you have any preference on how to merge it? I've already Acked this from the Tegra side, so feel free to pick it up if that's what you prefer. Thierry > diff --git a/drivers/cpufreq/tegra124-cpufreq.c b/drivers/cpufreq/tegra124-cpufreq.c > index 4f0c637b3b49..7a1ea6fdcab6 100644 > --- a/drivers/cpufreq/tegra124-cpufreq.c > +++ b/drivers/cpufreq/tegra124-cpufreq.c > @@ -6,6 +6,7 @@ > #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt > > #include <linux/clk.h> > +#include <linux/cpufreq.h> > #include <linux/err.h> > #include <linux/init.h> > #include <linux/kernel.h> > @@ -128,8 +129,66 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev) > return ret; > } > > +static int __maybe_unused tegra124_cpufreq_suspend(struct device *dev) > +{ > + struct tegra124_cpufreq_priv *priv = dev_get_drvdata(dev); > + int err; > + > + /* > + * PLLP rate 408Mhz is below the CPU Fmax at Vmin and is safe to > + * use during suspend and resume. So, switch the CPU clock source > + * to PLLP and disable DFLL. > + */ > + err = clk_set_parent(priv->cpu_clk, priv->pllp_clk); > + if (err < 0) { > + dev_err(dev, "failed to reparent to PLLP: %d\n", err); > + return err; > + } > + > + clk_disable_unprepare(priv->dfll_clk); > + > + return 0; > +} > + > +static int __maybe_unused tegra124_cpufreq_resume(struct device *dev) > +{ > + struct tegra124_cpufreq_priv *priv = dev_get_drvdata(dev); > + int err; > + > + /* > + * Warmboot code powers up the CPU with PLLP clock source. > + * Enable DFLL clock and switch CPU clock source back to DFLL. > + */ > + err = clk_prepare_enable(priv->dfll_clk); > + if (err < 0) { > + dev_err(dev, "failed to enable DFLL clock for CPU: %d\n", err); > + goto disable_cpufreq; > + } > + > + err = clk_set_parent(priv->cpu_clk, priv->dfll_clk); > + if (err < 0) { > + dev_err(dev, "failed to reparent to DFLL clock: %d\n", err); > + goto disable_dfll; > + } > + > + return 0; > + > +disable_dfll: > + clk_disable_unprepare(priv->dfll_clk); > +disable_cpufreq: > + disable_cpufreq(); > + > + return err; > +} > + > +static const struct dev_pm_ops tegra124_cpufreq_pm_ops = { > + SET_SYSTEM_SLEEP_PM_OPS(tegra124_cpufreq_suspend, > + tegra124_cpufreq_resume) > +}; > + > static struct platform_driver tegra124_cpufreq_platdrv = { > .driver.name = "cpufreq-tegra124", > + .driver.pm = &tegra124_cpufreq_pm_ops, > .probe = tegra124_cpufreq_probe, > }; > > -- > 2.7.4 > [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 833 bytes --]
next prev parent reply other threads:[~2019-11-02 14:42 UTC|newest] Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-08-16 19:41 [PATCH v9 00/22] SC7 entry and exit support for Tegra210 Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-16 19:41 ` [PATCH v9 01/22] pinctrl: tegra: Fix write barrier placement in pmx_writel Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-18 22:20 ` Linus Walleij 2019-08-18 22:20 ` Linus Walleij 2019-08-16 19:41 ` [PATCH v9 02/22] pinctrl: tegra: Flush pinctrl writes during resume Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-18 22:20 ` Linus Walleij 2019-08-18 22:20 ` Linus Walleij 2019-08-16 19:41 ` [PATCH v9 03/22] clk: tegra: divider: Save and restore divider rate Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-16 19:41 ` [PATCH v9 04/22] clk: tegra: pllout: Save and restore pllout context Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-16 19:41 ` [PATCH v9 05/22] clk: tegra: pll: Save and restore pll context Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-16 19:41 ` [PATCH v9 06/22] clk: tegra: Support for OSC context save and restore Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-16 19:41 ` [PATCH v9 07/22] clk: Add API to get index of the clock parent Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-11-06 23:10 ` Stephen Boyd 2019-11-06 23:10 ` Stephen Boyd 2019-11-07 0:54 ` Dmitry Osipenko 2019-11-07 15:21 ` Thierry Reding 2019-11-07 19:19 ` Stephen Boyd 2019-11-08 10:11 ` Thierry Reding 2019-11-08 18:12 ` Stephen Boyd 2019-11-08 18:55 ` Thierry Reding 2019-11-08 21:15 ` Stephen Boyd 2019-08-16 19:41 ` [PATCH v9 08/22] clk: tegra: periph: Add restore_context support Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-16 19:41 ` [PATCH v9 09/22] clk: tegra: clk-super: Fix to enable PLLP branches to CPU Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-16 19:41 ` [PATCH v9 10/22] clk: tegra: clk-super: Add restore-context support Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-16 19:41 ` [PATCH v9 11/22] clk: tegra: clk-dfll: Add suspend and resume support Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-11-08 21:20 ` Stephen Boyd 2019-11-08 21:20 ` Stephen Boyd 2019-11-08 23:38 ` Dmitry Osipenko 2019-08-16 19:41 ` [PATCH v9 12/22] cpufreq: tegra124: " Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-11-02 14:42 ` Thierry Reding [this message] 2019-11-02 14:42 ` Thierry Reding 2019-08-16 19:41 ` [PATCH v9 13/22] clk: tegra210: Use fence_udelay during PLLU init Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-16 19:41 ` [PATCH v9 14/22] clk: tegra: Share clk and rst register defines with Tegra clock driver Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-16 19:42 ` [PATCH v9 15/22] clk: tegra210: Add suspend and resume support Sowjanya Komatineni 2019-08-16 19:42 ` Sowjanya Komatineni 2019-08-19 16:47 ` Dmitry Osipenko 2019-08-16 19:42 ` [PATCH v9 16/22] soc/tegra: pmc: Allow to support more tegras wake Sowjanya Komatineni 2019-08-16 19:42 ` Sowjanya Komatineni 2019-08-16 19:42 ` [PATCH v9 17/22] soc/tegra: pmc: Add pmc wake support for tegra210 Sowjanya Komatineni 2019-08-16 19:42 ` Sowjanya Komatineni 2019-08-16 19:42 ` [PATCH v9 18/22] arm64: tegra: Enable wake from deep sleep on RTC alarm Sowjanya Komatineni 2019-08-16 19:42 ` Sowjanya Komatineni 2019-08-16 19:42 ` [PATCH v9 19/22] soc/tegra: pmc: Configure core power request polarity Sowjanya Komatineni 2019-08-16 19:42 ` Sowjanya Komatineni 2019-08-16 19:42 ` [PATCH v9 20/22] soc/tegra: pmc: Configure deep sleep control settings Sowjanya Komatineni 2019-08-16 19:42 ` Sowjanya Komatineni 2019-08-19 16:48 ` Dmitry Osipenko 2019-08-19 18:20 ` Sowjanya Komatineni 2019-08-19 18:20 ` Sowjanya Komatineni 2019-08-19 19:07 ` Sowjanya Komatineni 2019-08-19 19:07 ` Sowjanya Komatineni 2019-08-19 19:33 ` Dmitry Osipenko 2019-08-16 19:42 ` [PATCH v9 21/22] arm64: dts: tegra210-p2180: Jetson TX1 SC7 timings Sowjanya Komatineni 2019-08-16 19:42 ` Sowjanya Komatineni 2019-08-16 19:42 ` [PATCH v9 22/22] arm64: dts: tegra210-p3450: Jetson Nano " Sowjanya Komatineni 2019-08-16 19:42 ` Sowjanya Komatineni
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