[igt-dev] [PATCH v2 1/3] lib/rendercopy: Add AUX page table support

[igt-dev] [PATCH v2 1/3] lib/rendercopy: Add AUX page table support

[Imre Deak]

On GEN12+ the AUX CCS surfaces required by the render and media
compression must be specified by a 3 level page table directory, which
translates the main surface graphics address to the AUX CCS surface
graphics address. For this purpose add support for creating a GEM buffer
to translate the linear surface address range to the linear AUX surface
address range.

The buffers containing the main surface must be pinned down, since the
directory table entry indices depend on the surface address, and they
must be 64kB aligned. The page table can be relocated OTOH, so allow
that and emit the required relocation entries.

v2:
- Make level variables to be 0 based (l1..l3 -> level=0..2).
- Add missing drm_intel_bo_set_softpin_offset() stub to fix build on
  non-Intel archs.
- Fix missing offsets in reloc entries of already bound objects. (Chris)
- Randomize pin offsets, to try to avoid eviction. (Chris)
- Remove redundant MI_NOOPS around MI_LOAD_REGISTER_MEM
- Stop using explicit reloc cache domains, as these don't make sense on
  GEN12 anyway. (Chris)
- Fix missing autotools support. (Chris)
- s/igt_aux_pgtable/intel_aux_pgtable/, since the functionality is Intel
  specific. (Chris)

Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 lib/Makefile.sources         |   1 +
 lib/intel_aux_pgtable.c      | 379 +++++++++++++++++++++++++++++++++++
 lib/intel_aux_pgtable.h      |  12 ++
 lib/intel_reg.h              |   2 +
 lib/meson.build              |   1 +
 lib/rendercopy_gen9.c        | 232 ++++++++++++++++++++-
 lib/stubs/drm/intel_bufmgr.c |   6 +
 7 files changed, 627 insertions(+), 6 deletions(-)
 create mode 100644 lib/intel_aux_pgtable.c
 create mode 100644 lib/intel_aux_pgtable.h

diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index cf094ab8..1d0f45f7 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -100,6 +100,7 @@ lib_source_list =	 	\
 	surfaceformat.h		\
 	sw_sync.c		\
 	sw_sync.h		\
+	intel_aux_pgtable.c	\
 	intel_reg_map.c		\
 	intel_iosf.c		\
 	igt_kms.c		\
diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c
new file mode 100644
index 00000000..79402813
--- /dev/null
+++ b/lib/intel_aux_pgtable.c
@@ -0,0 +1,379 @@
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "drmtest.h"
+#include "intel_aux_pgtable.h"
+#include "intel_bufmgr.h"
+#include "intel_batchbuffer.h"
+#include "ioctl_wrappers.h"
+
+#include "i915/gem_mman.h"
+
+#define BITS_PER_LONG		(sizeof(long) * 8)
+#define BITMASK(e, s)		((~0UL << (s)) & \
+				 (~0UL >> (BITS_PER_LONG - 1 - (e))))
+
+#define ALIGN_DOWN(x, a)	ALIGN((x) - ((a) - 1), (a))
+
+/* The unit size to which the AUX CCS surface is aligned to. */
+#define AUX_CCS_UNIT_SIZE	64
+/*
+ * The block size on the AUX CCS surface which is mapped by one L1 AUX
+ * pagetable entry.
+ */
+#define AUX_CCS_BLOCK_SIZE	(4 * AUX_CCS_UNIT_SIZE)
+/*
+ * The block size on the main surface mapped by one AUX CCS block:
+ *   256 bytes per CCS block *
+ *   8   bits per byte /
+ *   2   bits per main surface CL *
+ *   64  bytes per main surface CL
+ */
+#define MAIN_SURFACE_BLOCK_SIZE	(AUX_CCS_BLOCK_SIZE * 8 / 2 * 64)
+
+#define GFX_ADDRESS_BITS	48
+
+#define max(a, b)		((a) > (b) ? (a) : (b))
+
+struct pgtable_level_desc {
+	int idx_shift;
+	int idx_bits;
+	int entry_ptr_shift;
+	int table_size;
+};
+
+struct pgtable_level_info {
+	const struct pgtable_level_desc *desc;
+	int table_count;
+	int alloc_base;
+	int alloc_ptr;
+};
+
+struct pgtable {
+	int levels;
+	struct pgtable_level_info *level_info;
+	int size;
+	int max_align;
+	drm_intel_bo *bo;
+};
+
+static int
+pgt_table_count(int address_bits, const struct igt_buf **bufs, int buf_count)
+{
+	uint64_t end;
+	int count;
+	int i;
+
+	count = 0;
+	end = 0;
+	for (i = 0; i < buf_count; i++) {
+		const struct igt_buf *buf = bufs[i];
+		uint64_t start;
+
+		/* We require bufs to be sorted. */
+		igt_assert(i == 0 ||
+			   buf->bo->offset64 >= bufs[i - 1]->bo->offset64 +
+						bufs[i - 1]->bo->size);
+
+		start = ALIGN_DOWN(buf->bo->offset64, 1UL << address_bits);
+		/* Avoid double counting for overlapping aligned bufs. */
+		start = max(start, end);
+
+		end = ALIGN(buf->bo->offset64 + buf->size, 1UL << address_bits);
+		igt_assert(end >= start);
+
+		count += (end - start) >> address_bits;
+	}
+
+	return count;
+}
+
+static void
+pgt_calc_size(struct pgtable *pgt, const struct igt_buf **bufs, int buf_count)
+{
+	int level;
+
+	pgt->size = 0;
+
+	for (level = pgt->levels - 1; level >= 0; level--) {
+		struct pgtable_level_info *li = &pgt->level_info[level];
+
+		li->alloc_base = ALIGN(pgt->size, li->desc->table_size);
+		li->alloc_ptr = li->alloc_base;
+
+		li->table_count = pgt_table_count(li->desc->idx_shift +
+						  li->desc->idx_bits,
+						  bufs, buf_count);
+
+		pgt->size = li->alloc_base +
+			    li->table_count * li->desc->table_size;
+	}
+}
+
+static uint64_t pgt_alloc_table(struct pgtable *pgt, int level)
+{
+	struct pgtable_level_info *li = &pgt->level_info[level];
+	uint64_t table;
+
+	table = li->alloc_ptr;
+	li->alloc_ptr += li->desc->table_size;
+
+	igt_assert(li->alloc_ptr <=
+		   li->alloc_base + li->table_count * li->desc->table_size);
+
+	return table;
+}
+
+static int pgt_address_index(struct pgtable *pgt, int level, uint64_t address)
+{
+	const struct pgtable_level_desc *ld = pgt->level_info[level].desc;
+	uint64_t mask = BITMASK(ld->idx_shift + ld->idx_bits - 1,
+				ld->idx_shift);
+
+	return (address & mask) >> ld->idx_shift;
+}
+
+static uint64_t ptr_mask(struct pgtable *pgt, int level)
+{
+	const struct pgtable_level_desc *ld = pgt->level_info[level].desc;
+
+	return BITMASK(GFX_ADDRESS_BITS - 1, ld->entry_ptr_shift);
+}
+
+static uint64_t pgt_entry_ptr(struct pgtable *pgt, int level, uint64_t entry)
+{
+	uint64_t ptr = entry & ptr_mask(pgt, level);
+
+	if (level)
+		ptr -= pgt->bo->offset64;
+	igt_assert(!(ptr & ~ptr_mask(pgt, level)));
+
+	return ptr;
+}
+
+static uint64_t pgt_mkentry(struct pgtable *pgt, int level, uint64_t ptr,
+			    uint64_t flags)
+{
+	if (level)
+		ptr += pgt->bo->offset64;
+	igt_assert(!(ptr & ~ptr_mask(pgt, level)));
+
+	return ptr | flags;
+}
+
+static uint64_t
+pgt_get_table(struct pgtable *pgt, uint64_t parent_table,
+	      int level, uint64_t address, uint64_t flags)
+{
+	uint64_t *table_ptr = pgt->bo->virtual + parent_table;
+	int entry_idx = pgt_address_index(pgt, level, address);
+	uint64_t *entry_ptr;
+
+	entry_ptr = &table_ptr[entry_idx];
+	if (!*entry_ptr) {
+		uint64_t child_table = pgt_alloc_table(pgt, level - 1);
+
+		*entry_ptr = pgt_mkentry(pgt, level, child_table, flags);
+
+		drm_intel_bo_emit_reloc(pgt->bo,
+					parent_table + entry_idx * sizeof(uint64_t),
+					pgt->bo, *entry_ptr, 0, 0);
+	}
+
+	return pgt_entry_ptr(pgt, level, *entry_ptr);
+}
+
+static void
+pgt_set_l1_entry(struct pgtable *pgt, uint64_t l1_table,
+		 uint64_t address, uint64_t ptr, uint64_t flags)
+{
+	uint64_t *l1_table_ptr;
+	uint64_t *l1_entry_ptr;
+
+	l1_table_ptr = pgt->bo->virtual + l1_table;
+	l1_entry_ptr = &l1_table_ptr[pgt_address_index(pgt, 0, address)];
+	*l1_entry_ptr = pgt_mkentry(pgt, 0, ptr, flags);
+}
+
+static uint64_t pgt_get_l1_flags(const struct igt_buf *buf)
+{
+	/*
+	 * The offset of .tile_mode isn't specifed by bspec, it's what Mesa
+	 * uses.
+	 */
+	union {
+		struct {
+			uint64_t	valid:1;
+			uint64_t	compression_mod:2;
+			uint64_t	lossy_compression:1;
+			uint64_t	pad:4;
+			uint64_t	addr:40;
+			uint64_t	pad2:4;
+			uint64_t	tile_mode:2;
+			uint64_t	depth:3;
+			uint64_t	ycr:1;
+			uint64_t	format:6;
+		} e;
+		uint64_t l;
+	} entry = {
+		.e = {
+			.valid = 1,
+			.tile_mode = buf->tiling == I915_TILING_Y ? 1 : 0,
+			.depth = 5,		/* 32bpp */
+			.format = 0xA,		/* B8G8R8A8_UNORM */
+		}
+	};
+
+	/*
+	 * TODO: Clarify if Yf is supported and if we need to differentiate
+	 *       Ys and Yf.
+	 *       Add support for more formats.
+	 */
+	igt_assert(buf->tiling == I915_TILING_Y ||
+		   buf->tiling == I915_TILING_Yf ||
+		   buf->tiling == I915_TILING_Ys);
+
+	igt_assert(buf->bpp == 32);
+
+	return entry.l;
+}
+
+static uint64_t pgt_get_lx_flags(void)
+{
+	union {
+		struct {
+			uint64_t        valid:1;
+			uint64_t        addr:47;
+			uint64_t        pad:16;
+		} e;
+		uint64_t l;
+	} entry = {
+		.e = {
+			.valid = 1,
+		}
+	};
+
+	return entry.l;
+}
+
+static void
+pgt_populate_entries_for_buf(struct pgtable *pgt,
+			       const struct igt_buf *buf,
+			       uint64_t top_table)
+{
+	uint64_t surface_addr = buf->bo->offset64;
+	uint64_t surface_end = surface_addr + buf->size;
+	uint64_t aux_addr = buf->bo->offset64 + buf->aux.offset;
+	uint64_t l1_flags = pgt_get_l1_flags(buf);
+	uint64_t lx_flags = pgt_get_lx_flags();
+
+	for (; surface_addr < surface_end;
+	     surface_addr += MAIN_SURFACE_BLOCK_SIZE,
+	     aux_addr += AUX_CCS_BLOCK_SIZE) {
+		uint64_t table = top_table;
+		int level;
+
+		for (level = pgt->levels - 1; level >= 1; level--)
+			table = pgt_get_table(pgt, table, level,
+					      surface_addr, lx_flags);
+
+		pgt_set_l1_entry(pgt, table, surface_addr, aux_addr, l1_flags);
+	}
+}
+
+static void pgt_populate_entries(struct pgtable *pgt,
+				 const struct igt_buf **bufs,
+				 int buf_count,
+				 drm_intel_bo *pgt_bo)
+{
+	uint64_t top_table;
+	int i;
+
+	pgt->bo = pgt_bo;
+
+	igt_assert(pgt_bo->size >= pgt->size);
+	memset(pgt_bo->virtual, 0, pgt->size);
+
+	top_table = pgt_alloc_table(pgt, pgt->levels - 1);
+	/* Top level table must be at offset 0. */
+	igt_assert(top_table == 0);
+
+	for (i = 0; i < buf_count; i++)
+		pgt_populate_entries_for_buf(pgt, bufs[i], top_table);
+}
+
+static struct pgtable *
+pgt_create(const struct pgtable_level_desc *level_descs, int levels,
+	   const struct igt_buf **bufs, int buf_count)
+{
+	struct pgtable *pgt;
+	int level;
+
+	pgt = calloc(1, sizeof(*pgt));
+	igt_assert(pgt);
+
+	pgt->levels = levels;
+
+	pgt->level_info = calloc(levels, sizeof(*pgt->level_info));
+	igt_assert(pgt->level_info);
+
+	for (level = 0; level < pgt->levels; level++) {
+		struct pgtable_level_info *li = &pgt->level_info[level];
+
+		li->desc = &level_descs[level];
+		if (li->desc->table_size > pgt->max_align)
+			pgt->max_align = li->desc->table_size;
+	}
+
+	pgt_calc_size(pgt, bufs, buf_count);
+
+	return pgt;
+}
+
+static void pgt_destroy(struct pgtable *pgt)
+{
+	free(pgt->level_info);
+	free(pgt);
+}
+
+drm_intel_bo *
+intel_aux_pgtable_create(drm_intel_bufmgr *bufmgr,
+		       const struct igt_buf **bufs, int buf_count)
+{
+	static const struct pgtable_level_desc level_desc[] = {
+		{
+			.idx_shift = 16,
+			.idx_bits = 8,
+			.entry_ptr_shift = 8,
+			.table_size = 8 * 1024,
+		},
+		{
+			.idx_shift = 24,
+			.idx_bits = 12,
+			.entry_ptr_shift = 13,
+			.table_size = 32 * 1024,
+		},
+		{
+			.idx_shift = 36,
+			.idx_bits = 12,
+			.entry_ptr_shift = 15,
+			.table_size = 32 * 1024,
+		},
+	};
+	struct pgtable *pgt;
+	drm_intel_bo *pgt_bo;
+
+	pgt = pgt_create(level_desc, ARRAY_SIZE(level_desc), bufs, buf_count);
+
+	pgt_bo = drm_intel_bo_alloc_for_render(bufmgr, "aux pgt",
+					       pgt->size, pgt->max_align);
+	igt_assert(pgt_bo);
+
+	igt_assert(drm_intel_bo_map(pgt_bo, true) == 0);
+	pgt_populate_entries(pgt, bufs, buf_count, pgt_bo);
+	igt_assert(drm_intel_bo_unmap(pgt_bo) == 0);
+
+	pgt_destroy(pgt);
+
+	return pgt_bo;
+}
diff --git a/lib/intel_aux_pgtable.h b/lib/intel_aux_pgtable.h
new file mode 100644
index 00000000..533d4491
--- /dev/null
+++ b/lib/intel_aux_pgtable.h
@@ -0,0 +1,12 @@
+#ifndef _IGT_AUX_PGTABLE_H_
+#define _IGT_AUX_PGTABLE_H_
+
+#include "intel_bufmgr.h"
+
+struct igt_buf;
+
+drm_intel_bo *
+intel_aux_pgtable_create(drm_intel_bufmgr *bufmgr,
+			 const struct igt_buf **bufs, int buf_count);
+
+#endif
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index 069440cb..755a78e6 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -673,6 +673,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define RING_VALID          0x00000001
 #define RING_INVALID        0x00000000
 
+#define GEN12_GFX_AUX_TABLE_BASE_ADDR	0x4200
 
 
 /* BitBlt Instructions
@@ -2570,6 +2571,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 #define MI_LOAD_SCAN_LINES_INCL		(0x12<<23)
 #define MI_LOAD_REGISTER_IMM		((0x22 << 23) | 1)
+#define MI_LOAD_REGISTER_MEM		((0x29 << 23) | (4 - 2))
 
 /* Flush */
 #define MI_FLUSH			(0x04<<23)
diff --git a/lib/meson.build b/lib/meson.build
index 221ae28c..33fef486 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -44,6 +44,7 @@ lib_sources = [
 	'rendercopy_gen8.c',
 	'rendercopy_gen9.c',
 	'sw_sync.c',
+	'intel_aux_pgtable.c',
 	'intel_reg_map.c',
 	'intel_iosf.c',
 	'igt_kms.c',
diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index 694eb3cf..2a84bb64 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -15,6 +15,7 @@
 #include <i915_drm.h>
 
 #include "drmtest.h"
+#include "intel_aux_pgtable.h"
 #include "intel_bufmgr.h"
 #include "intel_batchbuffer.h"
 #include "intel_io.h"
@@ -972,19 +973,224 @@ static void gen8_emit_primitive(struct intel_batchbuffer *batch, uint32_t offset
 
 #define BATCH_STATE_SPLIT 2048
 
+static void
+gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch, uint32_t state)
+{
+	if (!state)
+		return;
+
+	OUT_BATCH(MI_LOAD_REGISTER_MEM);
+	OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR);
+	OUT_RELOC(batch->bo, 0, 0, state);
+
+	OUT_BATCH(MI_LOAD_REGISTER_MEM);
+	OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR + 4);
+	OUT_RELOC(batch->bo, 0, 0, state + 4);
+}
+
+static void
+aux_pgtable_find_max_free_range(const struct igt_buf **bufs, int buf_count,
+				uint64_t *range_start, uint64_t *range_size)
+{
+	/*
+	 * Keep the first page reserved, so we can differentiate pinned
+	 * objects based on a non-NULL offset.
+	 */
+	uint64_t start = 0x1000;
+	/* For now alloc only from the first 4GB address space. */
+	const uint64_t end = 1ULL << 32;
+	uint64_t max_range_start = 0;
+	uint64_t max_range_size = 0;
+	int i;
+
+	for (i = 0; i < buf_count; i++) {
+		if (bufs[i]->bo->offset64 >= end)
+			break;
+
+		if (bufs[i]->bo->offset64 - start > max_range_size) {
+			max_range_start = start;
+			max_range_size = bufs[i]->bo->offset64 - start;
+		}
+		start = bufs[i]->bo->offset64 + bufs[i]->size;
+	}
+
+	if (start < end && end - start > max_range_size) {
+		max_range_start = start;
+		max_range_size = end - start;
+	}
+
+	*range_start = max_range_start;
+	*range_size = max_range_size;
+}
+
+static uint64_t
+aux_pgtable_find_free_range(const struct igt_buf **bufs, int buf_count,
+			    uint32_t size)
+{
+	uint64_t range_start;
+	uint64_t range_size;
+	/* A compressed surface must be 64kB aligned. */
+	const uint32_t align = 0x10000;
+	int pad;
+
+	aux_pgtable_find_max_free_range(bufs, buf_count,
+					&range_start, &range_size);
+
+	pad = ALIGN(range_start, align) - range_start;
+	range_start += pad;
+	range_size -= pad;
+	igt_assert(range_size >= size);
+
+	return range_start + ALIGN(rand() % (range_size - size), align);
+}
+
+static void
+aux_pgtable_reserve_range(const struct igt_buf **bufs, int buf_count,
+			  const struct igt_buf *new_buf)
+{
+	int i;
+
+	if (new_buf->aux.stride && !new_buf->bo->offset64) {
+		uint64_t pin_offset;
+
+		pin_offset = aux_pgtable_find_free_range(bufs, buf_count,
+							 new_buf->bo->size);
+		drm_intel_bo_set_softpin_offset(new_buf->bo, pin_offset);
+		igt_assert(new_buf->bo->offset64 == pin_offset);
+	}
+
+	for (i = 0; i < buf_count; i++)
+		if (bufs[i]->bo->offset64 > new_buf->bo->offset64)
+			break;
+
+	memmove(&bufs[i + 1], &bufs[i], sizeof(bufs[0]) * (buf_count - i));
+
+	bufs[i] = new_buf;
+}
+
+struct aux_pgtable_info {
+	int buf_count;
+	const struct igt_buf *bufs[2];
+	uint64_t buf_pin_offsets[2];
+	drm_intel_bo *pgtable_bo;
+};
+
+static void
+gen12_aux_pgtable_init(struct aux_pgtable_info *info,
+		       drm_intel_bufmgr *bufmgr,
+		       const struct igt_buf *src_buf,
+		       const struct igt_buf *dst_buf)
+{
+	const struct igt_buf *bufs[2];
+	const struct igt_buf *reserved_bufs[2];
+	int reserved_buf_count;
+	int i;
+
+	if (!src_buf->aux.stride && !dst_buf->aux.stride)
+		return;
+
+	bufs[0] = src_buf;
+	bufs[1] = dst_buf;
+
+	/*
+	 * Ideally we'd need a an IGT-wide GFX address space allocator, which
+	 * would consider all allocations and thus avoid evictions. For now use
+	 * a simpler scheme here, which only considers the buffers involved in
+	 * the blit, which should at least minimize the chance for evictions
+	 * in the case of subsequent blits:
+	 *   1. If they were already bound (bo->offset64 != 0), use this
+	 *      address.
+	 *   2. Pick a range randomly from the 4GB address space, that is not
+	 *      already occupied by a bound object, or an object we pinned.
+	 */
+	reserved_buf_count = 0;
+	/* First reserve space for any bufs that are bound already. */
+	for (i = 0; i < ARRAY_SIZE(bufs); i++)
+		if (bufs[i]->bo->offset64)
+			aux_pgtable_reserve_range(reserved_bufs,
+						  reserved_buf_count++,
+						  bufs[i]);
+
+	/* Next, reserve space for unbound bufs with an AUX surface. */
+	for (i = 0; i < ARRAY_SIZE(bufs); i++)
+		if (!bufs[i]->bo->offset64 && bufs[i]->aux.stride)
+			aux_pgtable_reserve_range(reserved_bufs,
+						  reserved_buf_count++,
+						  bufs[i]);
+
+	/* Create AUX pgtable entries only for bufs with an AUX surface */
+	info->buf_count = 0;
+	for (i = 0; i < reserved_buf_count; i++) {
+		if (!reserved_bufs[i]->aux.stride)
+			continue;
+
+		info->bufs[info->buf_count] = reserved_bufs[i];
+		info->buf_pin_offsets[info->buf_count] =
+			reserved_bufs[i]->bo->offset64;
+		info->buf_count++;
+	}
+
+	info->pgtable_bo = intel_aux_pgtable_create(bufmgr,
+						    info->bufs,
+						    info->buf_count);
+	igt_assert(info->pgtable_bo);
+}
+
+static void
+gen12_aux_pgtable_cleanup(struct aux_pgtable_info *info)
+{
+	int i;
+
+	/* Check that the pinned bufs kept their offset after the exec. */
+	for (i = 0; i < info->buf_count; i++)
+		igt_assert_eq_u64(info->bufs[i]->bo->offset64,
+				  info->buf_pin_offsets[i]);
+
+	drm_intel_bo_unreference(info->pgtable_bo);
+}
+
+static uint32_t
+gen12_create_aux_pgtable_state(struct intel_batchbuffer *batch,
+			       drm_intel_bo *aux_pgtable_bo)
+{
+	uint64_t *pgtable_ptr;
+	uint32_t pgtable_ptr_offset;
+	int ret;
+
+	if (!aux_pgtable_bo)
+		return 0;
+
+	pgtable_ptr = intel_batchbuffer_subdata_alloc(batch,
+						      sizeof(*pgtable_ptr),
+						      sizeof(*pgtable_ptr));
+	pgtable_ptr_offset = intel_batchbuffer_subdata_offset(batch,
+							      pgtable_ptr);
+
+	*pgtable_ptr = aux_pgtable_bo->offset64;
+	ret = drm_intel_bo_emit_reloc(batch->bo, pgtable_ptr_offset,
+				      aux_pgtable_bo, 0,
+				      0, 0);
+	assert(ret == 0);
+
+	return pgtable_ptr_offset;
+}
+
 static
 void _gen9_render_copyfunc(struct intel_batchbuffer *batch,
 			  drm_intel_context *context,
 			  const struct igt_buf *src, unsigned src_x,
 			  unsigned src_y, unsigned width, unsigned height,
 			  const struct igt_buf *dst, unsigned dst_x,
-			  unsigned dst_y, const uint32_t ps_kernel[][4],
+			  unsigned dst_y,
+			  drm_intel_bo *aux_pgtable_bo,
+			  const uint32_t ps_kernel[][4],
 			  uint32_t ps_kernel_size)
 {
 	uint32_t ps_sampler_state, ps_kernel_off, ps_binding_table;
 	uint32_t scissor_state;
 	uint32_t vertex_buffer;
 	uint32_t batch_end;
+	uint32_t aux_pgtable_state;
 
 	igt_assert(src->bpp == dst->bpp);
 	intel_batchbuffer_flush_with_context(batch, context);
@@ -1007,6 +1213,10 @@ void _gen9_render_copyfunc(struct intel_batchbuffer *batch,
 	viewport.cc_state = gen6_create_cc_viewport(batch);
 	viewport.sf_clip_state = gen7_create_sf_clip_viewport(batch);
 	scissor_state = gen6_create_scissor_rect(batch);
+
+	aux_pgtable_state = gen12_create_aux_pgtable_state(batch,
+							   aux_pgtable_bo);
+
 	/* TODO: theree is other state which isn't setup */
 
 	assert(batch->ptr < &batch->buffer[4095]);
@@ -1018,6 +1228,8 @@ void _gen9_render_copyfunc(struct intel_batchbuffer *batch,
 	OUT_BATCH(G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D |
 				GEN9_PIPELINE_SELECTION_MASK);
 
+	gen12_emit_aux_pgtable_state(batch, aux_pgtable_state);
+
 	gen8_emit_sip(batch);
 
 	gen7_emit_push_constants(batch);
@@ -1092,8 +1304,8 @@ void gen9_render_copyfunc(struct intel_batchbuffer *batch,
 
 {
 	_gen9_render_copyfunc(batch, context, src, src_x, src_y,
-			  width, height, dst, dst_x, dst_y, ps_kernel_gen9,
-			  sizeof(ps_kernel_gen9));
+			  width, height, dst, dst_x, dst_y, NULL,
+			  ps_kernel_gen9, sizeof(ps_kernel_gen9));
 }
 
 void gen11_render_copyfunc(struct intel_batchbuffer *batch,
@@ -1104,8 +1316,8 @@ void gen11_render_copyfunc(struct intel_batchbuffer *batch,
 
 {
 	_gen9_render_copyfunc(batch, context, src, src_x, src_y,
-			  width, height, dst, dst_x, dst_y, ps_kernel_gen11,
-			  sizeof(ps_kernel_gen11));
+			  width, height, dst, dst_x, dst_y, NULL,
+			  ps_kernel_gen11, sizeof(ps_kernel_gen11));
 }
 
 void gen12_render_copyfunc(struct intel_batchbuffer *batch,
@@ -1115,7 +1327,15 @@ void gen12_render_copyfunc(struct intel_batchbuffer *batch,
 			   const struct igt_buf *dst, unsigned dst_x, unsigned dst_y)
 
 {
+	struct aux_pgtable_info pgtable_info = { };
+
+	gen12_aux_pgtable_init(&pgtable_info, batch->bufmgr, src, dst);
+
 	_gen9_render_copyfunc(batch, context, src, src_x, src_y,
-			  width, height, dst, dst_x, dst_y, gen12_render_copy,
+			  width, height, dst, dst_x, dst_y,
+			  pgtable_info.pgtable_bo,
+			  gen12_render_copy,
 			  sizeof(gen12_render_copy));
+
+	gen12_aux_pgtable_cleanup(&pgtable_info);
 }
diff --git a/lib/stubs/drm/intel_bufmgr.c b/lib/stubs/drm/intel_bufmgr.c
index f87452ac..cbab2484 100644
--- a/lib/stubs/drm/intel_bufmgr.c
+++ b/lib/stubs/drm/intel_bufmgr.c
@@ -233,6 +233,12 @@ int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
 	return -ENODEV;
 }
 
+int drm_intel_bo_set_softpin_offset(drm_intel_bo *bo, uint64_t offset)
+{
+	igt_require_f(false, missing_support_str);
+	return -ENODEV;
+}
+
 int drm_intel_bo_disable_reuse(drm_intel_bo *bo)
 {
 	igt_require_f(false, missing_support_str);
-- 
2.17.1

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[igt-dev] [PATCH v2 2/3] tests/gem_render_copy: Adjust the tgl+ compressed buf alignments

[Imre Deak]

GEN12+ the render and media compressed surface have different alignment
requiremens than ICL, so adjust that.

v2:
- Clarify a bit the comments about AUX CCS units vs. main surface tiles.
  (Ville)

Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 tests/i915/gem_render_copy.c | 51 ++++++++++++++++++++++++++++--------
 1 file changed, 40 insertions(+), 11 deletions(-)

diff --git a/tests/i915/gem_render_copy.c b/tests/i915/gem_render_copy.c
index 261833d2..fd139e91 100644
--- a/tests/i915/gem_render_copy.c
+++ b/tests/i915/gem_render_copy.c
@@ -218,21 +218,37 @@ static void scratch_buf_write_to_png(data_t *data, struct igt_buf *buf,
 	free(linear);
 }
 
-static int scratch_buf_aux_width(const struct igt_buf *buf)
+static int scratch_buf_aux_width(uint32_t devid, const struct igt_buf *buf)
 {
+	/*
+	 * GEN12+: The AUX CCS unit size is 64 bytes mapping 4 main surface
+	 * tiles. Thus the width of the CCS unit is 4*32=128 pixels on the
+	 * main surface.
+	 */
+	if (intel_gen(devid) >= 12)
+		return DIV_ROUND_UP(igt_buf_width(buf), 128) * 64;
+
 	return DIV_ROUND_UP(igt_buf_width(buf), 1024) * 128;
 }
 
-static int scratch_buf_aux_height(const struct igt_buf *buf)
+static int scratch_buf_aux_height(uint32_t devid, const struct igt_buf *buf)
 {
+	/*
+	 * GEN12+: The AUX CCS unit size is 64 bytes mapping 4 main surface
+	 * tiles. Thus the height of the CCS unit is 32 pixel rows on the main
+	 * surface.
+	 */
+	if (intel_gen(devid) >= 12)
+		return DIV_ROUND_UP(igt_buf_height(buf), 32);
+
 	return DIV_ROUND_UP(igt_buf_height(buf), 512) * 32;
 }
 
 static void *linear_copy_aux(data_t *data, struct igt_buf *buf)
 {
 	void *map, *linear;
-	int aux_size = scratch_buf_aux_width(buf) *
-		scratch_buf_aux_height(buf);
+	int aux_size = scratch_buf_aux_width(data->devid, buf) *
+		scratch_buf_aux_height(data->devid, buf);
 
 	igt_assert_eq(posix_memalign(&linear, 16, aux_size), 0);
 
@@ -261,8 +277,8 @@ static void scratch_buf_aux_write_to_png(data_t *data,
 
 	surface = cairo_image_surface_create_for_data(linear,
 						      CAIRO_FORMAT_A8,
-						      scratch_buf_aux_width(buf),
-						      scratch_buf_aux_height(buf),
+						      scratch_buf_aux_width(data->devid, buf),
+						      scratch_buf_aux_height(data->devid, buf),
 						      buf->aux.stride);
 	ret = cairo_surface_write_to_png(surface, make_filename(filename));
 	igt_assert(ret == CAIRO_STATUS_SUCCESS);
@@ -413,13 +429,26 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf,
 		igt_assert(tiling == I915_TILING_Y ||
 			   tiling == I915_TILING_Yf);
 
-		buf->stride = ALIGN(width * (bpp / 8), 128);
+		/*
+		 * On GEN12+ we align the main surface to 4 * 4 main surface
+		 * tiles, which is 64kB. These 16 tiles are mapped by 4 AUX
+		 * CCS units, that is 4 * 64 bytes. These 4 CCS units are in
+		 * turn mapped by one L1 AUX page table entry.
+		 */
+		if (intel_gen(data->devid) >= 12)
+			buf->stride = ALIGN(width * (bpp / 8), 128 * 4);
+		else
+			buf->stride = ALIGN(width * (bpp / 8), 128);
+
+		if (intel_gen(data->devid) >= 12)
+			height = ALIGN(height, 4 * 32);
+
 		buf->size = buf->stride * height;
 		buf->tiling = tiling;
 		buf->bpp = bpp;
 
-		aux_width = scratch_buf_aux_width(buf);
-		aux_height = scratch_buf_aux_height(buf);
+		aux_width = scratch_buf_aux_width(data->devid, buf);
+		aux_height = scratch_buf_aux_height(data->devid, buf);
 
 		buf->aux.offset = buf->stride * ALIGN(height, 32);
 		buf->aux.stride = aux_width;
@@ -525,8 +554,8 @@ scratch_buf_check_all(data_t *data,
 static void scratch_buf_aux_check(data_t *data,
 				  struct igt_buf *buf)
 {
-	int aux_size = scratch_buf_aux_width(buf) *
-		scratch_buf_aux_height(buf);
+	int aux_size = scratch_buf_aux_width(data->devid, buf) *
+		scratch_buf_aux_height(data->devid, buf);
 	uint8_t *linear;
 	int i;
 
-- 
2.17.1

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[igt-dev] [PATCH v2 3/3] tests/gem_render_copy: Add compressed src to compressed dst subtests

[Imre Deak]

Add new subtests that blit from a compressed source to a compressed
destination buffer.

v2:
- Use the correct buffer when dumping the png for the compressed buf.

Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 tests/i915/gem_render_copy.c | 126 ++++++++++++++++++++++++++---------
 1 file changed, 93 insertions(+), 33 deletions(-)

diff --git a/tests/i915/gem_render_copy.c b/tests/i915/gem_render_copy.c
index fd139e91..383e86bc 100644
--- a/tests/i915/gem_render_copy.c
+++ b/tests/i915/gem_render_copy.c
@@ -572,9 +572,13 @@ static void scratch_buf_aux_check(data_t *data,
 		     "Aux surface indicates that nothing was compressed\n");
 }
 
-static void test(data_t *data, uint32_t tiling, uint64_t ccs_modifier)
+#define DST_COMPRESSED	1
+#define SRC_COMPRESSED	2
+
+static void test(data_t *data, uint32_t dst_tiling, uint32_t src_tiling,
+		 int flags)
 {
-	struct igt_buf dst, ccs, ref;
+	struct igt_buf dst, src_ccs, dst_ccs, ref;
 	struct {
 		struct igt_buf buf;
 		const char *filename;
@@ -602,22 +606,34 @@ static void test(data_t *data, uint32_t tiling, uint64_t ccs_modifier)
 			.x = 1, .y = 1,
 		},
 	};
-
 	int opt_dump_aub = igt_aub_dump_enabled();
 	int num_src = ARRAY_SIZE(src);
+	bool src_compressed = flags & SRC_COMPRESSED;
+	bool dst_compressed = flags & DST_COMPRESSED;
+
+	/*
+	 * The tiling for uncompressed source buffers is determined by the
+	 * tiling of the src[] buffers above.
+	 */
+	igt_assert(!src_tiling || src_compressed);
 
 	/* no Yf before gen9 */
 	if (intel_gen(data->devid) < 9)
 		num_src--;
 
-	if (tiling == I915_TILING_Yf || ccs_modifier)
+	if (dst_tiling == I915_TILING_Yf || src_tiling == I915_TILING_Yf ||
+	    src_compressed || dst_compressed)
 		igt_require(intel_gen(data->devid) >= 9);
 
 	for (int i = 0; i < num_src; i++)
 		scratch_buf_init(data, &src[i].buf, WIDTH, HEIGHT, src[i].tiling, false);
-	scratch_buf_init(data, &dst, WIDTH, HEIGHT, tiling, false);
-	if (ccs_modifier)
-		scratch_buf_init(data, &ccs, WIDTH, HEIGHT, ccs_modifier, true);
+	scratch_buf_init(data, &dst, WIDTH, HEIGHT, dst_tiling, false);
+	if (src_compressed)
+		scratch_buf_init(data, &src_ccs, WIDTH, HEIGHT,
+				 src_tiling, true);
+	if (dst_compressed)
+		scratch_buf_init(data, &dst_ccs, WIDTH, HEIGHT,
+				 dst_tiling, true);
 	scratch_buf_init(data, &ref, WIDTH, HEIGHT, I915_TILING_NONE, false);
 
 	for (int i = 0; i < num_src; i++)
@@ -657,26 +673,45 @@ static void test(data_t *data, uint32_t tiling, uint64_t ccs_modifier)
 	 *	 |dst|src|
 	 *	  -------
 	 */
-	if (ccs_modifier)
+	if (src_compressed)
 		data->render_copy(data->batch, NULL,
 				  &dst, 0, 0, WIDTH, HEIGHT,
-				  &ccs, 0, 0);
+				  &src_ccs, 0, 0);
 
 	for (int i = 0; i < num_src; i++)
 		data->render_copy(data->batch, NULL,
-				  &src[i].buf, WIDTH/4, HEIGHT/4, WIDTH/2-2, HEIGHT/2-2,
-				  ccs_modifier ? &ccs : &dst, src[i].x, src[i].y);
+				  &src[i].buf,
+				  WIDTH/4, HEIGHT/4, WIDTH/2-2, HEIGHT/2-2,
+				  src_compressed ? &src_ccs : &dst,
+				  src[i].x, src[i].y);
+
+	if (src_compressed || dst_compressed)
+		data->render_copy(data->batch, NULL,
+				  src_compressed ? &src_ccs : &dst,
+				  0, 0, WIDTH, HEIGHT,
+				  dst_compressed ? &dst_ccs : &dst,
+				  0, 0);
 
-	if (ccs_modifier)
+	if (dst_compressed)
 		data->render_copy(data->batch, NULL,
-				  &ccs, 0, 0, WIDTH, HEIGHT,
-				  &dst, 0, 0);
+				  &dst_ccs,
+				  0, 0, WIDTH, HEIGHT,
+				  &dst,
+				  0, 0);
 
 	if (opt_dump_png){
 		scratch_buf_write_to_png(data, &dst, "result.png");
-		if (ccs_modifier) {
-			scratch_buf_write_to_png(data, &ccs, "compressed.png");
-			scratch_buf_aux_write_to_png(data, &ccs, "compressed-aux.png");
+		if (src_compressed) {
+			scratch_buf_write_to_png(data, &src_ccs,
+						 "compressed-src.png");
+			scratch_buf_aux_write_to_png(data, &src_ccs,
+						     "compressed-src-aux.png");
+		}
+		if (dst_compressed) {
+			scratch_buf_write_to_png(data, &dst_ccs,
+						 "compressed-dst.png");
+			scratch_buf_aux_write_to_png(data, &dst_ccs,
+						     "compressed-dst-aux.png");
 		}
 	}
 
@@ -694,12 +729,16 @@ static void test(data_t *data, uint32_t tiling, uint64_t ccs_modifier)
 		scratch_buf_check(data, &dst, &ref, WIDTH - 10, HEIGHT - 10);
 	}
 
-	if (ccs_modifier)
-		scratch_buf_aux_check(data, &ccs);
+	if (src_compressed)
+		scratch_buf_aux_check(data, &src_ccs);
+	if (dst_compressed)
+		scratch_buf_aux_check(data, &dst_ccs);
 
 	scratch_buf_fini(&ref);
-	if (ccs_modifier)
-		scratch_buf_fini(&ccs);
+	if (dst_compressed)
+		scratch_buf_fini(&dst_ccs);
+	if (src_compressed)
+		scratch_buf_fini(&src_ccs);
 	scratch_buf_fini(&dst);
 	for (int i = 0; i < num_src; i++)
 		scratch_buf_fini(&src[i].buf);
@@ -749,31 +788,52 @@ igt_main_args("da", NULL, help_str, opt_handler, NULL)
 	}
 
 	igt_subtest("linear")
-		test(&data, I915_TILING_NONE, 0);
+		test(&data, I915_TILING_NONE, 0, 0);
 	igt_subtest("x-tiled")
-		test(&data, I915_TILING_X, 0);
+		test(&data, I915_TILING_X, 0, 0);
 	igt_subtest("y-tiled")
-		test(&data, I915_TILING_Y, 0);
+		test(&data, I915_TILING_Y, 0, 0);
 	igt_subtest("yf-tiled")
-		test(&data, I915_TILING_Yf, 0);
+		test(&data, I915_TILING_Yf, 0, 0);
 
 	igt_subtest("y-tiled-ccs-to-linear")
-		test(&data, I915_TILING_NONE, I915_TILING_Y);
+		test(&data, I915_TILING_NONE, I915_TILING_Y,
+		     SRC_COMPRESSED);
 	igt_subtest("y-tiled-ccs-to-x-tiled")
-		test(&data, I915_TILING_X, I915_TILING_Y);
+		test(&data, I915_TILING_X, I915_TILING_Y,
+		     SRC_COMPRESSED);
 	igt_subtest("y-tiled-ccs-to-y-tiled")
-		test(&data, I915_TILING_Y, I915_TILING_Y);
+		test(&data, I915_TILING_Y, I915_TILING_Y,
+		     SRC_COMPRESSED);
 	igt_subtest("y-tiled-ccs-to-yf-tiled")
-		test(&data, I915_TILING_Yf, I915_TILING_Y);
+		test(&data, I915_TILING_Yf, I915_TILING_Y,
+		     SRC_COMPRESSED);
 
 	igt_subtest("yf-tiled-ccs-to-linear")
-		test(&data, I915_TILING_NONE, I915_TILING_Yf);
+		test(&data, I915_TILING_NONE, I915_TILING_Yf,
+		     SRC_COMPRESSED);
 	igt_subtest("yf-tiled-ccs-to-x-tiled")
-		test(&data, I915_TILING_X, I915_TILING_Yf);
+		test(&data, I915_TILING_X, I915_TILING_Yf,
+		     SRC_COMPRESSED);
 	igt_subtest("yf-tiled-ccs-to-y-tiled")
-		test(&data, I915_TILING_Y, I915_TILING_Yf);
+		test(&data, I915_TILING_Y, I915_TILING_Yf,
+		     SRC_COMPRESSED);
 	igt_subtest("yf-tiled-ccs-to-yf-tiled")
-		test(&data, I915_TILING_Yf, I915_TILING_Yf);
+		test(&data, I915_TILING_Yf, I915_TILING_Yf,
+		     SRC_COMPRESSED);
+
+	igt_subtest("y-tiled-ccs-to-y-tiled-ccs")
+		test(&data, I915_TILING_Y, I915_TILING_Y,
+		     SRC_COMPRESSED | DST_COMPRESSED);
+	igt_subtest("yf-tiled-ccs-to-yf-tiled-ccs")
+		test(&data, I915_TILING_Yf, I915_TILING_Yf,
+		     SRC_COMPRESSED | DST_COMPRESSED);
+	igt_subtest("y-tiled-ccs-to-yf-tiled-ccs")
+		test(&data, I915_TILING_Yf, I915_TILING_Y,
+		     SRC_COMPRESSED | DST_COMPRESSED);
+	igt_subtest("yf-tiled-ccs-to-y-tiled-ccs")
+		test(&data, I915_TILING_Y, I915_TILING_Yf,
+		     SRC_COMPRESSED | DST_COMPRESSED);
 
 	igt_fixture {
 		igt_stop_hang_detector();
-- 
2.17.1

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[igt-dev] ✗ GitLab.Pipeline: failure for series starting with [v2,1/3] lib/rendercopy: Add AUX page table support

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/3] lib/rendercopy: Add AUX page table support
URL   : https://patchwork.freedesktop.org/series/69012/
State : failure

== Summary ==

ERROR! This series introduces new undocumented tests:

gem_render_copy@y-tiled-ccs-to-y-tiled-ccs
gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs
gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs
gem_render_copy@yf-tiled-ccs-to-yf-tiled-ccs

Can you document them as per the requirement in the [CONTRIBUTING.md]?

[Documentation] has more details on how to do this.

Here are few examples:
https://gitlab.freedesktop.org/drm/igt-gpu-tools/commit/0316695d03aa46108296b27f3982ec93200c7a6e
https://gitlab.freedesktop.org/drm/igt-gpu-tools/commit/443cc658e1e6b492ee17bf4f4d891029eb7a205d

Thanks in advance!

[CONTRIBUTING.md]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/blob/master/CONTRIBUTING.md#L19
[Documentation]: https://drm.pages.freedesktop.org/igt-gpu-tools/igt-gpu-tools-Core.html#igt-describe

Other than that, pipeline status: SUCCESS.

see https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/pipelines/76502 for more details

== Logs ==

For more details see: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/pipelines/76502
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[igt-dev] ✓ Fi.CI.BAT: success for series starting with [v2,1/3] lib/rendercopy: Add AUX page table support

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/3] lib/rendercopy: Add AUX page table support
URL   : https://patchwork.freedesktop.org/series/69012/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7262 -> IGTPW_3657
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/index.html

Known issues
------------

  Here are the changes found in IGTPW_3657 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_flink_basic@basic:
    - fi-icl-u3:          [PASS][1] -> [DMESG-WARN][2] ([fdo#107724] / [fdo#112052 ])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/fi-icl-u3/igt@gem_flink_basic@basic.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/fi-icl-u3/igt@gem_flink_basic@basic.html

  * igt@i915_selftest@live_gem_contexts:
    - fi-bsw-n3050:       [PASS][3] -> [INCOMPLETE][4] ([fdo# 111542])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/fi-bsw-n3050/igt@i915_selftest@live_gem_contexts.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/fi-bsw-n3050/igt@i915_selftest@live_gem_contexts.html

  
#### Possible fixes ####

  * igt@gem_exec_parallel@basic:
    - {fi-tgl-u}:         [INCOMPLETE][5] ([fdo#111887]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/fi-tgl-u/igt@gem_exec_parallel@basic.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/fi-tgl-u/igt@gem_exec_parallel@basic.html

  * igt@gem_flink_basic@double-flink:
    - fi-icl-u3:          [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/fi-icl-u3/igt@gem_flink_basic@double-flink.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/fi-icl-u3/igt@gem_flink_basic@double-flink.html

  * igt@i915_pm_rpm@module-reload:
    - fi-icl-u3:          [DMESG-WARN][9] ([fdo#106107]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/fi-icl-u3/igt@i915_pm_rpm@module-reload.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/fi-icl-u3/igt@i915_pm_rpm@module-reload.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][11] ([fdo#111045] / [fdo#111096]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo# 111542]: https://bugs.freedesktop.org/show_bug.cgi?id= 111542
  [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111887]: https://bugs.freedesktop.org/show_bug.cgi?id=111887
  [fdo#112052 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112052 


Participating hosts (51 -> 43)
------------------------------

  Additional (1): fi-cml-u2 
  Missing    (9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-bwr-2160 fi-ctg-p8600 fi-gdg-551 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5263 -> IGTPW_3657

  CI-20190529: 20190529
  CI_DRM_7262: 6d9033858175fc0e1ef5f77d6bd60356e6b70ee4 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_3657: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/index.html
  IGT_5263: 8a5d44dc5e51622cd43f23c2cf24d44c24a0564d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools



== Testlist changes ==

+igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled-ccs
+igt@gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs
+igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs
+igt@gem_render_copy@y-tiled-ccs-to-y-tiled-ccs

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/index.html
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[igt-dev] [PATCH v3 1/3] lib/rendercopy: Add AUX page table support

[Imre Deak]

On GEN12+ the AUX CCS surfaces required by the render and media
compression must be specified by a 3 level page table directory, which
translates the main surface graphics address to the AUX CCS surface
graphics address. For this purpose add support for creating a GEM buffer
to translate the linear surface address range to the linear AUX surface
address range.

The buffers containing the main surface must be pinned down, since the
directory table entry indices depend on the surface address, and they
must be 64kB aligned. The page table can be relocated OTOH, so allow
that and emit the required relocation entries.

v2:
- Make level variables to be 0 based (l1..l3 -> level=0..2).
- Add missing drm_intel_bo_set_softpin_offset() stub to fix build on
  non-Intel archs.
- Fix missing offsets in reloc entries of already bound objects. (Chris)
- Randomize pin offsets, to try to avoid eviction. (Chris)
- Remove redundant MI_NOOPS around MI_LOAD_REGISTER_MEM
- Stop using explicit reloc cache domains, as these don't make sense on
  GEN12 anyway. (Chris)
- Fix missing autotools support. (Chris)
- s/igt_aux_pgtable/intel_aux_pgtable/, since the functionality is Intel
  specific. (Chris)
v3:
- Make sure all objects with an AUX surface are pinned.

Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 lib/Makefile.sources         |   1 +
 lib/intel_aux_pgtable.c      | 379 +++++++++++++++++++++++++++++++++++
 lib/intel_aux_pgtable.h      |  12 ++
 lib/intel_reg.h              |   2 +
 lib/meson.build              |   1 +
 lib/rendercopy_gen9.c        | 234 ++++++++++++++++++++-
 lib/stubs/drm/intel_bufmgr.c |   6 +
 7 files changed, 629 insertions(+), 6 deletions(-)
 create mode 100644 lib/intel_aux_pgtable.c
 create mode 100644 lib/intel_aux_pgtable.h

diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index cf094ab8..1d0f45f7 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -100,6 +100,7 @@ lib_source_list =	 	\
 	surfaceformat.h		\
 	sw_sync.c		\
 	sw_sync.h		\
+	intel_aux_pgtable.c	\
 	intel_reg_map.c		\
 	intel_iosf.c		\
 	igt_kms.c		\
diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c
new file mode 100644
index 00000000..79402813
--- /dev/null
+++ b/lib/intel_aux_pgtable.c
@@ -0,0 +1,379 @@
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "drmtest.h"
+#include "intel_aux_pgtable.h"
+#include "intel_bufmgr.h"
+#include "intel_batchbuffer.h"
+#include "ioctl_wrappers.h"
+
+#include "i915/gem_mman.h"
+
+#define BITS_PER_LONG		(sizeof(long) * 8)
+#define BITMASK(e, s)		((~0UL << (s)) & \
+				 (~0UL >> (BITS_PER_LONG - 1 - (e))))
+
+#define ALIGN_DOWN(x, a)	ALIGN((x) - ((a) - 1), (a))
+
+/* The unit size to which the AUX CCS surface is aligned to. */
+#define AUX_CCS_UNIT_SIZE	64
+/*
+ * The block size on the AUX CCS surface which is mapped by one L1 AUX
+ * pagetable entry.
+ */
+#define AUX_CCS_BLOCK_SIZE	(4 * AUX_CCS_UNIT_SIZE)
+/*
+ * The block size on the main surface mapped by one AUX CCS block:
+ *   256 bytes per CCS block *
+ *   8   bits per byte /
+ *   2   bits per main surface CL *
+ *   64  bytes per main surface CL
+ */
+#define MAIN_SURFACE_BLOCK_SIZE	(AUX_CCS_BLOCK_SIZE * 8 / 2 * 64)
+
+#define GFX_ADDRESS_BITS	48
+
+#define max(a, b)		((a) > (b) ? (a) : (b))
+
+struct pgtable_level_desc {
+	int idx_shift;
+	int idx_bits;
+	int entry_ptr_shift;
+	int table_size;
+};
+
+struct pgtable_level_info {
+	const struct pgtable_level_desc *desc;
+	int table_count;
+	int alloc_base;
+	int alloc_ptr;
+};
+
+struct pgtable {
+	int levels;
+	struct pgtable_level_info *level_info;
+	int size;
+	int max_align;
+	drm_intel_bo *bo;
+};
+
+static int
+pgt_table_count(int address_bits, const struct igt_buf **bufs, int buf_count)
+{
+	uint64_t end;
+	int count;
+	int i;
+
+	count = 0;
+	end = 0;
+	for (i = 0; i < buf_count; i++) {
+		const struct igt_buf *buf = bufs[i];
+		uint64_t start;
+
+		/* We require bufs to be sorted. */
+		igt_assert(i == 0 ||
+			   buf->bo->offset64 >= bufs[i - 1]->bo->offset64 +
+						bufs[i - 1]->bo->size);
+
+		start = ALIGN_DOWN(buf->bo->offset64, 1UL << address_bits);
+		/* Avoid double counting for overlapping aligned bufs. */
+		start = max(start, end);
+
+		end = ALIGN(buf->bo->offset64 + buf->size, 1UL << address_bits);
+		igt_assert(end >= start);
+
+		count += (end - start) >> address_bits;
+	}
+
+	return count;
+}
+
+static void
+pgt_calc_size(struct pgtable *pgt, const struct igt_buf **bufs, int buf_count)
+{
+	int level;
+
+	pgt->size = 0;
+
+	for (level = pgt->levels - 1; level >= 0; level--) {
+		struct pgtable_level_info *li = &pgt->level_info[level];
+
+		li->alloc_base = ALIGN(pgt->size, li->desc->table_size);
+		li->alloc_ptr = li->alloc_base;
+
+		li->table_count = pgt_table_count(li->desc->idx_shift +
+						  li->desc->idx_bits,
+						  bufs, buf_count);
+
+		pgt->size = li->alloc_base +
+			    li->table_count * li->desc->table_size;
+	}
+}
+
+static uint64_t pgt_alloc_table(struct pgtable *pgt, int level)
+{
+	struct pgtable_level_info *li = &pgt->level_info[level];
+	uint64_t table;
+
+	table = li->alloc_ptr;
+	li->alloc_ptr += li->desc->table_size;
+
+	igt_assert(li->alloc_ptr <=
+		   li->alloc_base + li->table_count * li->desc->table_size);
+
+	return table;
+}
+
+static int pgt_address_index(struct pgtable *pgt, int level, uint64_t address)
+{
+	const struct pgtable_level_desc *ld = pgt->level_info[level].desc;
+	uint64_t mask = BITMASK(ld->idx_shift + ld->idx_bits - 1,
+				ld->idx_shift);
+
+	return (address & mask) >> ld->idx_shift;
+}
+
+static uint64_t ptr_mask(struct pgtable *pgt, int level)
+{
+	const struct pgtable_level_desc *ld = pgt->level_info[level].desc;
+
+	return BITMASK(GFX_ADDRESS_BITS - 1, ld->entry_ptr_shift);
+}
+
+static uint64_t pgt_entry_ptr(struct pgtable *pgt, int level, uint64_t entry)
+{
+	uint64_t ptr = entry & ptr_mask(pgt, level);
+
+	if (level)
+		ptr -= pgt->bo->offset64;
+	igt_assert(!(ptr & ~ptr_mask(pgt, level)));
+
+	return ptr;
+}
+
+static uint64_t pgt_mkentry(struct pgtable *pgt, int level, uint64_t ptr,
+			    uint64_t flags)
+{
+	if (level)
+		ptr += pgt->bo->offset64;
+	igt_assert(!(ptr & ~ptr_mask(pgt, level)));
+
+	return ptr | flags;
+}
+
+static uint64_t
+pgt_get_table(struct pgtable *pgt, uint64_t parent_table,
+	      int level, uint64_t address, uint64_t flags)
+{
+	uint64_t *table_ptr = pgt->bo->virtual + parent_table;
+	int entry_idx = pgt_address_index(pgt, level, address);
+	uint64_t *entry_ptr;
+
+	entry_ptr = &table_ptr[entry_idx];
+	if (!*entry_ptr) {
+		uint64_t child_table = pgt_alloc_table(pgt, level - 1);
+
+		*entry_ptr = pgt_mkentry(pgt, level, child_table, flags);
+
+		drm_intel_bo_emit_reloc(pgt->bo,
+					parent_table + entry_idx * sizeof(uint64_t),
+					pgt->bo, *entry_ptr, 0, 0);
+	}
+
+	return pgt_entry_ptr(pgt, level, *entry_ptr);
+}
+
+static void
+pgt_set_l1_entry(struct pgtable *pgt, uint64_t l1_table,
+		 uint64_t address, uint64_t ptr, uint64_t flags)
+{
+	uint64_t *l1_table_ptr;
+	uint64_t *l1_entry_ptr;
+
+	l1_table_ptr = pgt->bo->virtual + l1_table;
+	l1_entry_ptr = &l1_table_ptr[pgt_address_index(pgt, 0, address)];
+	*l1_entry_ptr = pgt_mkentry(pgt, 0, ptr, flags);
+}
+
+static uint64_t pgt_get_l1_flags(const struct igt_buf *buf)
+{
+	/*
+	 * The offset of .tile_mode isn't specifed by bspec, it's what Mesa
+	 * uses.
+	 */
+	union {
+		struct {
+			uint64_t	valid:1;
+			uint64_t	compression_mod:2;
+			uint64_t	lossy_compression:1;
+			uint64_t	pad:4;
+			uint64_t	addr:40;
+			uint64_t	pad2:4;
+			uint64_t	tile_mode:2;
+			uint64_t	depth:3;
+			uint64_t	ycr:1;
+			uint64_t	format:6;
+		} e;
+		uint64_t l;
+	} entry = {
+		.e = {
+			.valid = 1,
+			.tile_mode = buf->tiling == I915_TILING_Y ? 1 : 0,
+			.depth = 5,		/* 32bpp */
+			.format = 0xA,		/* B8G8R8A8_UNORM */
+		}
+	};
+
+	/*
+	 * TODO: Clarify if Yf is supported and if we need to differentiate
+	 *       Ys and Yf.
+	 *       Add support for more formats.
+	 */
+	igt_assert(buf->tiling == I915_TILING_Y ||
+		   buf->tiling == I915_TILING_Yf ||
+		   buf->tiling == I915_TILING_Ys);
+
+	igt_assert(buf->bpp == 32);
+
+	return entry.l;
+}
+
+static uint64_t pgt_get_lx_flags(void)
+{
+	union {
+		struct {
+			uint64_t        valid:1;
+			uint64_t        addr:47;
+			uint64_t        pad:16;
+		} e;
+		uint64_t l;
+	} entry = {
+		.e = {
+			.valid = 1,
+		}
+	};
+
+	return entry.l;
+}
+
+static void
+pgt_populate_entries_for_buf(struct pgtable *pgt,
+			       const struct igt_buf *buf,
+			       uint64_t top_table)
+{
+	uint64_t surface_addr = buf->bo->offset64;
+	uint64_t surface_end = surface_addr + buf->size;
+	uint64_t aux_addr = buf->bo->offset64 + buf->aux.offset;
+	uint64_t l1_flags = pgt_get_l1_flags(buf);
+	uint64_t lx_flags = pgt_get_lx_flags();
+
+	for (; surface_addr < surface_end;
+	     surface_addr += MAIN_SURFACE_BLOCK_SIZE,
+	     aux_addr += AUX_CCS_BLOCK_SIZE) {
+		uint64_t table = top_table;
+		int level;
+
+		for (level = pgt->levels - 1; level >= 1; level--)
+			table = pgt_get_table(pgt, table, level,
+					      surface_addr, lx_flags);
+
+		pgt_set_l1_entry(pgt, table, surface_addr, aux_addr, l1_flags);
+	}
+}
+
+static void pgt_populate_entries(struct pgtable *pgt,
+				 const struct igt_buf **bufs,
+				 int buf_count,
+				 drm_intel_bo *pgt_bo)
+{
+	uint64_t top_table;
+	int i;
+
+	pgt->bo = pgt_bo;
+
+	igt_assert(pgt_bo->size >= pgt->size);
+	memset(pgt_bo->virtual, 0, pgt->size);
+
+	top_table = pgt_alloc_table(pgt, pgt->levels - 1);
+	/* Top level table must be at offset 0. */
+	igt_assert(top_table == 0);
+
+	for (i = 0; i < buf_count; i++)
+		pgt_populate_entries_for_buf(pgt, bufs[i], top_table);
+}
+
+static struct pgtable *
+pgt_create(const struct pgtable_level_desc *level_descs, int levels,
+	   const struct igt_buf **bufs, int buf_count)
+{
+	struct pgtable *pgt;
+	int level;
+
+	pgt = calloc(1, sizeof(*pgt));
+	igt_assert(pgt);
+
+	pgt->levels = levels;
+
+	pgt->level_info = calloc(levels, sizeof(*pgt->level_info));
+	igt_assert(pgt->level_info);
+
+	for (level = 0; level < pgt->levels; level++) {
+		struct pgtable_level_info *li = &pgt->level_info[level];
+
+		li->desc = &level_descs[level];
+		if (li->desc->table_size > pgt->max_align)
+			pgt->max_align = li->desc->table_size;
+	}
+
+	pgt_calc_size(pgt, bufs, buf_count);
+
+	return pgt;
+}
+
+static void pgt_destroy(struct pgtable *pgt)
+{
+	free(pgt->level_info);
+	free(pgt);
+}
+
+drm_intel_bo *
+intel_aux_pgtable_create(drm_intel_bufmgr *bufmgr,
+		       const struct igt_buf **bufs, int buf_count)
+{
+	static const struct pgtable_level_desc level_desc[] = {
+		{
+			.idx_shift = 16,
+			.idx_bits = 8,
+			.entry_ptr_shift = 8,
+			.table_size = 8 * 1024,
+		},
+		{
+			.idx_shift = 24,
+			.idx_bits = 12,
+			.entry_ptr_shift = 13,
+			.table_size = 32 * 1024,
+		},
+		{
+			.idx_shift = 36,
+			.idx_bits = 12,
+			.entry_ptr_shift = 15,
+			.table_size = 32 * 1024,
+		},
+	};
+	struct pgtable *pgt;
+	drm_intel_bo *pgt_bo;
+
+	pgt = pgt_create(level_desc, ARRAY_SIZE(level_desc), bufs, buf_count);
+
+	pgt_bo = drm_intel_bo_alloc_for_render(bufmgr, "aux pgt",
+					       pgt->size, pgt->max_align);
+	igt_assert(pgt_bo);
+
+	igt_assert(drm_intel_bo_map(pgt_bo, true) == 0);
+	pgt_populate_entries(pgt, bufs, buf_count, pgt_bo);
+	igt_assert(drm_intel_bo_unmap(pgt_bo) == 0);
+
+	pgt_destroy(pgt);
+
+	return pgt_bo;
+}
diff --git a/lib/intel_aux_pgtable.h b/lib/intel_aux_pgtable.h
new file mode 100644
index 00000000..533d4491
--- /dev/null
+++ b/lib/intel_aux_pgtable.h
@@ -0,0 +1,12 @@
+#ifndef _IGT_AUX_PGTABLE_H_
+#define _IGT_AUX_PGTABLE_H_
+
+#include "intel_bufmgr.h"
+
+struct igt_buf;
+
+drm_intel_bo *
+intel_aux_pgtable_create(drm_intel_bufmgr *bufmgr,
+			 const struct igt_buf **bufs, int buf_count);
+
+#endif
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index 069440cb..755a78e6 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -673,6 +673,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define RING_VALID          0x00000001
 #define RING_INVALID        0x00000000
 
+#define GEN12_GFX_AUX_TABLE_BASE_ADDR	0x4200
 
 
 /* BitBlt Instructions
@@ -2570,6 +2571,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 #define MI_LOAD_SCAN_LINES_INCL		(0x12<<23)
 #define MI_LOAD_REGISTER_IMM		((0x22 << 23) | 1)
+#define MI_LOAD_REGISTER_MEM		((0x29 << 23) | (4 - 2))
 
 /* Flush */
 #define MI_FLUSH			(0x04<<23)
diff --git a/lib/meson.build b/lib/meson.build
index 221ae28c..33fef486 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -44,6 +44,7 @@ lib_sources = [
 	'rendercopy_gen8.c',
 	'rendercopy_gen9.c',
 	'sw_sync.c',
+	'intel_aux_pgtable.c',
 	'intel_reg_map.c',
 	'intel_iosf.c',
 	'igt_kms.c',
diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index 694eb3cf..447d6ce9 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -15,6 +15,7 @@
 #include <i915_drm.h>
 
 #include "drmtest.h"
+#include "intel_aux_pgtable.h"
 #include "intel_bufmgr.h"
 #include "intel_batchbuffer.h"
 #include "intel_io.h"
@@ -972,19 +973,226 @@ static void gen8_emit_primitive(struct intel_batchbuffer *batch, uint32_t offset
 
 #define BATCH_STATE_SPLIT 2048
 
+static void
+gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch, uint32_t state)
+{
+	if (!state)
+		return;
+
+	OUT_BATCH(MI_LOAD_REGISTER_MEM);
+	OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR);
+	OUT_RELOC(batch->bo, 0, 0, state);
+
+	OUT_BATCH(MI_LOAD_REGISTER_MEM);
+	OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR + 4);
+	OUT_RELOC(batch->bo, 0, 0, state + 4);
+}
+
+static void
+aux_pgtable_find_max_free_range(const struct igt_buf **bufs, int buf_count,
+				uint64_t *range_start, uint64_t *range_size)
+{
+	/*
+	 * Keep the first page reserved, so we can differentiate pinned
+	 * objects based on a non-NULL offset.
+	 */
+	uint64_t start = 0x1000;
+	/* For now alloc only from the first 4GB address space. */
+	const uint64_t end = 1ULL << 32;
+	uint64_t max_range_start = 0;
+	uint64_t max_range_size = 0;
+	int i;
+
+	for (i = 0; i < buf_count; i++) {
+		if (bufs[i]->bo->offset64 >= end)
+			break;
+
+		if (bufs[i]->bo->offset64 - start > max_range_size) {
+			max_range_start = start;
+			max_range_size = bufs[i]->bo->offset64 - start;
+		}
+		start = bufs[i]->bo->offset64 + bufs[i]->size;
+	}
+
+	if (start < end && end - start > max_range_size) {
+		max_range_start = start;
+		max_range_size = end - start;
+	}
+
+	*range_start = max_range_start;
+	*range_size = max_range_size;
+}
+
+static uint64_t
+aux_pgtable_find_free_range(const struct igt_buf **bufs, int buf_count,
+			    uint32_t size)
+{
+	uint64_t range_start;
+	uint64_t range_size;
+	/* A compressed surface must be 64kB aligned. */
+	const uint32_t align = 0x10000;
+	int pad;
+
+	aux_pgtable_find_max_free_range(bufs, buf_count,
+					&range_start, &range_size);
+
+	pad = ALIGN(range_start, align) - range_start;
+	range_start += pad;
+	range_size -= pad;
+	igt_assert(range_size >= size);
+
+	return range_start + ALIGN(rand() % (range_size - size), align);
+}
+
+static void
+aux_pgtable_reserve_range(const struct igt_buf **bufs, int buf_count,
+			  const struct igt_buf *new_buf)
+{
+	int i;
+
+	if (new_buf->aux.stride) {
+		uint64_t pin_offset = new_buf->bo->offset64;
+
+		if (!pin_offset)
+			pin_offset = aux_pgtable_find_free_range(bufs,
+								 buf_count,
+								 new_buf->bo->size);
+		drm_intel_bo_set_softpin_offset(new_buf->bo, pin_offset);
+		igt_assert(new_buf->bo->offset64 == pin_offset);
+	}
+
+	for (i = 0; i < buf_count; i++)
+		if (bufs[i]->bo->offset64 > new_buf->bo->offset64)
+			break;
+
+	memmove(&bufs[i + 1], &bufs[i], sizeof(bufs[0]) * (buf_count - i));
+
+	bufs[i] = new_buf;
+}
+
+struct aux_pgtable_info {
+	int buf_count;
+	const struct igt_buf *bufs[2];
+	uint64_t buf_pin_offsets[2];
+	drm_intel_bo *pgtable_bo;
+};
+
+static void
+gen12_aux_pgtable_init(struct aux_pgtable_info *info,
+		       drm_intel_bufmgr *bufmgr,
+		       const struct igt_buf *src_buf,
+		       const struct igt_buf *dst_buf)
+{
+	const struct igt_buf *bufs[2];
+	const struct igt_buf *reserved_bufs[2];
+	int reserved_buf_count;
+	int i;
+
+	if (!src_buf->aux.stride && !dst_buf->aux.stride)
+		return;
+
+	bufs[0] = src_buf;
+	bufs[1] = dst_buf;
+
+	/*
+	 * Ideally we'd need a an IGT-wide GFX address space allocator, which
+	 * would consider all allocations and thus avoid evictions. For now use
+	 * a simpler scheme here, which only considers the buffers involved in
+	 * the blit, which should at least minimize the chance for evictions
+	 * in the case of subsequent blits:
+	 *   1. If they were already bound (bo->offset64 != 0), use this
+	 *      address.
+	 *   2. Pick a range randomly from the 4GB address space, that is not
+	 *      already occupied by a bound object, or an object we pinned.
+	 */
+	reserved_buf_count = 0;
+	/* First reserve space for any bufs that are bound already. */
+	for (i = 0; i < ARRAY_SIZE(bufs); i++)
+		if (bufs[i]->bo->offset64)
+			aux_pgtable_reserve_range(reserved_bufs,
+						  reserved_buf_count++,
+						  bufs[i]);
+
+	/* Next, reserve space for unbound bufs with an AUX surface. */
+	for (i = 0; i < ARRAY_SIZE(bufs); i++)
+		if (!bufs[i]->bo->offset64 && bufs[i]->aux.stride)
+			aux_pgtable_reserve_range(reserved_bufs,
+						  reserved_buf_count++,
+						  bufs[i]);
+
+	/* Create AUX pgtable entries only for bufs with an AUX surface */
+	info->buf_count = 0;
+	for (i = 0; i < reserved_buf_count; i++) {
+		if (!reserved_bufs[i]->aux.stride)
+			continue;
+
+		info->bufs[info->buf_count] = reserved_bufs[i];
+		info->buf_pin_offsets[info->buf_count] =
+			reserved_bufs[i]->bo->offset64;
+		info->buf_count++;
+	}
+
+	info->pgtable_bo = intel_aux_pgtable_create(bufmgr,
+						    info->bufs,
+						    info->buf_count);
+	igt_assert(info->pgtable_bo);
+}
+
+static void
+gen12_aux_pgtable_cleanup(struct aux_pgtable_info *info)
+{
+	int i;
+
+	/* Check that the pinned bufs kept their offset after the exec. */
+	for (i = 0; i < info->buf_count; i++)
+		igt_assert_eq_u64(info->bufs[i]->bo->offset64,
+				  info->buf_pin_offsets[i]);
+
+	drm_intel_bo_unreference(info->pgtable_bo);
+}
+
+static uint32_t
+gen12_create_aux_pgtable_state(struct intel_batchbuffer *batch,
+			       drm_intel_bo *aux_pgtable_bo)
+{
+	uint64_t *pgtable_ptr;
+	uint32_t pgtable_ptr_offset;
+	int ret;
+
+	if (!aux_pgtable_bo)
+		return 0;
+
+	pgtable_ptr = intel_batchbuffer_subdata_alloc(batch,
+						      sizeof(*pgtable_ptr),
+						      sizeof(*pgtable_ptr));
+	pgtable_ptr_offset = intel_batchbuffer_subdata_offset(batch,
+							      pgtable_ptr);
+
+	*pgtable_ptr = aux_pgtable_bo->offset64;
+	ret = drm_intel_bo_emit_reloc(batch->bo, pgtable_ptr_offset,
+				      aux_pgtable_bo, 0,
+				      0, 0);
+	assert(ret == 0);
+
+	return pgtable_ptr_offset;
+}
+
 static
 void _gen9_render_copyfunc(struct intel_batchbuffer *batch,
 			  drm_intel_context *context,
 			  const struct igt_buf *src, unsigned src_x,
 			  unsigned src_y, unsigned width, unsigned height,
 			  const struct igt_buf *dst, unsigned dst_x,
-			  unsigned dst_y, const uint32_t ps_kernel[][4],
+			  unsigned dst_y,
+			  drm_intel_bo *aux_pgtable_bo,
+			  const uint32_t ps_kernel[][4],
 			  uint32_t ps_kernel_size)
 {
 	uint32_t ps_sampler_state, ps_kernel_off, ps_binding_table;
 	uint32_t scissor_state;
 	uint32_t vertex_buffer;
 	uint32_t batch_end;
+	uint32_t aux_pgtable_state;
 
 	igt_assert(src->bpp == dst->bpp);
 	intel_batchbuffer_flush_with_context(batch, context);
@@ -1007,6 +1215,10 @@ void _gen9_render_copyfunc(struct intel_batchbuffer *batch,
 	viewport.cc_state = gen6_create_cc_viewport(batch);
 	viewport.sf_clip_state = gen7_create_sf_clip_viewport(batch);
 	scissor_state = gen6_create_scissor_rect(batch);
+
+	aux_pgtable_state = gen12_create_aux_pgtable_state(batch,
+							   aux_pgtable_bo);
+
 	/* TODO: theree is other state which isn't setup */
 
 	assert(batch->ptr < &batch->buffer[4095]);
@@ -1018,6 +1230,8 @@ void _gen9_render_copyfunc(struct intel_batchbuffer *batch,
 	OUT_BATCH(G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D |
 				GEN9_PIPELINE_SELECTION_MASK);
 
+	gen12_emit_aux_pgtable_state(batch, aux_pgtable_state);
+
 	gen8_emit_sip(batch);
 
 	gen7_emit_push_constants(batch);
@@ -1092,8 +1306,8 @@ void gen9_render_copyfunc(struct intel_batchbuffer *batch,
 
 {
 	_gen9_render_copyfunc(batch, context, src, src_x, src_y,
-			  width, height, dst, dst_x, dst_y, ps_kernel_gen9,
-			  sizeof(ps_kernel_gen9));
+			  width, height, dst, dst_x, dst_y, NULL,
+			  ps_kernel_gen9, sizeof(ps_kernel_gen9));
 }
 
 void gen11_render_copyfunc(struct intel_batchbuffer *batch,
@@ -1104,8 +1318,8 @@ void gen11_render_copyfunc(struct intel_batchbuffer *batch,
 
 {
 	_gen9_render_copyfunc(batch, context, src, src_x, src_y,
-			  width, height, dst, dst_x, dst_y, ps_kernel_gen11,
-			  sizeof(ps_kernel_gen11));
+			  width, height, dst, dst_x, dst_y, NULL,
+			  ps_kernel_gen11, sizeof(ps_kernel_gen11));
 }
 
 void gen12_render_copyfunc(struct intel_batchbuffer *batch,
@@ -1115,7 +1329,15 @@ void gen12_render_copyfunc(struct intel_batchbuffer *batch,
 			   const struct igt_buf *dst, unsigned dst_x, unsigned dst_y)
 
 {
+	struct aux_pgtable_info pgtable_info = { };
+
+	gen12_aux_pgtable_init(&pgtable_info, batch->bufmgr, src, dst);
+
 	_gen9_render_copyfunc(batch, context, src, src_x, src_y,
-			  width, height, dst, dst_x, dst_y, gen12_render_copy,
+			  width, height, dst, dst_x, dst_y,
+			  pgtable_info.pgtable_bo,
+			  gen12_render_copy,
 			  sizeof(gen12_render_copy));
+
+	gen12_aux_pgtable_cleanup(&pgtable_info);
 }
diff --git a/lib/stubs/drm/intel_bufmgr.c b/lib/stubs/drm/intel_bufmgr.c
index f87452ac..cbab2484 100644
--- a/lib/stubs/drm/intel_bufmgr.c
+++ b/lib/stubs/drm/intel_bufmgr.c
@@ -233,6 +233,12 @@ int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
 	return -ENODEV;
 }
 
+int drm_intel_bo_set_softpin_offset(drm_intel_bo *bo, uint64_t offset)
+{
+	igt_require_f(false, missing_support_str);
+	return -ENODEV;
+}
+
 int drm_intel_bo_disable_reuse(drm_intel_bo *bo)
 {
 	igt_require_f(false, missing_support_str);
-- 
2.17.1

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[igt-dev] ✗ GitLab.Pipeline: failure for series starting with [v3,1/3] lib/rendercopy: Add AUX page table support (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [v3,1/3] lib/rendercopy: Add AUX page table support (rev2)
URL   : https://patchwork.freedesktop.org/series/69012/
State : failure

== Summary ==

ERROR! This series introduces new undocumented tests:

gem_render_copy@y-tiled-ccs-to-y-tiled-ccs
gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs
gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs
gem_render_copy@yf-tiled-ccs-to-yf-tiled-ccs

Can you document them as per the requirement in the [CONTRIBUTING.md]?

[Documentation] has more details on how to do this.

Here are few examples:
https://gitlab.freedesktop.org/drm/igt-gpu-tools/commit/0316695d03aa46108296b27f3982ec93200c7a6e
https://gitlab.freedesktop.org/drm/igt-gpu-tools/commit/443cc658e1e6b492ee17bf4f4d891029eb7a205d

Thanks in advance!

[CONTRIBUTING.md]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/blob/master/CONTRIBUTING.md#L19
[Documentation]: https://drm.pages.freedesktop.org/igt-gpu-tools/igt-gpu-tools-Core.html#igt-describe

Other than that, pipeline status: SUCCESS.

see https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/pipelines/76535 for more details

== Logs ==

For more details see: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/pipelines/76535
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[igt-dev] ✓ Fi.CI.BAT: success for series starting with [v3,1/3] lib/rendercopy: Add AUX page table support (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [v3,1/3] lib/rendercopy: Add AUX page table support (rev2)
URL   : https://patchwork.freedesktop.org/series/69012/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7263 -> IGTPW_3658
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_3658:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@prime_vgem@basic-fence-read:
    - {fi-icl-dsi}:       [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/fi-icl-dsi/igt@prime_vgem@basic-fence-read.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/fi-icl-dsi/igt@prime_vgem@basic-fence-read.html

  
Known issues
------------

  Here are the changes found in IGTPW_3658 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_flink_basic@bad-flink:
    - fi-icl-u3:          [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/fi-icl-u3/igt@gem_flink_basic@bad-flink.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/fi-icl-u3/igt@gem_flink_basic@bad-flink.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s4-devices:
    - fi-icl-u3:          [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/fi-icl-u3/igt@gem_exec_suspend@basic-s4-devices.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/fi-icl-u3/igt@gem_exec_suspend@basic-s4-devices.html

  * igt@i915_selftest@live_blt:
    - fi-bsw-nick:        [DMESG-FAIL][7] ([fdo#112176]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/fi-bsw-nick/igt@i915_selftest@live_blt.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/fi-bsw-nick/igt@i915_selftest@live_blt.html

  * igt@i915_selftest@live_gem_contexts:
    - fi-bsw-n3050:       [INCOMPLETE][9] ([fdo# 111542]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/fi-bsw-n3050/igt@i915_selftest@live_gem_contexts.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/fi-bsw-n3050/igt@i915_selftest@live_gem_contexts.html

  * {igt@i915_selftest@live_gt_timelines}:
    - {fi-tgl-u}:         [INCOMPLETE][11] ([fdo#111831]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/fi-tgl-u/igt@i915_selftest@live_gt_timelines.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/fi-tgl-u/igt@i915_selftest@live_gt_timelines.html

  * igt@kms_chamelium@dp-crc-fast:
    - {fi-icl-u4}:        [FAIL][13] ([fdo#111045]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/fi-icl-u4/igt@kms_chamelium@dp-crc-fast.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/fi-icl-u4/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][15] ([fdo#111407]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@kms_flip@basic-flip-vs-dpms:
    - fi-skl-6770hq:      [SKIP][17] ([fdo#109271]) -> [PASS][18] +26 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/fi-skl-6770hq/igt@kms_flip@basic-flip-vs-dpms.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/fi-skl-6770hq/igt@kms_flip@basic-flip-vs-dpms.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo# 111542]: https://bugs.freedesktop.org/show_bug.cgi?id= 111542
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
  [fdo#111831]: https://bugs.freedesktop.org/show_bug.cgi?id=111831
  [fdo#112176]: https://bugs.freedesktop.org/show_bug.cgi?id=112176


Participating hosts (52 -> 43)
------------------------------

  Missing    (9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-bwr-2160 fi-ctg-p8600 fi-gdg-551 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5263 -> IGTPW_3658

  CI-20190529: 20190529
  CI_DRM_7263: 52111484eec1ab70a78b8246b64290fbbb263f12 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_3658: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/index.html
  IGT_5263: 8a5d44dc5e51622cd43f23c2cf24d44c24a0564d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools



== Testlist changes ==

+igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled-ccs
+igt@gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs
+igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs
+igt@gem_render_copy@y-tiled-ccs-to-y-tiled-ccs

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/index.html
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Re: [igt-dev] [PATCH v3 1/3] lib/rendercopy: Add AUX page table support

[Chris Wilson]

Quoting Imre Deak (2019-11-05 21:42:20)
> @@ -2570,6 +2571,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>  
>  #define MI_LOAD_SCAN_LINES_INCL                (0x12<<23)
>  #define MI_LOAD_REGISTER_IMM           ((0x22 << 23) | 1)
> +#define MI_LOAD_REGISTER_MEM           ((0x29 << 23) | (4 - 2))

I would suggest not to include the len here, it varies by gen.
-Chris
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Re: [igt-dev] [PATCH v3 1/3] lib/rendercopy: Add AUX page table support

[Imre Deak]

On Tue, Nov 05, 2019 at 10:24:46PM +0000, Chris Wilson wrote:
> Quoting Imre Deak (2019-11-05 21:42:20)
> > @@ -2570,6 +2571,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
> >  
> >  #define MI_LOAD_SCAN_LINES_INCL                (0x12<<23)
> >  #define MI_LOAD_REGISTER_IMM           ((0x22 << 23) | 1)
> > +#define MI_LOAD_REGISTER_MEM           ((0x29 << 23) | (4 - 2))
> 
> I would suggest not to include the len here, it varies by gen.

How about MI_LOAD_REGISTER_MEM_GEN8?

> -Chris
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[igt-dev] [PATCH v4 1/3] lib/rendercopy: Add AUX page table support

[Imre Deak]

On GEN12+ the AUX CCS surfaces required by the render and media
compression must be specified by a 3 level page table directory, which
translates the main surface graphics address to the AUX CCS surface
graphics address. For this purpose add support for creating a GEM buffer
to translate the linear surface address range to the linear AUX surface
address range.

The buffers containing the main surface must be pinned down, since the
directory table entry indices depend on the surface address, and they
must be 64kB aligned. The page table can be relocated OTOH, so allow
that and emit the required relocation entries.

v2:
- Make level variables to be 0 based (l1..l3 -> level=0..2).
- Add missing drm_intel_bo_set_softpin_offset() stub to fix build on
  non-Intel archs.
- Fix missing offsets in reloc entries of already bound objects. (Chris)
- Randomize pin offsets, to try to avoid eviction. (Chris)
- Remove redundant MI_NOOPS around MI_LOAD_REGISTER_MEM
- Stop using explicit reloc cache domains, as these don't make sense on
  GEN12 anyway. (Chris)
- Fix missing autotools support. (Chris)
- s/igt_aux_pgtable/intel_aux_pgtable/, since the functionality is Intel
  specific. (Chris)
v3:
- Make sure all objects with an AUX surface are pinned.
v4:
- s/MI_LOAD_REGISTER_MEM/MI_LOAD_REGISTER_MEM_GEN8/ (Chris)
- Fix using buf->bo->size instead of buf->size when finding a free
  range for a pinned obj.
- Fix alignment of the reserved space start for a pinned obj.
- Move gen12_emit_aux_pgtable_state() to its logical spot.

Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 lib/Makefile.sources         |   1 +
 lib/drmtest.h                |   9 +
 lib/intel_aux_pgtable.c      | 377 +++++++++++++++++++++++++++++++++++
 lib/intel_aux_pgtable.h      |  12 ++
 lib/intel_reg.h              |   2 +
 lib/meson.build              |   1 +
 lib/rendercopy_gen9.c        | 234 +++++++++++++++++++++-
 lib/stubs/drm/intel_bufmgr.c |   6 +
 8 files changed, 636 insertions(+), 6 deletions(-)
 create mode 100644 lib/intel_aux_pgtable.c
 create mode 100644 lib/intel_aux_pgtable.h

diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index cf094ab8..1d0f45f7 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -100,6 +100,7 @@ lib_source_list =	 	\
 	surfaceformat.h		\
 	sw_sync.c		\
 	sw_sync.h		\
+	intel_aux_pgtable.c	\
 	intel_reg_map.c		\
 	intel_iosf.c		\
 	igt_kms.c		\
diff --git a/lib/drmtest.h b/lib/drmtest.h
index 614f57e6..05eb0860 100644
--- a/lib/drmtest.h
+++ b/lib/drmtest.h
@@ -77,6 +77,15 @@ void __set_forced_driver(const char *name);
  */
 #define ALIGN(v, a) (((v) + (a)-1) & ~((a)-1))
 
+/**
+ * ALIGN_DOWN:
+ * @v: value to be aligned down
+ * @a: alignment unit in bytes
+ *
+ * Macro to align down a value @v to a specified unit @a.
+ */
+#define ALIGN_DOWN(x, a)	ALIGN((x) - ((a) - 1), (a))
+
 int drm_open_driver(int chipset);
 int drm_open_driver_master(int chipset);
 int drm_open_driver_render(int chipset);
diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c
new file mode 100644
index 00000000..e1249dee
--- /dev/null
+++ b/lib/intel_aux_pgtable.c
@@ -0,0 +1,377 @@
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "drmtest.h"
+#include "intel_aux_pgtable.h"
+#include "intel_batchbuffer.h"
+#include "intel_bufmgr.h"
+#include "ioctl_wrappers.h"
+
+#include "i915/gem_mman.h"
+
+#define BITS_PER_LONG		(sizeof(long) * 8)
+#define BITMASK(e, s)		((~0UL << (s)) & \
+				 (~0UL >> (BITS_PER_LONG - 1 - (e))))
+
+/* The unit size to which the AUX CCS surface is aligned to. */
+#define AUX_CCS_UNIT_SIZE	64
+/*
+ * The block size on the AUX CCS surface which is mapped by one L1 AUX
+ * pagetable entry.
+ */
+#define AUX_CCS_BLOCK_SIZE	(4 * AUX_CCS_UNIT_SIZE)
+/*
+ * The block size on the main surface mapped by one AUX CCS block:
+ *   256 bytes per CCS block *
+ *   8   bits per byte /
+ *   2   bits per main surface CL *
+ *   64  bytes per main surface CL
+ */
+#define MAIN_SURFACE_BLOCK_SIZE	(AUX_CCS_BLOCK_SIZE * 8 / 2 * 64)
+
+#define GFX_ADDRESS_BITS	48
+
+#define max(a, b)		((a) > (b) ? (a) : (b))
+
+struct pgtable_level_desc {
+	int idx_shift;
+	int idx_bits;
+	int entry_ptr_shift;
+	int table_size;
+};
+
+struct pgtable_level_info {
+	const struct pgtable_level_desc *desc;
+	int table_count;
+	int alloc_base;
+	int alloc_ptr;
+};
+
+struct pgtable {
+	int levels;
+	struct pgtable_level_info *level_info;
+	int size;
+	int max_align;
+	drm_intel_bo *bo;
+};
+
+static int
+pgt_table_count(int address_bits, const struct igt_buf **bufs, int buf_count)
+{
+	uint64_t end;
+	int count;
+	int i;
+
+	count = 0;
+	end = 0;
+	for (i = 0; i < buf_count; i++) {
+		const struct igt_buf *buf = bufs[i];
+		uint64_t start;
+
+		/* We require bufs to be sorted. */
+		igt_assert(i == 0 ||
+			   buf->bo->offset64 >= bufs[i - 1]->bo->offset64 +
+						bufs[i - 1]->bo->size);
+
+		start = ALIGN_DOWN(buf->bo->offset64, 1UL << address_bits);
+		/* Avoid double counting for overlapping aligned bufs. */
+		start = max(start, end);
+
+		end = ALIGN(buf->bo->offset64 + buf->size, 1UL << address_bits);
+		igt_assert(end >= start);
+
+		count += (end - start) >> address_bits;
+	}
+
+	return count;
+}
+
+static void
+pgt_calc_size(struct pgtable *pgt, const struct igt_buf **bufs, int buf_count)
+{
+	int level;
+
+	pgt->size = 0;
+
+	for (level = pgt->levels - 1; level >= 0; level--) {
+		struct pgtable_level_info *li = &pgt->level_info[level];
+
+		li->alloc_base = ALIGN(pgt->size, li->desc->table_size);
+		li->alloc_ptr = li->alloc_base;
+
+		li->table_count = pgt_table_count(li->desc->idx_shift +
+						  li->desc->idx_bits,
+						  bufs, buf_count);
+
+		pgt->size = li->alloc_base +
+			    li->table_count * li->desc->table_size;
+	}
+}
+
+static uint64_t pgt_alloc_table(struct pgtable *pgt, int level)
+{
+	struct pgtable_level_info *li = &pgt->level_info[level];
+	uint64_t table;
+
+	table = li->alloc_ptr;
+	li->alloc_ptr += li->desc->table_size;
+
+	igt_assert(li->alloc_ptr <=
+		   li->alloc_base + li->table_count * li->desc->table_size);
+
+	return table;
+}
+
+static int pgt_address_index(struct pgtable *pgt, int level, uint64_t address)
+{
+	const struct pgtable_level_desc *ld = pgt->level_info[level].desc;
+	uint64_t mask = BITMASK(ld->idx_shift + ld->idx_bits - 1,
+				ld->idx_shift);
+
+	return (address & mask) >> ld->idx_shift;
+}
+
+static uint64_t ptr_mask(struct pgtable *pgt, int level)
+{
+	const struct pgtable_level_desc *ld = pgt->level_info[level].desc;
+
+	return BITMASK(GFX_ADDRESS_BITS - 1, ld->entry_ptr_shift);
+}
+
+static uint64_t pgt_entry_ptr(struct pgtable *pgt, int level, uint64_t entry)
+{
+	uint64_t ptr = entry & ptr_mask(pgt, level);
+
+	if (level)
+		ptr -= pgt->bo->offset64;
+	igt_assert(!(ptr & ~ptr_mask(pgt, level)));
+
+	return ptr;
+}
+
+static uint64_t pgt_mkentry(struct pgtable *pgt, int level, uint64_t ptr,
+			    uint64_t flags)
+{
+	if (level)
+		ptr += pgt->bo->offset64;
+	igt_assert(!(ptr & ~ptr_mask(pgt, level)));
+
+	return ptr | flags;
+}
+
+static uint64_t
+pgt_get_table(struct pgtable *pgt, uint64_t parent_table,
+	      int level, uint64_t address, uint64_t flags)
+{
+	uint64_t *table_ptr = pgt->bo->virtual + parent_table;
+	int entry_idx = pgt_address_index(pgt, level, address);
+	uint64_t *entry_ptr;
+
+	entry_ptr = &table_ptr[entry_idx];
+	if (!*entry_ptr) {
+		uint64_t child_table = pgt_alloc_table(pgt, level - 1);
+
+		*entry_ptr = pgt_mkentry(pgt, level, child_table, flags);
+
+		drm_intel_bo_emit_reloc(pgt->bo,
+					parent_table + entry_idx * sizeof(uint64_t),
+					pgt->bo, *entry_ptr, 0, 0);
+	}
+
+	return pgt_entry_ptr(pgt, level, *entry_ptr);
+}
+
+static void
+pgt_set_l1_entry(struct pgtable *pgt, uint64_t l1_table,
+		 uint64_t address, uint64_t ptr, uint64_t flags)
+{
+	uint64_t *l1_table_ptr;
+	uint64_t *l1_entry_ptr;
+
+	l1_table_ptr = pgt->bo->virtual + l1_table;
+	l1_entry_ptr = &l1_table_ptr[pgt_address_index(pgt, 0, address)];
+	*l1_entry_ptr = pgt_mkentry(pgt, 0, ptr, flags);
+}
+
+static uint64_t pgt_get_l1_flags(const struct igt_buf *buf)
+{
+	/*
+	 * The offset of .tile_mode isn't specifed by bspec, it's what Mesa
+	 * uses.
+	 */
+	union {
+		struct {
+			uint64_t	valid:1;
+			uint64_t	compression_mod:2;
+			uint64_t	lossy_compression:1;
+			uint64_t	pad:4;
+			uint64_t	addr:40;
+			uint64_t	pad2:4;
+			uint64_t	tile_mode:2;
+			uint64_t	depth:3;
+			uint64_t	ycr:1;
+			uint64_t	format:6;
+		} e;
+		uint64_t l;
+	} entry = {
+		.e = {
+			.valid = 1,
+			.tile_mode = buf->tiling == I915_TILING_Y ? 1 : 0,
+			.depth = 5,		/* 32bpp */
+			.format = 0xA,		/* B8G8R8A8_UNORM */
+		}
+	};
+
+	/*
+	 * TODO: Clarify if Yf is supported and if we need to differentiate
+	 *       Ys and Yf.
+	 *       Add support for more formats.
+	 */
+	igt_assert(buf->tiling == I915_TILING_Y ||
+		   buf->tiling == I915_TILING_Yf ||
+		   buf->tiling == I915_TILING_Ys);
+
+	igt_assert(buf->bpp == 32);
+
+	return entry.l;
+}
+
+static uint64_t pgt_get_lx_flags(void)
+{
+	union {
+		struct {
+			uint64_t        valid:1;
+			uint64_t        addr:47;
+			uint64_t        pad:16;
+		} e;
+		uint64_t l;
+	} entry = {
+		.e = {
+			.valid = 1,
+		}
+	};
+
+	return entry.l;
+}
+
+static void
+pgt_populate_entries_for_buf(struct pgtable *pgt,
+			       const struct igt_buf *buf,
+			       uint64_t top_table)
+{
+	uint64_t surface_addr = buf->bo->offset64;
+	uint64_t surface_end = surface_addr + buf->size;
+	uint64_t aux_addr = buf->bo->offset64 + buf->aux.offset;
+	uint64_t l1_flags = pgt_get_l1_flags(buf);
+	uint64_t lx_flags = pgt_get_lx_flags();
+
+	for (; surface_addr < surface_end;
+	     surface_addr += MAIN_SURFACE_BLOCK_SIZE,
+	     aux_addr += AUX_CCS_BLOCK_SIZE) {
+		uint64_t table = top_table;
+		int level;
+
+		for (level = pgt->levels - 1; level >= 1; level--)
+			table = pgt_get_table(pgt, table, level,
+					      surface_addr, lx_flags);
+
+		pgt_set_l1_entry(pgt, table, surface_addr, aux_addr, l1_flags);
+	}
+}
+
+static void pgt_populate_entries(struct pgtable *pgt,
+				 const struct igt_buf **bufs,
+				 int buf_count,
+				 drm_intel_bo *pgt_bo)
+{
+	uint64_t top_table;
+	int i;
+
+	pgt->bo = pgt_bo;
+
+	igt_assert(pgt_bo->size >= pgt->size);
+	memset(pgt_bo->virtual, 0, pgt->size);
+
+	top_table = pgt_alloc_table(pgt, pgt->levels - 1);
+	/* Top level table must be at offset 0. */
+	igt_assert(top_table == 0);
+
+	for (i = 0; i < buf_count; i++)
+		pgt_populate_entries_for_buf(pgt, bufs[i], top_table);
+}
+
+static struct pgtable *
+pgt_create(const struct pgtable_level_desc *level_descs, int levels,
+	   const struct igt_buf **bufs, int buf_count)
+{
+	struct pgtable *pgt;
+	int level;
+
+	pgt = calloc(1, sizeof(*pgt));
+	igt_assert(pgt);
+
+	pgt->levels = levels;
+
+	pgt->level_info = calloc(levels, sizeof(*pgt->level_info));
+	igt_assert(pgt->level_info);
+
+	for (level = 0; level < pgt->levels; level++) {
+		struct pgtable_level_info *li = &pgt->level_info[level];
+
+		li->desc = &level_descs[level];
+		if (li->desc->table_size > pgt->max_align)
+			pgt->max_align = li->desc->table_size;
+	}
+
+	pgt_calc_size(pgt, bufs, buf_count);
+
+	return pgt;
+}
+
+static void pgt_destroy(struct pgtable *pgt)
+{
+	free(pgt->level_info);
+	free(pgt);
+}
+
+drm_intel_bo *
+intel_aux_pgtable_create(drm_intel_bufmgr *bufmgr,
+		       const struct igt_buf **bufs, int buf_count)
+{
+	static const struct pgtable_level_desc level_desc[] = {
+		{
+			.idx_shift = 16,
+			.idx_bits = 8,
+			.entry_ptr_shift = 8,
+			.table_size = 8 * 1024,
+		},
+		{
+			.idx_shift = 24,
+			.idx_bits = 12,
+			.entry_ptr_shift = 13,
+			.table_size = 32 * 1024,
+		},
+		{
+			.idx_shift = 36,
+			.idx_bits = 12,
+			.entry_ptr_shift = 15,
+			.table_size = 32 * 1024,
+		},
+	};
+	struct pgtable *pgt;
+	drm_intel_bo *pgt_bo;
+
+	pgt = pgt_create(level_desc, ARRAY_SIZE(level_desc), bufs, buf_count);
+
+	pgt_bo = drm_intel_bo_alloc_for_render(bufmgr, "aux pgt",
+					       pgt->size, pgt->max_align);
+	igt_assert(pgt_bo);
+
+	igt_assert(drm_intel_bo_map(pgt_bo, true) == 0);
+	pgt_populate_entries(pgt, bufs, buf_count, pgt_bo);
+	igt_assert(drm_intel_bo_unmap(pgt_bo) == 0);
+
+	pgt_destroy(pgt);
+
+	return pgt_bo;
+}
diff --git a/lib/intel_aux_pgtable.h b/lib/intel_aux_pgtable.h
new file mode 100644
index 00000000..c0f001b4
--- /dev/null
+++ b/lib/intel_aux_pgtable.h
@@ -0,0 +1,12 @@
+#ifndef __INTEL_AUX_PGTABLE_H__
+#define __INTEL_AUX_PGTABLE_H__
+
+#include "intel_bufmgr.h"
+
+struct igt_buf;
+
+drm_intel_bo *
+intel_aux_pgtable_create(drm_intel_bufmgr *bufmgr,
+			 const struct igt_buf **bufs, int buf_count);
+
+#endif
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index 069440cb..84f746a6 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -673,6 +673,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define RING_VALID          0x00000001
 #define RING_INVALID        0x00000000
 
+#define GEN12_GFX_AUX_TABLE_BASE_ADDR	0x4200
 
 
 /* BitBlt Instructions
@@ -2570,6 +2571,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 #define MI_LOAD_SCAN_LINES_INCL		(0x12<<23)
 #define MI_LOAD_REGISTER_IMM		((0x22 << 23) | 1)
+#define MI_LOAD_REGISTER_MEM_GEN8	((0x29 << 23) | (4 - 2))
 
 /* Flush */
 #define MI_FLUSH			(0x04<<23)
diff --git a/lib/meson.build b/lib/meson.build
index 221ae28c..33fef486 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -44,6 +44,7 @@ lib_sources = [
 	'rendercopy_gen8.c',
 	'rendercopy_gen9.c',
 	'sw_sync.c',
+	'intel_aux_pgtable.c',
 	'intel_reg_map.c',
 	'intel_iosf.c',
 	'igt_kms.c',
diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index 694eb3cf..e3f2af25 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -15,6 +15,7 @@
 #include <i915_drm.h>
 
 #include "drmtest.h"
+#include "intel_aux_pgtable.h"
 #include "intel_bufmgr.h"
 #include "intel_batchbuffer.h"
 #include "intel_io.h"
@@ -972,19 +973,226 @@ static void gen8_emit_primitive(struct intel_batchbuffer *batch, uint32_t offset
 
 #define BATCH_STATE_SPLIT 2048
 
+static void
+aux_pgtable_find_max_free_range(const struct igt_buf **bufs, int buf_count,
+				uint64_t *range_start, uint64_t *range_size)
+{
+	/*
+	 * Keep the first page reserved, so we can differentiate pinned
+	 * objects based on a non-NULL offset.
+	 */
+	uint64_t start = 0x1000;
+	/* For now alloc only from the first 4GB address space. */
+	const uint64_t end = 1ULL << 32;
+	uint64_t max_range_start = 0;
+	uint64_t max_range_size = 0;
+	int i;
+
+	for (i = 0; i < buf_count; i++) {
+		if (bufs[i]->bo->offset64 >= end)
+			break;
+
+		if (bufs[i]->bo->offset64 - start > max_range_size) {
+			max_range_start = start;
+			max_range_size = bufs[i]->bo->offset64 - start;
+		}
+		start = bufs[i]->bo->offset64 + bufs[i]->bo->size;
+	}
+
+	if (start < end && end - start > max_range_size) {
+		max_range_start = start;
+		max_range_size = end - start;
+	}
+
+	*range_start = max_range_start;
+	*range_size = max_range_size;
+}
+
+static uint64_t
+aux_pgtable_find_free_range(const struct igt_buf **bufs, int buf_count,
+			    uint32_t size)
+{
+	uint64_t range_start;
+	uint64_t range_size;
+	/* A compressed surface must be 64kB aligned. */
+	const uint32_t align = 0x10000;
+	int pad;
+
+	aux_pgtable_find_max_free_range(bufs, buf_count,
+					&range_start, &range_size);
+
+	pad = ALIGN(range_start, align) - range_start;
+	range_start += pad;
+	range_size -= pad;
+	igt_assert(range_size >= size);
+
+	return range_start + ALIGN_DOWN(rand() % (range_size - size), align);
+}
+
+static void
+aux_pgtable_reserve_range(const struct igt_buf **bufs, int buf_count,
+			  const struct igt_buf *new_buf)
+{
+	int i;
+
+	if (new_buf->aux.stride) {
+		uint64_t pin_offset = new_buf->bo->offset64;
+
+		if (!pin_offset)
+			pin_offset = aux_pgtable_find_free_range(bufs,
+								 buf_count,
+								 new_buf->bo->size);
+		drm_intel_bo_set_softpin_offset(new_buf->bo, pin_offset);
+		igt_assert(new_buf->bo->offset64 == pin_offset);
+	}
+
+	for (i = 0; i < buf_count; i++)
+		if (bufs[i]->bo->offset64 > new_buf->bo->offset64)
+			break;
+
+	memmove(&bufs[i + 1], &bufs[i], sizeof(bufs[0]) * (buf_count - i));
+
+	bufs[i] = new_buf;
+}
+
+struct aux_pgtable_info {
+	int buf_count;
+	const struct igt_buf *bufs[2];
+	uint64_t buf_pin_offsets[2];
+	drm_intel_bo *pgtable_bo;
+};
+
+static void
+gen12_aux_pgtable_init(struct aux_pgtable_info *info,
+		       drm_intel_bufmgr *bufmgr,
+		       const struct igt_buf *src_buf,
+		       const struct igt_buf *dst_buf)
+{
+	const struct igt_buf *bufs[2];
+	const struct igt_buf *reserved_bufs[2];
+	int reserved_buf_count;
+	int i;
+
+	if (!src_buf->aux.stride && !dst_buf->aux.stride)
+		return;
+
+	bufs[0] = src_buf;
+	bufs[1] = dst_buf;
+
+	/*
+	 * Ideally we'd need an IGT-wide GFX address space allocator, which
+	 * would consider all allocations and thus avoid evictions. For now use
+	 * a simpler scheme here, which only considers the buffers involved in
+	 * the blit, which should at least minimize the chance for evictions
+	 * in the case of subsequent blits:
+	 *   1. If they were already bound (bo->offset64 != 0), use this
+	 *      address.
+	 *   2. Pick a range randomly from the 4GB address space, that is not
+	 *      already occupied by a bound object, or an object we pinned.
+	 */
+	reserved_buf_count = 0;
+	/* First reserve space for any bufs that are bound already. */
+	for (i = 0; i < ARRAY_SIZE(bufs); i++)
+		if (bufs[i]->bo->offset64)
+			aux_pgtable_reserve_range(reserved_bufs,
+						  reserved_buf_count++,
+						  bufs[i]);
+
+	/* Next, reserve space for unbound bufs with an AUX surface. */
+	for (i = 0; i < ARRAY_SIZE(bufs); i++)
+		if (!bufs[i]->bo->offset64 && bufs[i]->aux.stride)
+			aux_pgtable_reserve_range(reserved_bufs,
+						  reserved_buf_count++,
+						  bufs[i]);
+
+	/* Create AUX pgtable entries only for bufs with an AUX surface */
+	info->buf_count = 0;
+	for (i = 0; i < reserved_buf_count; i++) {
+		if (!reserved_bufs[i]->aux.stride)
+			continue;
+
+		info->bufs[info->buf_count] = reserved_bufs[i];
+		info->buf_pin_offsets[info->buf_count] =
+			reserved_bufs[i]->bo->offset64;
+		info->buf_count++;
+	}
+
+	info->pgtable_bo = intel_aux_pgtable_create(bufmgr,
+						    info->bufs,
+						    info->buf_count);
+	igt_assert(info->pgtable_bo);
+}
+
+static void
+gen12_aux_pgtable_cleanup(struct aux_pgtable_info *info)
+{
+	int i;
+
+	/* Check that the pinned bufs kept their offset after the exec. */
+	for (i = 0; i < info->buf_count; i++)
+		igt_assert_eq_u64(info->bufs[i]->bo->offset64,
+				  info->buf_pin_offsets[i]);
+
+	drm_intel_bo_unreference(info->pgtable_bo);
+}
+
+static uint32_t
+gen12_create_aux_pgtable_state(struct intel_batchbuffer *batch,
+			       drm_intel_bo *aux_pgtable_bo)
+{
+	uint64_t *pgtable_ptr;
+	uint32_t pgtable_ptr_offset;
+	int ret;
+
+	if (!aux_pgtable_bo)
+		return 0;
+
+	pgtable_ptr = intel_batchbuffer_subdata_alloc(batch,
+						      sizeof(*pgtable_ptr),
+						      sizeof(*pgtable_ptr));
+	pgtable_ptr_offset = intel_batchbuffer_subdata_offset(batch,
+							      pgtable_ptr);
+
+	*pgtable_ptr = aux_pgtable_bo->offset64;
+	ret = drm_intel_bo_emit_reloc(batch->bo, pgtable_ptr_offset,
+				      aux_pgtable_bo, 0,
+				      0, 0);
+	assert(ret == 0);
+
+	return pgtable_ptr_offset;
+}
+
+static void
+gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch, uint32_t state)
+{
+	if (!state)
+		return;
+
+	OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8);
+	OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR);
+	OUT_RELOC(batch->bo, 0, 0, state);
+
+	OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8);
+	OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR + 4);
+	OUT_RELOC(batch->bo, 0, 0, state + 4);
+}
+
 static
 void _gen9_render_copyfunc(struct intel_batchbuffer *batch,
 			  drm_intel_context *context,
 			  const struct igt_buf *src, unsigned src_x,
 			  unsigned src_y, unsigned width, unsigned height,
 			  const struct igt_buf *dst, unsigned dst_x,
-			  unsigned dst_y, const uint32_t ps_kernel[][4],
+			  unsigned dst_y,
+			  drm_intel_bo *aux_pgtable_bo,
+			  const uint32_t ps_kernel[][4],
 			  uint32_t ps_kernel_size)
 {
 	uint32_t ps_sampler_state, ps_kernel_off, ps_binding_table;
 	uint32_t scissor_state;
 	uint32_t vertex_buffer;
 	uint32_t batch_end;
+	uint32_t aux_pgtable_state;
 
 	igt_assert(src->bpp == dst->bpp);
 	intel_batchbuffer_flush_with_context(batch, context);
@@ -1007,6 +1215,10 @@ void _gen9_render_copyfunc(struct intel_batchbuffer *batch,
 	viewport.cc_state = gen6_create_cc_viewport(batch);
 	viewport.sf_clip_state = gen7_create_sf_clip_viewport(batch);
 	scissor_state = gen6_create_scissor_rect(batch);
+
+	aux_pgtable_state = gen12_create_aux_pgtable_state(batch,
+							   aux_pgtable_bo);
+
 	/* TODO: theree is other state which isn't setup */
 
 	assert(batch->ptr < &batch->buffer[4095]);
@@ -1018,6 +1230,8 @@ void _gen9_render_copyfunc(struct intel_batchbuffer *batch,
 	OUT_BATCH(G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D |
 				GEN9_PIPELINE_SELECTION_MASK);
 
+	gen12_emit_aux_pgtable_state(batch, aux_pgtable_state);
+
 	gen8_emit_sip(batch);
 
 	gen7_emit_push_constants(batch);
@@ -1092,8 +1306,8 @@ void gen9_render_copyfunc(struct intel_batchbuffer *batch,
 
 {
 	_gen9_render_copyfunc(batch, context, src, src_x, src_y,
-			  width, height, dst, dst_x, dst_y, ps_kernel_gen9,
-			  sizeof(ps_kernel_gen9));
+			  width, height, dst, dst_x, dst_y, NULL,
+			  ps_kernel_gen9, sizeof(ps_kernel_gen9));
 }
 
 void gen11_render_copyfunc(struct intel_batchbuffer *batch,
@@ -1104,8 +1318,8 @@ void gen11_render_copyfunc(struct intel_batchbuffer *batch,
 
 {
 	_gen9_render_copyfunc(batch, context, src, src_x, src_y,
-			  width, height, dst, dst_x, dst_y, ps_kernel_gen11,
-			  sizeof(ps_kernel_gen11));
+			  width, height, dst, dst_x, dst_y, NULL,
+			  ps_kernel_gen11, sizeof(ps_kernel_gen11));
 }
 
 void gen12_render_copyfunc(struct intel_batchbuffer *batch,
@@ -1115,7 +1329,15 @@ void gen12_render_copyfunc(struct intel_batchbuffer *batch,
 			   const struct igt_buf *dst, unsigned dst_x, unsigned dst_y)
 
 {
+	struct aux_pgtable_info pgtable_info = { };
+
+	gen12_aux_pgtable_init(&pgtable_info, batch->bufmgr, src, dst);
+
 	_gen9_render_copyfunc(batch, context, src, src_x, src_y,
-			  width, height, dst, dst_x, dst_y, gen12_render_copy,
+			  width, height, dst, dst_x, dst_y,
+			  pgtable_info.pgtable_bo,
+			  gen12_render_copy,
 			  sizeof(gen12_render_copy));
+
+	gen12_aux_pgtable_cleanup(&pgtable_info);
 }
diff --git a/lib/stubs/drm/intel_bufmgr.c b/lib/stubs/drm/intel_bufmgr.c
index f87452ac..cbab2484 100644
--- a/lib/stubs/drm/intel_bufmgr.c
+++ b/lib/stubs/drm/intel_bufmgr.c
@@ -233,6 +233,12 @@ int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
 	return -ENODEV;
 }
 
+int drm_intel_bo_set_softpin_offset(drm_intel_bo *bo, uint64_t offset)
+{
+	igt_require_f(false, missing_support_str);
+	return -ENODEV;
+}
+
 int drm_intel_bo_disable_reuse(drm_intel_bo *bo)
 {
 	igt_require_f(false, missing_support_str);
-- 
2.17.1

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[igt-dev] ✗ GitLab.Pipeline: failure for series starting with [v4,1/3] lib/rendercopy: Add AUX page table support (rev3)

[Patchwork]

== Series Details ==

Series: series starting with [v4,1/3] lib/rendercopy: Add AUX page table support (rev3)
URL   : https://patchwork.freedesktop.org/series/69012/
State : failure

== Summary ==

ERROR! This series introduces new undocumented tests:

gem_render_copy@y-tiled-ccs-to-y-tiled-ccs
gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs
gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs
gem_render_copy@yf-tiled-ccs-to-yf-tiled-ccs

Can you document them as per the requirement in the [CONTRIBUTING.md]?

[Documentation] has more details on how to do this.

Here are few examples:
https://gitlab.freedesktop.org/drm/igt-gpu-tools/commit/0316695d03aa46108296b27f3982ec93200c7a6e
https://gitlab.freedesktop.org/drm/igt-gpu-tools/commit/443cc658e1e6b492ee17bf4f4d891029eb7a205d

Thanks in advance!

[CONTRIBUTING.md]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/blob/master/CONTRIBUTING.md#L19
[Documentation]: https://drm.pages.freedesktop.org/igt-gpu-tools/igt-gpu-tools-Core.html#igt-describe

Other than that, pipeline status: SUCCESS.

see https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/pipelines/76630 for more details

== Logs ==

For more details see: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/pipelines/76630
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[igt-dev] ✓ Fi.CI.BAT: success for series starting with [v4,1/3] lib/rendercopy: Add AUX page table support (rev3)

[Patchwork]

== Series Details ==

Series: series starting with [v4,1/3] lib/rendercopy: Add AUX page table support (rev3)
URL   : https://patchwork.freedesktop.org/series/69012/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7264 -> IGTPW_3659
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/index.html

Known issues
------------

  Here are the changes found in IGTPW_3659 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_mmap_gtt@basic-short:
    - fi-icl-u3:          [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +2 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/fi-icl-u3/igt@gem_mmap_gtt@basic-short.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/fi-icl-u3/igt@gem_mmap_gtt@basic-short.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-hsw-peppy:       [PASS][3] -> [DMESG-WARN][4] ([fdo#102614])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html

  
#### Possible fixes ####

  * igt@gem_mmap_gtt@basic-write-cpu-read-gtt:
    - fi-icl-u3:          [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/fi-icl-u3/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/fi-icl-u3/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html

  * igt@i915_module_load@reload:
    - {fi-icl-dsi}:       [INCOMPLETE][7] ([fdo#107713]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/fi-icl-dsi/igt@i915_module_load@reload.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/fi-icl-dsi/igt@i915_module_load@reload.html

  * igt@kms_chamelium@hdmi-edid-read:
    - {fi-icl-u4}:        [FAIL][9] ([fdo#111045]) -> [PASS][10] +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/fi-icl-u4/igt@kms_chamelium@hdmi-edid-read.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/fi-icl-u4/igt@kms_chamelium@hdmi-edid-read.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
  [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111049]: https://bugs.freedesktop.org/show_bug.cgi?id=111049
  [fdo#112120]: https://bugs.freedesktop.org/show_bug.cgi?id=112120


Participating hosts (51 -> 42)
------------------------------

  Missing    (9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-bwr-2160 fi-ctg-p8600 fi-gdg-551 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5263 -> IGTPW_3659

  CI-20190529: 20190529
  CI_DRM_7264: f5cfd96ad87b58bf3b5dfa5365f8beb8bac15a38 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_3659: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/index.html
  IGT_5263: 8a5d44dc5e51622cd43f23c2cf24d44c24a0564d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools



== Testlist changes ==

+igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled-ccs
+igt@gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs
+igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs
+igt@gem_render_copy@y-tiled-ccs-to-y-tiled-ccs

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/index.html
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Re: [igt-dev] [PATCH v3 1/3] lib/rendercopy: Add AUX page table support

[Chris Wilson]

Quoting Imre Deak (2019-11-05 21:42:20)
> On GEN12+ the AUX CCS surfaces required by the render and media
> compression must be specified by a 3 level page table directory, which
> translates the main surface graphics address to the AUX CCS surface
> graphics address. For this purpose add support for creating a GEM buffer
> to translate the linear surface address range to the linear AUX surface
> address range.
> 
> The buffers containing the main surface must be pinned down, since the
> directory table entry indices depend on the surface address, and they
> must be 64kB aligned. The page table can be relocated OTOH, so allow
> that and emit the required relocation entries.
> 
> v2:
> - Make level variables to be 0 based (l1..l3 -> level=0..2).
> - Add missing drm_intel_bo_set_softpin_offset() stub to fix build on
>   non-Intel archs.
> - Fix missing offsets in reloc entries of already bound objects. (Chris)
> - Randomize pin offsets, to try to avoid eviction. (Chris)
> - Remove redundant MI_NOOPS around MI_LOAD_REGISTER_MEM
> - Stop using explicit reloc cache domains, as these don't make sense on
>   GEN12 anyway. (Chris)
> - Fix missing autotools support. (Chris)
> - s/igt_aux_pgtable/intel_aux_pgtable/, since the functionality is Intel
>   specific. (Chris)
> v3:
> - Make sure all objects with an AUX surface are pinned.
> 
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Brian Welty <brian.welty@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  lib/Makefile.sources         |   1 +
>  lib/intel_aux_pgtable.c      | 379 +++++++++++++++++++++++++++++++++++
>  lib/intel_aux_pgtable.h      |  12 ++
>  lib/intel_reg.h              |   2 +
>  lib/meson.build              |   1 +
>  lib/rendercopy_gen9.c        | 234 ++++++++++++++++++++-
>  lib/stubs/drm/intel_bufmgr.c |   6 +
>  7 files changed, 629 insertions(+), 6 deletions(-)
>  create mode 100644 lib/intel_aux_pgtable.c
>  create mode 100644 lib/intel_aux_pgtable.h
> 
> diff --git a/lib/Makefile.sources b/lib/Makefile.sources
> index cf094ab8..1d0f45f7 100644
> --- a/lib/Makefile.sources
> +++ b/lib/Makefile.sources
> @@ -100,6 +100,7 @@ lib_source_list =           \
>         surfaceformat.h         \
>         sw_sync.c               \
>         sw_sync.h               \
> +       intel_aux_pgtable.c     \
>         intel_reg_map.c         \
>         intel_iosf.c            \
>         igt_kms.c               \
> diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c
> new file mode 100644
> index 00000000..79402813
> --- /dev/null
> +++ b/lib/intel_aux_pgtable.c
> @@ -0,0 +1,379 @@
> +#include <stdint.h>
> +#include <stdbool.h>
> +
> +#include "drmtest.h"
> +#include "intel_aux_pgtable.h"
> +#include "intel_bufmgr.h"
> +#include "intel_batchbuffer.h"
> +#include "ioctl_wrappers.h"
> +
> +#include "i915/gem_mman.h"
> +
> +#define BITS_PER_LONG          (sizeof(long) * 8)
> +#define BITMASK(e, s)          ((~0UL << (s)) & \
> +                                (~0UL >> (BITS_PER_LONG - 1 - (e))))
> +
> +#define ALIGN_DOWN(x, a)       ALIGN((x) - ((a) - 1), (a))
> +
> +/* The unit size to which the AUX CCS surface is aligned to. */
> +#define AUX_CCS_UNIT_SIZE      64
> +/*
> + * The block size on the AUX CCS surface which is mapped by one L1 AUX
> + * pagetable entry.
> + */
> +#define AUX_CCS_BLOCK_SIZE     (4 * AUX_CCS_UNIT_SIZE)
> +/*
> + * The block size on the main surface mapped by one AUX CCS block:
> + *   256 bytes per CCS block *
> + *   8   bits per byte /
> + *   2   bits per main surface CL *
> + *   64  bytes per main surface CL
> + */
> +#define MAIN_SURFACE_BLOCK_SIZE        (AUX_CCS_BLOCK_SIZE * 8 / 2 * 64)
> +
> +#define GFX_ADDRESS_BITS       48
> +
> +#define max(a, b)              ((a) > (b) ? (a) : (b))
> +
> +struct pgtable_level_desc {
> +       int idx_shift;
> +       int idx_bits;
> +       int entry_ptr_shift;
> +       int table_size;
> +};
> +
> +struct pgtable_level_info {
> +       const struct pgtable_level_desc *desc;
> +       int table_count;
> +       int alloc_base;
> +       int alloc_ptr;
> +};
> +
> +struct pgtable {
> +       int levels;
> +       struct pgtable_level_info *level_info;
> +       int size;
> +       int max_align;
> +       drm_intel_bo *bo;
> +};
> +
> +static int
> +pgt_table_count(int address_bits, const struct igt_buf **bufs, int buf_count)
> +{
> +       uint64_t end;
> +       int count;
> +       int i;
> +
> +       count = 0;
> +       end = 0;
> +       for (i = 0; i < buf_count; i++) {
> +               const struct igt_buf *buf = bufs[i];
> +               uint64_t start;
> +
> +               /* We require bufs to be sorted. */
> +               igt_assert(i == 0 ||
> +                          buf->bo->offset64 >= bufs[i - 1]->bo->offset64 +
> +                                               bufs[i - 1]->bo->size);
> +
> +               start = ALIGN_DOWN(buf->bo->offset64, 1UL << address_bits);
> +               /* Avoid double counting for overlapping aligned bufs. */
> +               start = max(start, end);
> +
> +               end = ALIGN(buf->bo->offset64 + buf->size, 1UL << address_bits);
> +               igt_assert(end >= start);
> +
> +               count += (end - start) >> address_bits;
> +       }
> +
> +       return count;
> +}
> +
> +static void
> +pgt_calc_size(struct pgtable *pgt, const struct igt_buf **bufs, int buf_count)
> +{
> +       int level;
> +
> +       pgt->size = 0;
> +
> +       for (level = pgt->levels - 1; level >= 0; level--) {
> +               struct pgtable_level_info *li = &pgt->level_info[level];
> +
> +               li->alloc_base = ALIGN(pgt->size, li->desc->table_size);
> +               li->alloc_ptr = li->alloc_base;
> +
> +               li->table_count = pgt_table_count(li->desc->idx_shift +
> +                                                 li->desc->idx_bits,
> +                                                 bufs, buf_count);
> +
> +               pgt->size = li->alloc_base +
> +                           li->table_count * li->desc->table_size;
> +       }
> +}
> +
> +static uint64_t pgt_alloc_table(struct pgtable *pgt, int level)
> +{
> +       struct pgtable_level_info *li = &pgt->level_info[level];
> +       uint64_t table;
> +
> +       table = li->alloc_ptr;
> +       li->alloc_ptr += li->desc->table_size;
> +
> +       igt_assert(li->alloc_ptr <=
> +                  li->alloc_base + li->table_count * li->desc->table_size);
> +
> +       return table;
> +}
> +
> +static int pgt_address_index(struct pgtable *pgt, int level, uint64_t address)
> +{
> +       const struct pgtable_level_desc *ld = pgt->level_info[level].desc;
> +       uint64_t mask = BITMASK(ld->idx_shift + ld->idx_bits - 1,
> +                               ld->idx_shift);
> +
> +       return (address & mask) >> ld->idx_shift;
> +}
> +
> +static uint64_t ptr_mask(struct pgtable *pgt, int level)
> +{
> +       const struct pgtable_level_desc *ld = pgt->level_info[level].desc;
> +
> +       return BITMASK(GFX_ADDRESS_BITS - 1, ld->entry_ptr_shift);
> +}
> +
> +static uint64_t pgt_entry_ptr(struct pgtable *pgt, int level, uint64_t entry)
> +{
> +       uint64_t ptr = entry & ptr_mask(pgt, level);
> +
> +       if (level)
> +               ptr -= pgt->bo->offset64;
> +       igt_assert(!(ptr & ~ptr_mask(pgt, level)));
> +
> +       return ptr;
> +}
> +
> +static uint64_t pgt_mkentry(struct pgtable *pgt, int level, uint64_t ptr,
> +                           uint64_t flags)
> +{
> +       if (level)
> +               ptr += pgt->bo->offset64;
> +       igt_assert(!(ptr & ~ptr_mask(pgt, level)));
> +
> +       return ptr | flags;
> +}
> +
> +static uint64_t
> +pgt_get_table(struct pgtable *pgt, uint64_t parent_table,
> +             int level, uint64_t address, uint64_t flags)
> +{
> +       uint64_t *table_ptr = pgt->bo->virtual + parent_table;
> +       int entry_idx = pgt_address_index(pgt, level, address);
> +       uint64_t *entry_ptr;
> +
> +       entry_ptr = &table_ptr[entry_idx];
> +       if (!*entry_ptr) {
> +               uint64_t child_table = pgt_alloc_table(pgt, level - 1);
> +
> +               *entry_ptr = pgt_mkentry(pgt, level, child_table, flags);

The value in the batch is the absolute address, good.

> +
> +               drm_intel_bo_emit_reloc(pgt->bo,
> +                                       parent_table + entry_idx * sizeof(uint64_t),
> +                                       pgt->bo, *entry_ptr, 0, 0);

But you then pass the absolute address as the relocation delta. Not so
good.

> +       }
> +
> +       return pgt_entry_ptr(pgt, level, *entry_ptr);

You only use pgt_entry_ptr, here so just keep the batch entry separate
from the relative offset.

uint64_t pte = pgt_mkentry(pgt, level, child_table, flags);

Hmm, note this interface is limited to s32.
igt_assert(pte < S32_MAX);

*entry_ptr = bo->offset64 + pte;
drm_intel_bo_emit_reloc(pgt->bo,
	parent_table + entry_idx * sizeof(uint64_t),
	pgt->bo, offset, 0, 0);


return offset & ptr_mask(pgt, level);

What's the coherency model for the pgt->bo? There's a lot of writes here
from the CPU how are you making sure they are visible to the GPU?
-Chris
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Re: [igt-dev] [PATCH v3 1/3] lib/rendercopy: Add AUX page table support

[Imre Deak]

On Wed, Nov 06, 2019 at 11:11:40AM +0000, Chris Wilson wrote:
> Quoting Imre Deak (2019-11-05 21:42:20)
> > On GEN12+ the AUX CCS surfaces required by the render and media
> > compression must be specified by a 3 level page table directory, which
> > translates the main surface graphics address to the AUX CCS surface
> > graphics address. For this purpose add support for creating a GEM buffer
> > to translate the linear surface address range to the linear AUX surface
> > address range.
> > 
> > The buffers containing the main surface must be pinned down, since the
> > directory table entry indices depend on the surface address, and they
> > must be 64kB aligned. The page table can be relocated OTOH, so allow
> > that and emit the required relocation entries.
> > 
> > v2:
> > - Make level variables to be 0 based (l1..l3 -> level=0..2).
> > - Add missing drm_intel_bo_set_softpin_offset() stub to fix build on
> >   non-Intel archs.
> > - Fix missing offsets in reloc entries of already bound objects. (Chris)
> > - Randomize pin offsets, to try to avoid eviction. (Chris)
> > - Remove redundant MI_NOOPS around MI_LOAD_REGISTER_MEM
> > - Stop using explicit reloc cache domains, as these don't make sense on
> >   GEN12 anyway. (Chris)
> > - Fix missing autotools support. (Chris)
> > - s/igt_aux_pgtable/intel_aux_pgtable/, since the functionality is Intel
> >   specific. (Chris)
> > v3:
> > - Make sure all objects with an AUX surface are pinned.
> > 
> > Cc: Mika Kahola <mika.kahola@intel.com>
> > Cc: Brian Welty <brian.welty@intel.com>
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  lib/Makefile.sources         |   1 +
> >  lib/intel_aux_pgtable.c      | 379 +++++++++++++++++++++++++++++++++++
> >  lib/intel_aux_pgtable.h      |  12 ++
> >  lib/intel_reg.h              |   2 +
> >  lib/meson.build              |   1 +
> >  lib/rendercopy_gen9.c        | 234 ++++++++++++++++++++-
> >  lib/stubs/drm/intel_bufmgr.c |   6 +
> >  7 files changed, 629 insertions(+), 6 deletions(-)
> >  create mode 100644 lib/intel_aux_pgtable.c
> >  create mode 100644 lib/intel_aux_pgtable.h
> > 
> > diff --git a/lib/Makefile.sources b/lib/Makefile.sources
> > index cf094ab8..1d0f45f7 100644
> > --- a/lib/Makefile.sources
> > +++ b/lib/Makefile.sources
> > @@ -100,6 +100,7 @@ lib_source_list =           \
> >         surfaceformat.h         \
> >         sw_sync.c               \
> >         sw_sync.h               \
> > +       intel_aux_pgtable.c     \
> >         intel_reg_map.c         \
> >         intel_iosf.c            \
> >         igt_kms.c               \
> > diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c
> > new file mode 100644
> > index 00000000..79402813
> > --- /dev/null
> > +++ b/lib/intel_aux_pgtable.c
> > @@ -0,0 +1,379 @@
> > +#include <stdint.h>
> > +#include <stdbool.h>
> > +
> > +#include "drmtest.h"
> > +#include "intel_aux_pgtable.h"
> > +#include "intel_bufmgr.h"
> > +#include "intel_batchbuffer.h"
> > +#include "ioctl_wrappers.h"
> > +
> > +#include "i915/gem_mman.h"
> > +
> > +#define BITS_PER_LONG          (sizeof(long) * 8)
> > +#define BITMASK(e, s)          ((~0UL << (s)) & \
> > +                                (~0UL >> (BITS_PER_LONG - 1 - (e))))
> > +
> > +#define ALIGN_DOWN(x, a)       ALIGN((x) - ((a) - 1), (a))
> > +
> > +/* The unit size to which the AUX CCS surface is aligned to. */
> > +#define AUX_CCS_UNIT_SIZE      64
> > +/*
> > + * The block size on the AUX CCS surface which is mapped by one L1 AUX
> > + * pagetable entry.
> > + */
> > +#define AUX_CCS_BLOCK_SIZE     (4 * AUX_CCS_UNIT_SIZE)
> > +/*
> > + * The block size on the main surface mapped by one AUX CCS block:
> > + *   256 bytes per CCS block *
> > + *   8   bits per byte /
> > + *   2   bits per main surface CL *
> > + *   64  bytes per main surface CL
> > + */
> > +#define MAIN_SURFACE_BLOCK_SIZE        (AUX_CCS_BLOCK_SIZE * 8 / 2 * 64)
> > +
> > +#define GFX_ADDRESS_BITS       48
> > +
> > +#define max(a, b)              ((a) > (b) ? (a) : (b))
> > +
> > +struct pgtable_level_desc {
> > +       int idx_shift;
> > +       int idx_bits;
> > +       int entry_ptr_shift;
> > +       int table_size;
> > +};
> > +
> > +struct pgtable_level_info {
> > +       const struct pgtable_level_desc *desc;
> > +       int table_count;
> > +       int alloc_base;
> > +       int alloc_ptr;
> > +};
> > +
> > +struct pgtable {
> > +       int levels;
> > +       struct pgtable_level_info *level_info;
> > +       int size;
> > +       int max_align;
> > +       drm_intel_bo *bo;
> > +};
> > +
> > +static int
> > +pgt_table_count(int address_bits, const struct igt_buf **bufs, int buf_count)
> > +{
> > +       uint64_t end;
> > +       int count;
> > +       int i;
> > +
> > +       count = 0;
> > +       end = 0;
> > +       for (i = 0; i < buf_count; i++) {
> > +               const struct igt_buf *buf = bufs[i];
> > +               uint64_t start;
> > +
> > +               /* We require bufs to be sorted. */
> > +               igt_assert(i == 0 ||
> > +                          buf->bo->offset64 >= bufs[i - 1]->bo->offset64 +
> > +                                               bufs[i - 1]->bo->size);
> > +
> > +               start = ALIGN_DOWN(buf->bo->offset64, 1UL << address_bits);
> > +               /* Avoid double counting for overlapping aligned bufs. */
> > +               start = max(start, end);
> > +
> > +               end = ALIGN(buf->bo->offset64 + buf->size, 1UL << address_bits);
> > +               igt_assert(end >= start);
> > +
> > +               count += (end - start) >> address_bits;
> > +       }
> > +
> > +       return count;
> > +}
> > +
> > +static void
> > +pgt_calc_size(struct pgtable *pgt, const struct igt_buf **bufs, int buf_count)
> > +{
> > +       int level;
> > +
> > +       pgt->size = 0;
> > +
> > +       for (level = pgt->levels - 1; level >= 0; level--) {
> > +               struct pgtable_level_info *li = &pgt->level_info[level];
> > +
> > +               li->alloc_base = ALIGN(pgt->size, li->desc->table_size);
> > +               li->alloc_ptr = li->alloc_base;
> > +
> > +               li->table_count = pgt_table_count(li->desc->idx_shift +
> > +                                                 li->desc->idx_bits,
> > +                                                 bufs, buf_count);
> > +
> > +               pgt->size = li->alloc_base +
> > +                           li->table_count * li->desc->table_size;
> > +       }
> > +}
> > +
> > +static uint64_t pgt_alloc_table(struct pgtable *pgt, int level)
> > +{
> > +       struct pgtable_level_info *li = &pgt->level_info[level];
> > +       uint64_t table;
> > +
> > +       table = li->alloc_ptr;
> > +       li->alloc_ptr += li->desc->table_size;
> > +
> > +       igt_assert(li->alloc_ptr <=
> > +                  li->alloc_base + li->table_count * li->desc->table_size);
> > +
> > +       return table;
> > +}
> > +
> > +static int pgt_address_index(struct pgtable *pgt, int level, uint64_t address)
> > +{
> > +       const struct pgtable_level_desc *ld = pgt->level_info[level].desc;
> > +       uint64_t mask = BITMASK(ld->idx_shift + ld->idx_bits - 1,
> > +                               ld->idx_shift);
> > +
> > +       return (address & mask) >> ld->idx_shift;
> > +}
> > +
> > +static uint64_t ptr_mask(struct pgtable *pgt, int level)
> > +{
> > +       const struct pgtable_level_desc *ld = pgt->level_info[level].desc;
> > +
> > +       return BITMASK(GFX_ADDRESS_BITS - 1, ld->entry_ptr_shift);
> > +}
> > +
> > +static uint64_t pgt_entry_ptr(struct pgtable *pgt, int level, uint64_t entry)
> > +{
> > +       uint64_t ptr = entry & ptr_mask(pgt, level);
> > +
> > +       if (level)
> > +               ptr -= pgt->bo->offset64;
> > +       igt_assert(!(ptr & ~ptr_mask(pgt, level)));
> > +
> > +       return ptr;
> > +}
> > +
> > +static uint64_t pgt_mkentry(struct pgtable *pgt, int level, uint64_t ptr,
> > +                           uint64_t flags)
> > +{
> > +       if (level)
> > +               ptr += pgt->bo->offset64;
> > +       igt_assert(!(ptr & ~ptr_mask(pgt, level)));
> > +
> > +       return ptr | flags;
> > +}
> > +
> > +static uint64_t
> > +pgt_get_table(struct pgtable *pgt, uint64_t parent_table,
> > +             int level, uint64_t address, uint64_t flags)
> > +{
> > +       uint64_t *table_ptr = pgt->bo->virtual + parent_table;
> > +       int entry_idx = pgt_address_index(pgt, level, address);
> > +       uint64_t *entry_ptr;
> > +
> > +       entry_ptr = &table_ptr[entry_idx];
> > +       if (!*entry_ptr) {
> > +               uint64_t child_table = pgt_alloc_table(pgt, level - 1);
> > +
> > +               *entry_ptr = pgt_mkentry(pgt, level, child_table, flags);
> 
> The value in the batch is the absolute address, good.
> 
> > +
> > +               drm_intel_bo_emit_reloc(pgt->bo,
> > +                                       parent_table + entry_idx * sizeof(uint64_t),
> > +                                       pgt->bo, *entry_ptr, 0, 0);
> 
> But you then pass the absolute address as the relocation delta. Not so
> good.

Doh', botched it again. Yes I meant to pass only the delta here (and the
flags), but screwed it up when fixing the previous issue you found.

My attempt to test if relocs work fine, is pinning the pgt->bo to a
non-zero address; but with that I obviously circumwent relocation
itself:/ I suppose I can test it then by pinning another object in place
of pgt->bo (in case it's newly allocated then offset 0) forcing the
relocation for pgt->bo.

> 
> > +       }
> > +
> > +       return pgt_entry_ptr(pgt, level, *entry_ptr);
> 
> You only use pgt_entry_ptr, here so just keep the batch entry separate
> from the relative offset.
> 
> uint64_t pte = pgt_mkentry(pgt, level, child_table, flags);

Ok, will fix it along that line.

> 
> Hmm, note this interface is limited to s32.
> igt_assert(pte < S32_MAX);

Ok, missed that. Except for the L1 PTEs - which would need a 64 bit
delta - the 31 bit delta is enough. I'll add this assert here.

> 
> *entry_ptr = bo->offset64 + pte;
> drm_intel_bo_emit_reloc(pgt->bo,
> 	parent_table + entry_idx * sizeof(uint64_t),
> 	pgt->bo, offset, 0, 0);
> 
> 
> return offset & ptr_mask(pgt, level);
> 
> What's the coherency model for the pgt->bo? There's a lot of writes here
> from the CPU how are you making sure they are visible to the GPU?

My understanding: execbuf will do a clflush for the buf on non-LLC
platforms, while on LLC platforms that's not needed; not sure if there
will be any non-LLC platforms where the AUX pagetable will be needed.

On top of that the AUX GAM has its own caches - found that now in an HSD
doc - which will be invalidated whenever GAM's top level table base
pointer register is set from the context image, which happens whenver
switching to the context.

> -Chris
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Re: [igt-dev] [PATCH v3 1/3] lib/rendercopy: Add AUX page table support

[Chris Wilson]

Quoting Imre Deak (2019-11-06 16:00:16)
> On Wed, Nov 06, 2019 at 11:11:40AM +0000, Chris Wilson wrote:
> > What's the coherency model for the pgt->bo? There's a lot of writes here
> > from the CPU how are you making sure they are visible to the GPU?
> 
> My understanding: execbuf will do a clflush for the buf on non-LLC
> platforms, while on LLC platforms that's not needed; not sure if there
> will be any non-LLC platforms where the AUX pagetable will be needed.

No, we don't unless you tell us you modified it between batches. That
would be the case if you were using drm_intel_bo_map(true) everytime,
but again that will then stall the GPU between every batch -- which we
definitely do not want when testing [as it will hide every bug] :)

> On top of that the AUX GAM has its own caches - found that now in an HSD
> doc - which will be invalidated whenever GAM's top level table base
> pointer register is set from the context image, which happens whenver
> switching to the context.

But not for a lite-restore? So we have a problem when updating existing
entries between batches inside the same context? We put a big hammer at
the front of the request for TLB invalidation. If there's a flush we can
add, we need it there.
-Chris
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Re: [igt-dev] [PATCH v3 1/3] lib/rendercopy: Add AUX page table support

[Imre Deak]

On Wed, Nov 06, 2019 at 04:14:36PM +0000, Chris Wilson wrote:
> Quoting Imre Deak (2019-11-06 16:00:16)
> > On Wed, Nov 06, 2019 at 11:11:40AM +0000, Chris Wilson wrote:
> > > What's the coherency model for the pgt->bo? There's a lot of writes here
> > > from the CPU how are you making sure they are visible to the GPU?
> > 
> > My understanding: execbuf will do a clflush for the buf on non-LLC
> > platforms, while on LLC platforms that's not needed; not sure if there
> > will be any non-LLC platforms where the AUX pagetable will be needed.
> 
> No, we don't unless you tell us you modified it between batches. That
> would be the case if you were using drm_intel_bo_map(true) everytime,
> but again that will then stall the GPU between every batch -- which we
> definitely do not want when testing [as it will hide every bug] :)

Do you see a problem with the way I program it here though? I call
drm_intel_bo_map(true) for the purpose of programming a new table. If
you see a problem with that what do you suggest instead?

> > On top of that the AUX GAM has its own caches - found that now in an HSD
> > doc - which will be invalidated whenever GAM's top level table base
> > pointer register is set from the context image, which happens whenver
> > switching to the context.
> 
> But not for a lite-restore?

We still write the top level table regsiter from the batch, so that
could in itself trigger the invalidation.

> So we have a problem when updating existing entries between batches
> inside the same context? We put a big hammer at the front of the
> request for TLB invalidation. If there's a flush we can add, we need
> it there.

Yes, there is, see the CCS_AUX_INV reg in bspec. But I suspect this
would have the same effect as writing the table ptr register, so not
sure when exactly this would be needed. 

> -Chris
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[igt-dev] ✓ Fi.CI.IGT: success for series starting with [v2,1/3] lib/rendercopy: Add AUX page table support

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/3] lib/rendercopy: Add AUX page table support
URL   : https://patchwork.freedesktop.org/series/69012/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7262_full -> IGTPW_3657_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/index.html

New tests
---------

  New tests have been introduced between CI_DRM_7262_full and IGTPW_3657_full:

### New IGT tests (4) ###

  * igt@gem_render_copy@y-tiled-ccs-to-y-tiled-ccs:
    - Statuses : 5 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.24] s

  * igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs:
    - Statuses : 5 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.23] s

  * igt@gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs:
    - Statuses : 5 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.24] s

  * igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled-ccs:
    - Statuses : 4 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.23] s

  

Known issues
------------

  Here are the changes found in IGTPW_3657_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_switch@rcs0-heavy-queue:
    - shard-glk:          [PASS][1] -> [INCOMPLETE][2] ([fdo#103359] / [k.org#198133])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-glk3/igt@gem_ctx_switch@rcs0-heavy-queue.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-glk1/igt@gem_ctx_switch@rcs0-heavy-queue.html

  * igt@gem_exec_balancer@smoke:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([fdo#110854])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-iclb4/igt@gem_exec_balancer@smoke.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-iclb3/igt@gem_exec_balancer@smoke.html

  * igt@gem_exec_schedule@out-order-bsd2:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#109276]) +18 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-iclb2/igt@gem_exec_schedule@out-order-bsd2.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-iclb3/igt@gem_exec_schedule@out-order-bsd2.html

  * igt@gem_exec_schedule@preempt-other-chain-bsd:
    - shard-iclb:         [PASS][7] -> [SKIP][8] ([fdo#112146]) +3 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-iclb3/igt@gem_exec_schedule@preempt-other-chain-bsd.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-iclb2/igt@gem_exec_schedule@preempt-other-chain-bsd.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-hsw:          [PASS][9] -> [DMESG-WARN][10] ([fdo#111870])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-hsw6/igt@gem_userptr_blits@dmabuf-unsync.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-hsw7/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@gem_userptr_blits@sync-unmap:
    - shard-snb:          [PASS][11] -> [DMESG-WARN][12] ([fdo#111870]) +2 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-snb6/igt@gem_userptr_blits@sync-unmap.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-snb5/igt@gem_userptr_blits@sync-unmap.html

  * igt@i915_selftest@live_hangcheck:
    - shard-snb:          [PASS][13] -> [INCOMPLETE][14] ([fdo#105411])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-snb1/igt@i915_selftest@live_hangcheck.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-snb4/igt@i915_selftest@live_hangcheck.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-apl:          [PASS][15] -> [FAIL][16] ([fdo#105363])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-apl7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-apl7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-blt:
    - shard-iclb:         [PASS][17] -> [FAIL][18] ([fdo#103167]) +3 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-blt.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
    - shard-iclb:         [PASS][19] -> [DMESG-WARN][20] ([fdo#111764])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-iclb2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-iclb2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
    - shard-apl:          [PASS][21] -> [DMESG-WARN][22] ([fdo#108566])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html

  * igt@kms_psr2_su@page_flip:
    - shard-iclb:         [PASS][23] -> [SKIP][24] ([fdo#109642] / [fdo#111068])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-iclb2/igt@kms_psr2_su@page_flip.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-iclb3/igt@kms_psr2_su@page_flip.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [PASS][25] -> [SKIP][26] ([fdo#109441]) +1 similar issue
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-iclb5/igt@kms_psr@psr2_cursor_render.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-kbl:          [PASS][27] -> [DMESG-WARN][28] ([fdo#108566]) +8 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  * igt@perf_pmu@busy-no-semaphores-vcs1:
    - shard-iclb:         [PASS][29] -> [SKIP][30] ([fdo#112080]) +11 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-iclb4/igt@perf_pmu@busy-no-semaphores-vcs1.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-iclb6/igt@perf_pmu@busy-no-semaphores-vcs1.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@vecs0-s3:
    - {shard-tglb}:       [INCOMPLETE][31] ([fdo#111832]) -> [PASS][32] +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-tglb2/igt@gem_ctx_isolation@vecs0-s3.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-tglb9/igt@gem_ctx_isolation@vecs0-s3.html

  * {igt@gem_ctx_persistence@vcs1-queued}:
    - shard-iclb:         [SKIP][33] ([fdo#109276] / [fdo#112080]) -> [PASS][34] +4 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-iclb7/igt@gem_ctx_persistence@vcs1-queued.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-iclb4/igt@gem_ctx_persistence@vcs1-queued.html

  * igt@gem_ctx_shared@exec-single-timeline-bsd:
    - shard-iclb:         [SKIP][35] ([fdo#110841]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-iclb8/igt@gem_ctx_shared@exec-single-timeline-bsd.html

  * igt@gem_exec_schedule@promotion-bsd1:
    - shard-iclb:         [SKIP][37] ([fdo#109276]) -> [PASS][38] +15 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-iclb7/igt@gem_exec_schedule@promotion-bsd1.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-iclb4/igt@gem_exec_schedule@promotion-bsd1.html

  * igt@gem_exec_schedule@reorder-wide-bsd:
    - shard-iclb:         [SKIP][39] ([fdo#112146]) -> [PASS][40] +5 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-iclb2/igt@gem_exec_schedule@reorder-wide-bsd.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-iclb8/igt@gem_exec_schedule@reorder-wide-bsd.html

  * igt@gem_render_copy@yf-tiled-ccs-to-linear:
    - {shard-tglb}:       [FAIL][41] ([fdo#111771]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-tglb7/igt@gem_render_copy@yf-tiled-ccs-to-linear.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-tglb2/igt@gem_render_copy@yf-tiled-ccs-to-linear.html

  * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
    - shard-snb:          [DMESG-WARN][43] ([fdo#111870]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-snb1/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
    - shard-hsw:          [DMESG-WARN][45] ([fdo#111870]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-hsw6/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-hsw8/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html

  * {igt@i915_pm_dc@dc6-psr}:
    - shard-iclb:         [FAIL][47] ([fdo#110548]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-iclb8/igt@i915_pm_dc@dc6-psr.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-iclb1/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_pm_rc6_residency@rc6-accuracy:
    - shard-kbl:          [SKIP][49] ([fdo#109271]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-kbl7/igt@i915_pm_rc6_residency@rc6-accuracy.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-kbl6/igt@i915_pm_rc6_residency@rc6-accuracy.html

  * igt@i915_selftest@live_execlists:
    - {shard-tglb}:       [INCOMPLETE][51] ([fdo#111934]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-tglb1/igt@i915_selftest@live_execlists.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-tglb7/igt@i915_selftest@live_execlists.html

  * igt@i915_suspend@sysfs-reader:
    - shard-snb:          [DMESG-WARN][53] ([fdo#102365]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-snb1/igt@i915_suspend@sysfs-reader.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-snb1/igt@i915_suspend@sysfs-reader.html

  * igt@kms_cursor_crc@pipe-b-cursor-size-change:
    - shard-kbl:          [FAIL][55] ([fdo#103232]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-kbl6/igt@kms_cursor_crc@pipe-b-cursor-size-change.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-kbl7/igt@kms_cursor_crc@pipe-b-cursor-size-change.html
    - shard-apl:          [FAIL][57] ([fdo#103232]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-apl1/igt@kms_cursor_crc@pipe-b-cursor-size-change.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-apl6/igt@kms_cursor_crc@pipe-b-cursor-size-change.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-glk:          [FAIL][59] ([fdo#105363]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-glk5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-glk7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt:
    - {shard-tglb}:       [FAIL][61] ([fdo#103167]) -> [PASS][62] +1 similar issue
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - {shard-tglb}:       [INCOMPLETE][63] ([fdo#111832] / [fdo#111850] / [fdo#111884]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
    - shard-iclb:         [FAIL][65] ([fdo#103167]) -> [PASS][66] +7 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
    - shard-kbl:          [DMESG-WARN][67] ([fdo#108566]) -> [PASS][68] +1 similar issue
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
    - {shard-tglb}:       [INCOMPLETE][69] ([fdo#111832] / [fdo#111850]) -> [PASS][70] +4 similar issues
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-tglb4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-tglb9/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-apl:          [DMESG-WARN][71] ([fdo#108566]) -> [PASS][72] +1 similar issue
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_plane_lowres@pipe-a-tiling-y:
    - shard-iclb:         [FAIL][73] ([fdo#103166]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-y.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-iclb8/igt@kms_plane_lowres@pipe-a-tiling-y.html

  * igt@kms_psr@psr2_suspend:
    - shard-iclb:         [SKIP][75] ([fdo#109441]) -> [PASS][76] +1 similar issue
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-iclb5/igt@kms_psr@psr2_suspend.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-iclb2/igt@kms_psr@psr2_suspend.html

  * igt@perf_pmu@init-busy-vcs1:
    - shard-iclb:         [SKIP][77] ([fdo#112080]) -> [PASS][78] +8 similar issues
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-iclb8/igt@perf_pmu@init-busy-vcs1.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-iclb1/igt@perf_pmu@init-busy-vcs1.html

  
#### Warnings ####

  * igt@gem_mocs_settings@mocs-settings-bsd2:
    - shard-iclb:         [FAIL][79] ([fdo#111330]) -> [SKIP][80] ([fdo#109276]) +1 similar issue
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-iclb2/igt@gem_mocs_settings@mocs-settings-bsd2.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-iclb7/igt@gem_mocs_settings@mocs-settings-bsd2.html

  * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
    - shard-hsw:          [DMESG-WARN][81] ([fdo#111870]) -> [DMESG-WARN][82] ([fdo#110789] / [fdo#111870])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-hsw8/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-hsw6/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-kbl:          [DMESG-WARN][83] ([fdo#108566]) -> [DMESG-WARN][84] ([fdo#103313] / [fdo#108566])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7262/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102365]: https://bugs.freedesktop.org/show_bug.cgi?id=102365
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103313]: https://bugs.freedesktop.org/show_bug.cgi?id=103313
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110548]: https://bugs.freedesktop.org/show_bug.cgi?id=110548
  [fdo#110789]: https://bugs.freedesktop.org/show_bug.cgi?id=110789
  [fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
  [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
  [fdo#111606]: https://bugs.freedesktop.org/show_bug.cgi?id=111606
  [fdo#111646]: https://bugs.freedesktop.org/show_bug.cgi?id=111646
  [fdo#111671]: https://bugs.freedesktop.org/show_bug.cgi?id=111671
  [fdo#111677]: https://bugs.freedesktop.org/show_bug.cgi?id=111677
  [fdo#111764]: https://bugs.freedesktop.org/show_bug.cgi?id=111764
  [fdo#111771]: https://bugs.freedesktop.org/show_bug.cgi?id=111771
  [fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832
  [fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
  [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
  [fdo#111884]: https://bugs.freedesktop.org/show_bug.cgi?id=111884
  [fdo#111912]: https://bugs.freedesktop.org/show_bug.cgi?id=111912
  [fdo#111934]: https://bugs.freedesktop.org/show_bug.cgi?id=111934
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
  [fdo#112217]: https://bugs.freedesktop.org/show_bug.cgi?id=112217
  [fdo#112218]: https://bugs.freedesktop.org/show_bug.cgi?id=112218
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (11 -> 8)
------------------------------

  Missing    (3): pig-skl-6260u pig-glk-j5005 pig-hsw-4770r 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5263 -> IGTPW_3657
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_7262: 6d9033858175fc0e1ef5f77d6bd60356e6b70ee4 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_3657: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/index.html
  IGT_5263: 8a5d44dc5e51622cd43f23c2cf24d44c24a0564d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3657/index.html
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Re: [igt-dev] [PATCH v3 1/3] lib/rendercopy: Add AUX page table support

[Chris Wilson]

Quoting Imre Deak (2019-11-06 16:36:49)
> On Wed, Nov 06, 2019 at 04:14:36PM +0000, Chris Wilson wrote:
> > Quoting Imre Deak (2019-11-06 16:00:16)
> > > On Wed, Nov 06, 2019 at 11:11:40AM +0000, Chris Wilson wrote:
> > > > What's the coherency model for the pgt->bo? There's a lot of writes here
> > > > from the CPU how are you making sure they are visible to the GPU?
> > > 
> > > My understanding: execbuf will do a clflush for the buf on non-LLC
> > > platforms, while on LLC platforms that's not needed; not sure if there
> > > will be any non-LLC platforms where the AUX pagetable will be needed.
> > 
> > No, we don't unless you tell us you modified it between batches. That
> > would be the case if you were using drm_intel_bo_map(true) everytime,
> > but again that will then stall the GPU between every batch -- which we
> > definitely do not want when testing [as it will hide every bug] :)
> 
> Do you see a problem with the way I program it here though? I call
> drm_intel_bo_map(true) for the purpose of programming a new table. If
> you see a problem with that what do you suggest instead?

You create a new pagetable for every batch. Good for solitary render
copies, not so good for validation :( I expect we are invoking too many
stalls to be able to detect missing flushes and invalidations.

I would not suggest this interface is suitable long term. There is a
large leap between this and userspace, that I feel like we should be
covering more of the stepping stones so that userspace can trust the
layers it is built on [for some value of trust].

> > > On top of that the AUX GAM has its own caches - found that now in an HSD
> > > doc - which will be invalidated whenever GAM's top level table base
> > > pointer register is set from the context image, which happens whenver
> > > switching to the context.
> > 
> > But not for a lite-restore?
> 
> We still write the top level table regsiter from the batch, so that
> could in itself trigger the invalidation.

I would not expect that to be true for real clients. Or is it the only
recommended programming model?

> > So we have a problem when updating existing entries between batches
> > inside the same context? We put a big hammer at the front of the
> > request for TLB invalidation. If there's a flush we can add, we need
> > it there.
> 
> Yes, there is, see the CCS_AUX_INV reg in bspec. But I suspect this
> would have the same effect as writing the table ptr register, so not
> sure when exactly this would be needed. 

But the top level base pointer will not be updated on a lite restore;
are you sure the invalidation will occur if sublevels of the tt are
updated?

The good thing is that this is all virtual addresses, though there is a
slight danger with using system pages if the TLB is not flushed before
release (i.e. it can still access the page contents after someone else
uses them).
-Chris
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[igt-dev] ✗ Fi.CI.IGT: failure for series starting with [v3,1/3] lib/rendercopy: Add AUX page table support (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [v3,1/3] lib/rendercopy: Add AUX page table support (rev2)
URL   : https://patchwork.freedesktop.org/series/69012/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7263_full -> IGTPW_3658_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_3658_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_3658_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_3658_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
    - shard-iclb:         [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-iclb3/igt@kms_plane@pixel-format-pipe-c-planes-source-clamping.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-iclb4/igt@kms_plane@pixel-format-pipe-c-planes-source-clamping.html

  
New tests
---------

  New tests have been introduced between CI_DRM_7263_full and IGTPW_3658_full:

### New IGT tests (4) ###

  * igt@gem_render_copy@y-tiled-ccs-to-y-tiled-ccs:
    - Statuses : 5 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.24] s

  * igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs:
    - Statuses : 5 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.23] s

  * igt@gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs:
    - Statuses : 5 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.24] s

  * igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled-ccs:
    - Statuses : 4 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.23] s

  

Known issues
------------

  Here are the changes found in IGTPW_3658_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@vcs1-none:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-iclb2/igt@gem_ctx_isolation@vcs1-none.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-iclb6/igt@gem_ctx_isolation@vcs1-none.html

  * igt@gem_ctx_shared@exec-single-timeline-bsd:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#110841])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-iclb7/igt@gem_ctx_shared@exec-single-timeline-bsd.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-iclb2/igt@gem_ctx_shared@exec-single-timeline-bsd.html

  * igt@gem_exec_parallel@vcs1-fds:
    - shard-iclb:         [PASS][7] -> [SKIP][8] ([fdo#112080]) +5 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-iclb1/igt@gem_exec_parallel@vcs1-fds.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-iclb7/igt@gem_exec_parallel@vcs1-fds.html

  * igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd:
    - shard-iclb:         [PASS][9] -> [SKIP][10] ([fdo#112146]) +4 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-iclb8/igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-iclb4/igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd.html

  * igt@gem_exec_suspend@basic-s3:
    - shard-kbl:          [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +3 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-kbl7/igt@gem_exec_suspend@basic-s3.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-kbl3/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_persistent_relocs@forked-interruptible-thrashing:
    - shard-iclb:         [PASS][13] -> [FAIL][14] ([fdo#112037])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-iclb2/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-iclb4/igt@gem_persistent_relocs@forked-interruptible-thrashing.html

  * igt@gem_softpin@noreloc-s3:
    - shard-apl:          [PASS][15] -> [DMESG-WARN][16] ([fdo#108566])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-apl2/igt@gem_softpin@noreloc-s3.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-apl4/igt@gem_softpin@noreloc-s3.html

  * igt@gem_userptr_blits@sync-unmap:
    - shard-snb:          [PASS][17] -> [DMESG-WARN][18] ([fdo#111870]) +1 similar issue
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-snb5/igt@gem_userptr_blits@sync-unmap.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-snb6/igt@gem_userptr_blits@sync-unmap.html

  * igt@kms_color@pipe-b-ctm-green-to-red:
    - shard-apl:          [PASS][19] -> [FAIL][20] ([fdo#107201])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-apl8/igt@kms_color@pipe-b-ctm-green-to-red.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-apl1/igt@kms_color@pipe-b-ctm-green-to-red.html
    - shard-kbl:          [PASS][21] -> [FAIL][22] ([fdo#107201])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-kbl1/igt@kms_color@pipe-b-ctm-green-to-red.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-kbl2/igt@kms_color@pipe-b-ctm-green-to-red.html

  * igt@kms_color@pipe-c-degamma:
    - shard-apl:          [PASS][23] -> [FAIL][24] ([fdo#104782])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-apl3/igt@kms_color@pipe-c-degamma.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-apl3/igt@kms_color@pipe-c-degamma.html
    - shard-kbl:          [PASS][25] -> [FAIL][26] ([fdo#104782])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-kbl2/igt@kms_color@pipe-c-degamma.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-kbl1/igt@kms_color@pipe-c-degamma.html

  * igt@kms_cursor_crc@pipe-b-cursor-256x256-onscreen:
    - shard-apl:          [PASS][27] -> [FAIL][28] ([fdo#103232])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-apl1/igt@kms_cursor_crc@pipe-b-cursor-256x256-onscreen.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-apl1/igt@kms_cursor_crc@pipe-b-cursor-256x256-onscreen.html
    - shard-kbl:          [PASS][29] -> [FAIL][30] ([fdo#103232])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-kbl1/igt@kms_cursor_crc@pipe-b-cursor-256x256-onscreen.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-kbl4/igt@kms_cursor_crc@pipe-b-cursor-256x256-onscreen.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-hsw:          [PASS][31] -> [INCOMPLETE][32] ([fdo#103540]) +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-hsw8/igt@kms_flip@flip-vs-suspend-interruptible.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-hsw1/igt@kms_flip@flip-vs-suspend-interruptible.html
    - shard-snb:          [PASS][33] -> [INCOMPLETE][34] ([fdo#105411])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-snb4/igt@kms_flip@flip-vs-suspend-interruptible.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-snb1/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt:
    - shard-iclb:         [PASS][35] -> [FAIL][36] ([fdo#103167]) +5 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_plane_lowres@pipe-a-tiling-x:
    - shard-iclb:         [PASS][37] -> [FAIL][38] ([fdo#103166])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-iclb5/igt@kms_plane_lowres@pipe-a-tiling-x.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-iclb1/igt@kms_plane_lowres@pipe-a-tiling-x.html

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         [PASS][39] -> [SKIP][40] ([fdo#109441]) +2 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-iclb8/igt@kms_psr@psr2_sprite_plane_move.html

  * igt@kms_psr@suspend:
    - shard-iclb:         [PASS][41] -> [DMESG-WARN][42] ([fdo#111764])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-iclb6/igt@kms_psr@suspend.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-iclb1/igt@kms_psr@suspend.html

  * igt@kms_setmode@basic:
    - shard-apl:          [PASS][43] -> [FAIL][44] ([fdo#99912])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-apl1/igt@kms_setmode@basic.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-apl8/igt@kms_setmode@basic.html

  * igt@prime_busy@hang-bsd2:
    - shard-iclb:         [PASS][45] -> [SKIP][46] ([fdo#109276]) +18 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-iclb4/igt@prime_busy@hang-bsd2.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-iclb5/igt@prime_busy@hang-bsd2.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@rcs0-s3:
    - shard-kbl:          [DMESG-WARN][47] ([fdo#108566]) -> [PASS][48] +3 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-kbl4/igt@gem_ctx_isolation@rcs0-s3.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-kbl3/igt@gem_ctx_isolation@rcs0-s3.html

  * igt@gem_ctx_isolation@vcs1-dirty-create:
    - shard-iclb:         [SKIP][49] ([fdo#109276] / [fdo#112080]) -> [PASS][50] +2 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-iclb6/igt@gem_ctx_isolation@vcs1-dirty-create.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-iclb4/igt@gem_ctx_isolation@vcs1-dirty-create.html

  * igt@gem_eio@reset-stress:
    - shard-snb:          [FAIL][51] ([fdo#109661]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-snb2/igt@gem_eio@reset-stress.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-snb1/igt@gem_eio@reset-stress.html

  * igt@gem_exec_balancer@smoke:
    - shard-iclb:         [SKIP][53] ([fdo#110854]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-iclb6/igt@gem_exec_balancer@smoke.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-iclb2/igt@gem_exec_balancer@smoke.html

  * igt@gem_exec_create@forked:
    - {shard-tglb}:       [INCOMPLETE][55] ([fdo#108838] / [fdo#111747]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-tglb6/igt@gem_exec_create@forked.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-tglb3/igt@gem_exec_create@forked.html

  * igt@gem_exec_schedule@preempt-queue-bsd1:
    - shard-iclb:         [SKIP][57] ([fdo#109276]) -> [PASS][58] +13 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-iclb6/igt@gem_exec_schedule@preempt-queue-bsd1.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd1.html

  * igt@gem_exec_schedule@reorder-wide-bsd:
    - shard-iclb:         [SKIP][59] ([fdo#112146]) -> [PASS][60] +4 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-iclb2/igt@gem_exec_schedule@reorder-wide-bsd.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-iclb7/igt@gem_exec_schedule@reorder-wide-bsd.html

  * igt@gem_exec_schedule@smoketest-all:
    - {shard-tglb}:       [INCOMPLETE][61] ([fdo#111855]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-tglb3/igt@gem_exec_schedule@smoketest-all.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-tglb1/igt@gem_exec_schedule@smoketest-all.html

  * igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive:
    - shard-iclb:         [TIMEOUT][63] ([fdo#112068 ]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-iclb4/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-iclb8/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html

  * igt@gem_persistent_relocs@forked-interruptible-thrashing:
    - {shard-tglb}:       [FAIL][65] ([fdo#112037]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-tglb4/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-tglb3/igt@gem_persistent_relocs@forked-interruptible-thrashing.html

  * igt@gem_render_copy@yf-tiled-ccs-to-linear:
    - {shard-tglb}:       [FAIL][67] ([fdo#111771]) -> [PASS][68] +5 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-tglb9/igt@gem_render_copy@yf-tiled-ccs-to-linear.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-tglb1/igt@gem_render_copy@yf-tiled-ccs-to-linear.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
    - shard-hsw:          [DMESG-WARN][69] ([fdo#111870]) -> [PASS][70] +2 similar issues
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html

  * igt@gem_wait@write-busy-vcs1:
    - shard-iclb:         [SKIP][71] ([fdo#112080]) -> [PASS][72] +12 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-iclb7/igt@gem_wait@write-busy-vcs1.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-iclb4/igt@gem_wait@write-busy-vcs1.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - {shard-tglb}:       [INCOMPLETE][73] ([fdo#111832] / [fdo#111850]) -> [PASS][74] +2 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-tglb8/igt@i915_suspend@fence-restore-tiled2untiled.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-tglb6/igt@i915_suspend@fence-restore-tiled2untiled.html
    - shard-apl:          [DMESG-WARN][75] ([fdo#108566]) -> [PASS][76] +2 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-apl6/igt@i915_suspend@fence-restore-tiled2untiled.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-apl7/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_cursor_crc@pipe-b-cursor-size-change:
    - shard-kbl:          [FAIL][77] ([fdo#103232]) -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-kbl7/igt@kms_cursor_crc@pipe-b-cursor-size-change.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-kbl1/igt@kms_cursor_crc@pipe-b-cursor-size-change.html
    - shard-apl:          [FAIL][79] ([fdo#103232]) -> [PASS][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-apl1/igt@kms_cursor_crc@pipe-b-cursor-size-change.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-apl3/igt@kms_cursor_crc@pipe-b-cursor-size-change.html

  * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
    - shard-iclb:         [FAIL][81] ([fdo#103167]) -> [PASS][82] +2 similar issues
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt:
    - {shard-tglb}:       [FAIL][83] ([fdo#103167]) -> [PASS][84] +3 similar issues
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-tglb9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt.html

  * igt@kms_psr2_su@page_flip:
    - shard-iclb:         [SKIP][85] ([fdo#109642] / [fdo#111068]) -> [PASS][86]
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-iclb3/igt@kms_psr2_su@page_flip.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-iclb2/igt@kms_psr2_su@page_flip.html

  * igt@kms_psr@psr2_sprite_blt:
    - shard-iclb:         [SKIP][87] ([fdo#109441]) -> [PASS][88] +1 similar issue
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-iclb1/igt@kms_psr@psr2_sprite_blt.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html

  
#### Warnings ####

  * igt@gem_mocs_settings@mocs-reset-bsd2:
    - shard-iclb:         [SKIP][89] ([fdo#109276]) -> [FAIL][90] ([fdo#111330]) +1 similar issue
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7263/shard-iclb5/igt@gem_mocs_settings@mocs-reset-bsd2.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/shard-iclb2/igt@gem_mocs_settings@mocs-reset-bsd2.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo# 111852 ]: https://bugs.freedesktop.org/show_bug.cgi?id= 111852 
  [fdo# 112163]: https://bugs.freedesktop.org/show_bug.cgi?id= 112163
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#107201]: https://bugs.freedesktop.org/show_bug.cgi?id=107201
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108838]: https://bugs.freedesktop.org/show_bug.cgi?id=108838
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
  [fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
  [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
  [fdo#111703]: https://bugs.freedesktop.org/show_bug.cgi?id=111703
  [fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
  [fdo#111764]: https://bugs.freedesktop.org/show_bug.cgi?id=111764
  [fdo#111771]: https://bugs.freedesktop.org/show_bug.cgi?id=111771
  [fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832
  [fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
  [fdo#111855]: https://bugs.freedesktop.org/show_bug.cgi?id=111855
  [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
  [fdo#111884]: https://bugs.freedesktop.org/show_bug.cgi?id=111884
  [fdo#112016 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112016 
  [fdo#112021 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112021 
  [fdo#112037]: https://bugs.freedesktop.org/show_bug.cgi?id=112037
  [fdo#112068 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112068 
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
  [fdo#112217]: https://bugs.free

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3658/index.html
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Re: [igt-dev] [PATCH v3 1/3] lib/rendercopy: Add AUX page table support

[Imre Deak]

On Wed, Nov 06, 2019 at 05:02:30PM +0000, Chris Wilson wrote:
> Quoting Imre Deak (2019-11-06 16:36:49)
> > On Wed, Nov 06, 2019 at 04:14:36PM +0000, Chris Wilson wrote:
> > > Quoting Imre Deak (2019-11-06 16:00:16)
> > > > On Wed, Nov 06, 2019 at 11:11:40AM +0000, Chris Wilson wrote:
> > > > > What's the coherency model for the pgt->bo? There's a lot of writes here
> > > > > from the CPU how are you making sure they are visible to the GPU?
> > > > 
> > > > My understanding: execbuf will do a clflush for the buf on non-LLC
> > > > platforms, while on LLC platforms that's not needed; not sure if there
> > > > will be any non-LLC platforms where the AUX pagetable will be needed.
> > > 
> > > No, we don't unless you tell us you modified it between batches. That
> > > would be the case if you were using drm_intel_bo_map(true) everytime,
> > > but again that will then stall the GPU between every batch -- which we
> > > definitely do not want when testing [as it will hide every bug] :)
> > 
> > Do you see a problem with the way I program it here though? I call
> > drm_intel_bo_map(true) for the purpose of programming a new table. If
> > you see a problem with that what do you suggest instead?
> 
> You create a new pagetable for every batch. Good for solitary render
> copies, not so good for validation :( I expect we are invoking too many
> stalls to be able to detect missing flushes and invalidations.
> 
> I would not suggest this interface is suitable long term. There is a
> large leap between this and userspace, that I feel like we should be
> covering more of the stepping stones so that userspace can trust the
> layers it is built on [for some value of trust].

Yes, but the stall you mention should only happen on non-LLC platofrms.
At least on LLC we don't need to flush CPU caches, so it's not clear
what would cause the stall.

An API to create the pagetable at a higher level would be more efficient
in any case. Are you ok implementing that as a follow-up and starting
with the current approach?

> > > > On top of that the AUX GAM has its own caches - found that now in an HSD
> > > > doc - which will be invalidated whenever GAM's top level table base
> > > > pointer register is set from the context image, which happens whenver
> > > > switching to the context.
> > > 
> > > But not for a lite-restore?
> > 
> > We still write the top level table regsiter from the batch, so that
> > could in itself trigger the invalidation.
> 
> I would not expect that to be true for real clients. Or is it the only
> recommended programming model?

The spec doesn't detail programming models, it only describes the page
table format. I suppose programming the pgt pointer only once for a
context and then using CCS_AUX_INV later after entries have been
modified would be another way.

> > > So we have a problem when updating existing entries between batches
> > > inside the same context? We put a big hammer at the front of the
> > > request for TLB invalidation. If there's a flush we can add, we need
> > > it there.
> > 
> > Yes, there is, see the CCS_AUX_INV reg in bspec. But I suspect this
> > would have the same effect as writing the table ptr register, so not
> > sure when exactly this would be needed. 
> 
> But the top level base pointer will not be updated on a lite restore;
> are you sure the invalidation will occur if sublevels of the tt are
> updated?

No, that doesn't. So if the batch wouldn't write the top level table
register, we would need to invalidate the caches using CCS_AUX_INV.

> The good thing is that this is all virtual addresses, though there is a
> slight danger with using system pages if the TLB is not flushed before
> release (i.e. it can still access the page contents after someone else
> uses them).

You mean we'd need to invalidate the AUX pgt caches when releasing the
pages for a surface? Agreed that makes sense for robustness, even though
I can't see how writes could go astray if we invalidate the graphics
address mapping for the surface anyway.

--Imre
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Re: [igt-dev] [PATCH v3 1/3] lib/rendercopy: Add AUX page table support

[Chris Wilson]

Quoting Imre Deak (2019-11-06 19:04:10)
> On Wed, Nov 06, 2019 at 05:02:30PM +0000, Chris Wilson wrote:
> > Quoting Imre Deak (2019-11-06 16:36:49)
> > > On Wed, Nov 06, 2019 at 04:14:36PM +0000, Chris Wilson wrote:
> > > > Quoting Imre Deak (2019-11-06 16:00:16)
> > > > > On Wed, Nov 06, 2019 at 11:11:40AM +0000, Chris Wilson wrote:
> > > > > > What's the coherency model for the pgt->bo? There's a lot of writes here
> > > > > > from the CPU how are you making sure they are visible to the GPU?
> > > > > 
> > > > > My understanding: execbuf will do a clflush for the buf on non-LLC
> > > > > platforms, while on LLC platforms that's not needed; not sure if there
> > > > > will be any non-LLC platforms where the AUX pagetable will be needed.
> > > > 
> > > > No, we don't unless you tell us you modified it between batches. That
> > > > would be the case if you were using drm_intel_bo_map(true) everytime,
> > > > but again that will then stall the GPU between every batch -- which we
> > > > definitely do not want when testing [as it will hide every bug] :)
> > > 
> > > Do you see a problem with the way I program it here though? I call
> > > drm_intel_bo_map(true) for the purpose of programming a new table. If
> > > you see a problem with that what do you suggest instead?
> > 
> > You create a new pagetable for every batch. Good for solitary render
> > copies, not so good for validation :( I expect we are invoking too many
> > stalls to be able to detect missing flushes and invalidations.
> > 
> > I would not suggest this interface is suitable long term. There is a
> > large leap between this and userspace, that I feel like we should be
> > covering more of the stepping stones so that userspace can trust the
> > layers it is built on [for some value of trust].
> 
> Yes, but the stall you mention should only happen on non-LLC platofrms.
> At least on LLC we don't need to flush CPU caches, so it's not clear
> what would cause the stall.

Even LLC would be stalled due to the sync point inside the
drm_intel_bo_map(). If we were reusing page tables between batches...

> An API to create the pagetable at a higher level would be more efficient
> in any case. Are you ok implementing that as a follow-up and starting
> with the current approach?

I'm ok with accepting this as proof we can do end-to-end compression
onto scanout. But there's plenty of work if we want to try and break the
kernel :-p

> > > > > On top of that the AUX GAM has its own caches - found that now in an HSD
> > > > > doc - which will be invalidated whenever GAM's top level table base
> > > > > pointer register is set from the context image, which happens whenver
> > > > > switching to the context.
> > > > 
> > > > But not for a lite-restore?
> > > 
> > > We still write the top level table regsiter from the batch, so that
> > > could in itself trigger the invalidation.
> > 
> > I would not expect that to be true for real clients. Or is it the only
> > recommended programming model?
> 
> The spec doesn't detail programming models, it only describes the page
> table format. I suppose programming the pgt pointer only once for a
> context and then using CCS_AUX_INV later after entries have been
> modified would be another way.
> 
> > > > So we have a problem when updating existing entries between batches
> > > > inside the same context? We put a big hammer at the front of the
> > > > request for TLB invalidation. If there's a flush we can add, we need
> > > > it there.
> > > 
> > > Yes, there is, see the CCS_AUX_INV reg in bspec. But I suspect this
> > > would have the same effect as writing the table ptr register, so not
> > > sure when exactly this would be needed. 
> > 
> > But the top level base pointer will not be updated on a lite restore;
> > are you sure the invalidation will occur if sublevels of the tt are
> > updated?
> 
> No, that doesn't. So if the batch wouldn't write the top level table
> register, we would need to invalidate the caches using CCS_AUX_INV.

I think we're good leaving it to userspace poking around in its own page
tables to invalidate as it needs, except for the caveat below... (Which
is outside the flow of batches)
 
> > The good thing is that this is all virtual addresses, though there is a
> > slight danger with using system pages if the TLB is not flushed before
> > release (i.e. it can still access the page contents after someone else
> > uses them).
> 
> You mean we'd need to invalidate the AUX pgt caches when releasing the
> pages for a surface? Agreed that makes sense for robustness, even though
> I can't see how writes could go astray if we invalidate the graphics
> address mapping for the surface anyway.

* mutters

(The issue is that we don't invalidate before the surface goes away, so
there is^W may be a window of opportunity for peeking and poking.)
-Chris
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[igt-dev] ✓ Fi.CI.IGT: success for series starting with [v4,1/3] lib/rendercopy: Add AUX page table support (rev3)

[Patchwork]

== Series Details ==

Series: series starting with [v4,1/3] lib/rendercopy: Add AUX page table support (rev3)
URL   : https://patchwork.freedesktop.org/series/69012/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7264_full -> IGTPW_3659_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/index.html

New tests
---------

  New tests have been introduced between CI_DRM_7264_full and IGTPW_3659_full:

### New IGT tests (4) ###

  * igt@gem_render_copy@y-tiled-ccs-to-y-tiled-ccs:
    - Statuses : 4 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.25] s

  * igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs:
    - Statuses : 4 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.23] s

  * igt@gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs:
    - Statuses : 4 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.24] s

  * igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled-ccs:
    - Statuses : 5 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.38] s

  

Known issues
------------

  Here are the changes found in IGTPW_3659_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_busy@busy-vcs1:
    - shard-iclb:         [PASS][1] -> [SKIP][2] ([fdo#112080]) +11 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb2/igt@gem_busy@busy-vcs1.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-iclb3/igt@gem_busy@busy-vcs1.html

  * igt@gem_ctx_isolation@vcs1-clean:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080]) +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb4/igt@gem_ctx_isolation@vcs1-clean.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-iclb6/igt@gem_ctx_isolation@vcs1-clean.html

  * igt@gem_ctx_shared@exec-single-timeline-bsd:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#110841])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb5/igt@gem_ctx_shared@exec-single-timeline-bsd.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-iclb4/igt@gem_ctx_shared@exec-single-timeline-bsd.html

  * igt@gem_exec_schedule@preempt-other-chain-bsd:
    - shard-iclb:         [PASS][7] -> [SKIP][8] ([fdo#112146]) +8 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb8/igt@gem_exec_schedule@preempt-other-chain-bsd.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-iclb2/igt@gem_exec_schedule@preempt-other-chain-bsd.html

  * igt@gem_exec_schedule@preempt-queue-bsd2:
    - shard-iclb:         [PASS][9] -> [SKIP][10] ([fdo#109276]) +14 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb2/igt@gem_exec_schedule@preempt-queue-bsd2.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-iclb5/igt@gem_exec_schedule@preempt-queue-bsd2.html

  * igt@gem_persistent_relocs@forked-thrashing:
    - shard-hsw:          [PASS][11] -> [FAIL][12] ([fdo#112037])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-hsw5/igt@gem_persistent_relocs@forked-thrashing.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-hsw4/igt@gem_persistent_relocs@forked-thrashing.html

  * igt@gem_userptr_blits@sync-unmap:
    - shard-snb:          [PASS][13] -> [DMESG-WARN][14] ([fdo#111870]) +2 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-snb1/igt@gem_userptr_blits@sync-unmap.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-snb7/igt@gem_userptr_blits@sync-unmap.html

  * igt@gem_userptr_blits@sync-unmap-after-close:
    - shard-hsw:          [PASS][15] -> [DMESG-WARN][16] ([fdo#111870]) +2 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-hsw4/igt@gem_userptr_blits@sync-unmap-after-close.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-hsw4/igt@gem_userptr_blits@sync-unmap-after-close.html

  * igt@i915_suspend@forcewake:
    - shard-iclb:         [PASS][17] -> [DMESG-WARN][18] ([fdo#111764])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb4/igt@i915_suspend@forcewake.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-iclb8/igt@i915_suspend@forcewake.html

  * igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen:
    - shard-kbl:          [PASS][19] -> [INCOMPLETE][20] ([fdo#103665])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
    - shard-glk:          [PASS][21] -> [FAIL][22] ([fdo#105363])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt:
    - shard-iclb:         [PASS][23] -> [FAIL][24] ([fdo#103167]) +6 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-fullscreen:
    - shard-glk:          [PASS][25] -> [FAIL][26] ([fdo#103167])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-glk4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-fullscreen.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-glk1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-fullscreen.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
    - shard-kbl:          [PASS][27] -> [DMESG-WARN][28] ([fdo#108566])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html

  * igt@kms_psr@psr2_primary_page_flip:
    - shard-iclb:         [PASS][29] -> [SKIP][30] ([fdo#109441]) +1 similar issue
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-iclb4/igt@kms_psr@psr2_primary_page_flip.html

  * igt@kms_setmode@basic:
    - shard-apl:          [PASS][31] -> [FAIL][32] ([fdo#99912])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-apl1/igt@kms_setmode@basic.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-apl7/igt@kms_setmode@basic.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-apl:          [PASS][33] -> [DMESG-WARN][34] ([fdo#108566]) +3 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-apl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-apl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  * igt@perf@short-reads:
    - shard-apl:          [PASS][35] -> [TIMEOUT][36] ([fdo#103183])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-apl1/igt@perf@short-reads.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-apl6/igt@perf@short-reads.html

  
#### Possible fixes ####

  * {igt@gem_ctx_persistence@vcs1-queued}:
    - shard-iclb:         [SKIP][37] ([fdo#109276] / [fdo#112080]) -> [PASS][38] +3 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb6/igt@gem_ctx_persistence@vcs1-queued.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-iclb1/igt@gem_ctx_persistence@vcs1-queued.html

  * igt@gem_ctx_switch@vcs1:
    - shard-iclb:         [SKIP][39] ([fdo#112080]) -> [PASS][40] +7 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb8/igt@gem_ctx_switch@vcs1.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-iclb2/igt@gem_ctx_switch@vcs1.html

  * {igt@gem_eio@kms}:
    - shard-snb:          [INCOMPLETE][41] ([fdo#105411]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-snb2/igt@gem_eio@kms.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-snb2/igt@gem_eio@kms.html

  * igt@gem_exec_schedule@preempt-other-bsd:
    - shard-iclb:         [SKIP][43] ([fdo#112146]) -> [PASS][44] +3 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb2/igt@gem_exec_schedule@preempt-other-bsd.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-iclb7/igt@gem_exec_schedule@preempt-other-bsd.html

  * igt@gem_exec_schedule@smoketest-all:
    - {shard-tglb}:       [INCOMPLETE][45] ([fdo#111855]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-tglb3/igt@gem_exec_schedule@smoketest-all.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-tglb3/igt@gem_exec_schedule@smoketest-all.html

  * igt@gem_persistent_relocs@forked-interruptible-thrashing:
    - shard-hsw:          [FAIL][47] ([fdo#112037]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-hsw8/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-hsw2/igt@gem_persistent_relocs@forked-interruptible-thrashing.html

  * igt@gem_render_copy@yf-tiled-ccs-to-linear:
    - {shard-tglb}:       [FAIL][49] ([fdo#111771]) -> [PASS][50] +3 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-tglb9/igt@gem_render_copy@yf-tiled-ccs-to-linear.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-tglb2/igt@gem_render_copy@yf-tiled-ccs-to-linear.html

  * igt@gem_softpin@noreloc-s3:
    - {shard-tglb}:       [INCOMPLETE][51] ([fdo#111832]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-tglb7/igt@gem_softpin@noreloc-s3.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-tglb9/igt@gem_softpin@noreloc-s3.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
    - shard-hsw:          [DMESG-WARN][53] ([fdo#111870]) -> [PASS][54] +4 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-hsw2/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-hsw5/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html

  * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
    - shard-snb:          [DMESG-WARN][55] ([fdo#111870]) -> [PASS][56] +1 similar issue
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-snb7/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html

  * igt@gem_workarounds@suspend-resume-context:
    - shard-apl:          [DMESG-WARN][57] ([fdo#108566]) -> [PASS][58] +2 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-apl4/igt@gem_workarounds@suspend-resume-context.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-apl7/igt@gem_workarounds@suspend-resume-context.html

  * {igt@i915_pm_dc@dc6-dpms}:
    - shard-iclb:         [FAIL][59] ([fdo#110548]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-iclb7/igt@i915_pm_dc@dc6-dpms.html

  * {igt@i915_selftest@live_gt_timelines}:
    - {shard-tglb}:       [INCOMPLETE][61] ([fdo#111831]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-tglb6/igt@i915_selftest@live_gt_timelines.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-tglb7/igt@i915_selftest@live_gt_timelines.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - {shard-tglb}:       [INCOMPLETE][63] ([fdo#111832] / [fdo#111850]) -> [PASS][64] +2 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-tglb7/igt@i915_suspend@fence-restore-tiled2untiled.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-tglb3/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-kbl:          [DMESG-WARN][65] ([fdo#108566]) -> [PASS][66] +3 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_cursor_crc@pipe-b-cursor-size-change:
    - shard-kbl:          [FAIL][67] ([fdo#103232]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-kbl1/igt@kms_cursor_crc@pipe-b-cursor-size-change.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-kbl2/igt@kms_cursor_crc@pipe-b-cursor-size-change.html
    - shard-apl:          [FAIL][69] ([fdo#103232]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-apl1/igt@kms_cursor_crc@pipe-b-cursor-size-change.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-apl7/igt@kms_cursor_crc@pipe-b-cursor-size-change.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt:
    - {shard-tglb}:       [FAIL][71] ([fdo#103167]) -> [PASS][72] +1 similar issue
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-tglb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite:
    - shard-iclb:         [FAIL][73] ([fdo#103167]) -> [PASS][74] +3 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html

  * igt@kms_psr@no_drrs:
    - shard-iclb:         [FAIL][75] ([fdo#108341]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb1/igt@kms_psr@no_drrs.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-iclb5/igt@kms_psr@no_drrs.html

  * igt@kms_psr@psr2_sprite_render:
    - shard-iclb:         [SKIP][77] ([fdo#109441]) -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb5/igt@kms_psr@psr2_sprite_render.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-iclb2/igt@kms_psr@psr2_sprite_render.html

  * igt@kms_setmode@basic:
    - shard-kbl:          [FAIL][79] ([fdo#99912]) -> [PASS][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-kbl2/igt@kms_setmode@basic.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-kbl7/igt@kms_setmode@basic.html

  * igt@kms_vblank@pipe-d-ts-continuation-suspend:
    - {shard-tglb}:       [INCOMPLETE][81] ([fdo#111850]) -> [PASS][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-tglb3/igt@kms_vblank@pipe-d-ts-continuation-suspend.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-tglb3/igt@kms_vblank@pipe-d-ts-continuation-suspend.html

  * igt@prime_busy@hang-bsd2:
    - shard-iclb:         [SKIP][83] ([fdo#109276]) -> [PASS][84] +15 similar issues
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb6/igt@prime_busy@hang-bsd2.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-iclb2/igt@prime_busy@hang-bsd2.html

  * igt@tools_test@tools_test:
    - shard-snb:          [SKIP][85] ([fdo#109271]) -> [PASS][86]
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-snb5/igt@tools_test@tools_test.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-snb1/igt@tools_test@tools_test.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs1-nonpriv:
    - shard-iclb:         [FAIL][87] ([fdo#111329]) -> [SKIP][88] ([fdo#109276] / [fdo#112080])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/shard-iclb5/igt@gem_ctx_isolation@vcs1-nonpriv.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103183]: https://bugs.freedesktop.org/show_bug.cgi?id=103183
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110548]: https://bugs.freedesktop.org/show_bug.cgi?id=110548
  [fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
  [fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
  [fdo#111677]: https://bugs.freedesktop.org/show_bug.cgi?id=111677
  [fdo#111703]: https://bugs.freedesktop.org/show_bug.cgi?id=111703
  [fdo#111764]: https://bugs.freedesktop.org/show_bug.cgi?id=111764
  [fdo#111771]: https://bugs.freedesktop.org/show_bug.cgi?id=111771
  [fdo#111830 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111830 
  [fdo#111831]: https://bugs.freedesktop.org/show_bug.cgi?id=111831
  [fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832
  [fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
  [fdo#111855]: https://bugs.freedesktop.org/show_bug.cgi?id=111855
  [fdo#111865]: https://bugs.freedesktop.org/show_bug.cgi?id=111865
  [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
  [fdo#111912]: https://bugs.freedesktop.org/show_bug.cgi?id=111912
  [fdo#112031]: https://bugs.freedesktop.org/show_bug.cgi?id=112031
  [fdo#112037]: https://bugs.freedesktop.org/show_bug.cgi?id=112037
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (11 -> 8)
------------------------------

  Missing    (3): pig-skl-6260u pig-glk-j5005 pig-hsw-4770r 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5263 -> IGTPW_3659
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_7264: f5cfd96ad87b58bf3b5dfa5365f8beb8bac15a38 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_3659: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/index.html
  IGT_5263: 8a5d44dc5e51622cd43f23c2cf24d44c24a0564d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3659/index.html
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Re: [igt-dev] [PATCH v3 1/3] lib/rendercopy: Add AUX page table support

[Chris Wilson]

Quoting Chris Wilson (2019-11-06 21:25:03)
> Quoting Imre Deak (2019-11-06 19:04:10)
> > An API to create the pagetable at a higher level would be more efficient
> > in any case. Are you ok implementing that as a follow-up and starting
> > with the current approach?
> 
> I'm ok with accepting this as proof we can do end-to-end compression
> onto scanout. But there's plenty of work if we want to try and break the
> kernel :-p

Suffice to say, fix up the reloc delta, and have a 
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
for the series. I did not check the shifts against spec, but the
structure looks sane.
-Chris
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[igt-dev] [PATCH v5 1/3] lib/rendercopy: Add AUX page table support

[Imre Deak]

On GEN12+ the AUX CCS surfaces required by the render and media
compression must be specified by a 3 level page table directory, which
translates the main surface graphics address to the AUX CCS surface
graphics address. For this purpose add support for creating a GEM buffer
to translate the linear surface address range to the linear AUX surface
address range.

The buffers containing the main surface must be pinned down, since the
directory table entry indices depend on the surface address, and they
must be 64kB aligned. The page table can be relocated OTOH, so allow
that and emit the required relocation entries.

v2:
- Make level variables to be 0 based (l1..l3 -> level=0..2).
- Add missing drm_intel_bo_set_softpin_offset() stub to fix build on
  non-Intel archs.
- Fix missing offsets in reloc entries of already bound objects. (Chris)
- Randomize pin offsets, to try to avoid eviction. (Chris)
- Remove redundant MI_NOOPS around MI_LOAD_REGISTER_MEM
- Stop using explicit reloc cache domains, as these don't make sense on
  GEN12 anyway. (Chris)
- Fix missing autotools support. (Chris)
- s/igt_aux_pgtable/intel_aux_pgtable/, since the functionality is Intel
  specific. (Chris)
v3:
- Make sure all objects with an AUX surface are pinned.
v4:
- s/MI_LOAD_REGISTER_MEM/MI_LOAD_REGISTER_MEM_GEN8/ (Chris)
- Fix using buf->bo->size instead of buf->size when finding a free
  range for a pinned obj.
- Fix alignment of the reserved space start for a pinned obj.
- Move gen12_emit_aux_pgtable_state() to its logical spot.
v5:
- Fix reloc emit call, passing a relative instead of absolute target
  offset. (Chris)
- Fix off-by-one error when generating a random offset for pinned objs.

Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/Makefile.sources         |   1 +
 lib/drmtest.h                |   9 +
 lib/intel_aux_pgtable.c      | 372 +++++++++++++++++++++++++++++++++++
 lib/intel_aux_pgtable.h      |  12 ++
 lib/intel_reg.h              |   2 +
 lib/meson.build              |   1 +
 lib/rendercopy_gen9.c        | 235 +++++++++++++++++++++-
 lib/stubs/drm/intel_bufmgr.c |   6 +
 8 files changed, 632 insertions(+), 6 deletions(-)
 create mode 100644 lib/intel_aux_pgtable.c
 create mode 100644 lib/intel_aux_pgtable.h

diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 34e0c012..e544c27b 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -100,6 +100,7 @@ lib_source_list =	 	\
 	surfaceformat.h		\
 	sw_sync.c		\
 	sw_sync.h		\
+	intel_aux_pgtable.c	\
 	intel_reg_map.c		\
 	intel_iosf.c		\
 	igt_kms.c		\
diff --git a/lib/drmtest.h b/lib/drmtest.h
index 614f57e6..05eb0860 100644
--- a/lib/drmtest.h
+++ b/lib/drmtest.h
@@ -77,6 +77,15 @@ void __set_forced_driver(const char *name);
  */
 #define ALIGN(v, a) (((v) + (a)-1) & ~((a)-1))
 
+/**
+ * ALIGN_DOWN:
+ * @v: value to be aligned down
+ * @a: alignment unit in bytes
+ *
+ * Macro to align down a value @v to a specified unit @a.
+ */
+#define ALIGN_DOWN(x, a)	ALIGN((x) - ((a) - 1), (a))
+
 int drm_open_driver(int chipset);
 int drm_open_driver_master(int chipset);
 int drm_open_driver_render(int chipset);
diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c
new file mode 100644
index 00000000..ea909ec0
--- /dev/null
+++ b/lib/intel_aux_pgtable.c
@@ -0,0 +1,372 @@
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "drmtest.h"
+#include "intel_aux_pgtable.h"
+#include "intel_batchbuffer.h"
+#include "intel_bufmgr.h"
+#include "ioctl_wrappers.h"
+
+#include "i915/gem_mman.h"
+
+#define BITS_PER_LONG		(sizeof(long) * 8)
+#define BITMASK(e, s)		((~0UL << (s)) & \
+				 (~0UL >> (BITS_PER_LONG - 1 - (e))))
+
+/* The unit size to which the AUX CCS surface is aligned to. */
+#define AUX_CCS_UNIT_SIZE	64
+/*
+ * The block size on the AUX CCS surface which is mapped by one L1 AUX
+ * pagetable entry.
+ */
+#define AUX_CCS_BLOCK_SIZE	(4 * AUX_CCS_UNIT_SIZE)
+/*
+ * The block size on the main surface mapped by one AUX CCS block:
+ *   256 bytes per CCS block *
+ *   8   bits per byte /
+ *   2   bits per main surface CL *
+ *   64  bytes per main surface CL
+ */
+#define MAIN_SURFACE_BLOCK_SIZE	(AUX_CCS_BLOCK_SIZE * 8 / 2 * 64)
+
+#define GFX_ADDRESS_BITS	48
+
+#define max(a, b)		((a) > (b) ? (a) : (b))
+
+struct pgtable_level_desc {
+	int idx_shift;
+	int idx_bits;
+	int entry_ptr_shift;
+	int table_size;
+};
+
+struct pgtable_level_info {
+	const struct pgtable_level_desc *desc;
+	int table_count;
+	int alloc_base;
+	int alloc_ptr;
+};
+
+struct pgtable {
+	int levels;
+	struct pgtable_level_info *level_info;
+	int size;
+	int max_align;
+	drm_intel_bo *bo;
+};
+
+static int
+pgt_table_count(int address_bits, const struct igt_buf **bufs, int buf_count)
+{
+	uint64_t end;
+	int count;
+	int i;
+
+	count = 0;
+	end = 0;
+	for (i = 0; i < buf_count; i++) {
+		const struct igt_buf *buf = bufs[i];
+		uint64_t start;
+
+		/* We require bufs to be sorted. */
+		igt_assert(i == 0 ||
+			   buf->bo->offset64 >= bufs[i - 1]->bo->offset64 +
+						bufs[i - 1]->bo->size);
+
+		start = ALIGN_DOWN(buf->bo->offset64, 1UL << address_bits);
+		/* Avoid double counting for overlapping aligned bufs. */
+		start = max(start, end);
+
+		end = ALIGN(buf->bo->offset64 + buf->size, 1UL << address_bits);
+		igt_assert(end >= start);
+
+		count += (end - start) >> address_bits;
+	}
+
+	return count;
+}
+
+static void
+pgt_calc_size(struct pgtable *pgt, const struct igt_buf **bufs, int buf_count)
+{
+	int level;
+
+	pgt->size = 0;
+
+	for (level = pgt->levels - 1; level >= 0; level--) {
+		struct pgtable_level_info *li = &pgt->level_info[level];
+
+		li->alloc_base = ALIGN(pgt->size, li->desc->table_size);
+		li->alloc_ptr = li->alloc_base;
+
+		li->table_count = pgt_table_count(li->desc->idx_shift +
+						  li->desc->idx_bits,
+						  bufs, buf_count);
+
+		pgt->size = li->alloc_base +
+			    li->table_count * li->desc->table_size;
+	}
+}
+
+static uint64_t pgt_alloc_table(struct pgtable *pgt, int level)
+{
+	struct pgtable_level_info *li = &pgt->level_info[level];
+	uint64_t table;
+
+	table = li->alloc_ptr;
+	li->alloc_ptr += li->desc->table_size;
+
+	igt_assert(li->alloc_ptr <=
+		   li->alloc_base + li->table_count * li->desc->table_size);
+
+	return table;
+}
+
+static int pgt_entry_index(struct pgtable *pgt, int level, uint64_t address)
+{
+	const struct pgtable_level_desc *ld = pgt->level_info[level].desc;
+	uint64_t mask = BITMASK(ld->idx_shift + ld->idx_bits - 1,
+				ld->idx_shift);
+
+	return (address & mask) >> ld->idx_shift;
+}
+
+static uint64_t ptr_mask(struct pgtable *pgt, int level)
+{
+	const struct pgtable_level_desc *ld = pgt->level_info[level].desc;
+
+	return BITMASK(GFX_ADDRESS_BITS - 1, ld->entry_ptr_shift);
+}
+
+static uint64_t
+pgt_get_child_table(struct pgtable *pgt, uint64_t parent_table,
+		    int level, uint64_t address, uint64_t flags)
+{
+	uint64_t *parent_table_ptr;
+	int child_entry_idx;
+	uint64_t *child_entry_ptr;
+	uint64_t child_table;
+
+	parent_table_ptr = pgt->bo->virtual + parent_table;
+	child_entry_idx = pgt_entry_index(pgt, level, address);
+	child_entry_ptr = &parent_table_ptr[child_entry_idx];
+
+	if (!*child_entry_ptr) {
+		uint64_t pte;
+
+		child_table = pgt_alloc_table(pgt, level - 1);
+		igt_assert(!((child_table + pgt->bo->offset64) &
+			     ~ptr_mask(pgt, level)));
+
+		pte = child_table | flags;
+		*child_entry_ptr = pgt->bo->offset64 + pte;
+
+		igt_assert(pte <= INT32_MAX);
+		drm_intel_bo_emit_reloc(pgt->bo,
+					parent_table +
+						child_entry_idx * sizeof(uint64_t),
+					pgt->bo, pte, 0, 0);
+	} else {
+		child_table = (*child_entry_ptr & ptr_mask(pgt, level)) -
+			      pgt->bo->offset64;
+	}
+
+	return child_table;
+}
+
+static void
+pgt_set_l1_entry(struct pgtable *pgt, uint64_t l1_table,
+		 uint64_t address, uint64_t ptr, uint64_t flags)
+{
+	uint64_t *l1_table_ptr;
+	uint64_t *l1_entry_ptr;
+
+	l1_table_ptr = pgt->bo->virtual + l1_table;
+	l1_entry_ptr = &l1_table_ptr[pgt_entry_index(pgt, 0, address)];
+
+	igt_assert(!(ptr & ~ptr_mask(pgt, 0)));
+	*l1_entry_ptr = ptr | flags;
+}
+
+static uint64_t pgt_get_l1_flags(const struct igt_buf *buf)
+{
+	/*
+	 * The offset of .tile_mode isn't specifed by bspec, it's what Mesa
+	 * uses.
+	 */
+	union {
+		struct {
+			uint64_t	valid:1;
+			uint64_t	compression_mod:2;
+			uint64_t	lossy_compression:1;
+			uint64_t	pad:4;
+			uint64_t	addr:40;
+			uint64_t	pad2:4;
+			uint64_t	tile_mode:2;
+			uint64_t	depth:3;
+			uint64_t	ycr:1;
+			uint64_t	format:6;
+		} e;
+		uint64_t l;
+	} entry = {
+		.e = {
+			.valid = 1,
+			.tile_mode = buf->tiling == I915_TILING_Y ? 1 : 0,
+			.depth = 5,		/* 32bpp */
+			.format = 0xA,		/* B8G8R8A8_UNORM */
+		}
+	};
+
+	/*
+	 * TODO: Clarify if Yf is supported and if we need to differentiate
+	 *       Ys and Yf.
+	 *       Add support for more formats.
+	 */
+	igt_assert(buf->tiling == I915_TILING_Y ||
+		   buf->tiling == I915_TILING_Yf ||
+		   buf->tiling == I915_TILING_Ys);
+
+	igt_assert(buf->bpp == 32);
+
+	return entry.l;
+}
+
+static uint64_t pgt_get_lx_flags(void)
+{
+	union {
+		struct {
+			uint64_t        valid:1;
+			uint64_t        addr:47;
+			uint64_t        pad:16;
+		} e;
+		uint64_t l;
+	} entry = {
+		.e = {
+			.valid = 1,
+		}
+	};
+
+	return entry.l;
+}
+
+static void
+pgt_populate_entries_for_buf(struct pgtable *pgt,
+			       const struct igt_buf *buf,
+			       uint64_t top_table)
+{
+	uint64_t surface_addr = buf->bo->offset64;
+	uint64_t surface_end = surface_addr + buf->size;
+	uint64_t aux_addr = buf->bo->offset64 + buf->aux.offset;
+	uint64_t l1_flags = pgt_get_l1_flags(buf);
+	uint64_t lx_flags = pgt_get_lx_flags();
+
+	for (; surface_addr < surface_end;
+	     surface_addr += MAIN_SURFACE_BLOCK_SIZE,
+	     aux_addr += AUX_CCS_BLOCK_SIZE) {
+		uint64_t table = top_table;
+		int level;
+
+		for (level = pgt->levels - 1; level >= 1; level--)
+			table = pgt_get_child_table(pgt, table, level,
+						    surface_addr, lx_flags);
+
+		pgt_set_l1_entry(pgt, table, surface_addr, aux_addr, l1_flags);
+	}
+}
+
+static void pgt_populate_entries(struct pgtable *pgt,
+				 const struct igt_buf **bufs,
+				 int buf_count,
+				 drm_intel_bo *pgt_bo)
+{
+	uint64_t top_table;
+	int i;
+
+	pgt->bo = pgt_bo;
+
+	igt_assert(pgt_bo->size >= pgt->size);
+	memset(pgt_bo->virtual, 0, pgt->size);
+
+	top_table = pgt_alloc_table(pgt, pgt->levels - 1);
+	/* Top level table must be at offset 0. */
+	igt_assert(top_table == 0);
+
+	for (i = 0; i < buf_count; i++)
+		pgt_populate_entries_for_buf(pgt, bufs[i], top_table);
+}
+
+static struct pgtable *
+pgt_create(const struct pgtable_level_desc *level_descs, int levels,
+	   const struct igt_buf **bufs, int buf_count)
+{
+	struct pgtable *pgt;
+	int level;
+
+	pgt = calloc(1, sizeof(*pgt));
+	igt_assert(pgt);
+
+	pgt->levels = levels;
+
+	pgt->level_info = calloc(levels, sizeof(*pgt->level_info));
+	igt_assert(pgt->level_info);
+
+	for (level = 0; level < pgt->levels; level++) {
+		struct pgtable_level_info *li = &pgt->level_info[level];
+
+		li->desc = &level_descs[level];
+		if (li->desc->table_size > pgt->max_align)
+			pgt->max_align = li->desc->table_size;
+	}
+
+	pgt_calc_size(pgt, bufs, buf_count);
+
+	return pgt;
+}
+
+static void pgt_destroy(struct pgtable *pgt)
+{
+	free(pgt->level_info);
+	free(pgt);
+}
+
+drm_intel_bo *
+intel_aux_pgtable_create(drm_intel_bufmgr *bufmgr,
+		       const struct igt_buf **bufs, int buf_count)
+{
+	static const struct pgtable_level_desc level_desc[] = {
+		{
+			.idx_shift = 16,
+			.idx_bits = 8,
+			.entry_ptr_shift = 8,
+			.table_size = 8 * 1024,
+		},
+		{
+			.idx_shift = 24,
+			.idx_bits = 12,
+			.entry_ptr_shift = 13,
+			.table_size = 32 * 1024,
+		},
+		{
+			.idx_shift = 36,
+			.idx_bits = 12,
+			.entry_ptr_shift = 15,
+			.table_size = 32 * 1024,
+		},
+	};
+	struct pgtable *pgt;
+	drm_intel_bo *pgt_bo;
+
+	pgt = pgt_create(level_desc, ARRAY_SIZE(level_desc), bufs, buf_count);
+
+	pgt_bo = drm_intel_bo_alloc_for_render(bufmgr, "aux pgt",
+					       pgt->size, pgt->max_align);
+	igt_assert(pgt_bo);
+
+	igt_assert(drm_intel_bo_map(pgt_bo, true) == 0);
+	pgt_populate_entries(pgt, bufs, buf_count, pgt_bo);
+	igt_assert(drm_intel_bo_unmap(pgt_bo) == 0);
+
+	pgt_destroy(pgt);
+
+	return pgt_bo;
+}
diff --git a/lib/intel_aux_pgtable.h b/lib/intel_aux_pgtable.h
new file mode 100644
index 00000000..c0f001b4
--- /dev/null
+++ b/lib/intel_aux_pgtable.h
@@ -0,0 +1,12 @@
+#ifndef __INTEL_AUX_PGTABLE_H__
+#define __INTEL_AUX_PGTABLE_H__
+
+#include "intel_bufmgr.h"
+
+struct igt_buf;
+
+drm_intel_bo *
+intel_aux_pgtable_create(drm_intel_bufmgr *bufmgr,
+			 const struct igt_buf **bufs, int buf_count);
+
+#endif
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index 069440cb..84f746a6 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -673,6 +673,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define RING_VALID          0x00000001
 #define RING_INVALID        0x00000000
 
+#define GEN12_GFX_AUX_TABLE_BASE_ADDR	0x4200
 
 
 /* BitBlt Instructions
@@ -2570,6 +2571,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 #define MI_LOAD_SCAN_LINES_INCL		(0x12<<23)
 #define MI_LOAD_REGISTER_IMM		((0x22 << 23) | 1)
+#define MI_LOAD_REGISTER_MEM_GEN8	((0x29 << 23) | (4 - 2))
 
 /* Flush */
 #define MI_FLUSH			(0x04<<23)
diff --git a/lib/meson.build b/lib/meson.build
index fbc0c8d1..edaca091 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -44,6 +44,7 @@ lib_sources = [
 	'rendercopy_gen8.c',
 	'rendercopy_gen9.c',
 	'sw_sync.c',
+	'intel_aux_pgtable.c',
 	'intel_reg_map.c',
 	'intel_iosf.c',
 	'igt_kms.c',
diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index 694eb3cf..3189594f 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -15,6 +15,7 @@
 #include <i915_drm.h>
 
 #include "drmtest.h"
+#include "intel_aux_pgtable.h"
 #include "intel_bufmgr.h"
 #include "intel_batchbuffer.h"
 #include "intel_io.h"
@@ -972,19 +973,227 @@ static void gen8_emit_primitive(struct intel_batchbuffer *batch, uint32_t offset
 
 #define BATCH_STATE_SPLIT 2048
 
+static void
+aux_pgtable_find_max_free_range(const struct igt_buf **bufs, int buf_count,
+				uint64_t *range_start, uint64_t *range_size)
+{
+	/*
+	 * Keep the first page reserved, so we can differentiate pinned
+	 * objects based on a non-NULL offset.
+	 */
+	uint64_t start = 0x1000;
+	/* For now alloc only from the first 4GB address space. */
+	const uint64_t end = 1ULL << 32;
+	uint64_t max_range_start = 0;
+	uint64_t max_range_size = 0;
+	int i;
+
+	for (i = 0; i < buf_count; i++) {
+		if (bufs[i]->bo->offset64 >= end)
+			break;
+
+		if (bufs[i]->bo->offset64 - start > max_range_size) {
+			max_range_start = start;
+			max_range_size = bufs[i]->bo->offset64 - start;
+		}
+		start = bufs[i]->bo->offset64 + bufs[i]->bo->size;
+	}
+
+	if (start < end && end - start > max_range_size) {
+		max_range_start = start;
+		max_range_size = end - start;
+	}
+
+	*range_start = max_range_start;
+	*range_size = max_range_size;
+}
+
+static uint64_t
+aux_pgtable_find_free_range(const struct igt_buf **bufs, int buf_count,
+			    uint32_t size)
+{
+	uint64_t range_start;
+	uint64_t range_size;
+	/* A compressed surface must be 64kB aligned. */
+	const uint32_t align = 0x10000;
+	int pad;
+
+	aux_pgtable_find_max_free_range(bufs, buf_count,
+					&range_start, &range_size);
+
+	pad = ALIGN(range_start, align) - range_start;
+	range_start += pad;
+	range_size -= pad;
+	igt_assert(range_size >= size);
+
+	return range_start +
+	       ALIGN_DOWN(rand() % ((range_size - size) + 1), align);
+}
+
+static void
+aux_pgtable_reserve_range(const struct igt_buf **bufs, int buf_count,
+			  const struct igt_buf *new_buf)
+{
+	int i;
+
+	if (new_buf->aux.stride) {
+		uint64_t pin_offset = new_buf->bo->offset64;
+
+		if (!pin_offset)
+			pin_offset = aux_pgtable_find_free_range(bufs,
+								 buf_count,
+								 new_buf->bo->size);
+		drm_intel_bo_set_softpin_offset(new_buf->bo, pin_offset);
+		igt_assert(new_buf->bo->offset64 == pin_offset);
+	}
+
+	for (i = 0; i < buf_count; i++)
+		if (bufs[i]->bo->offset64 > new_buf->bo->offset64)
+			break;
+
+	memmove(&bufs[i + 1], &bufs[i], sizeof(bufs[0]) * (buf_count - i));
+
+	bufs[i] = new_buf;
+}
+
+struct aux_pgtable_info {
+	int buf_count;
+	const struct igt_buf *bufs[2];
+	uint64_t buf_pin_offsets[2];
+	drm_intel_bo *pgtable_bo;
+};
+
+static void
+gen12_aux_pgtable_init(struct aux_pgtable_info *info,
+		       drm_intel_bufmgr *bufmgr,
+		       const struct igt_buf *src_buf,
+		       const struct igt_buf *dst_buf)
+{
+	const struct igt_buf *bufs[2];
+	const struct igt_buf *reserved_bufs[2];
+	int reserved_buf_count;
+	int i;
+
+	if (!src_buf->aux.stride && !dst_buf->aux.stride)
+		return;
+
+	bufs[0] = src_buf;
+	bufs[1] = dst_buf;
+
+	/*
+	 * Ideally we'd need an IGT-wide GFX address space allocator, which
+	 * would consider all allocations and thus avoid evictions. For now use
+	 * a simpler scheme here, which only considers the buffers involved in
+	 * the blit, which should at least minimize the chance for evictions
+	 * in the case of subsequent blits:
+	 *   1. If they were already bound (bo->offset64 != 0), use this
+	 *      address.
+	 *   2. Pick a range randomly from the 4GB address space, that is not
+	 *      already occupied by a bound object, or an object we pinned.
+	 */
+	reserved_buf_count = 0;
+	/* First reserve space for any bufs that are bound already. */
+	for (i = 0; i < ARRAY_SIZE(bufs); i++)
+		if (bufs[i]->bo->offset64)
+			aux_pgtable_reserve_range(reserved_bufs,
+						  reserved_buf_count++,
+						  bufs[i]);
+
+	/* Next, reserve space for unbound bufs with an AUX surface. */
+	for (i = 0; i < ARRAY_SIZE(bufs); i++)
+		if (!bufs[i]->bo->offset64 && bufs[i]->aux.stride)
+			aux_pgtable_reserve_range(reserved_bufs,
+						  reserved_buf_count++,
+						  bufs[i]);
+
+	/* Create AUX pgtable entries only for bufs with an AUX surface */
+	info->buf_count = 0;
+	for (i = 0; i < reserved_buf_count; i++) {
+		if (!reserved_bufs[i]->aux.stride)
+			continue;
+
+		info->bufs[info->buf_count] = reserved_bufs[i];
+		info->buf_pin_offsets[info->buf_count] =
+			reserved_bufs[i]->bo->offset64;
+		info->buf_count++;
+	}
+
+	info->pgtable_bo = intel_aux_pgtable_create(bufmgr,
+						    info->bufs,
+						    info->buf_count);
+	igt_assert(info->pgtable_bo);
+}
+
+static void
+gen12_aux_pgtable_cleanup(struct aux_pgtable_info *info)
+{
+	int i;
+
+	/* Check that the pinned bufs kept their offset after the exec. */
+	for (i = 0; i < info->buf_count; i++)
+		igt_assert_eq_u64(info->bufs[i]->bo->offset64,
+				  info->buf_pin_offsets[i]);
+
+	drm_intel_bo_unreference(info->pgtable_bo);
+}
+
+static uint32_t
+gen12_create_aux_pgtable_state(struct intel_batchbuffer *batch,
+			       drm_intel_bo *aux_pgtable_bo)
+{
+	uint64_t *pgtable_ptr;
+	uint32_t pgtable_ptr_offset;
+	int ret;
+
+	if (!aux_pgtable_bo)
+		return 0;
+
+	pgtable_ptr = intel_batchbuffer_subdata_alloc(batch,
+						      sizeof(*pgtable_ptr),
+						      sizeof(*pgtable_ptr));
+	pgtable_ptr_offset = intel_batchbuffer_subdata_offset(batch,
+							      pgtable_ptr);
+
+	*pgtable_ptr = aux_pgtable_bo->offset64;
+	ret = drm_intel_bo_emit_reloc(batch->bo, pgtable_ptr_offset,
+				      aux_pgtable_bo, 0,
+				      0, 0);
+	assert(ret == 0);
+
+	return pgtable_ptr_offset;
+}
+
+static void
+gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch, uint32_t state)
+{
+	if (!state)
+		return;
+
+	OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8);
+	OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR);
+	OUT_RELOC(batch->bo, 0, 0, state);
+
+	OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8);
+	OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR + 4);
+	OUT_RELOC(batch->bo, 0, 0, state + 4);
+}
+
 static
 void _gen9_render_copyfunc(struct intel_batchbuffer *batch,
 			  drm_intel_context *context,
 			  const struct igt_buf *src, unsigned src_x,
 			  unsigned src_y, unsigned width, unsigned height,
 			  const struct igt_buf *dst, unsigned dst_x,
-			  unsigned dst_y, const uint32_t ps_kernel[][4],
+			  unsigned dst_y,
+			  drm_intel_bo *aux_pgtable_bo,
+			  const uint32_t ps_kernel[][4],
 			  uint32_t ps_kernel_size)
 {
 	uint32_t ps_sampler_state, ps_kernel_off, ps_binding_table;
 	uint32_t scissor_state;
 	uint32_t vertex_buffer;
 	uint32_t batch_end;
+	uint32_t aux_pgtable_state;
 
 	igt_assert(src->bpp == dst->bpp);
 	intel_batchbuffer_flush_with_context(batch, context);
@@ -1007,6 +1216,10 @@ void _gen9_render_copyfunc(struct intel_batchbuffer *batch,
 	viewport.cc_state = gen6_create_cc_viewport(batch);
 	viewport.sf_clip_state = gen7_create_sf_clip_viewport(batch);
 	scissor_state = gen6_create_scissor_rect(batch);
+
+	aux_pgtable_state = gen12_create_aux_pgtable_state(batch,
+							   aux_pgtable_bo);
+
 	/* TODO: theree is other state which isn't setup */
 
 	assert(batch->ptr < &batch->buffer[4095]);
@@ -1018,6 +1231,8 @@ void _gen9_render_copyfunc(struct intel_batchbuffer *batch,
 	OUT_BATCH(G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D |
 				GEN9_PIPELINE_SELECTION_MASK);
 
+	gen12_emit_aux_pgtable_state(batch, aux_pgtable_state);
+
 	gen8_emit_sip(batch);
 
 	gen7_emit_push_constants(batch);
@@ -1092,8 +1307,8 @@ void gen9_render_copyfunc(struct intel_batchbuffer *batch,
 
 {
 	_gen9_render_copyfunc(batch, context, src, src_x, src_y,
-			  width, height, dst, dst_x, dst_y, ps_kernel_gen9,
-			  sizeof(ps_kernel_gen9));
+			  width, height, dst, dst_x, dst_y, NULL,
+			  ps_kernel_gen9, sizeof(ps_kernel_gen9));
 }
 
 void gen11_render_copyfunc(struct intel_batchbuffer *batch,
@@ -1104,8 +1319,8 @@ void gen11_render_copyfunc(struct intel_batchbuffer *batch,
 
 {
 	_gen9_render_copyfunc(batch, context, src, src_x, src_y,
-			  width, height, dst, dst_x, dst_y, ps_kernel_gen11,
-			  sizeof(ps_kernel_gen11));
+			  width, height, dst, dst_x, dst_y, NULL,
+			  ps_kernel_gen11, sizeof(ps_kernel_gen11));
 }
 
 void gen12_render_copyfunc(struct intel_batchbuffer *batch,
@@ -1115,7 +1330,15 @@ void gen12_render_copyfunc(struct intel_batchbuffer *batch,
 			   const struct igt_buf *dst, unsigned dst_x, unsigned dst_y)
 
 {
+	struct aux_pgtable_info pgtable_info = { };
+
+	gen12_aux_pgtable_init(&pgtable_info, batch->bufmgr, src, dst);
+
 	_gen9_render_copyfunc(batch, context, src, src_x, src_y,
-			  width, height, dst, dst_x, dst_y, gen12_render_copy,
+			  width, height, dst, dst_x, dst_y,
+			  pgtable_info.pgtable_bo,
+			  gen12_render_copy,
 			  sizeof(gen12_render_copy));
+
+	gen12_aux_pgtable_cleanup(&pgtable_info);
 }
diff --git a/lib/stubs/drm/intel_bufmgr.c b/lib/stubs/drm/intel_bufmgr.c
index f87452ac..cbab2484 100644
--- a/lib/stubs/drm/intel_bufmgr.c
+++ b/lib/stubs/drm/intel_bufmgr.c
@@ -233,6 +233,12 @@ int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
 	return -ENODEV;
 }
 
+int drm_intel_bo_set_softpin_offset(drm_intel_bo *bo, uint64_t offset)
+{
+	igt_require_f(false, missing_support_str);
+	return -ENODEV;
+}
+
 int drm_intel_bo_disable_reuse(drm_intel_bo *bo)
 {
 	igt_require_f(false, missing_support_str);
-- 
2.17.1

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Re: [igt-dev] [PATCH v3 1/3] lib/rendercopy: Add AUX page table support

[Imre Deak]

On Thu, Nov 07, 2019 at 12:41:35PM +0000, Chris Wilson wrote:
> Quoting Chris Wilson (2019-11-06 21:25:03)
> > Quoting Imre Deak (2019-11-06 19:04:10)
> > > An API to create the pagetable at a higher level would be more efficient
> > > in any case. Are you ok implementing that as a follow-up and starting
> > > with the current approach?
> > 
> > I'm ok with accepting this as proof we can do end-to-end compression
> > onto scanout. But there's plenty of work if we want to try and break the
> > kernel :-p
> 
> Suffice to say, fix up the reloc delta, and have a 
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> for the series. I did not check the shifts against spec, but the
> structure looks sane.

Thanks, I also tested now more the relocations.

> -Chris
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[igt-dev] ✓ Fi.CI.BAT: success for series starting with [v5,1/3] lib/rendercopy: Add AUX page table support (rev4)

[Patchwork]

== Series Details ==

Series: series starting with [v5,1/3] lib/rendercopy: Add AUX page table support (rev4)
URL   : https://patchwork.freedesktop.org/series/69012/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7288 -> IGTPW_3664
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/index.html

Known issues
------------

  Here are the changes found in IGTPW_3664 that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@gem_exec_create@basic:
    - {fi-tgl-u}:         [INCOMPLETE][1] ([fdo#111736]) -> [PASS][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-tgl-u/igt@gem_exec_create@basic.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/fi-tgl-u/igt@gem_exec_create@basic.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][3] ([fdo#111407]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-skl-6700k2:      [INCOMPLETE][5] ([fdo#104108]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-skl-6700k2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/fi-skl-6700k2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
  [fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736


Participating hosts (51 -> 45)
------------------------------

  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5266 -> IGTPW_3664

  CI-20190529: 20190529
  CI_DRM_7288: 41eb27f39e60d822edc75e6aaeb416b72bc1dcf2 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_3664: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/index.html
  IGT_5266: 60a67653613c87a69ebecf12cf00aa362ac87597 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools



== Testlist changes ==

+igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled-ccs
+igt@gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs
+igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs
+igt@gem_render_copy@y-tiled-ccs-to-y-tiled-ccs

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/index.html
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[igt-dev] ✗ GitLab.Pipeline: failure for series starting with [v5,1/3] lib/rendercopy: Add AUX page table support (rev4)

[Patchwork]

== Series Details ==

Series: series starting with [v5,1/3] lib/rendercopy: Add AUX page table support (rev4)
URL   : https://patchwork.freedesktop.org/series/69012/
State : failure

== Summary ==

ERROR! This series introduces new undocumented tests:

gem_render_copy@y-tiled-ccs-to-y-tiled-ccs
gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs
gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs
gem_render_copy@yf-tiled-ccs-to-yf-tiled-ccs

Can you document them as per the requirement in the [CONTRIBUTING.md]?

[Documentation] has more details on how to do this.

Here are few examples:
https://gitlab.freedesktop.org/drm/igt-gpu-tools/commit/0316695d03aa46108296b27f3982ec93200c7a6e
https://gitlab.freedesktop.org/drm/igt-gpu-tools/commit/443cc658e1e6b492ee17bf4f4d891029eb7a205d

Thanks in advance!

[CONTRIBUTING.md]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/blob/master/CONTRIBUTING.md#L19
[Documentation]: https://drm.pages.freedesktop.org/igt-gpu-tools/igt-gpu-tools-Core.html#igt-describe

Other than that, pipeline status: SUCCESS.

see https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/pipelines/77212 for more details

== Logs ==

For more details see: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/pipelines/77212
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[igt-dev] [PATCH v3 3/3] tests/gem_render_copy: Add compressed src to compressed dst subtests

[Imre Deak]

Add new subtests that blit from a compressed source to a compressed
destination buffer.

While at it also add descriptions for the subtests.

v2:
- Use the correct buffer when dumping the png for the compressed buf.
v3:
- Add subtest descriptions.

Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 tests/i915/gem_render_copy.c | 164 +++++++++++++++++++++++++----------
 1 file changed, 117 insertions(+), 47 deletions(-)

diff --git a/tests/i915/gem_render_copy.c b/tests/i915/gem_render_copy.c
index fd139e91..7e6657b4 100644
--- a/tests/i915/gem_render_copy.c
+++ b/tests/i915/gem_render_copy.c
@@ -572,9 +572,13 @@ static void scratch_buf_aux_check(data_t *data,
 		     "Aux surface indicates that nothing was compressed\n");
 }
 
-static void test(data_t *data, uint32_t tiling, uint64_t ccs_modifier)
+#define SRC_COMPRESSED	1
+#define DST_COMPRESSED	2
+
+static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling,
+		 int flags)
 {
-	struct igt_buf dst, ccs, ref;
+	struct igt_buf dst, src_ccs, dst_ccs, ref;
 	struct {
 		struct igt_buf buf;
 		const char *filename;
@@ -602,22 +606,34 @@ static void test(data_t *data, uint32_t tiling, uint64_t ccs_modifier)
 			.x = 1, .y = 1,
 		},
 	};
-
 	int opt_dump_aub = igt_aub_dump_enabled();
 	int num_src = ARRAY_SIZE(src);
+	bool src_compressed = flags & SRC_COMPRESSED;
+	bool dst_compressed = flags & DST_COMPRESSED;
+
+	/*
+	 * The tiling for uncompressed source buffers is determined by the
+	 * tiling of the src[] buffers above.
+	 */
+	igt_assert(!src_tiling || src_compressed);
 
 	/* no Yf before gen9 */
 	if (intel_gen(data->devid) < 9)
 		num_src--;
 
-	if (tiling == I915_TILING_Yf || ccs_modifier)
+	if (src_tiling == I915_TILING_Yf || dst_tiling == I915_TILING_Yf ||
+	    src_compressed || dst_compressed)
 		igt_require(intel_gen(data->devid) >= 9);
 
 	for (int i = 0; i < num_src; i++)
 		scratch_buf_init(data, &src[i].buf, WIDTH, HEIGHT, src[i].tiling, false);
-	scratch_buf_init(data, &dst, WIDTH, HEIGHT, tiling, false);
-	if (ccs_modifier)
-		scratch_buf_init(data, &ccs, WIDTH, HEIGHT, ccs_modifier, true);
+	scratch_buf_init(data, &dst, WIDTH, HEIGHT, dst_tiling, false);
+	if (src_compressed)
+		scratch_buf_init(data, &src_ccs, WIDTH, HEIGHT,
+				 src_tiling, true);
+	if (dst_compressed)
+		scratch_buf_init(data, &dst_ccs, WIDTH, HEIGHT,
+				 dst_tiling, true);
 	scratch_buf_init(data, &ref, WIDTH, HEIGHT, I915_TILING_NONE, false);
 
 	for (int i = 0; i < num_src; i++)
@@ -657,26 +673,45 @@ static void test(data_t *data, uint32_t tiling, uint64_t ccs_modifier)
 	 *	 |dst|src|
 	 *	  -------
 	 */
-	if (ccs_modifier)
+	if (src_compressed)
 		data->render_copy(data->batch, NULL,
 				  &dst, 0, 0, WIDTH, HEIGHT,
-				  &ccs, 0, 0);
+				  &src_ccs, 0, 0);
 
 	for (int i = 0; i < num_src; i++)
 		data->render_copy(data->batch, NULL,
-				  &src[i].buf, WIDTH/4, HEIGHT/4, WIDTH/2-2, HEIGHT/2-2,
-				  ccs_modifier ? &ccs : &dst, src[i].x, src[i].y);
+				  &src[i].buf,
+				  WIDTH/4, HEIGHT/4, WIDTH/2-2, HEIGHT/2-2,
+				  src_compressed ? &src_ccs : &dst,
+				  src[i].x, src[i].y);
 
-	if (ccs_modifier)
+	if (src_compressed || dst_compressed)
 		data->render_copy(data->batch, NULL,
-				  &ccs, 0, 0, WIDTH, HEIGHT,
-				  &dst, 0, 0);
+				  src_compressed ? &src_ccs : &dst,
+				  0, 0, WIDTH, HEIGHT,
+				  dst_compressed ? &dst_ccs : &dst,
+				  0, 0);
+
+	if (dst_compressed)
+		data->render_copy(data->batch, NULL,
+				  &dst_ccs,
+				  0, 0, WIDTH, HEIGHT,
+				  &dst,
+				  0, 0);
 
 	if (opt_dump_png){
 		scratch_buf_write_to_png(data, &dst, "result.png");
-		if (ccs_modifier) {
-			scratch_buf_write_to_png(data, &ccs, "compressed.png");
-			scratch_buf_aux_write_to_png(data, &ccs, "compressed-aux.png");
+		if (src_compressed) {
+			scratch_buf_write_to_png(data, &src_ccs,
+						 "compressed-src.png");
+			scratch_buf_aux_write_to_png(data, &src_ccs,
+						     "compressed-src-aux.png");
+		}
+		if (dst_compressed) {
+			scratch_buf_write_to_png(data, &dst_ccs,
+						 "compressed-dst.png");
+			scratch_buf_aux_write_to_png(data, &dst_ccs,
+						     "compressed-dst-aux.png");
 		}
 	}
 
@@ -694,12 +729,16 @@ static void test(data_t *data, uint32_t tiling, uint64_t ccs_modifier)
 		scratch_buf_check(data, &dst, &ref, WIDTH - 10, HEIGHT - 10);
 	}
 
-	if (ccs_modifier)
-		scratch_buf_aux_check(data, &ccs);
+	if (src_compressed)
+		scratch_buf_aux_check(data, &src_ccs);
+	if (dst_compressed)
+		scratch_buf_aux_check(data, &dst_ccs);
 
 	scratch_buf_fini(&ref);
-	if (ccs_modifier)
-		scratch_buf_fini(&ccs);
+	if (dst_compressed)
+		scratch_buf_fini(&dst_ccs);
+	if (src_compressed)
+		scratch_buf_fini(&src_ccs);
 	scratch_buf_fini(&dst);
 	for (int i = 0; i < num_src; i++)
 		scratch_buf_fini(&src[i].buf);
@@ -726,8 +765,49 @@ const char *help_str =
 	"  -a\tCheck all pixels\n"
 	;
 
+static const char *buf_mode_str(uint32_t tiling, bool compressed)
+{
+	switch (tiling) {
+	default:
+	case I915_TILING_NONE:
+		return "linear";
+	case I915_TILING_X:
+		return "x-tiled";
+	case I915_TILING_Y:
+		return compressed ? "y-tiled-ccs" : "y-tiled";
+	case I915_TILING_Yf:
+		return compressed ? "yf-tiled-ccs" : "yf-tiled";
+	}
+}
+
 igt_main_args("da", NULL, help_str, opt_handler, NULL)
 {
+	static const struct test_desc {
+		int src_tiling;
+		int dst_tiling;
+		int flags;
+	} tests[] = {
+		{ I915_TILING_NONE, I915_TILING_X,    0 },
+		{ I915_TILING_NONE, I915_TILING_Y,    0 },
+		{ I915_TILING_NONE, I915_TILING_Yf,   0 },
+
+		{ I915_TILING_Y,    I915_TILING_NONE, SRC_COMPRESSED },
+		{ I915_TILING_Y,    I915_TILING_X,    SRC_COMPRESSED },
+		{ I915_TILING_Y,    I915_TILING_Y,    SRC_COMPRESSED },
+		{ I915_TILING_Y,    I915_TILING_Yf,   SRC_COMPRESSED },
+
+		{ I915_TILING_Yf,   I915_TILING_NONE, SRC_COMPRESSED },
+		{ I915_TILING_Yf,   I915_TILING_X,    SRC_COMPRESSED },
+		{ I915_TILING_Yf,   I915_TILING_Y,    SRC_COMPRESSED },
+		{ I915_TILING_Yf,   I915_TILING_Yf,   SRC_COMPRESSED },
+
+		{ I915_TILING_Y,    I915_TILING_Y,    SRC_COMPRESSED | DST_COMPRESSED },
+		{ I915_TILING_Yf,   I915_TILING_Yf,   SRC_COMPRESSED | DST_COMPRESSED },
+		{ I915_TILING_Y,    I915_TILING_Yf,   SRC_COMPRESSED | DST_COMPRESSED },
+		{ I915_TILING_Yf,   I915_TILING_Y,    SRC_COMPRESSED | DST_COMPRESSED },
+	};
+	int i;
+
 	data_t data = {0, };
 
 	igt_fixture {
@@ -748,32 +828,22 @@ igt_main_args("da", NULL, help_str, opt_handler, NULL)
 		igt_fork_hang_detector(data.drm_fd);
 	}
 
-	igt_subtest("linear")
-		test(&data, I915_TILING_NONE, 0);
-	igt_subtest("x-tiled")
-		test(&data, I915_TILING_X, 0);
-	igt_subtest("y-tiled")
-		test(&data, I915_TILING_Y, 0);
-	igt_subtest("yf-tiled")
-		test(&data, I915_TILING_Yf, 0);
-
-	igt_subtest("y-tiled-ccs-to-linear")
-		test(&data, I915_TILING_NONE, I915_TILING_Y);
-	igt_subtest("y-tiled-ccs-to-x-tiled")
-		test(&data, I915_TILING_X, I915_TILING_Y);
-	igt_subtest("y-tiled-ccs-to-y-tiled")
-		test(&data, I915_TILING_Y, I915_TILING_Y);
-	igt_subtest("y-tiled-ccs-to-yf-tiled")
-		test(&data, I915_TILING_Yf, I915_TILING_Y);
-
-	igt_subtest("yf-tiled-ccs-to-linear")
-		test(&data, I915_TILING_NONE, I915_TILING_Yf);
-	igt_subtest("yf-tiled-ccs-to-x-tiled")
-		test(&data, I915_TILING_X, I915_TILING_Yf);
-	igt_subtest("yf-tiled-ccs-to-y-tiled")
-		test(&data, I915_TILING_Y, I915_TILING_Yf);
-	igt_subtest("yf-tiled-ccs-to-yf-tiled")
-		test(&data, I915_TILING_Yf, I915_TILING_Yf);
+	for (i = 0; i < ARRAY_SIZE(tests); i++) {
+		const struct test_desc *t = &tests[i];
+		const char *src_mode = buf_mode_str(t->src_tiling,
+						    t->flags & SRC_COMPRESSED);
+		const char *dst_mode = buf_mode_str(t->dst_tiling,
+						    t->flags & DST_COMPRESSED);
+
+		igt_describe_f("Test render_copy() from a %s to a %s buffer.",
+			       src_mode, dst_mode);
+
+		igt_subtest_f("%s%s%s",
+			      t->flags ? src_mode : "",
+			      t->flags ? "-to-" : "",
+			      dst_mode)
+			test(&data, t->src_tiling, t->dst_tiling, t->flags);
+	}
 
 	igt_fixture {
 		igt_stop_hang_detector();
-- 
2.17.1

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[igt-dev] ✓ Fi.CI.BAT: success for series starting with [v5,1/3] lib/rendercopy: Add AUX page table support (rev5)

[Patchwork]

== Series Details ==

Series: series starting with [v5,1/3] lib/rendercopy: Add AUX page table support (rev5)
URL   : https://patchwork.freedesktop.org/series/69012/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7298 -> IGTPW_3671
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/index.html

Known issues
------------

  Here are the changes found in IGTPW_3671 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live_gem_contexts:
    - fi-bsw-kefka:       [PASS][1] -> [INCOMPLETE][2] ([fdo# 111542])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/fi-bsw-kefka/igt@i915_selftest@live_gem_contexts.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/fi-bsw-kefka/igt@i915_selftest@live_gem_contexts.html

  
#### Possible fixes ####

  * igt@i915_pm_rpm@module-reload:
    - fi-icl-u3:          [DMESG-WARN][3] -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/fi-icl-u3/igt@i915_pm_rpm@module-reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/fi-icl-u3/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live_hangcheck:
    - fi-icl-dsi:         [INCOMPLETE][5] ([fdo#107713] / [fdo#108569]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
    - fi-hsw-4770r:       [DMESG-FAIL][7] ([fdo#111991]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-icl-u2:          [FAIL][9] ([fdo#109635 ] / [fdo#110387]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo# 111542]: https://bugs.freedesktop.org/show_bug.cgi?id= 111542
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 
  [fdo#110387]: https://bugs.freedesktop.org/show_bug.cgi?id=110387
  [fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
  [fdo#111991]: https://bugs.freedesktop.org/show_bug.cgi?id=111991


Participating hosts (51 -> 44)
------------------------------

  Missing    (7): fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5268 -> IGTPW_3671

  CI-20190529: 20190529
  CI_DRM_7298: 1281ac91aabe4bed2f89e539a7f2073475d0124b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_3671: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/index.html
  IGT_5268: c94958b8f7caefcda72392417ae6f3a98e36a48b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools



== Testlist changes ==

+igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled-ccs
+igt@gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs
+igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs
+igt@gem_render_copy@y-tiled-ccs-to-y-tiled-ccs
-igt@gem_render_copy@linear

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/index.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] ✓ Fi.CI.IGT: success for series starting with [v5,1/3] lib/rendercopy: Add AUX page table support (rev4)

[Patchwork]

== Series Details ==

Series: series starting with [v5,1/3] lib/rendercopy: Add AUX page table support (rev4)
URL   : https://patchwork.freedesktop.org/series/69012/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7288_full -> IGTPW_3664_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/index.html

New tests
---------

  New tests have been introduced between CI_DRM_7288_full and IGTPW_3664_full:

### New IGT tests (4) ###

  * igt@gem_render_copy@y-tiled-ccs-to-y-tiled-ccs:
    - Statuses : 4 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.24] s

  * igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs:
    - Statuses : 5 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.23] s

  * igt@gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs:
    - Statuses : 4 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.25] s

  * igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled-ccs:
    - Statuses : 5 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.23] s

  

Known issues
------------

  Here are the changes found in IGTPW_3664_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_exec@basic-invalid-context-vcs1:
    - shard-iclb:         [PASS][1] -> [SKIP][2] ([fdo#112080]) +10 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb1/igt@gem_ctx_exec@basic-invalid-context-vcs1.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-iclb5/igt@gem_ctx_exec@basic-invalid-context-vcs1.html

  * igt@gem_ctx_isolation@bcs0-s3:
    - shard-tglb:         [PASS][3] -> [INCOMPLETE][4] ([fdo#111832]) +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb9/igt@gem_ctx_isolation@bcs0-s3.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-tglb4/igt@gem_ctx_isolation@bcs0-s3.html

  * igt@gem_ctx_isolation@vcs1-clean:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#109276] / [fdo#112080]) +3 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb2/igt@gem_ctx_isolation@vcs1-clean.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-iclb5/igt@gem_ctx_isolation@vcs1-clean.html

  * igt@gem_eio@in-flight-contexts-1us:
    - shard-snb:          [PASS][7] -> [FAIL][8] ([fdo#111946])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-snb7/igt@gem_eio@in-flight-contexts-1us.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-snb6/igt@gem_eio@in-flight-contexts-1us.html

  * igt@gem_exec_create@madvise:
    - shard-tglb:         [PASS][9] -> [INCOMPLETE][10] ([fdo#111747])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb5/igt@gem_exec_create@madvise.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-tglb6/igt@gem_exec_create@madvise.html

  * igt@gem_exec_schedule@preempt-queue-bsd1:
    - shard-iclb:         [PASS][11] -> [SKIP][12] ([fdo#109276]) +16 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb2/igt@gem_exec_schedule@preempt-queue-bsd1.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-iclb8/igt@gem_exec_schedule@preempt-queue-bsd1.html

  * igt@gem_exec_schedule@preempt-queue-vebox:
    - shard-tglb:         [PASS][13] -> [INCOMPLETE][14] ([fdo#111677])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb1/igt@gem_exec_schedule@preempt-queue-vebox.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-tglb6/igt@gem_exec_schedule@preempt-queue-vebox.html

  * igt@gem_exec_schedule@wide-bsd:
    - shard-iclb:         [PASS][15] -> [SKIP][16] ([fdo#112146]) +3 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb3/igt@gem_exec_schedule@wide-bsd.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-iclb1/igt@gem_exec_schedule@wide-bsd.html

  * igt@gem_sync@basic-many-each:
    - shard-tglb:         [PASS][17] -> [INCOMPLETE][18] ([fdo#111998])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb8/igt@gem_sync@basic-many-each.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-tglb7/igt@gem_sync@basic-many-each.html

  * igt@gem_userptr_blits@sync-unmap-after-close:
    - shard-snb:          [PASS][19] -> [DMESG-WARN][20] ([fdo#111870]) +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-snb1/igt@gem_userptr_blits@sync-unmap-after-close.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-snb4/igt@gem_userptr_blits@sync-unmap-after-close.html

  * igt@gem_userptr_blits@sync-unmap-cycles:
    - shard-hsw:          [PASS][21] -> [DMESG-WARN][22] ([fdo#111870]) +1 similar issue
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-hsw4/igt@gem_userptr_blits@sync-unmap-cycles.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-hsw8/igt@gem_userptr_blits@sync-unmap-cycles.html

  * igt@gem_workarounds@suspend-resume-context:
    - shard-tglb:         [PASS][23] -> [INCOMPLETE][24] ([fdo#111832] / [fdo#111850]) +1 similar issue
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb9/igt@gem_workarounds@suspend-resume-context.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-tglb3/igt@gem_workarounds@suspend-resume-context.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-iclb:         [PASS][25] -> [FAIL][26] ([fdo#110548])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb1/igt@i915_pm_dc@dc6-dpms.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html

  * igt@i915_selftest@live_gt_timelines:
    - shard-tglb:         [PASS][27] -> [INCOMPLETE][28] ([fdo#111831])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb7/igt@i915_selftest@live_gt_timelines.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-tglb6/igt@i915_selftest@live_gt_timelines.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-tglb:         [PASS][29] -> [INCOMPLETE][30] ([fdo#111747] / [fdo#111832] / [fdo#111850])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb9/igt@kms_fbcon_fbt@fbc-suspend.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-tglb1/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-snb:          [PASS][31] -> [INCOMPLETE][32] ([fdo#105411])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-snb7/igt@kms_flip@flip-vs-suspend-interruptible.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-snb1/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
    - shard-iclb:         [PASS][33] -> [FAIL][34] ([fdo#103167]) +4 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-iclb:         [PASS][35] -> [DMESG-WARN][36] ([fdo#111764])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-tglb:         [PASS][37] -> [FAIL][38] ([fdo#103167]) +6 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-apl:          [PASS][39] -> [DMESG-WARN][40] ([fdo#108566]) +2 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_psr@psr2_primary_render:
    - shard-iclb:         [PASS][41] -> [SKIP][42] ([fdo#109441])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb2/igt@kms_psr@psr2_primary_render.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-iclb5/igt@kms_psr@psr2_primary_render.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@vcs1-dirty-create:
    - shard-iclb:         [SKIP][43] ([fdo#109276] / [fdo#112080]) -> [PASS][44] +2 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb6/igt@gem_ctx_isolation@vcs1-dirty-create.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-iclb4/igt@gem_ctx_isolation@vcs1-dirty-create.html

  * igt@gem_ctx_shared@exec-single-timeline-bsd:
    - shard-iclb:         [SKIP][45] ([fdo#110841]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-iclb6/igt@gem_ctx_shared@exec-single-timeline-bsd.html

  * igt@gem_ctx_switch@all-light:
    - shard-tglb:         [INCOMPLETE][47] ([fdo#111672]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb9/igt@gem_ctx_switch@all-light.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-tglb3/igt@gem_ctx_switch@all-light.html

  * igt@gem_exec_create@basic:
    - shard-tglb:         [INCOMPLETE][49] ([fdo#111736]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb6/igt@gem_exec_create@basic.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-tglb2/igt@gem_exec_create@basic.html

  * igt@gem_exec_schedule@preempt-queue-contexts-blt:
    - shard-tglb:         [INCOMPLETE][51] ([fdo#111606] / [fdo#111677]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb6/igt@gem_exec_schedule@preempt-queue-contexts-blt.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-tglb1/igt@gem_exec_schedule@preempt-queue-contexts-blt.html

  * igt@gem_exec_schedule@preemptive-hang-bsd:
    - shard-iclb:         [SKIP][53] ([fdo#112146]) -> [PASS][54] +3 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-iclb7/igt@gem_exec_schedule@preemptive-hang-bsd.html

  * igt@gem_exec_schedule@promotion-bsd1:
    - shard-iclb:         [SKIP][55] ([fdo#109276]) -> [PASS][56] +10 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb8/igt@gem_exec_schedule@promotion-bsd1.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-iclb2/igt@gem_exec_schedule@promotion-bsd1.html

  * igt@gem_exec_suspend@basic-s3:
    - shard-tglb:         [INCOMPLETE][57] ([fdo#111736] / [fdo#111850]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb3/igt@gem_exec_suspend@basic-s3.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-tglb4/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_render_copy@y-tiled-ccs-to-y-tiled:
    - shard-tglb:         [FAIL][59] ([fdo#111771]) -> [PASS][60] +1 similar issue
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb7/igt@gem_render_copy@y-tiled-ccs-to-y-tiled.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-tglb6/igt@gem_render_copy@y-tiled-ccs-to-y-tiled.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy:
    - shard-snb:          [DMESG-WARN][61] ([fdo#110789] / [fdo#111870]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-snb7/igt@gem_userptr_blits@map-fixed-invalidate-busy.html

  * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
    - shard-hsw:          [DMESG-WARN][63] ([fdo#111870]) -> [PASS][64] +1 similar issue
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-hsw7/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html

  * igt@gem_userptr_blits@sync-unmap:
    - shard-snb:          [DMESG-WARN][65] ([fdo#111870]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-snb2/igt@gem_userptr_blits@sync-unmap.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-snb5/igt@gem_userptr_blits@sync-unmap.html

  * igt@i915_selftest@live_hangcheck:
    - shard-snb:          [INCOMPLETE][67] ([fdo#105411]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-snb4/igt@i915_selftest@live_hangcheck.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-snb5/igt@i915_selftest@live_hangcheck.html

  * igt@i915_suspend@sysfs-reader:
    - shard-apl:          [DMESG-WARN][69] ([fdo#108566]) -> [PASS][70] +2 similar issues
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-apl6/igt@i915_suspend@sysfs-reader.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-apl7/igt@i915_suspend@sysfs-reader.html

  * igt@kms_atomic_transition@plane-all-modeset-transition:
    - shard-hsw:          [DMESG-WARN][71] ([fdo#102614]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-hsw5/igt@kms_atomic_transition@plane-all-modeset-transition.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-hsw2/igt@kms_atomic_transition@plane-all-modeset-transition.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-kbl:          [DMESG-WARN][73] ([fdo#108566]) -> [PASS][74] +8 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_draw_crc@fill-fb:
    - shard-hsw:          [DMESG-WARN][75] -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-hsw4/igt@kms_draw_crc@fill-fb.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-hsw5/igt@kms_draw_crc@fill-fb.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-hsw:          [INCOMPLETE][77] ([fdo#103540]) -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-hsw4/igt@kms_flip@flip-vs-suspend.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-hsw1/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt:
    - shard-tglb:         [FAIL][79] ([fdo#103167]) -> [PASS][80] +1 similar issue
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
    - shard-iclb:         [FAIL][81] ([fdo#103167]) -> [PASS][82] +4 similar issues
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         [SKIP][83] ([fdo#109441]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb7/igt@kms_psr@psr2_sprite_plane_move.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html

  * igt@kms_setmode@basic:
    - shard-kbl:          [FAIL][85] ([fdo#99912]) -> [PASS][86]
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-kbl4/igt@kms_setmode@basic.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-kbl7/igt@kms_setmode@basic.html

  * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
    - shard-tglb:         [INCOMPLETE][87] ([fdo#111832] / [fdo#111850]) -> [PASS][88] +1 similar issue
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb8/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-tglb7/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html

  * igt@perf_pmu@busy-accuracy-2-vcs1:
    - shard-iclb:         [SKIP][89] ([fdo#112080]) -> [PASS][90] +6 similar issues
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb3/igt@perf_pmu@busy-accuracy-2-vcs1.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-iclb4/igt@perf_pmu@busy-accuracy-2-vcs1.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs1-nonpriv:
    - shard-iclb:         [SKIP][91] ([fdo#109276] / [fdo#112080]) -> [FAIL][92] ([fdo#111329])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb5/igt@gem_ctx_isolation@vcs1-nonpriv.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html

  * igt@gem_ctx_switch@vcs2-heavy-queue:
    - shard-tglb:         [TIMEOUT][93] ([fdo#112126]) -> [SKIP][94] ([fdo#112080])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb2/igt@gem_ctx_switch@vcs2-heavy-queue.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-tglb3/igt@gem_ctx_switch@vcs2-heavy-queue.html

  * igt@gem_exec_schedule@deep-blt:
    - shard-tglb:         [FAIL][95] ([fdo#111646]) -> [INCOMPLETE][96] ([fdo#111671])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb8/igt@gem_exec_schedule@deep-blt.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-tglb5/igt@gem_exec_schedule@deep-blt.html

  * igt@gem_mocs_settings@mocs-reset-bsd2:
    - shard-iclb:         [FAIL][97] ([fdo#111330]) -> [SKIP][98] ([fdo#109276]) +1 similar issue
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb2/igt@gem_mocs_settings@mocs-reset-bsd2.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-iclb3/igt@gem_mocs_settings@mocs-reset-bsd2.html

  * igt@gem_workarounds@suspend-resume:
    - shard-kbl:          [DMESG-WARN][99] ([fdo#103313]) -> [DMESG-WARN][100] ([fdo#108566])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-kbl4/igt@gem_workarounds@suspend-resume.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-kbl7/igt@gem_workarounds@suspend-resume.html

  * igt@kms_psr@psr2_suspend:
    - shard-iclb:         [SKIP][101] ([fdo#109441]) -> [DMESG-WARN][102] ([fdo#107724])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb5/igt@kms_psr@psr2_suspend.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/shard-iclb2/igt@kms_psr@psr2_suspend.html

  
  [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103313]: https://bugs.freedesktop.org/show_bug.cgi?id=103313
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#108566]: https://bugs.f

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3664/index.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] ✗ Fi.CI.IGT: failure for series starting with [v5,1/3] lib/rendercopy: Add AUX page table support (rev5)

[Patchwork]

== Series Details ==

Series: series starting with [v5,1/3] lib/rendercopy: Add AUX page table support (rev5)
URL   : https://patchwork.freedesktop.org/series/69012/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7298_full -> IGTPW_3671_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_3671_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_3671_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_3671_full:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_pm_dc@dc6-dpms:
    - shard-kbl:          NOTRUN -> [FAIL][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-kbl2/igt@i915_pm_dc@dc6-dpms.html
    - shard-tglb:         NOTRUN -> [FAIL][2]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-tglb8/igt@i915_pm_dc@dc6-dpms.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@i915_pm_dc@dc3co-vpb-simulation}:
    - shard-tglb:         [PASS][3] -> [SKIP][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-tglb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-tglb4/igt@i915_pm_dc@dc3co-vpb-simulation.html

  
New tests
---------

  New tests have been introduced between CI_DRM_7298_full and IGTPW_3671_full:

### New IGT tests (4) ###

  * igt@gem_render_copy@y-tiled-ccs-to-y-tiled-ccs:
    - Statuses : 5 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.24] s

  * igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs:
    - Statuses : 5 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.23] s

  * igt@gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs:
    - Statuses : 5 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.25] s

  * igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled-ccs:
    - Statuses : 4 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.35] s

  

Known issues
------------

  Here are the changes found in IGTPW_3671_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_busy@busy-vcs1:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#112080]) +7 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-iclb2/igt@gem_busy@busy-vcs1.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-iclb8/igt@gem_busy@busy-vcs1.html

  * igt@gem_ctx_persistence@vcs1-queued:
    - shard-iclb:         [PASS][7] -> [SKIP][8] ([fdo#109276] / [fdo#112080]) +2 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-iclb4/igt@gem_ctx_persistence@vcs1-queued.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-iclb8/igt@gem_ctx_persistence@vcs1-queued.html

  * igt@gem_exec_await@wide-contexts:
    - shard-tglb:         [PASS][9] -> [INCOMPLETE][10] ([fdo#111736])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-tglb1/igt@gem_exec_await@wide-contexts.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-tglb6/igt@gem_exec_await@wide-contexts.html

  * igt@gem_exec_schedule@preempt-queue-bsd:
    - shard-iclb:         [PASS][11] -> [SKIP][12] ([fdo#112146]) +3 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-iclb8/igt@gem_exec_schedule@preempt-queue-bsd.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd.html

  * igt@gem_exec_schedule@preempt-queue-chain-bsd2:
    - shard-tglb:         [PASS][13] -> [INCOMPLETE][14] ([fdo#111677])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-tglb8/igt@gem_exec_schedule@preempt-queue-chain-bsd2.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-tglb6/igt@gem_exec_schedule@preempt-queue-chain-bsd2.html

  * igt@gem_exec_suspend@basic-s0:
    - shard-tglb:         [PASS][15] -> [INCOMPLETE][16] ([fdo#111832])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-tglb5/igt@gem_exec_suspend@basic-s0.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-tglb4/igt@gem_exec_suspend@basic-s0.html

  * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
    - shard-hsw:          [PASS][17] -> [DMESG-WARN][18] ([fdo#111870])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-hsw2/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-hsw5/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html

  * igt@gem_userptr_blits@sync-unmap-cycles:
    - shard-snb:          [PASS][19] -> [DMESG-WARN][20] ([fdo#111870]) +2 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-snb2/igt@gem_userptr_blits@sync-unmap-cycles.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-snb1/igt@gem_userptr_blits@sync-unmap-cycles.html

  * igt@i915_pm_rc6_residency@rc6-accuracy:
    - shard-kbl:          [PASS][21] -> [SKIP][22] ([fdo#109271])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-kbl6/igt@i915_pm_rc6_residency@rc6-accuracy.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-kbl7/igt@i915_pm_rc6_residency@rc6-accuracy.html

  * igt@i915_selftest@live_hangcheck:
    - shard-hsw:          [PASS][23] -> [DMESG-FAIL][24] ([fdo#111991])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-hsw2/igt@i915_selftest@live_hangcheck.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-hsw1/igt@i915_selftest@live_hangcheck.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-apl:          [PASS][25] -> [DMESG-WARN][26] ([fdo#108566])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-apl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-apl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
    - shard-iclb:         [PASS][27] -> [FAIL][28] ([fdo#103167]) +7 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite:
    - shard-tglb:         [PASS][29] -> [FAIL][30] ([fdo#103167]) +3 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
    - shard-kbl:          [PASS][31] -> [DMESG-WARN][32] ([fdo#108566]) +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
    - shard-iclb:         [PASS][33] -> [INCOMPLETE][34] ([fdo#107713] / [fdo#110042])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-iclb4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-iclb3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html

  * igt@kms_plane_lowres@pipe-a-tiling-x:
    - shard-iclb:         [PASS][35] -> [FAIL][36] ([fdo#103166])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-iclb3/igt@kms_plane_lowres@pipe-a-tiling-x.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-iclb7/igt@kms_plane_lowres@pipe-a-tiling-x.html

  * igt@kms_psr@psr2_suspend:
    - shard-iclb:         [PASS][37] -> [SKIP][38] ([fdo#109441]) +1 similar issue
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-iclb2/igt@kms_psr@psr2_suspend.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-iclb7/igt@kms_psr@psr2_suspend.html

  * igt@kms_vblank@pipe-c-wait-forked-busy-hang:
    - shard-hsw:          [PASS][39] -> [INCOMPLETE][40] ([fdo#103540])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-hsw6/igt@kms_vblank@pipe-c-wait-forked-busy-hang.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-hsw5/igt@kms_vblank@pipe-c-wait-forked-busy-hang.html

  * igt@prime_vgem@fence-wait-bsd2:
    - shard-iclb:         [PASS][41] -> [SKIP][42] ([fdo#109276]) +17 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-iclb4/igt@prime_vgem@fence-wait-bsd2.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-iclb7/igt@prime_vgem@fence-wait-bsd2.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@vcs0-s3:
    - shard-tglb:         [INCOMPLETE][43] ([fdo#111832]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-tglb5/igt@gem_ctx_isolation@vcs0-s3.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-tglb6/igt@gem_ctx_isolation@vcs0-s3.html
    - shard-apl:          [DMESG-WARN][45] ([fdo#108566]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-apl1/igt@gem_ctx_isolation@vcs0-s3.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-apl2/igt@gem_ctx_isolation@vcs0-s3.html

  * igt@gem_ctx_persistence@vcs1-mixed-process:
    - shard-iclb:         [SKIP][47] ([fdo#109276] / [fdo#112080]) -> [PASS][48] +2 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-iclb5/igt@gem_ctx_persistence@vcs1-mixed-process.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-iclb4/igt@gem_ctx_persistence@vcs1-mixed-process.html

  * igt@gem_ctx_switch@legacy-bsd2-heavy-queue:
    - shard-kbl:          [INCOMPLETE][49] ([fdo#103665]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-kbl4/igt@gem_ctx_switch@legacy-bsd2-heavy-queue.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-kbl6/igt@gem_ctx_switch@legacy-bsd2-heavy-queue.html

  * igt@gem_ctx_switch@vcs1-heavy:
    - shard-iclb:         [SKIP][51] ([fdo#112080]) -> [PASS][52] +9 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-iclb8/igt@gem_ctx_switch@vcs1-heavy.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-iclb2/igt@gem_ctx_switch@vcs1-heavy.html

  * igt@gem_eio@in-flight-contexts-1us:
    - shard-snb:          [FAIL][53] ([fdo#111946]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-snb4/igt@gem_eio@in-flight-contexts-1us.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-snb2/igt@gem_eio@in-flight-contexts-1us.html

  * igt@gem_eio@reset-stress:
    - shard-snb:          [FAIL][55] ([fdo#109661]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-snb4/igt@gem_eio@reset-stress.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-snb7/igt@gem_eio@reset-stress.html

  * igt@gem_exec_schedule@preempt-queue-bsd2:
    - shard-tglb:         [INCOMPLETE][57] ([fdo#111606] / [fdo#111677]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-tglb6/igt@gem_exec_schedule@preempt-queue-bsd2.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-tglb8/igt@gem_exec_schedule@preempt-queue-bsd2.html

  * igt@gem_exec_schedule@preemptive-hang-bsd:
    - shard-iclb:         [SKIP][59] ([fdo#112146]) -> [PASS][60] +4 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-iclb1/igt@gem_exec_schedule@preemptive-hang-bsd.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-iclb6/igt@gem_exec_schedule@preemptive-hang-bsd.html

  * igt@gem_persistent_relocs@forked-interruptible-thrashing:
    - shard-hsw:          [FAIL][61] ([fdo#112037]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-hsw6/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-hsw6/igt@gem_persistent_relocs@forked-interruptible-thrashing.html

  * igt@gem_render_copy@yf-tiled-ccs-to-x-tiled:
    - shard-tglb:         [FAIL][63] ([fdo#111771]) -> [PASS][64] +3 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-tglb4/igt@gem_render_copy@yf-tiled-ccs-to-x-tiled.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-tglb3/igt@gem_render_copy@yf-tiled-ccs-to-x-tiled.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-snb:          [DMESG-WARN][65] ([fdo#111870]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-snb2/igt@gem_userptr_blits@dmabuf-unsync.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-snb5/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-tglb:         [INCOMPLETE][67] ([fdo#111832] / [fdo#111850]) -> [PASS][68] +1 similar issue
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-tglb7/igt@i915_suspend@fence-restore-tiled2untiled.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-tglb5/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-kbl:          [DMESG-WARN][69] ([fdo#108566]) -> [PASS][70] +4 similar issues
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
    - shard-hsw:          [FAIL][71] ([fdo#105767]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-hsw5/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html

  * igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack:
    - shard-tglb:         [FAIL][73] ([fdo#103167]) -> [PASS][74] +1 similar issue
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt:
    - shard-iclb:         [FAIL][75] ([fdo#103167]) -> [PASS][76] +4 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_psr@psr2_sprite_blt:
    - shard-iclb:         [SKIP][77] ([fdo#109441]) -> [PASS][78] +1 similar issue
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-iclb4/igt@kms_psr@psr2_sprite_blt.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html

  * igt@prime_busy@hang-bsd2:
    - shard-iclb:         [SKIP][79] ([fdo#109276]) -> [PASS][80] +14 similar issues
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-iclb8/igt@prime_busy@hang-bsd2.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-iclb2/igt@prime_busy@hang-bsd2.html

  
#### Warnings ####

  * igt@gem_eio@kms:
    - shard-snb:          [DMESG-WARN][81] ([fdo# 112000 ] / [fdo#111781]) -> [INCOMPLETE][82] ([fdo#105411])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-snb5/igt@gem_eio@kms.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-snb1/igt@gem_eio@kms.html

  * igt@gem_mocs_settings@mocs-isolation-bsd2:
    - shard-iclb:         [FAIL][83] ([fdo#111330]) -> [SKIP][84] ([fdo#109276])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-iclb1/igt@gem_mocs_settings@mocs-isolation-bsd2.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-iclb6/igt@gem_mocs_settings@mocs-isolation-bsd2.html

  * igt@gem_mocs_settings@mocs-settings-bsd2:
    - shard-iclb:         [SKIP][85] ([fdo#109276]) -> [FAIL][86] ([fdo#111330])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-iclb6/igt@gem_mocs_settings@mocs-settings-bsd2.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-iclb4/igt@gem_mocs_settings@mocs-settings-bsd2.html

  * igt@gem_userptr_blits@sync-unmap:
    - shard-hsw:          [DMESG-WARN][87] ([fdo#110789] / [fdo#111870]) -> [DMESG-WARN][88] ([fdo#111870])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-hsw5/igt@gem_userptr_blits@sync-unmap.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-hsw5/igt@gem_userptr_blits@sync-unmap.html

  * igt@kms_flip@2x-flip-vs-wf_vblank:
    - shard-tglb:         [SKIP][89] ([fdo#111825]) -> [TIMEOUT][90] ([fdo#112168])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-tglb1/igt@kms_flip@2x-flip-vs-wf_vblank.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-tglb7/igt@kms_flip@2x-flip-vs-wf_vblank.html

  * igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
    - shard-tglb:         [INCOMPLETE][91] ([fdo#111850]) -> [INCOMPLETE][92] ([fdo#111832] / [fdo#111850])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7298/shard-tglb3/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/shard-tglb5/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo# 112000 ]: https://bugs.freedesktop.org/show_bug.cgi?id= 112000 
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
  [fdo#110042]: https://bugs.freedesktop.org/show_bug.cgi?id=110042
  [fdo#110789]: https://bugs.freedesktop.org/show_bug.cgi?id=110789
  [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
  [fdo#111606]: https://bugs.freedesktop.org/show_bug.cgi?id=111606
  [fdo#111677]: https://bugs.freedesktop.org/show_bug.cgi?id=111677
  [fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736
  [fdo#111771]: https://bugs.freedesktop.org/show_bug.cgi?id=111771
  [fdo#111781]: https://bugs.freedesktop.org/show_bug.cgi?id=111781
  [fdo#111825]: https://bugs.freede

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3671/index.html
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Re: [igt-dev] [PATCH v2 3/3] tests/gem_render_copy: Add compressed src to compressed dst subtests

[Brian Welty]

On 11/5/2019 11:34 AM, Imre Deak wrote:
> Add new subtests that blit from a compressed source to a compressed
> destination buffer.
> 
> v2:
> - Use the correct buffer when dumping the png for the compressed buf.
> 
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Brian Welty <brian.welty@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---


Perhaps add a:
References: https://bugs.freedesktop.org/show_bug.cgi?id=111771
and close that out?

I had been looking at gem_render_copy as part of above and your changes
look fine to me.
So for patches 2 and 3 you can have my:
Reviewed-by: Brian Welty <brian.welty@intel.com>

Up to you if you need additional reviewed-by or not for this.

-Brian


>  tests/i915/gem_render_copy.c | 126 ++++++++++++++++++++++++++---------
>  1 file changed, 93 insertions(+), 33 deletions(-)
> 
> diff --git a/tests/i915/gem_render_copy.c b/tests/i915/gem_render_copy.c
> index fd139e91..383e86bc 100644
> --- a/tests/i915/gem_render_copy.c
> +++ b/tests/i915/gem_render_copy.c
> @@ -572,9 +572,13 @@ static void scratch_buf_aux_check(data_t *data,
>  		     "Aux surface indicates that nothing was compressed\n");
>  }
>  
> -static void test(data_t *data, uint32_t tiling, uint64_t ccs_modifier)
> +#define DST_COMPRESSED	1
> +#define SRC_COMPRESSED	2
> +
> +static void test(data_t *data, uint32_t dst_tiling, uint32_t src_tiling,
> +		 int flags)
>  {
> -	struct igt_buf dst, ccs, ref;
> +	struct igt_buf dst, src_ccs, dst_ccs, ref;
>  	struct {
>  		struct igt_buf buf;
>  		const char *filename;
> @@ -602,22 +606,34 @@ static void test(data_t *data, uint32_t tiling, uint64_t ccs_modifier)
>  			.x = 1, .y = 1,
>  		},
>  	};
> -
>  	int opt_dump_aub = igt_aub_dump_enabled();
>  	int num_src = ARRAY_SIZE(src);
> +	bool src_compressed = flags & SRC_COMPRESSED;
> +	bool dst_compressed = flags & DST_COMPRESSED;
> +
> +	/*
> +	 * The tiling for uncompressed source buffers is determined by the
> +	 * tiling of the src[] buffers above.
> +	 */
> +	igt_assert(!src_tiling || src_compressed);
>  
>  	/* no Yf before gen9 */
>  	if (intel_gen(data->devid) < 9)
>  		num_src--;
>  
> -	if (tiling == I915_TILING_Yf || ccs_modifier)
> +	if (dst_tiling == I915_TILING_Yf || src_tiling == I915_TILING_Yf ||
> +	    src_compressed || dst_compressed)
>  		igt_require(intel_gen(data->devid) >= 9);
>  
>  	for (int i = 0; i < num_src; i++)
>  		scratch_buf_init(data, &src[i].buf, WIDTH, HEIGHT, src[i].tiling, false);
> -	scratch_buf_init(data, &dst, WIDTH, HEIGHT, tiling, false);
> -	if (ccs_modifier)
> -		scratch_buf_init(data, &ccs, WIDTH, HEIGHT, ccs_modifier, true);
> +	scratch_buf_init(data, &dst, WIDTH, HEIGHT, dst_tiling, false);
> +	if (src_compressed)
> +		scratch_buf_init(data, &src_ccs, WIDTH, HEIGHT,
> +				 src_tiling, true);
> +	if (dst_compressed)
> +		scratch_buf_init(data, &dst_ccs, WIDTH, HEIGHT,
> +				 dst_tiling, true);
>  	scratch_buf_init(data, &ref, WIDTH, HEIGHT, I915_TILING_NONE, false);
>  
>  	for (int i = 0; i < num_src; i++)
> @@ -657,26 +673,45 @@ static void test(data_t *data, uint32_t tiling, uint64_t ccs_modifier)
>  	 *	 |dst|src|
>  	 *	  -------
>  	 */
> -	if (ccs_modifier)
> +	if (src_compressed)
>  		data->render_copy(data->batch, NULL,
>  				  &dst, 0, 0, WIDTH, HEIGHT,
> -				  &ccs, 0, 0);
> +				  &src_ccs, 0, 0);
>  
>  	for (int i = 0; i < num_src; i++)
>  		data->render_copy(data->batch, NULL,
> -				  &src[i].buf, WIDTH/4, HEIGHT/4, WIDTH/2-2, HEIGHT/2-2,
> -				  ccs_modifier ? &ccs : &dst, src[i].x, src[i].y);
> +				  &src[i].buf,
> +				  WIDTH/4, HEIGHT/4, WIDTH/2-2, HEIGHT/2-2,
> +				  src_compressed ? &src_ccs : &dst,
> +				  src[i].x, src[i].y);
> +
> +	if (src_compressed || dst_compressed)
> +		data->render_copy(data->batch, NULL,
> +				  src_compressed ? &src_ccs : &dst,
> +				  0, 0, WIDTH, HEIGHT,
> +				  dst_compressed ? &dst_ccs : &dst,
> +				  0, 0);
>  
> -	if (ccs_modifier)
> +	if (dst_compressed)
>  		data->render_copy(data->batch, NULL,
> -				  &ccs, 0, 0, WIDTH, HEIGHT,
> -				  &dst, 0, 0);
> +				  &dst_ccs,
> +				  0, 0, WIDTH, HEIGHT,
> +				  &dst,
> +				  0, 0);
>  
>  	if (opt_dump_png){
>  		scratch_buf_write_to_png(data, &dst, "result.png");
> -		if (ccs_modifier) {
> -			scratch_buf_write_to_png(data, &ccs, "compressed.png");
> -			scratch_buf_aux_write_to_png(data, &ccs, "compressed-aux.png");
> +		if (src_compressed) {
> +			scratch_buf_write_to_png(data, &src_ccs,
> +						 "compressed-src.png");
> +			scratch_buf_aux_write_to_png(data, &src_ccs,
> +						     "compressed-src-aux.png");
> +		}
> +		if (dst_compressed) {
> +			scratch_buf_write_to_png(data, &dst_ccs,
> +						 "compressed-dst.png");
> +			scratch_buf_aux_write_to_png(data, &dst_ccs,
> +						     "compressed-dst-aux.png");
>  		}
>  	}
>  
> @@ -694,12 +729,16 @@ static void test(data_t *data, uint32_t tiling, uint64_t ccs_modifier)
>  		scratch_buf_check(data, &dst, &ref, WIDTH - 10, HEIGHT - 10);
>  	}
>  
> -	if (ccs_modifier)
> -		scratch_buf_aux_check(data, &ccs);
> +	if (src_compressed)
> +		scratch_buf_aux_check(data, &src_ccs);
> +	if (dst_compressed)
> +		scratch_buf_aux_check(data, &dst_ccs);
>  
>  	scratch_buf_fini(&ref);
> -	if (ccs_modifier)
> -		scratch_buf_fini(&ccs);
> +	if (dst_compressed)
> +		scratch_buf_fini(&dst_ccs);
> +	if (src_compressed)
> +		scratch_buf_fini(&src_ccs);
>  	scratch_buf_fini(&dst);
>  	for (int i = 0; i < num_src; i++)
>  		scratch_buf_fini(&src[i].buf);
> @@ -749,31 +788,52 @@ igt_main_args("da", NULL, help_str, opt_handler, NULL)
>  	}
>  
>  	igt_subtest("linear")
> -		test(&data, I915_TILING_NONE, 0);
> +		test(&data, I915_TILING_NONE, 0, 0);
>  	igt_subtest("x-tiled")
> -		test(&data, I915_TILING_X, 0);
> +		test(&data, I915_TILING_X, 0, 0);
>  	igt_subtest("y-tiled")
> -		test(&data, I915_TILING_Y, 0);
> +		test(&data, I915_TILING_Y, 0, 0);
>  	igt_subtest("yf-tiled")
> -		test(&data, I915_TILING_Yf, 0);
> +		test(&data, I915_TILING_Yf, 0, 0);
>  
>  	igt_subtest("y-tiled-ccs-to-linear")
> -		test(&data, I915_TILING_NONE, I915_TILING_Y);
> +		test(&data, I915_TILING_NONE, I915_TILING_Y,
> +		     SRC_COMPRESSED);
>  	igt_subtest("y-tiled-ccs-to-x-tiled")
> -		test(&data, I915_TILING_X, I915_TILING_Y);
> +		test(&data, I915_TILING_X, I915_TILING_Y,
> +		     SRC_COMPRESSED);
>  	igt_subtest("y-tiled-ccs-to-y-tiled")
> -		test(&data, I915_TILING_Y, I915_TILING_Y);
> +		test(&data, I915_TILING_Y, I915_TILING_Y,
> +		     SRC_COMPRESSED);
>  	igt_subtest("y-tiled-ccs-to-yf-tiled")
> -		test(&data, I915_TILING_Yf, I915_TILING_Y);
> +		test(&data, I915_TILING_Yf, I915_TILING_Y,
> +		     SRC_COMPRESSED);
>  
>  	igt_subtest("yf-tiled-ccs-to-linear")
> -		test(&data, I915_TILING_NONE, I915_TILING_Yf);
> +		test(&data, I915_TILING_NONE, I915_TILING_Yf,
> +		     SRC_COMPRESSED);
>  	igt_subtest("yf-tiled-ccs-to-x-tiled")
> -		test(&data, I915_TILING_X, I915_TILING_Yf);
> +		test(&data, I915_TILING_X, I915_TILING_Yf,
> +		     SRC_COMPRESSED);
>  	igt_subtest("yf-tiled-ccs-to-y-tiled")
> -		test(&data, I915_TILING_Y, I915_TILING_Yf);
> +		test(&data, I915_TILING_Y, I915_TILING_Yf,
> +		     SRC_COMPRESSED);
>  	igt_subtest("yf-tiled-ccs-to-yf-tiled")
> -		test(&data, I915_TILING_Yf, I915_TILING_Yf);
> +		test(&data, I915_TILING_Yf, I915_TILING_Yf,
> +		     SRC_COMPRESSED);
> +
> +	igt_subtest("y-tiled-ccs-to-y-tiled-ccs")
> +		test(&data, I915_TILING_Y, I915_TILING_Y,
> +		     SRC_COMPRESSED | DST_COMPRESSED);
> +	igt_subtest("yf-tiled-ccs-to-yf-tiled-ccs")
> +		test(&data, I915_TILING_Yf, I915_TILING_Yf,
> +		     SRC_COMPRESSED | DST_COMPRESSED);
> +	igt_subtest("y-tiled-ccs-to-yf-tiled-ccs")
> +		test(&data, I915_TILING_Yf, I915_TILING_Y,
> +		     SRC_COMPRESSED | DST_COMPRESSED);
> +	igt_subtest("yf-tiled-ccs-to-y-tiled-ccs")
> +		test(&data, I915_TILING_Y, I915_TILING_Yf,
> +		     SRC_COMPRESSED | DST_COMPRESSED);
>  
>  	igt_fixture {
>  		igt_stop_hang_detector();
> 
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[igt-dev] [PATCH v4 3/3] tests/gem_render_copy: Add compressed src to compressed dst subtests

[Imre Deak]

Add new subtests that blit from a compressed source to a compressed
destination buffer.

While at it also add descriptions for the subtests.

v2:
- Use the correct buffer when dumping the png for the compressed buf.
v3:
- Add subtest descriptions.
v4:
- Add Bugzilla link. (Brian)
- Add back linear subtest removed by mistake.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111771
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 tests/i915/gem_render_copy.c | 165 +++++++++++++++++++++++++----------
 1 file changed, 118 insertions(+), 47 deletions(-)

diff --git a/tests/i915/gem_render_copy.c b/tests/i915/gem_render_copy.c
index fd139e91..67be079c 100644
--- a/tests/i915/gem_render_copy.c
+++ b/tests/i915/gem_render_copy.c
@@ -572,9 +572,13 @@ static void scratch_buf_aux_check(data_t *data,
 		     "Aux surface indicates that nothing was compressed\n");
 }
 
-static void test(data_t *data, uint32_t tiling, uint64_t ccs_modifier)
+#define SRC_COMPRESSED	1
+#define DST_COMPRESSED	2
+
+static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling,
+		 int flags)
 {
-	struct igt_buf dst, ccs, ref;
+	struct igt_buf dst, src_ccs, dst_ccs, ref;
 	struct {
 		struct igt_buf buf;
 		const char *filename;
@@ -602,22 +606,34 @@ static void test(data_t *data, uint32_t tiling, uint64_t ccs_modifier)
 			.x = 1, .y = 1,
 		},
 	};
-
 	int opt_dump_aub = igt_aub_dump_enabled();
 	int num_src = ARRAY_SIZE(src);
+	bool src_compressed = flags & SRC_COMPRESSED;
+	bool dst_compressed = flags & DST_COMPRESSED;
+
+	/*
+	 * The tiling for uncompressed source buffers is determined by the
+	 * tiling of the src[] buffers above.
+	 */
+	igt_assert(!src_tiling || src_compressed);
 
 	/* no Yf before gen9 */
 	if (intel_gen(data->devid) < 9)
 		num_src--;
 
-	if (tiling == I915_TILING_Yf || ccs_modifier)
+	if (src_tiling == I915_TILING_Yf || dst_tiling == I915_TILING_Yf ||
+	    src_compressed || dst_compressed)
 		igt_require(intel_gen(data->devid) >= 9);
 
 	for (int i = 0; i < num_src; i++)
 		scratch_buf_init(data, &src[i].buf, WIDTH, HEIGHT, src[i].tiling, false);
-	scratch_buf_init(data, &dst, WIDTH, HEIGHT, tiling, false);
-	if (ccs_modifier)
-		scratch_buf_init(data, &ccs, WIDTH, HEIGHT, ccs_modifier, true);
+	scratch_buf_init(data, &dst, WIDTH, HEIGHT, dst_tiling, false);
+	if (src_compressed)
+		scratch_buf_init(data, &src_ccs, WIDTH, HEIGHT,
+				 src_tiling, true);
+	if (dst_compressed)
+		scratch_buf_init(data, &dst_ccs, WIDTH, HEIGHT,
+				 dst_tiling, true);
 	scratch_buf_init(data, &ref, WIDTH, HEIGHT, I915_TILING_NONE, false);
 
 	for (int i = 0; i < num_src; i++)
@@ -657,26 +673,45 @@ static void test(data_t *data, uint32_t tiling, uint64_t ccs_modifier)
 	 *	 |dst|src|
 	 *	  -------
 	 */
-	if (ccs_modifier)
+	if (src_compressed)
 		data->render_copy(data->batch, NULL,
 				  &dst, 0, 0, WIDTH, HEIGHT,
-				  &ccs, 0, 0);
+				  &src_ccs, 0, 0);
 
 	for (int i = 0; i < num_src; i++)
 		data->render_copy(data->batch, NULL,
-				  &src[i].buf, WIDTH/4, HEIGHT/4, WIDTH/2-2, HEIGHT/2-2,
-				  ccs_modifier ? &ccs : &dst, src[i].x, src[i].y);
+				  &src[i].buf,
+				  WIDTH/4, HEIGHT/4, WIDTH/2-2, HEIGHT/2-2,
+				  src_compressed ? &src_ccs : &dst,
+				  src[i].x, src[i].y);
 
-	if (ccs_modifier)
+	if (src_compressed || dst_compressed)
 		data->render_copy(data->batch, NULL,
-				  &ccs, 0, 0, WIDTH, HEIGHT,
-				  &dst, 0, 0);
+				  src_compressed ? &src_ccs : &dst,
+				  0, 0, WIDTH, HEIGHT,
+				  dst_compressed ? &dst_ccs : &dst,
+				  0, 0);
+
+	if (dst_compressed)
+		data->render_copy(data->batch, NULL,
+				  &dst_ccs,
+				  0, 0, WIDTH, HEIGHT,
+				  &dst,
+				  0, 0);
 
 	if (opt_dump_png){
 		scratch_buf_write_to_png(data, &dst, "result.png");
-		if (ccs_modifier) {
-			scratch_buf_write_to_png(data, &ccs, "compressed.png");
-			scratch_buf_aux_write_to_png(data, &ccs, "compressed-aux.png");
+		if (src_compressed) {
+			scratch_buf_write_to_png(data, &src_ccs,
+						 "compressed-src.png");
+			scratch_buf_aux_write_to_png(data, &src_ccs,
+						     "compressed-src-aux.png");
+		}
+		if (dst_compressed) {
+			scratch_buf_write_to_png(data, &dst_ccs,
+						 "compressed-dst.png");
+			scratch_buf_aux_write_to_png(data, &dst_ccs,
+						     "compressed-dst-aux.png");
 		}
 	}
 
@@ -694,12 +729,16 @@ static void test(data_t *data, uint32_t tiling, uint64_t ccs_modifier)
 		scratch_buf_check(data, &dst, &ref, WIDTH - 10, HEIGHT - 10);
 	}
 
-	if (ccs_modifier)
-		scratch_buf_aux_check(data, &ccs);
+	if (src_compressed)
+		scratch_buf_aux_check(data, &src_ccs);
+	if (dst_compressed)
+		scratch_buf_aux_check(data, &dst_ccs);
 
 	scratch_buf_fini(&ref);
-	if (ccs_modifier)
-		scratch_buf_fini(&ccs);
+	if (dst_compressed)
+		scratch_buf_fini(&dst_ccs);
+	if (src_compressed)
+		scratch_buf_fini(&src_ccs);
 	scratch_buf_fini(&dst);
 	for (int i = 0; i < num_src; i++)
 		scratch_buf_fini(&src[i].buf);
@@ -726,8 +765,50 @@ const char *help_str =
 	"  -a\tCheck all pixels\n"
 	;
 
+static const char *buf_mode_str(uint32_t tiling, bool compressed)
+{
+	switch (tiling) {
+	default:
+	case I915_TILING_NONE:
+		return "linear";
+	case I915_TILING_X:
+		return "x-tiled";
+	case I915_TILING_Y:
+		return compressed ? "y-tiled-ccs" : "y-tiled";
+	case I915_TILING_Yf:
+		return compressed ? "yf-tiled-ccs" : "yf-tiled";
+	}
+}
+
 igt_main_args("da", NULL, help_str, opt_handler, NULL)
 {
+	static const struct test_desc {
+		int src_tiling;
+		int dst_tiling;
+		int flags;
+	} tests[] = {
+		{ I915_TILING_NONE, I915_TILING_NONE, 0 },
+		{ I915_TILING_NONE, I915_TILING_X,    0 },
+		{ I915_TILING_NONE, I915_TILING_Y,    0 },
+		{ I915_TILING_NONE, I915_TILING_Yf,   0 },
+
+		{ I915_TILING_Y,    I915_TILING_NONE, SRC_COMPRESSED },
+		{ I915_TILING_Y,    I915_TILING_X,    SRC_COMPRESSED },
+		{ I915_TILING_Y,    I915_TILING_Y,    SRC_COMPRESSED },
+		{ I915_TILING_Y,    I915_TILING_Yf,   SRC_COMPRESSED },
+
+		{ I915_TILING_Yf,   I915_TILING_NONE, SRC_COMPRESSED },
+		{ I915_TILING_Yf,   I915_TILING_X,    SRC_COMPRESSED },
+		{ I915_TILING_Yf,   I915_TILING_Y,    SRC_COMPRESSED },
+		{ I915_TILING_Yf,   I915_TILING_Yf,   SRC_COMPRESSED },
+
+		{ I915_TILING_Y,    I915_TILING_Y,    SRC_COMPRESSED | DST_COMPRESSED },
+		{ I915_TILING_Yf,   I915_TILING_Yf,   SRC_COMPRESSED | DST_COMPRESSED },
+		{ I915_TILING_Y,    I915_TILING_Yf,   SRC_COMPRESSED | DST_COMPRESSED },
+		{ I915_TILING_Yf,   I915_TILING_Y,    SRC_COMPRESSED | DST_COMPRESSED },
+	};
+	int i;
+
 	data_t data = {0, };
 
 	igt_fixture {
@@ -748,32 +829,22 @@ igt_main_args("da", NULL, help_str, opt_handler, NULL)
 		igt_fork_hang_detector(data.drm_fd);
 	}
 
-	igt_subtest("linear")
-		test(&data, I915_TILING_NONE, 0);
-	igt_subtest("x-tiled")
-		test(&data, I915_TILING_X, 0);
-	igt_subtest("y-tiled")
-		test(&data, I915_TILING_Y, 0);
-	igt_subtest("yf-tiled")
-		test(&data, I915_TILING_Yf, 0);
-
-	igt_subtest("y-tiled-ccs-to-linear")
-		test(&data, I915_TILING_NONE, I915_TILING_Y);
-	igt_subtest("y-tiled-ccs-to-x-tiled")
-		test(&data, I915_TILING_X, I915_TILING_Y);
-	igt_subtest("y-tiled-ccs-to-y-tiled")
-		test(&data, I915_TILING_Y, I915_TILING_Y);
-	igt_subtest("y-tiled-ccs-to-yf-tiled")
-		test(&data, I915_TILING_Yf, I915_TILING_Y);
-
-	igt_subtest("yf-tiled-ccs-to-linear")
-		test(&data, I915_TILING_NONE, I915_TILING_Yf);
-	igt_subtest("yf-tiled-ccs-to-x-tiled")
-		test(&data, I915_TILING_X, I915_TILING_Yf);
-	igt_subtest("yf-tiled-ccs-to-y-tiled")
-		test(&data, I915_TILING_Y, I915_TILING_Yf);
-	igt_subtest("yf-tiled-ccs-to-yf-tiled")
-		test(&data, I915_TILING_Yf, I915_TILING_Yf);
+	for (i = 0; i < ARRAY_SIZE(tests); i++) {
+		const struct test_desc *t = &tests[i];
+		const char *src_mode = buf_mode_str(t->src_tiling,
+						    t->flags & SRC_COMPRESSED);
+		const char *dst_mode = buf_mode_str(t->dst_tiling,
+						    t->flags & DST_COMPRESSED);
+
+		igt_describe_f("Test render_copy() from a %s to a %s buffer.",
+			       src_mode, dst_mode);
+
+		igt_subtest_f("%s%s%s",
+			      t->flags ? src_mode : "",
+			      t->flags ? "-to-" : "",
+			      dst_mode)
+			test(&data, t->src_tiling, t->dst_tiling, t->flags);
+	}
 
 	igt_fixture {
 		igt_stop_hang_detector();
-- 
2.17.1

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Re: [igt-dev] [PATCH v2 3/3] tests/gem_render_copy: Add compressed src to compressed dst subtests

[Imre Deak]

On Tue, Nov 12, 2019 at 12:15:50PM -0800, Brian Welty wrote:
> 
> On 11/5/2019 11:34 AM, Imre Deak wrote:
> > Add new subtests that blit from a compressed source to a compressed
> > destination buffer.
> > 
> > v2:
> > - Use the correct buffer when dumping the png for the compressed buf.
> > 
> > Cc: Mika Kahola <mika.kahola@intel.com>
> > Cc: Brian Welty <brian.welty@intel.com>
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> 
> 
> Perhaps add a:
> References: https://bugs.freedesktop.org/show_bug.cgi?id=111771
> and close that out?

Ok, added that.

> I had been looking at gem_render_copy as part of above and your changes
> look fine to me.
> So for patches 2 and 3 you can have my:
> Reviewed-by: Brian Welty <brian.welty@intel.com>
> 
> Up to you if you need additional reviewed-by or not for this.

Thanks. I added back a subtest I removed by mistake in patch 3. I'll add
your r-b to the latest version of patch 2 and 3.

> 
> -Brian
> 
> 
> >  tests/i915/gem_render_copy.c | 126 ++++++++++++++++++++++++++---------
> >  1 file changed, 93 insertions(+), 33 deletions(-)
> > 
> > diff --git a/tests/i915/gem_render_copy.c b/tests/i915/gem_render_copy.c
> > index fd139e91..383e86bc 100644
> > --- a/tests/i915/gem_render_copy.c
> > +++ b/tests/i915/gem_render_copy.c
> > @@ -572,9 +572,13 @@ static void scratch_buf_aux_check(data_t *data,
> >  		     "Aux surface indicates that nothing was compressed\n");
> >  }
> >  
> > -static void test(data_t *data, uint32_t tiling, uint64_t ccs_modifier)
> > +#define DST_COMPRESSED	1
> > +#define SRC_COMPRESSED	2
> > +
> > +static void test(data_t *data, uint32_t dst_tiling, uint32_t src_tiling,
> > +		 int flags)
> >  {
> > -	struct igt_buf dst, ccs, ref;
> > +	struct igt_buf dst, src_ccs, dst_ccs, ref;
> >  	struct {
> >  		struct igt_buf buf;
> >  		const char *filename;
> > @@ -602,22 +606,34 @@ static void test(data_t *data, uint32_t tiling, uint64_t ccs_modifier)
> >  			.x = 1, .y = 1,
> >  		},
> >  	};
> > -
> >  	int opt_dump_aub = igt_aub_dump_enabled();
> >  	int num_src = ARRAY_SIZE(src);
> > +	bool src_compressed = flags & SRC_COMPRESSED;
> > +	bool dst_compressed = flags & DST_COMPRESSED;
> > +
> > +	/*
> > +	 * The tiling for uncompressed source buffers is determined by the
> > +	 * tiling of the src[] buffers above.
> > +	 */
> > +	igt_assert(!src_tiling || src_compressed);
> >  
> >  	/* no Yf before gen9 */
> >  	if (intel_gen(data->devid) < 9)
> >  		num_src--;
> >  
> > -	if (tiling == I915_TILING_Yf || ccs_modifier)
> > +	if (dst_tiling == I915_TILING_Yf || src_tiling == I915_TILING_Yf ||
> > +	    src_compressed || dst_compressed)
> >  		igt_require(intel_gen(data->devid) >= 9);
> >  
> >  	for (int i = 0; i < num_src; i++)
> >  		scratch_buf_init(data, &src[i].buf, WIDTH, HEIGHT, src[i].tiling, false);
> > -	scratch_buf_init(data, &dst, WIDTH, HEIGHT, tiling, false);
> > -	if (ccs_modifier)
> > -		scratch_buf_init(data, &ccs, WIDTH, HEIGHT, ccs_modifier, true);
> > +	scratch_buf_init(data, &dst, WIDTH, HEIGHT, dst_tiling, false);
> > +	if (src_compressed)
> > +		scratch_buf_init(data, &src_ccs, WIDTH, HEIGHT,
> > +				 src_tiling, true);
> > +	if (dst_compressed)
> > +		scratch_buf_init(data, &dst_ccs, WIDTH, HEIGHT,
> > +				 dst_tiling, true);
> >  	scratch_buf_init(data, &ref, WIDTH, HEIGHT, I915_TILING_NONE, false);
> >  
> >  	for (int i = 0; i < num_src; i++)
> > @@ -657,26 +673,45 @@ static void test(data_t *data, uint32_t tiling, uint64_t ccs_modifier)
> >  	 *	 |dst|src|
> >  	 *	  -------
> >  	 */
> > -	if (ccs_modifier)
> > +	if (src_compressed)
> >  		data->render_copy(data->batch, NULL,
> >  				  &dst, 0, 0, WIDTH, HEIGHT,
> > -				  &ccs, 0, 0);
> > +				  &src_ccs, 0, 0);
> >  
> >  	for (int i = 0; i < num_src; i++)
> >  		data->render_copy(data->batch, NULL,
> > -				  &src[i].buf, WIDTH/4, HEIGHT/4, WIDTH/2-2, HEIGHT/2-2,
> > -				  ccs_modifier ? &ccs : &dst, src[i].x, src[i].y);
> > +				  &src[i].buf,
> > +				  WIDTH/4, HEIGHT/4, WIDTH/2-2, HEIGHT/2-2,
> > +				  src_compressed ? &src_ccs : &dst,
> > +				  src[i].x, src[i].y);
> > +
> > +	if (src_compressed || dst_compressed)
> > +		data->render_copy(data->batch, NULL,
> > +				  src_compressed ? &src_ccs : &dst,
> > +				  0, 0, WIDTH, HEIGHT,
> > +				  dst_compressed ? &dst_ccs : &dst,
> > +				  0, 0);
> >  
> > -	if (ccs_modifier)
> > +	if (dst_compressed)
> >  		data->render_copy(data->batch, NULL,
> > -				  &ccs, 0, 0, WIDTH, HEIGHT,
> > -				  &dst, 0, 0);
> > +				  &dst_ccs,
> > +				  0, 0, WIDTH, HEIGHT,
> > +				  &dst,
> > +				  0, 0);
> >  
> >  	if (opt_dump_png){
> >  		scratch_buf_write_to_png(data, &dst, "result.png");
> > -		if (ccs_modifier) {
> > -			scratch_buf_write_to_png(data, &ccs, "compressed.png");
> > -			scratch_buf_aux_write_to_png(data, &ccs, "compressed-aux.png");
> > +		if (src_compressed) {
> > +			scratch_buf_write_to_png(data, &src_ccs,
> > +						 "compressed-src.png");
> > +			scratch_buf_aux_write_to_png(data, &src_ccs,
> > +						     "compressed-src-aux.png");
> > +		}
> > +		if (dst_compressed) {
> > +			scratch_buf_write_to_png(data, &dst_ccs,
> > +						 "compressed-dst.png");
> > +			scratch_buf_aux_write_to_png(data, &dst_ccs,
> > +						     "compressed-dst-aux.png");
> >  		}
> >  	}
> >  
> > @@ -694,12 +729,16 @@ static void test(data_t *data, uint32_t tiling, uint64_t ccs_modifier)
> >  		scratch_buf_check(data, &dst, &ref, WIDTH - 10, HEIGHT - 10);
> >  	}
> >  
> > -	if (ccs_modifier)
> > -		scratch_buf_aux_check(data, &ccs);
> > +	if (src_compressed)
> > +		scratch_buf_aux_check(data, &src_ccs);
> > +	if (dst_compressed)
> > +		scratch_buf_aux_check(data, &dst_ccs);
> >  
> >  	scratch_buf_fini(&ref);
> > -	if (ccs_modifier)
> > -		scratch_buf_fini(&ccs);
> > +	if (dst_compressed)
> > +		scratch_buf_fini(&dst_ccs);
> > +	if (src_compressed)
> > +		scratch_buf_fini(&src_ccs);
> >  	scratch_buf_fini(&dst);
> >  	for (int i = 0; i < num_src; i++)
> >  		scratch_buf_fini(&src[i].buf);
> > @@ -749,31 +788,52 @@ igt_main_args("da", NULL, help_str, opt_handler, NULL)
> >  	}
> >  
> >  	igt_subtest("linear")
> > -		test(&data, I915_TILING_NONE, 0);
> > +		test(&data, I915_TILING_NONE, 0, 0);
> >  	igt_subtest("x-tiled")
> > -		test(&data, I915_TILING_X, 0);
> > +		test(&data, I915_TILING_X, 0, 0);
> >  	igt_subtest("y-tiled")
> > -		test(&data, I915_TILING_Y, 0);
> > +		test(&data, I915_TILING_Y, 0, 0);
> >  	igt_subtest("yf-tiled")
> > -		test(&data, I915_TILING_Yf, 0);
> > +		test(&data, I915_TILING_Yf, 0, 0);
> >  
> >  	igt_subtest("y-tiled-ccs-to-linear")
> > -		test(&data, I915_TILING_NONE, I915_TILING_Y);
> > +		test(&data, I915_TILING_NONE, I915_TILING_Y,
> > +		     SRC_COMPRESSED);
> >  	igt_subtest("y-tiled-ccs-to-x-tiled")
> > -		test(&data, I915_TILING_X, I915_TILING_Y);
> > +		test(&data, I915_TILING_X, I915_TILING_Y,
> > +		     SRC_COMPRESSED);
> >  	igt_subtest("y-tiled-ccs-to-y-tiled")
> > -		test(&data, I915_TILING_Y, I915_TILING_Y);
> > +		test(&data, I915_TILING_Y, I915_TILING_Y,
> > +		     SRC_COMPRESSED);
> >  	igt_subtest("y-tiled-ccs-to-yf-tiled")
> > -		test(&data, I915_TILING_Yf, I915_TILING_Y);
> > +		test(&data, I915_TILING_Yf, I915_TILING_Y,
> > +		     SRC_COMPRESSED);
> >  
> >  	igt_subtest("yf-tiled-ccs-to-linear")
> > -		test(&data, I915_TILING_NONE, I915_TILING_Yf);
> > +		test(&data, I915_TILING_NONE, I915_TILING_Yf,
> > +		     SRC_COMPRESSED);
> >  	igt_subtest("yf-tiled-ccs-to-x-tiled")
> > -		test(&data, I915_TILING_X, I915_TILING_Yf);
> > +		test(&data, I915_TILING_X, I915_TILING_Yf,
> > +		     SRC_COMPRESSED);
> >  	igt_subtest("yf-tiled-ccs-to-y-tiled")
> > -		test(&data, I915_TILING_Y, I915_TILING_Yf);
> > +		test(&data, I915_TILING_Y, I915_TILING_Yf,
> > +		     SRC_COMPRESSED);
> >  	igt_subtest("yf-tiled-ccs-to-yf-tiled")
> > -		test(&data, I915_TILING_Yf, I915_TILING_Yf);
> > +		test(&data, I915_TILING_Yf, I915_TILING_Yf,
> > +		     SRC_COMPRESSED);
> > +
> > +	igt_subtest("y-tiled-ccs-to-y-tiled-ccs")
> > +		test(&data, I915_TILING_Y, I915_TILING_Y,
> > +		     SRC_COMPRESSED | DST_COMPRESSED);
> > +	igt_subtest("yf-tiled-ccs-to-yf-tiled-ccs")
> > +		test(&data, I915_TILING_Yf, I915_TILING_Yf,
> > +		     SRC_COMPRESSED | DST_COMPRESSED);
> > +	igt_subtest("y-tiled-ccs-to-yf-tiled-ccs")
> > +		test(&data, I915_TILING_Yf, I915_TILING_Y,
> > +		     SRC_COMPRESSED | DST_COMPRESSED);
> > +	igt_subtest("yf-tiled-ccs-to-y-tiled-ccs")
> > +		test(&data, I915_TILING_Y, I915_TILING_Yf,
> > +		     SRC_COMPRESSED | DST_COMPRESSED);
> >  
> >  	igt_fixture {
> >  		igt_stop_hang_detector();
> > 
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] ✓ Fi.CI.BAT: success for series starting with [v5,1/3] lib/rendercopy: Add AUX page table support (rev6)

[Patchwork]

== Series Details ==

Series: series starting with [v5,1/3] lib/rendercopy: Add AUX page table support (rev6)
URL   : https://patchwork.freedesktop.org/series/69012/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7331 -> IGTPW_3692
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/index.html

Known issues
------------

  Here are the changes found in IGTPW_3692 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live_execlists:
    - fi-glk-dsi:         [PASS][1] -> [INCOMPLETE][2] ([fdo#103359] / [k.org#198133])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/fi-glk-dsi/igt@i915_selftest@live_execlists.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/fi-glk-dsi/igt@i915_selftest@live_execlists.html

  * igt@i915_selftest@live_gem_contexts:
    - fi-bsw-kefka:       [PASS][3] -> [INCOMPLETE][4] ([fdo# 111542])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/fi-bsw-kefka/igt@i915_selftest@live_gem_contexts.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/fi-bsw-kefka/igt@i915_selftest@live_gem_contexts.html

  * igt@kms_flip@basic-flip-vs-wf_vblank:
    - fi-skl-6770hq:      [PASS][5] -> [DMESG-WARN][6] ([fdo#105541])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/fi-skl-6770hq/igt@kms_flip@basic-flip-vs-wf_vblank.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/fi-skl-6770hq/igt@kms_flip@basic-flip-vs-wf_vblank.html

  
#### Possible fixes ####

  * igt@i915_module_load@reload-no-display:
    - fi-skl-lmem:        [DMESG-WARN][7] ([fdo#112261]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/fi-skl-lmem/igt@i915_module_load@reload-no-display.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/fi-skl-lmem/igt@i915_module_load@reload-no-display.html

  * igt@kms_chamelium@hdmi-crc-fast:
    - fi-icl-u2:          [FAIL][9] ([fdo#109635 ]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/fi-icl-u2/igt@kms_chamelium@hdmi-crc-fast.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/fi-icl-u2/igt@kms_chamelium@hdmi-crc-fast.html

  * igt@kms_chamelium@hdmi-edid-read:
    - fi-kbl-7500u:       [FAIL][11] ([fdo#109483]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/fi-kbl-7500u/igt@kms_chamelium@hdmi-edid-read.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/fi-kbl-7500u/igt@kms_chamelium@hdmi-edid-read.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][13] ([fdo#111045] / [fdo#111096]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
#### Warnings ####

  * igt@i915_selftest@live_gt_pm:
    - fi-icl-guc:         [DMESG-FAIL][15] ([fdo#112205]) -> [INCOMPLETE][16] ([fdo#107713])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/fi-icl-guc/igt@i915_selftest@live_gt_pm.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/fi-icl-guc/igt@i915_selftest@live_gt_pm.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo# 111542]: https://bugs.freedesktop.org/show_bug.cgi?id= 111542
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#105541]: https://bugs.freedesktop.org/show_bug.cgi?id=105541
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
  [fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
  [fdo#112205]: https://bugs.freedesktop.org/show_bug.cgi?id=112205
  [fdo#112261]: https://bugs.freedesktop.org/show_bug.cgi?id=112261
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (53 -> 46)
------------------------------

  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5276 -> IGTPW_3692

  CI-20190529: 20190529
  CI_DRM_7331: 4ea40d641218a45e90dd213b89a207ce8bec34dd @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_3692: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/index.html
  IGT_5276: 868d38c2bc075b6756ebed486db6e7152ed2c5be @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools



== Testlist changes ==

+igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled-ccs
+igt@gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs
+igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs
+igt@gem_render_copy@y-tiled-ccs-to-y-tiled-ccs

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/index.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] ✓ Fi.CI.IGT: success for series starting with [v5,1/3] lib/rendercopy: Add AUX page table support (rev6)

[Patchwork]

== Series Details ==

Series: series starting with [v5,1/3] lib/rendercopy: Add AUX page table support (rev6)
URL   : https://patchwork.freedesktop.org/series/69012/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7331_full -> IGTPW_3692_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/index.html

New tests
---------

  New tests have been introduced between CI_DRM_7331_full and IGTPW_3692_full:

### New IGT tests (4) ###

  * igt@gem_render_copy@y-tiled-ccs-to-y-tiled-ccs:
    - Statuses : 4 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.24] s

  * igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs:
    - Statuses : 5 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.23] s

  * igt@gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled-ccs:
    - Statuses : 5 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.28] s

  

Known issues
------------

  Here are the changes found in IGTPW_3692_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_persistence@vcs1-queued:
    - shard-iclb:         [PASS][1] -> [SKIP][2] ([fdo#109276] / [fdo#112080]) +2 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb1/igt@gem_ctx_persistence@vcs1-queued.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb5/igt@gem_ctx_persistence@vcs1-queued.html

  * igt@gem_ctx_switch@all-light:
    - shard-tglb:         [PASS][3] -> [INCOMPLETE][4] ([fdo#111672])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-tglb4/igt@gem_ctx_switch@all-light.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-tglb6/igt@gem_ctx_switch@all-light.html

  * igt@gem_exec_balancer@smoke:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#110854])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb4/igt@gem_exec_balancer@smoke.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb5/igt@gem_exec_balancer@smoke.html

  * igt@gem_exec_nop@basic-parallel:
    - shard-tglb:         [PASS][7] -> [INCOMPLETE][8] ([fdo#111747])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-tglb6/igt@gem_exec_nop@basic-parallel.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-tglb5/igt@gem_exec_nop@basic-parallel.html

  * igt@gem_exec_schedule@preempt-queue-contexts-chain-blt:
    - shard-tglb:         [PASS][9] -> [INCOMPLETE][10] ([fdo#111606] / [fdo#111677])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-tglb2/igt@gem_exec_schedule@preempt-queue-contexts-chain-blt.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-tglb6/igt@gem_exec_schedule@preempt-queue-contexts-chain-blt.html

  * igt@gem_exec_schedule@promotion-bsd:
    - shard-iclb:         [PASS][11] -> [SKIP][12] ([fdo#112146]) +3 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb7/igt@gem_exec_schedule@promotion-bsd.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb2/igt@gem_exec_schedule@promotion-bsd.html

  * igt@gem_exec_schedule@promotion-bsd1:
    - shard-iclb:         [PASS][13] -> [SKIP][14] ([fdo#109276]) +11 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb1/igt@gem_exec_schedule@promotion-bsd1.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb7/igt@gem_exec_schedule@promotion-bsd1.html

  * igt@gem_exec_suspend@basic-s0:
    - shard-tglb:         [PASS][15] -> [INCOMPLETE][16] ([fdo#111832]) +1 similar issue
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-tglb9/igt@gem_exec_suspend@basic-s0.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-tglb4/igt@gem_exec_suspend@basic-s0.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-snb:          [PASS][17] -> [DMESG-WARN][18] ([fdo#111870])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-snb7/igt@gem_userptr_blits@dmabuf-unsync.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-snb4/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@gem_workarounds@suspend-resume:
    - shard-tglb:         [PASS][19] -> [INCOMPLETE][20] ([fdo#111832] / [fdo#111850]) +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-tglb7/igt@gem_workarounds@suspend-resume.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-tglb4/igt@gem_workarounds@suspend-resume.html

  * igt@i915_selftest@mock_requests:
    - shard-glk:          [PASS][21] -> [DMESG-WARN][22] ([fdo#112158])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-glk3/igt@i915_selftest@mock_requests.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-glk6/igt@i915_selftest@mock_requests.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-kbl:          [PASS][23] -> [DMESG-WARN][24] ([fdo#108566]) +2 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-tglb:         [PASS][25] -> [INCOMPLETE][26] ([fdo#111832] / [fdo#111850] / [fdo#112031])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-tglb9/igt@kms_flip@flip-vs-suspend-interruptible.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-tglb5/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu:
    - shard-tglb:         [PASS][27] -> [FAIL][28] ([fdo#103167])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-tglb9/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-tglb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-slowdraw:
    - shard-iclb:         [PASS][29] -> [FAIL][30] ([fdo#103167]) +1 similar issue
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-slowdraw.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-slowdraw.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-apl:          [PASS][31] -> [DMESG-WARN][32] ([fdo#108566]) +2 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_psr@psr2_sprite_render:
    - shard-iclb:         [PASS][33] -> [SKIP][34] ([fdo#109441]) +1 similar issue
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb2/igt@kms_psr@psr2_sprite_render.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb8/igt@kms_psr@psr2_sprite_render.html

  * igt@perf_pmu@init-busy-vcs1:
    - shard-iclb:         [PASS][35] -> [SKIP][36] ([fdo#112080]) +13 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb1/igt@perf_pmu@init-busy-vcs1.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb5/igt@perf_pmu@init-busy-vcs1.html

  
#### Possible fixes ####

  * igt@gem_busy@busy-vcs1:
    - shard-iclb:         [SKIP][37] ([fdo#112080]) -> [PASS][38] +17 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb7/igt@gem_busy@busy-vcs1.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb4/igt@gem_busy@busy-vcs1.html

  * igt@gem_ctx_isolation@vcs1-none:
    - shard-iclb:         [SKIP][39] ([fdo#109276] / [fdo#112080]) -> [PASS][40] +4 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb8/igt@gem_ctx_isolation@vcs1-none.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb2/igt@gem_ctx_isolation@vcs1-none.html

  * igt@gem_exec_schedule@preempt-other-chain-bsd:
    - shard-iclb:         [SKIP][41] ([fdo#112146]) -> [PASS][42] +3 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb2/igt@gem_exec_schedule@preempt-other-chain-bsd.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb3/igt@gem_exec_schedule@preempt-other-chain-bsd.html

  * igt@gem_exec_schedule@preempt-queue-contexts-chain-vebox:
    - shard-tglb:         [INCOMPLETE][43] ([fdo#111606] / [fdo#111677]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-tglb6/igt@gem_exec_schedule@preempt-queue-contexts-chain-vebox.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-tglb1/igt@gem_exec_schedule@preempt-queue-contexts-chain-vebox.html

  * igt@gem_render_copy@yf-tiled-ccs-to-y-tiled:
    - shard-tglb:         [FAIL][45] ([fdo#111771]) -> [PASS][46] +2 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-tglb1/igt@gem_render_copy@yf-tiled-ccs-to-y-tiled.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-tglb6/igt@gem_render_copy@yf-tiled-ccs-to-y-tiled.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
    - shard-snb:          [DMESG-WARN][47] ([fdo#111870]) -> [PASS][48] +1 similar issue
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html

  * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
    - shard-hsw:          [DMESG-WARN][49] ([fdo#111870]) -> [PASS][50] +1 similar issue
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-hsw5/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-hsw6/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-kbl:          [DMESG-WARN][51] ([fdo#108566]) -> [PASS][52] +1 similar issue
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-kbl1/igt@gem_workarounds@suspend-resume-fd.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-kbl7/igt@gem_workarounds@suspend-resume-fd.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
    - shard-iclb:         [FAIL][53] ([fdo#103167]) -> [PASS][54] +3 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite:
    - shard-tglb:         [FAIL][55] ([fdo#103167]) -> [PASS][56] +1 similar issue
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-suspend:
    - shard-tglb:         [INCOMPLETE][57] ([fdo#111832] / [fdo#111850] / [fdo#111884]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
    - shard-tglb:         [INCOMPLETE][59] ([fdo#111832] / [fdo#111850]) -> [PASS][60] +3 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-tglb2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-tglb1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html

  * igt@kms_psr@psr2_no_drrs:
    - shard-iclb:         [SKIP][61] ([fdo#109441]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb8/igt@kms_psr@psr2_no_drrs.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb2/igt@kms_psr@psr2_no_drrs.html

  * igt@kms_setmode@basic:
    - shard-apl:          [FAIL][63] ([fdo#99912]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-apl1/igt@kms_setmode@basic.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-apl4/igt@kms_setmode@basic.html
    - shard-kbl:          [FAIL][65] ([fdo#99912]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-kbl3/igt@kms_setmode@basic.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-kbl2/igt@kms_setmode@basic.html

  * igt@prime_busy@hang-bsd2:
    - shard-iclb:         [SKIP][67] ([fdo#109276]) -> [PASS][68] +16 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb8/igt@prime_busy@hang-bsd2.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb4/igt@prime_busy@hang-bsd2.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs1-nonpriv:
    - shard-iclb:         [SKIP][69] ([fdo#109276] / [fdo#112080]) -> [FAIL][70] ([fdo#111329])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb5/igt@gem_ctx_isolation@vcs1-nonpriv.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb2/igt@gem_ctx_isolation@vcs1-nonpriv.html

  * igt@gem_eio@kms:
    - shard-snb:          [DMESG-WARN][71] ([fdo# 112000 ] / [fdo#111781]) -> [INCOMPLETE][72] ([fdo#105411])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-snb6/igt@gem_eio@kms.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-snb5/igt@gem_eio@kms.html

  * igt@gem_exec_schedule@deep-bsd2:
    - shard-tglb:         [INCOMPLETE][73] ([fdo#111671]) -> [FAIL][74] ([fdo#111646])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-tglb9/igt@gem_exec_schedule@deep-bsd2.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-tglb3/igt@gem_exec_schedule@deep-bsd2.html

  * igt@gem_exec_schedule@deep-vebox:
    - shard-tglb:         [FAIL][75] ([fdo#111646]) -> [INCOMPLETE][76] ([fdo#111671])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-tglb4/igt@gem_exec_schedule@deep-vebox.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-tglb2/igt@gem_exec_schedule@deep-vebox.html

  * igt@gem_mocs_settings@mocs-isolation-bsd2:
    - shard-iclb:         [SKIP][77] ([fdo#109276]) -> [FAIL][78] ([fdo#111330])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb5/igt@gem_mocs_settings@mocs-isolation-bsd2.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb4/igt@gem_mocs_settings@mocs-isolation-bsd2.html

  * igt@gem_mocs_settings@mocs-rc6-bsd2:
    - shard-iclb:         [FAIL][79] ([fdo#111330]) -> [SKIP][80] ([fdo#109276])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb2/igt@gem_mocs_settings@mocs-rc6-bsd2.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb6/igt@gem_mocs_settings@mocs-rc6-bsd2.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-tglb:         [FAIL][81] ([fdo#111830 ]) -> [SKIP][82] ([fdo#111865])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-tglb3/igt@i915_pm_dc@dc6-dpms.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-tglb6/igt@i915_pm_dc@dc6-dpms.html

  
  [fdo# 112000 ]: https://bugs.freedesktop.org/show_bug.cgi?id= 112000 
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
  [fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
  [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
  [fdo#111606]: https://bugs.freedesktop.org/show_bug.cgi?id=111606
  [fdo#111646]: https://bugs.freedesktop.org/show_bug.cgi?id=111646
  [fdo#111671]: https://bugs.freedesktop.org/show_bug.cgi?id=111671
  [fdo#111672]: https://bugs.freedesktop.org/show_bug.cgi?id=111672
  [fdo#111677]: https://bugs.freedesktop.org/show_bug.cgi?id=111677
  [fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
  [fdo#111771]: https://bugs.freedesktop.org/show_bug.cgi?id=111771
  [fdo#111781]: https://bugs.freedesktop.org/show_bug.cgi?id=111781
  [fdo#111830 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111830 
  [fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832
  [fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
  [fdo#111865]: https://bugs.freedesktop.org/show_bug.cgi?id=111865
  [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
  [fdo#111884]: https://bugs.freedesktop.org/show_bug.cgi?id=111884
  [fdo#112031]: https://bugs.freedesktop.org/show_bug.cgi?id=112031
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
  [fdo#112158]: https://bugs.freedesktop.org/show_bug.cgi?id=112158
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (11 -> 8)
------------------------------

  Missing    (3): pig-skl-6260u pig-glk-j5005 pig-hsw-4770r 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5276 -> IGTPW_3692
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_7331: 4ea40d641218a45e90dd213b89a207ce8bec34dd @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_3692: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/index.html
  IGT_5276: 868d38c2bc075b6756ebed486db6e7152ed2c5be @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/index.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

Re: [igt-dev] ✓ Fi.CI.IGT: success for series starting with [v5,1/3] lib/rendercopy: Add AUX page table support (rev6)

[Imre Deak]

On Thu, Nov 14, 2019 at 04:52:30AM +0000, Patchwork wrote:
> == Series Details ==
> 
> Series: series starting with [v5,1/3] lib/rendercopy: Add AUX page table support (rev6)
> URL   : https://patchwork.freedesktop.org/series/69012/
> State : success

Thanks for the reviews, patchset is pushed.

> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_7331_full -> IGTPW_3692_full
> ====================================================
> 
> Summary
> -------
> 
>   **SUCCESS**
> 
>   No regressions found.
> 
>   External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/index.html
> 
> New tests
> ---------
> 
>   New tests have been introduced between CI_DRM_7331_full and IGTPW_3692_full:
> 
> ### New IGT tests (4) ###
> 
>   * igt@gem_render_copy@y-tiled-ccs-to-y-tiled-ccs:
>     - Statuses : 4 pass(s) 2 skip(s)
>     - Exec time: [0.0, 0.24] s
> 
>   * igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs:
>     - Statuses : 5 pass(s) 2 skip(s)
>     - Exec time: [0.0, 0.23] s
> 
>   * igt@gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs:
>     - Statuses : 1 pass(s)
>     - Exec time: [0.13] s
> 
>   * igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled-ccs:
>     - Statuses : 5 pass(s) 2 skip(s)
>     - Exec time: [0.0, 0.28] s
> 
>   
> 
> Known issues
> ------------
> 
>   Here are the changes found in IGTPW_3692_full that come from known issues:
> 
> ### IGT changes ###
> 
> #### Issues hit ####
> 
>   * igt@gem_ctx_persistence@vcs1-queued:
>     - shard-iclb:         [PASS][1] -> [SKIP][2] ([fdo#109276] / [fdo#112080]) +2 similar issues
>    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb1/igt@gem_ctx_persistence@vcs1-queued.html
>    [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb5/igt@gem_ctx_persistence@vcs1-queued.html
> 
>   * igt@gem_ctx_switch@all-light:
>     - shard-tglb:         [PASS][3] -> [INCOMPLETE][4] ([fdo#111672])
>    [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-tglb4/igt@gem_ctx_switch@all-light.html
>    [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-tglb6/igt@gem_ctx_switch@all-light.html
> 
>   * igt@gem_exec_balancer@smoke:
>     - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#110854])
>    [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb4/igt@gem_exec_balancer@smoke.html
>    [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb5/igt@gem_exec_balancer@smoke.html
> 
>   * igt@gem_exec_nop@basic-parallel:
>     - shard-tglb:         [PASS][7] -> [INCOMPLETE][8] ([fdo#111747])
>    [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-tglb6/igt@gem_exec_nop@basic-parallel.html
>    [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-tglb5/igt@gem_exec_nop@basic-parallel.html
> 
>   * igt@gem_exec_schedule@preempt-queue-contexts-chain-blt:
>     - shard-tglb:         [PASS][9] -> [INCOMPLETE][10] ([fdo#111606] / [fdo#111677])
>    [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-tglb2/igt@gem_exec_schedule@preempt-queue-contexts-chain-blt.html
>    [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-tglb6/igt@gem_exec_schedule@preempt-queue-contexts-chain-blt.html
> 
>   * igt@gem_exec_schedule@promotion-bsd:
>     - shard-iclb:         [PASS][11] -> [SKIP][12] ([fdo#112146]) +3 similar issues
>    [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb7/igt@gem_exec_schedule@promotion-bsd.html
>    [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb2/igt@gem_exec_schedule@promotion-bsd.html
> 
>   * igt@gem_exec_schedule@promotion-bsd1:
>     - shard-iclb:         [PASS][13] -> [SKIP][14] ([fdo#109276]) +11 similar issues
>    [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb1/igt@gem_exec_schedule@promotion-bsd1.html
>    [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb7/igt@gem_exec_schedule@promotion-bsd1.html
> 
>   * igt@gem_exec_suspend@basic-s0:
>     - shard-tglb:         [PASS][15] -> [INCOMPLETE][16] ([fdo#111832]) +1 similar issue
>    [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-tglb9/igt@gem_exec_suspend@basic-s0.html
>    [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-tglb4/igt@gem_exec_suspend@basic-s0.html
> 
>   * igt@gem_userptr_blits@dmabuf-unsync:
>     - shard-snb:          [PASS][17] -> [DMESG-WARN][18] ([fdo#111870])
>    [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-snb7/igt@gem_userptr_blits@dmabuf-unsync.html
>    [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-snb4/igt@gem_userptr_blits@dmabuf-unsync.html
> 
>   * igt@gem_workarounds@suspend-resume:
>     - shard-tglb:         [PASS][19] -> [INCOMPLETE][20] ([fdo#111832] / [fdo#111850]) +1 similar issue
>    [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-tglb7/igt@gem_workarounds@suspend-resume.html
>    [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-tglb4/igt@gem_workarounds@suspend-resume.html
> 
>   * igt@i915_selftest@mock_requests:
>     - shard-glk:          [PASS][21] -> [DMESG-WARN][22] ([fdo#112158])
>    [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-glk3/igt@i915_selftest@mock_requests.html
>    [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-glk6/igt@i915_selftest@mock_requests.html
> 
>   * igt@kms_cursor_crc@pipe-a-cursor-suspend:
>     - shard-kbl:          [PASS][23] -> [DMESG-WARN][24] ([fdo#108566]) +2 similar issues
>    [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
>    [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
> 
>   * igt@kms_flip@flip-vs-suspend-interruptible:
>     - shard-tglb:         [PASS][25] -> [INCOMPLETE][26] ([fdo#111832] / [fdo#111850] / [fdo#112031])
>    [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-tglb9/igt@kms_flip@flip-vs-suspend-interruptible.html
>    [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-tglb5/igt@kms_flip@flip-vs-suspend-interruptible.html
> 
>   * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu:
>     - shard-tglb:         [PASS][27] -> [FAIL][28] ([fdo#103167])
>    [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-tglb9/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu.html
>    [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-tglb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu.html
> 
>   * igt@kms_frontbuffer_tracking@fbcpsr-slowdraw:
>     - shard-iclb:         [PASS][29] -> [FAIL][30] ([fdo#103167]) +1 similar issue
>    [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-slowdraw.html
>    [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-slowdraw.html
> 
>   * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
>     - shard-apl:          [PASS][31] -> [DMESG-WARN][32] ([fdo#108566]) +2 similar issues
>    [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
>    [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
> 
>   * igt@kms_psr@psr2_sprite_render:
>     - shard-iclb:         [PASS][33] -> [SKIP][34] ([fdo#109441]) +1 similar issue
>    [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb2/igt@kms_psr@psr2_sprite_render.html
>    [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb8/igt@kms_psr@psr2_sprite_render.html
> 
>   * igt@perf_pmu@init-busy-vcs1:
>     - shard-iclb:         [PASS][35] -> [SKIP][36] ([fdo#112080]) +13 similar issues
>    [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb1/igt@perf_pmu@init-busy-vcs1.html
>    [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb5/igt@perf_pmu@init-busy-vcs1.html
> 
>   
> #### Possible fixes ####
> 
>   * igt@gem_busy@busy-vcs1:
>     - shard-iclb:         [SKIP][37] ([fdo#112080]) -> [PASS][38] +17 similar issues
>    [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb7/igt@gem_busy@busy-vcs1.html
>    [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb4/igt@gem_busy@busy-vcs1.html
> 
>   * igt@gem_ctx_isolation@vcs1-none:
>     - shard-iclb:         [SKIP][39] ([fdo#109276] / [fdo#112080]) -> [PASS][40] +4 similar issues
>    [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb8/igt@gem_ctx_isolation@vcs1-none.html
>    [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb2/igt@gem_ctx_isolation@vcs1-none.html
> 
>   * igt@gem_exec_schedule@preempt-other-chain-bsd:
>     - shard-iclb:         [SKIP][41] ([fdo#112146]) -> [PASS][42] +3 similar issues
>    [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb2/igt@gem_exec_schedule@preempt-other-chain-bsd.html
>    [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb3/igt@gem_exec_schedule@preempt-other-chain-bsd.html
> 
>   * igt@gem_exec_schedule@preempt-queue-contexts-chain-vebox:
>     - shard-tglb:         [INCOMPLETE][43] ([fdo#111606] / [fdo#111677]) -> [PASS][44]
>    [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-tglb6/igt@gem_exec_schedule@preempt-queue-contexts-chain-vebox.html
>    [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-tglb1/igt@gem_exec_schedule@preempt-queue-contexts-chain-vebox.html
> 
>   * igt@gem_render_copy@yf-tiled-ccs-to-y-tiled:
>     - shard-tglb:         [FAIL][45] ([fdo#111771]) -> [PASS][46] +2 similar issues
>    [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-tglb1/igt@gem_render_copy@yf-tiled-ccs-to-y-tiled.html
>    [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-tglb6/igt@gem_render_copy@yf-tiled-ccs-to-y-tiled.html
> 
>   * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
>     - shard-snb:          [DMESG-WARN][47] ([fdo#111870]) -> [PASS][48] +1 similar issue
>    [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
>    [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
> 
>   * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
>     - shard-hsw:          [DMESG-WARN][49] ([fdo#111870]) -> [PASS][50] +1 similar issue
>    [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-hsw5/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
>    [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-hsw6/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
> 
>   * igt@gem_workarounds@suspend-resume-fd:
>     - shard-kbl:          [DMESG-WARN][51] ([fdo#108566]) -> [PASS][52] +1 similar issue
>    [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-kbl1/igt@gem_workarounds@suspend-resume-fd.html
>    [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-kbl7/igt@gem_workarounds@suspend-resume-fd.html
> 
>   * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
>     - shard-iclb:         [FAIL][53] ([fdo#103167]) -> [PASS][54] +3 similar issues
>    [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
>    [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
> 
>   * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite:
>     - shard-tglb:         [FAIL][55] ([fdo#103167]) -> [PASS][56] +1 similar issue
>    [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html
>    [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html
> 
>   * igt@kms_frontbuffer_tracking@fbcpsr-suspend:
>     - shard-tglb:         [INCOMPLETE][57] ([fdo#111832] / [fdo#111850] / [fdo#111884]) -> [PASS][58]
>    [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
>    [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
> 
>   * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
>     - shard-tglb:         [INCOMPLETE][59] ([fdo#111832] / [fdo#111850]) -> [PASS][60] +3 similar issues
>    [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-tglb2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
>    [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-tglb1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
> 
>   * igt@kms_psr@psr2_no_drrs:
>     - shard-iclb:         [SKIP][61] ([fdo#109441]) -> [PASS][62]
>    [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb8/igt@kms_psr@psr2_no_drrs.html
>    [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
> 
>   * igt@kms_setmode@basic:
>     - shard-apl:          [FAIL][63] ([fdo#99912]) -> [PASS][64]
>    [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-apl1/igt@kms_setmode@basic.html
>    [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-apl4/igt@kms_setmode@basic.html
>     - shard-kbl:          [FAIL][65] ([fdo#99912]) -> [PASS][66]
>    [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-kbl3/igt@kms_setmode@basic.html
>    [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-kbl2/igt@kms_setmode@basic.html
> 
>   * igt@prime_busy@hang-bsd2:
>     - shard-iclb:         [SKIP][67] ([fdo#109276]) -> [PASS][68] +16 similar issues
>    [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb8/igt@prime_busy@hang-bsd2.html
>    [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb4/igt@prime_busy@hang-bsd2.html
> 
>   
> #### Warnings ####
> 
>   * igt@gem_ctx_isolation@vcs1-nonpriv:
>     - shard-iclb:         [SKIP][69] ([fdo#109276] / [fdo#112080]) -> [FAIL][70] ([fdo#111329])
>    [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb5/igt@gem_ctx_isolation@vcs1-nonpriv.html
>    [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb2/igt@gem_ctx_isolation@vcs1-nonpriv.html
> 
>   * igt@gem_eio@kms:
>     - shard-snb:          [DMESG-WARN][71] ([fdo# 112000 ] / [fdo#111781]) -> [INCOMPLETE][72] ([fdo#105411])
>    [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-snb6/igt@gem_eio@kms.html
>    [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-snb5/igt@gem_eio@kms.html
> 
>   * igt@gem_exec_schedule@deep-bsd2:
>     - shard-tglb:         [INCOMPLETE][73] ([fdo#111671]) -> [FAIL][74] ([fdo#111646])
>    [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-tglb9/igt@gem_exec_schedule@deep-bsd2.html
>    [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-tglb3/igt@gem_exec_schedule@deep-bsd2.html
> 
>   * igt@gem_exec_schedule@deep-vebox:
>     - shard-tglb:         [FAIL][75] ([fdo#111646]) -> [INCOMPLETE][76] ([fdo#111671])
>    [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-tglb4/igt@gem_exec_schedule@deep-vebox.html
>    [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-tglb2/igt@gem_exec_schedule@deep-vebox.html
> 
>   * igt@gem_mocs_settings@mocs-isolation-bsd2:
>     - shard-iclb:         [SKIP][77] ([fdo#109276]) -> [FAIL][78] ([fdo#111330])
>    [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb5/igt@gem_mocs_settings@mocs-isolation-bsd2.html
>    [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb4/igt@gem_mocs_settings@mocs-isolation-bsd2.html
> 
>   * igt@gem_mocs_settings@mocs-rc6-bsd2:
>     - shard-iclb:         [FAIL][79] ([fdo#111330]) -> [SKIP][80] ([fdo#109276])
>    [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-iclb2/igt@gem_mocs_settings@mocs-rc6-bsd2.html
>    [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-iclb6/igt@gem_mocs_settings@mocs-rc6-bsd2.html
> 
>   * igt@i915_pm_dc@dc6-dpms:
>     - shard-tglb:         [FAIL][81] ([fdo#111830 ]) -> [SKIP][82] ([fdo#111865])
>    [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7331/shard-tglb3/igt@i915_pm_dc@dc6-dpms.html
>    [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/shard-tglb6/igt@i915_pm_dc@dc6-dpms.html
> 
>   
>   [fdo# 112000 ]: https://bugs.freedesktop.org/show_bug.cgi?id= 112000 
>   [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
>   [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
>   [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
>   [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
>   [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
>   [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
>   [fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
>   [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
>   [fdo#111606]: https://bugs.freedesktop.org/show_bug.cgi?id=111606
>   [fdo#111646]: https://bugs.freedesktop.org/show_bug.cgi?id=111646
>   [fdo#111671]: https://bugs.freedesktop.org/show_bug.cgi?id=111671
>   [fdo#111672]: https://bugs.freedesktop.org/show_bug.cgi?id=111672
>   [fdo#111677]: https://bugs.freedesktop.org/show_bug.cgi?id=111677
>   [fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
>   [fdo#111771]: https://bugs.freedesktop.org/show_bug.cgi?id=111771
>   [fdo#111781]: https://bugs.freedesktop.org/show_bug.cgi?id=111781
>   [fdo#111830 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111830 
>   [fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832
>   [fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
>   [fdo#111865]: https://bugs.freedesktop.org/show_bug.cgi?id=111865
>   [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
>   [fdo#111884]: https://bugs.freedesktop.org/show_bug.cgi?id=111884
>   [fdo#112031]: https://bugs.freedesktop.org/show_bug.cgi?id=112031
>   [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
>   [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
>   [fdo#112158]: https://bugs.freedesktop.org/show_bug.cgi?id=112158
>   [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
> 
> 
> Participating hosts (11 -> 8)
> ------------------------------
> 
>   Missing    (3): pig-skl-6260u pig-glk-j5005 pig-hsw-4770r 
> 
> 
> Build changes
> -------------
> 
>   * CI: CI-20190529 -> None
>   * IGT: IGT_5276 -> IGTPW_3692
>   * Piglit: piglit_4509 -> None
> 
>   CI-20190529: 20190529
>   CI_DRM_7331: 4ea40d641218a45e90dd213b89a207ce8bec34dd @ git://anongit.freedesktop.org/gfx-ci/linux
>   IGTPW_3692: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/index.html
>   IGT_5276: 868d38c2bc075b6756ebed486db6e7152ed2c5be @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>   piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3692/index.html
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