From: Yann Gautier <yann.gautier@st.com> To: <alexandre.torgue@st.com> Cc: <mcoquelin.stm32@gmail.com>, <robh+dt@kernel.org>, <mark.rutland@arm.com>, <linux-stm32@st-md-mailman.stormreply.com>, <linux-arm-kernel@lists.infradead.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, Yann Gautier <yann.gautier@st.com>, "Ludovic Barre" <ludovic.barre@st.com> Subject: [PATCH 4/4] ARM: dts: stm32: add sdmmc3 node for STM32MP1 boards Date: Wed, 6 Nov 2019 11:09:38 +0100 [thread overview] Message-ID: <20191106100938.11368-5-yann.gautier@st.com> (raw) In-Reply-To: <20191106100938.11368-1-yann.gautier@st.com> On STM32MP1 EVAL and DISCOVERY boards, the SDMMC3 internal peripheral can be used through the GPIO extension connector. The sdmmc3 node is then added in the boards DT files, and the required pins are also added. The node status is disabled as there is no device connected by default. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> --- arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 54 +++++++++++++++++++++++ arch/arm/boot/dts/stm32mp157a-dk1.dts | 12 +++++ arch/arm/boot/dts/stm32mp157c-ev1.dts | 12 +++++ 3 files changed, 78 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi index a907d93f8916..d31a4661f7b5 100644 --- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi @@ -926,6 +926,60 @@ }; }; + sdmmc3_b4_pins_a: sdmmc3-b4-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ + <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ + <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */ + <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */ + <STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ + <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ + <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */ + <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + pins3 { + pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */ + <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */ + <STM32_PINMUX('F', 5, ANALOG)>, /* SDMMC3_D2 */ + <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */ + <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */ + <STM32_PINMUX('F', 1, ANALOG)>; /* SDMMC3_CMD */ + }; + }; + spdifrx_pins_a: spdifrx-0 { pins { pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */ diff --git a/arch/arm/boot/dts/stm32mp157a-dk1.dts b/arch/arm/boot/dts/stm32mp157a-dk1.dts index 0615d1c8a6fc..b86c32e6a829 100644 --- a/arch/arm/boot/dts/stm32mp157a-dk1.dts +++ b/arch/arm/boot/dts/stm32mp157a-dk1.dts @@ -444,6 +444,18 @@ status = "okay"; }; +&sdmmc3 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_a>; + pinctrl-1 = <&sdmmc3_b4_od_pins_a>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; + broken-cd; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "disabled"; +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index 89d29b50c3f4..d047901c51ea 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -293,6 +293,18 @@ }; }; +&sdmmc3 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_a>; + pinctrl-1 = <&sdmmc3_b4_od_pins_a>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; + broken-cd; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "disabled"; +}; + &spi1 { pinctrl-names = "default"; pinctrl-0 = <&spi1_pins_a>; -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Yann Gautier <yann.gautier@st.com> To: <alexandre.torgue@st.com> Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, Yann Gautier <yann.gautier@st.com>, linux-kernel@vger.kernel.org, robh+dt@kernel.org, Ludovic Barre <ludovic.barre@st.com>, mcoquelin.stm32@gmail.com, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH 4/4] ARM: dts: stm32: add sdmmc3 node for STM32MP1 boards Date: Wed, 6 Nov 2019 11:09:38 +0100 [thread overview] Message-ID: <20191106100938.11368-5-yann.gautier@st.com> (raw) In-Reply-To: <20191106100938.11368-1-yann.gautier@st.com> On STM32MP1 EVAL and DISCOVERY boards, the SDMMC3 internal peripheral can be used through the GPIO extension connector. The sdmmc3 node is then added in the boards DT files, and the required pins are also added. The node status is disabled as there is no device connected by default. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> --- arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 54 +++++++++++++++++++++++ arch/arm/boot/dts/stm32mp157a-dk1.dts | 12 +++++ arch/arm/boot/dts/stm32mp157c-ev1.dts | 12 +++++ 3 files changed, 78 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi index a907d93f8916..d31a4661f7b5 100644 --- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi @@ -926,6 +926,60 @@ }; }; + sdmmc3_b4_pins_a: sdmmc3-b4-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ + <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ + <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */ + <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */ + <STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ + <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ + <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */ + <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + pins3 { + pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */ + <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */ + <STM32_PINMUX('F', 5, ANALOG)>, /* SDMMC3_D2 */ + <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */ + <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */ + <STM32_PINMUX('F', 1, ANALOG)>; /* SDMMC3_CMD */ + }; + }; + spdifrx_pins_a: spdifrx-0 { pins { pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */ diff --git a/arch/arm/boot/dts/stm32mp157a-dk1.dts b/arch/arm/boot/dts/stm32mp157a-dk1.dts index 0615d1c8a6fc..b86c32e6a829 100644 --- a/arch/arm/boot/dts/stm32mp157a-dk1.dts +++ b/arch/arm/boot/dts/stm32mp157a-dk1.dts @@ -444,6 +444,18 @@ status = "okay"; }; +&sdmmc3 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_a>; + pinctrl-1 = <&sdmmc3_b4_od_pins_a>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; + broken-cd; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "disabled"; +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index 89d29b50c3f4..d047901c51ea 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -293,6 +293,18 @@ }; }; +&sdmmc3 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_a>; + pinctrl-1 = <&sdmmc3_b4_od_pins_a>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; + broken-cd; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "disabled"; +}; + &spi1 { pinctrl-names = "default"; pinctrl-0 = <&spi1_pins_a>; -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-11-06 10:10 UTC|newest] Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-06 10:09 [PATCH 0/4] Update sdmmc nodes for STM32MP1 Yann Gautier 2019-11-06 10:09 ` Yann Gautier 2019-11-06 10:09 ` [PATCH 1/4] ARM: dts: stm32: update slew-rate properties for sdmmc1 on stm32mp157 Yann Gautier 2019-11-06 10:09 ` Yann Gautier 2019-11-06 10:09 ` [PATCH 2/4] ARM: dts: stm32: add sdmmc2 & 3 nodes for STM32MP157 SoC Yann Gautier 2019-11-06 10:09 ` Yann Gautier 2019-11-06 10:09 ` [PATCH 3/4] ARM: dts: stm32: enable sdmmc2 node for stm32mp157c-ed1 board Yann Gautier 2019-11-06 10:09 ` Yann Gautier 2019-11-06 10:09 ` Yann Gautier [this message] 2019-11-06 10:09 ` [PATCH 4/4] ARM: dts: stm32: add sdmmc3 node for STM32MP1 boards Yann Gautier 2019-11-15 10:50 ` [PATCH 0/4] Update sdmmc nodes for STM32MP1 Alexandre Torgue 2019-11-15 10:50 ` Alexandre Torgue
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