* [PATCH 2/3] drm/rockchip: add ability to handle external dphys in mipi-dsi
@ 2019-11-06 11:26 ` Heiko Stuebner
0 siblings, 0 replies; 15+ messages in thread
From: Heiko Stuebner @ 2019-11-06 11:26 UTC (permalink / raw)
To: dri-devel, a.hajda
Cc: mark.rutland, devicetree, jernej.skrabec, jonas, linux-kernel,
narmstrong, philippe.cornu, yannick.fertre, linux-rockchip,
robh+dt, Laurent.pinchart, Heiko Stuebner, linux-arm-kernel,
christoph.muellner
While the common case is that the dsi controller uses an internal dphy,
accessed through the phy registers inside the dsi controller, there is
also the possibility to use a separate dphy from a different vendor.
One such case is the Rockchip px30 that uses a Innosilicon Mipi dphy,
so add the support for handling such a constellation, including the pll
also getting generated inside that external phy.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
---
.../display/rockchip/dw_mipi_dsi_rockchip.txt | 7 ++-
.../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 54 ++++++++++++++++++-
2 files changed, 57 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
index ce4c1fc9116c..8b25156a9dcf 100644
--- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -8,8 +8,9 @@ Required properties:
"rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
- reg: Represent the physical address range of the controller.
- interrupts: Represent the controller's interrupt to the CPU(s).
-- clocks, clock-names: Phandles to the controller's pll reference
- clock(ref) and APB clock(pclk). For RK3399, a phy config clock
+- clocks, clock-names: Phandles to the controller's and APB clock(pclk)
+ and either a pll reference clock(ref) (internal dphy) or pll clock(pll)
+ (when connected to an external phy). For RK3399, a phy config clock
(phy_cfg) and a grf clock(grf) are required. As described in [1].
- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
- ports: contain a port node with endpoint definitions as defined in [2].
@@ -18,6 +19,8 @@ Required properties:
- video port 1 for either a panel or subsequent encoder
Optional properties:
+- phys: from general PHY binding: the phandle for the PHY device.
+- phy-names: Should be "dphy" if phys references an external phy.
- power-domains: a phandle to mipi dsi power domain node.
- resets: list of phandle + reset specifier pairs, as described in [3].
- reset-names: string reset name, must be "apb".
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
index bc073ec5c183..99ec625e0448 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
@@ -12,6 +12,7 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of_device.h>
+#include <linux/phy/phy.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
@@ -223,6 +224,9 @@ struct dw_mipi_dsi_rockchip {
bool is_slave;
struct dw_mipi_dsi_rockchip *slave;
+ /* optional external dphy */
+ struct phy *phy;
+
unsigned int lane_mbps; /* per lane */
u16 input_div;
u16 feedback_div;
@@ -359,6 +363,9 @@ static int dw_mipi_dsi_phy_init(void *priv_data)
struct dw_mipi_dsi_rockchip *dsi = priv_data;
int ret, i, vco;
+ if (dsi->phy)
+ return 0;
+
/*
* Get vco from frequency(lane_mbps)
* vco frequency table
@@ -467,6 +474,27 @@ static int dw_mipi_dsi_phy_init(void *priv_data)
return ret;
}
+static void dw_mipi_dsi_phy_power_on(void *priv_data)
+{
+ struct dw_mipi_dsi_rockchip *dsi = priv_data;
+ int ret;
+
+ ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY);
+ if (ret) {
+ DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret);
+ return;
+ }
+
+ phy_power_on(dsi->phy);
+}
+
+static void dw_mipi_dsi_phy_power_off(void *priv_data)
+{
+ struct dw_mipi_dsi_rockchip *dsi = priv_data;
+
+ phy_power_off(dsi->phy);
+}
+
static int
dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
unsigned long mode_flags, u32 lanes, u32 format,
@@ -504,9 +532,21 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
"DPHY clock frequency is out of range\n");
}
- fin = clk_get_rate(dsi->pllref_clk);
fout = target_mbps * USEC_PER_SEC;
+ /* an external phy does have a controllable pll clk */
+ if (dsi->phy) {
+ fout = clk_round_rate(dsi->pllref_clk, fout);
+ clk_set_rate(dsi->pllref_clk, fout);
+
+ dsi->lane_mbps = target_mbps;
+ *lane_mbps = dsi->lane_mbps;
+
+ return 0;
+ }
+
+ fin = clk_get_rate(dsi->pllref_clk);
+
/* constraint: 5Mhz <= Fref / N <= 40MHz */
min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC);
max_prediv = fin / (5 * USEC_PER_SEC);
@@ -561,6 +601,8 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = {
.init = dw_mipi_dsi_phy_init,
+ .power_on = dw_mipi_dsi_phy_power_on,
+ .power_off = dw_mipi_dsi_phy_power_off,
.get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
};
@@ -920,7 +962,15 @@ static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
return -EINVAL;
}
- dsi->pllref_clk = devm_clk_get(dev, "ref");
+ /* try to get a possible external dphy */
+ dsi->phy = devm_phy_optional_get(dev, "dphy");
+ if (IS_ERR(dsi->phy)) {
+ ret = PTR_ERR(dsi->phy);
+ DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret);
+ return ret;
+ }
+
+ dsi->pllref_clk = devm_clk_get(dev, dsi->phy ? "pll" : "ref");
if (IS_ERR(dsi->pllref_clk)) {
ret = PTR_ERR(dsi->pllref_clk);
DRM_DEV_ERROR(dev,
--
2.23.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/3] drm/rockchip: add ability to handle external dphys in mipi-dsi
@ 2019-11-06 11:26 ` Heiko Stuebner
0 siblings, 0 replies; 15+ messages in thread
From: Heiko Stuebner @ 2019-11-06 11:26 UTC (permalink / raw)
To: dri-devel, a.hajda
Cc: mark.rutland, devicetree, jernej.skrabec, heiko, jonas,
linux-kernel, narmstrong, hjc, philippe.cornu, yannick.fertre,
linux-rockchip, robh+dt, Laurent.pinchart, Heiko Stuebner,
linux-arm-kernel, christoph.muellner
While the common case is that the dsi controller uses an internal dphy,
accessed through the phy registers inside the dsi controller, there is
also the possibility to use a separate dphy from a different vendor.
One such case is the Rockchip px30 that uses a Innosilicon Mipi dphy,
so add the support for handling such a constellation, including the pll
also getting generated inside that external phy.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
---
.../display/rockchip/dw_mipi_dsi_rockchip.txt | 7 ++-
.../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 54 ++++++++++++++++++-
2 files changed, 57 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
index ce4c1fc9116c..8b25156a9dcf 100644
--- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -8,8 +8,9 @@ Required properties:
"rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
- reg: Represent the physical address range of the controller.
- interrupts: Represent the controller's interrupt to the CPU(s).
-- clocks, clock-names: Phandles to the controller's pll reference
- clock(ref) and APB clock(pclk). For RK3399, a phy config clock
+- clocks, clock-names: Phandles to the controller's and APB clock(pclk)
+ and either a pll reference clock(ref) (internal dphy) or pll clock(pll)
+ (when connected to an external phy). For RK3399, a phy config clock
(phy_cfg) and a grf clock(grf) are required. As described in [1].
- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
- ports: contain a port node with endpoint definitions as defined in [2].
@@ -18,6 +19,8 @@ Required properties:
- video port 1 for either a panel or subsequent encoder
Optional properties:
+- phys: from general PHY binding: the phandle for the PHY device.
+- phy-names: Should be "dphy" if phys references an external phy.
- power-domains: a phandle to mipi dsi power domain node.
- resets: list of phandle + reset specifier pairs, as described in [3].
- reset-names: string reset name, must be "apb".
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
index bc073ec5c183..99ec625e0448 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
@@ -12,6 +12,7 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of_device.h>
+#include <linux/phy/phy.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
@@ -223,6 +224,9 @@ struct dw_mipi_dsi_rockchip {
bool is_slave;
struct dw_mipi_dsi_rockchip *slave;
+ /* optional external dphy */
+ struct phy *phy;
+
unsigned int lane_mbps; /* per lane */
u16 input_div;
u16 feedback_div;
@@ -359,6 +363,9 @@ static int dw_mipi_dsi_phy_init(void *priv_data)
struct dw_mipi_dsi_rockchip *dsi = priv_data;
int ret, i, vco;
+ if (dsi->phy)
+ return 0;
+
/*
* Get vco from frequency(lane_mbps)
* vco frequency table
@@ -467,6 +474,27 @@ static int dw_mipi_dsi_phy_init(void *priv_data)
return ret;
}
+static void dw_mipi_dsi_phy_power_on(void *priv_data)
+{
+ struct dw_mipi_dsi_rockchip *dsi = priv_data;
+ int ret;
+
+ ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY);
+ if (ret) {
+ DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret);
+ return;
+ }
+
+ phy_power_on(dsi->phy);
+}
+
+static void dw_mipi_dsi_phy_power_off(void *priv_data)
+{
+ struct dw_mipi_dsi_rockchip *dsi = priv_data;
+
+ phy_power_off(dsi->phy);
+}
+
static int
dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
unsigned long mode_flags, u32 lanes, u32 format,
@@ -504,9 +532,21 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
"DPHY clock frequency is out of range\n");
}
- fin = clk_get_rate(dsi->pllref_clk);
fout = target_mbps * USEC_PER_SEC;
+ /* an external phy does have a controllable pll clk */
+ if (dsi->phy) {
+ fout = clk_round_rate(dsi->pllref_clk, fout);
+ clk_set_rate(dsi->pllref_clk, fout);
+
+ dsi->lane_mbps = target_mbps;
+ *lane_mbps = dsi->lane_mbps;
+
+ return 0;
+ }
+
+ fin = clk_get_rate(dsi->pllref_clk);
+
/* constraint: 5Mhz <= Fref / N <= 40MHz */
min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC);
max_prediv = fin / (5 * USEC_PER_SEC);
@@ -561,6 +601,8 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = {
.init = dw_mipi_dsi_phy_init,
+ .power_on = dw_mipi_dsi_phy_power_on,
+ .power_off = dw_mipi_dsi_phy_power_off,
.get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
};
@@ -920,7 +962,15 @@ static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
return -EINVAL;
}
- dsi->pllref_clk = devm_clk_get(dev, "ref");
+ /* try to get a possible external dphy */
+ dsi->phy = devm_phy_optional_get(dev, "dphy");
+ if (IS_ERR(dsi->phy)) {
+ ret = PTR_ERR(dsi->phy);
+ DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret);
+ return ret;
+ }
+
+ dsi->pllref_clk = devm_clk_get(dev, dsi->phy ? "pll" : "ref");
if (IS_ERR(dsi->pllref_clk)) {
ret = PTR_ERR(dsi->pllref_clk);
DRM_DEV_ERROR(dev,
--
2.23.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 2/3] drm/rockchip: add ability to handle external dphys in mipi-dsi
2019-11-06 11:26 ` Heiko Stuebner
(?)
@ 2019-11-06 13:05 ` Laurent Pinchart
-1 siblings, 0 replies; 15+ messages in thread
From: Laurent Pinchart @ 2019-11-06 13:05 UTC (permalink / raw)
To: Heiko Stuebner
Cc: dri-devel, a.hajda, hjc, robh+dt, mark.rutland, narmstrong,
jonas, jernej.skrabec, philippe.cornu, yannick.fertre,
devicetree, linux-arm-kernel, linux-rockchip, linux-kernel,
heiko, christoph.muellner
Hi Heiko,
Thank you for the patch.
On Wed, Nov 06, 2019 at 12:26:49PM +0100, Heiko Stuebner wrote:
> While the common case is that the dsi controller uses an internal dphy,
> accessed through the phy registers inside the dsi controller, there is
> also the possibility to use a separate dphy from a different vendor.
>
> One such case is the Rockchip px30 that uses a Innosilicon Mipi dphy,
> so add the support for handling such a constellation, including the pll
> also getting generated inside that external phy.
>
> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> ---
> .../display/rockchip/dw_mipi_dsi_rockchip.txt | 7 ++-
> .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 54 ++++++++++++++++++-
> 2 files changed, 57 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
> index ce4c1fc9116c..8b25156a9dcf 100644
> --- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
> +++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
> @@ -8,8 +8,9 @@ Required properties:
> "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
> - reg: Represent the physical address range of the controller.
> - interrupts: Represent the controller's interrupt to the CPU(s).
> -- clocks, clock-names: Phandles to the controller's pll reference
> - clock(ref) and APB clock(pclk). For RK3399, a phy config clock
> +- clocks, clock-names: Phandles to the controller's and APB clock(pclk)
> + and either a pll reference clock(ref) (internal dphy) or pll clock(pll)
> + (when connected to an external phy). For RK3399, a phy config clock
Why does external PHY clock need to be specified here ? Shouldn't it be
handled by the PHY instead ?
> (phy_cfg) and a grf clock(grf) are required. As described in [1].
> - rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
> - ports: contain a port node with endpoint definitions as defined in [2].
> @@ -18,6 +19,8 @@ Required properties:
> - video port 1 for either a panel or subsequent encoder
>
> Optional properties:
> +- phys: from general PHY binding: the phandle for the PHY device.
> +- phy-names: Should be "dphy" if phys references an external phy.
> - power-domains: a phandle to mipi dsi power domain node.
> - resets: list of phandle + reset specifier pairs, as described in [3].
> - reset-names: string reset name, must be "apb".
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> index bc073ec5c183..99ec625e0448 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> @@ -12,6 +12,7 @@
> #include <linux/mfd/syscon.h>
> #include <linux/module.h>
> #include <linux/of_device.h>
> +#include <linux/phy/phy.h>
> #include <linux/pm_runtime.h>
> #include <linux/regmap.h>
>
> @@ -223,6 +224,9 @@ struct dw_mipi_dsi_rockchip {
> bool is_slave;
> struct dw_mipi_dsi_rockchip *slave;
>
> + /* optional external dphy */
> + struct phy *phy;
> +
> unsigned int lane_mbps; /* per lane */
> u16 input_div;
> u16 feedback_div;
> @@ -359,6 +363,9 @@ static int dw_mipi_dsi_phy_init(void *priv_data)
> struct dw_mipi_dsi_rockchip *dsi = priv_data;
> int ret, i, vco;
>
> + if (dsi->phy)
> + return 0;
> +
> /*
> * Get vco from frequency(lane_mbps)
> * vco frequency table
> @@ -467,6 +474,27 @@ static int dw_mipi_dsi_phy_init(void *priv_data)
> return ret;
> }
>
> +static void dw_mipi_dsi_phy_power_on(void *priv_data)
> +{
> + struct dw_mipi_dsi_rockchip *dsi = priv_data;
> + int ret;
> +
> + ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY);
> + if (ret) {
> + DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret);
> + return;
> + }
> +
> + phy_power_on(dsi->phy);
> +}
> +
> +static void dw_mipi_dsi_phy_power_off(void *priv_data)
> +{
> + struct dw_mipi_dsi_rockchip *dsi = priv_data;
> +
> + phy_power_off(dsi->phy);
> +}
> +
> static int
> dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
> unsigned long mode_flags, u32 lanes, u32 format,
> @@ -504,9 +532,21 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
> "DPHY clock frequency is out of range\n");
> }
>
> - fin = clk_get_rate(dsi->pllref_clk);
> fout = target_mbps * USEC_PER_SEC;
>
> + /* an external phy does have a controllable pll clk */
> + if (dsi->phy) {
> + fout = clk_round_rate(dsi->pllref_clk, fout);
> + clk_set_rate(dsi->pllref_clk, fout);
> +
> + dsi->lane_mbps = target_mbps;
> + *lane_mbps = dsi->lane_mbps;
> +
> + return 0;
> + }
> +
> + fin = clk_get_rate(dsi->pllref_clk);
> +
> /* constraint: 5Mhz <= Fref / N <= 40MHz */
> min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC);
> max_prediv = fin / (5 * USEC_PER_SEC);
> @@ -561,6 +601,8 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
>
> static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = {
> .init = dw_mipi_dsi_phy_init,
> + .power_on = dw_mipi_dsi_phy_power_on,
> + .power_off = dw_mipi_dsi_phy_power_off,
> .get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
> };
>
> @@ -920,7 +962,15 @@ static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
> return -EINVAL;
> }
>
> - dsi->pllref_clk = devm_clk_get(dev, "ref");
> + /* try to get a possible external dphy */
> + dsi->phy = devm_phy_optional_get(dev, "dphy");
> + if (IS_ERR(dsi->phy)) {
> + ret = PTR_ERR(dsi->phy);
> + DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret);
> + return ret;
> + }
> +
> + dsi->pllref_clk = devm_clk_get(dev, dsi->phy ? "pll" : "ref");
> if (IS_ERR(dsi->pllref_clk)) {
> ret = PTR_ERR(dsi->pllref_clk);
> DRM_DEV_ERROR(dev,
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/3] drm/rockchip: add ability to handle external dphys in mipi-dsi
@ 2019-11-06 13:05 ` Laurent Pinchart
0 siblings, 0 replies; 15+ messages in thread
From: Laurent Pinchart @ 2019-11-06 13:05 UTC (permalink / raw)
To: Heiko Stuebner
Cc: mark.rutland, devicetree, jernej.skrabec, narmstrong,
linux-kernel, jonas, dri-devel, philippe.cornu, yannick.fertre,
robh+dt, linux-rockchip, linux-arm-kernel, christoph.muellner
Hi Heiko,
Thank you for the patch.
On Wed, Nov 06, 2019 at 12:26:49PM +0100, Heiko Stuebner wrote:
> While the common case is that the dsi controller uses an internal dphy,
> accessed through the phy registers inside the dsi controller, there is
> also the possibility to use a separate dphy from a different vendor.
>
> One such case is the Rockchip px30 that uses a Innosilicon Mipi dphy,
> so add the support for handling such a constellation, including the pll
> also getting generated inside that external phy.
>
> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> ---
> .../display/rockchip/dw_mipi_dsi_rockchip.txt | 7 ++-
> .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 54 ++++++++++++++++++-
> 2 files changed, 57 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
> index ce4c1fc9116c..8b25156a9dcf 100644
> --- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
> +++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
> @@ -8,8 +8,9 @@ Required properties:
> "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
> - reg: Represent the physical address range of the controller.
> - interrupts: Represent the controller's interrupt to the CPU(s).
> -- clocks, clock-names: Phandles to the controller's pll reference
> - clock(ref) and APB clock(pclk). For RK3399, a phy config clock
> +- clocks, clock-names: Phandles to the controller's and APB clock(pclk)
> + and either a pll reference clock(ref) (internal dphy) or pll clock(pll)
> + (when connected to an external phy). For RK3399, a phy config clock
Why does external PHY clock need to be specified here ? Shouldn't it be
handled by the PHY instead ?
> (phy_cfg) and a grf clock(grf) are required. As described in [1].
> - rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
> - ports: contain a port node with endpoint definitions as defined in [2].
> @@ -18,6 +19,8 @@ Required properties:
> - video port 1 for either a panel or subsequent encoder
>
> Optional properties:
> +- phys: from general PHY binding: the phandle for the PHY device.
> +- phy-names: Should be "dphy" if phys references an external phy.
> - power-domains: a phandle to mipi dsi power domain node.
> - resets: list of phandle + reset specifier pairs, as described in [3].
> - reset-names: string reset name, must be "apb".
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> index bc073ec5c183..99ec625e0448 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> @@ -12,6 +12,7 @@
> #include <linux/mfd/syscon.h>
> #include <linux/module.h>
> #include <linux/of_device.h>
> +#include <linux/phy/phy.h>
> #include <linux/pm_runtime.h>
> #include <linux/regmap.h>
>
> @@ -223,6 +224,9 @@ struct dw_mipi_dsi_rockchip {
> bool is_slave;
> struct dw_mipi_dsi_rockchip *slave;
>
> + /* optional external dphy */
> + struct phy *phy;
> +
> unsigned int lane_mbps; /* per lane */
> u16 input_div;
> u16 feedback_div;
> @@ -359,6 +363,9 @@ static int dw_mipi_dsi_phy_init(void *priv_data)
> struct dw_mipi_dsi_rockchip *dsi = priv_data;
> int ret, i, vco;
>
> + if (dsi->phy)
> + return 0;
> +
> /*
> * Get vco from frequency(lane_mbps)
> * vco frequency table
> @@ -467,6 +474,27 @@ static int dw_mipi_dsi_phy_init(void *priv_data)
> return ret;
> }
>
> +static void dw_mipi_dsi_phy_power_on(void *priv_data)
> +{
> + struct dw_mipi_dsi_rockchip *dsi = priv_data;
> + int ret;
> +
> + ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY);
> + if (ret) {
> + DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret);
> + return;
> + }
> +
> + phy_power_on(dsi->phy);
> +}
> +
> +static void dw_mipi_dsi_phy_power_off(void *priv_data)
> +{
> + struct dw_mipi_dsi_rockchip *dsi = priv_data;
> +
> + phy_power_off(dsi->phy);
> +}
> +
> static int
> dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
> unsigned long mode_flags, u32 lanes, u32 format,
> @@ -504,9 +532,21 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
> "DPHY clock frequency is out of range\n");
> }
>
> - fin = clk_get_rate(dsi->pllref_clk);
> fout = target_mbps * USEC_PER_SEC;
>
> + /* an external phy does have a controllable pll clk */
> + if (dsi->phy) {
> + fout = clk_round_rate(dsi->pllref_clk, fout);
> + clk_set_rate(dsi->pllref_clk, fout);
> +
> + dsi->lane_mbps = target_mbps;
> + *lane_mbps = dsi->lane_mbps;
> +
> + return 0;
> + }
> +
> + fin = clk_get_rate(dsi->pllref_clk);
> +
> /* constraint: 5Mhz <= Fref / N <= 40MHz */
> min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC);
> max_prediv = fin / (5 * USEC_PER_SEC);
> @@ -561,6 +601,8 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
>
> static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = {
> .init = dw_mipi_dsi_phy_init,
> + .power_on = dw_mipi_dsi_phy_power_on,
> + .power_off = dw_mipi_dsi_phy_power_off,
> .get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
> };
>
> @@ -920,7 +962,15 @@ static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
> return -EINVAL;
> }
>
> - dsi->pllref_clk = devm_clk_get(dev, "ref");
> + /* try to get a possible external dphy */
> + dsi->phy = devm_phy_optional_get(dev, "dphy");
> + if (IS_ERR(dsi->phy)) {
> + ret = PTR_ERR(dsi->phy);
> + DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret);
> + return ret;
> + }
> +
> + dsi->pllref_clk = devm_clk_get(dev, dsi->phy ? "pll" : "ref");
> if (IS_ERR(dsi->pllref_clk)) {
> ret = PTR_ERR(dsi->pllref_clk);
> DRM_DEV_ERROR(dev,
--
Regards,
Laurent Pinchart
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/3] drm/rockchip: add ability to handle external dphys in mipi-dsi
@ 2019-11-06 13:05 ` Laurent Pinchart
0 siblings, 0 replies; 15+ messages in thread
From: Laurent Pinchart @ 2019-11-06 13:05 UTC (permalink / raw)
To: Heiko Stuebner
Cc: mark.rutland, devicetree, jernej.skrabec, heiko, narmstrong,
linux-kernel, jonas, hjc, dri-devel, philippe.cornu,
yannick.fertre, a.hajda, robh+dt, linux-rockchip,
linux-arm-kernel, christoph.muellner
Hi Heiko,
Thank you for the patch.
On Wed, Nov 06, 2019 at 12:26:49PM +0100, Heiko Stuebner wrote:
> While the common case is that the dsi controller uses an internal dphy,
> accessed through the phy registers inside the dsi controller, there is
> also the possibility to use a separate dphy from a different vendor.
>
> One such case is the Rockchip px30 that uses a Innosilicon Mipi dphy,
> so add the support for handling such a constellation, including the pll
> also getting generated inside that external phy.
>
> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> ---
> .../display/rockchip/dw_mipi_dsi_rockchip.txt | 7 ++-
> .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 54 ++++++++++++++++++-
> 2 files changed, 57 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
> index ce4c1fc9116c..8b25156a9dcf 100644
> --- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
> +++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
> @@ -8,8 +8,9 @@ Required properties:
> "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
> - reg: Represent the physical address range of the controller.
> - interrupts: Represent the controller's interrupt to the CPU(s).
> -- clocks, clock-names: Phandles to the controller's pll reference
> - clock(ref) and APB clock(pclk). For RK3399, a phy config clock
> +- clocks, clock-names: Phandles to the controller's and APB clock(pclk)
> + and either a pll reference clock(ref) (internal dphy) or pll clock(pll)
> + (when connected to an external phy). For RK3399, a phy config clock
Why does external PHY clock need to be specified here ? Shouldn't it be
handled by the PHY instead ?
> (phy_cfg) and a grf clock(grf) are required. As described in [1].
> - rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
> - ports: contain a port node with endpoint definitions as defined in [2].
> @@ -18,6 +19,8 @@ Required properties:
> - video port 1 for either a panel or subsequent encoder
>
> Optional properties:
> +- phys: from general PHY binding: the phandle for the PHY device.
> +- phy-names: Should be "dphy" if phys references an external phy.
> - power-domains: a phandle to mipi dsi power domain node.
> - resets: list of phandle + reset specifier pairs, as described in [3].
> - reset-names: string reset name, must be "apb".
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> index bc073ec5c183..99ec625e0448 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> @@ -12,6 +12,7 @@
> #include <linux/mfd/syscon.h>
> #include <linux/module.h>
> #include <linux/of_device.h>
> +#include <linux/phy/phy.h>
> #include <linux/pm_runtime.h>
> #include <linux/regmap.h>
>
> @@ -223,6 +224,9 @@ struct dw_mipi_dsi_rockchip {
> bool is_slave;
> struct dw_mipi_dsi_rockchip *slave;
>
> + /* optional external dphy */
> + struct phy *phy;
> +
> unsigned int lane_mbps; /* per lane */
> u16 input_div;
> u16 feedback_div;
> @@ -359,6 +363,9 @@ static int dw_mipi_dsi_phy_init(void *priv_data)
> struct dw_mipi_dsi_rockchip *dsi = priv_data;
> int ret, i, vco;
>
> + if (dsi->phy)
> + return 0;
> +
> /*
> * Get vco from frequency(lane_mbps)
> * vco frequency table
> @@ -467,6 +474,27 @@ static int dw_mipi_dsi_phy_init(void *priv_data)
> return ret;
> }
>
> +static void dw_mipi_dsi_phy_power_on(void *priv_data)
> +{
> + struct dw_mipi_dsi_rockchip *dsi = priv_data;
> + int ret;
> +
> + ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY);
> + if (ret) {
> + DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret);
> + return;
> + }
> +
> + phy_power_on(dsi->phy);
> +}
> +
> +static void dw_mipi_dsi_phy_power_off(void *priv_data)
> +{
> + struct dw_mipi_dsi_rockchip *dsi = priv_data;
> +
> + phy_power_off(dsi->phy);
> +}
> +
> static int
> dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
> unsigned long mode_flags, u32 lanes, u32 format,
> @@ -504,9 +532,21 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
> "DPHY clock frequency is out of range\n");
> }
>
> - fin = clk_get_rate(dsi->pllref_clk);
> fout = target_mbps * USEC_PER_SEC;
>
> + /* an external phy does have a controllable pll clk */
> + if (dsi->phy) {
> + fout = clk_round_rate(dsi->pllref_clk, fout);
> + clk_set_rate(dsi->pllref_clk, fout);
> +
> + dsi->lane_mbps = target_mbps;
> + *lane_mbps = dsi->lane_mbps;
> +
> + return 0;
> + }
> +
> + fin = clk_get_rate(dsi->pllref_clk);
> +
> /* constraint: 5Mhz <= Fref / N <= 40MHz */
> min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC);
> max_prediv = fin / (5 * USEC_PER_SEC);
> @@ -561,6 +601,8 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
>
> static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = {
> .init = dw_mipi_dsi_phy_init,
> + .power_on = dw_mipi_dsi_phy_power_on,
> + .power_off = dw_mipi_dsi_phy_power_off,
> .get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
> };
>
> @@ -920,7 +962,15 @@ static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
> return -EINVAL;
> }
>
> - dsi->pllref_clk = devm_clk_get(dev, "ref");
> + /* try to get a possible external dphy */
> + dsi->phy = devm_phy_optional_get(dev, "dphy");
> + if (IS_ERR(dsi->phy)) {
> + ret = PTR_ERR(dsi->phy);
> + DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret);
> + return ret;
> + }
> +
> + dsi->pllref_clk = devm_clk_get(dev, dsi->phy ? "pll" : "ref");
> if (IS_ERR(dsi->pllref_clk)) {
> ret = PTR_ERR(dsi->pllref_clk);
> DRM_DEV_ERROR(dev,
--
Regards,
Laurent Pinchart
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/3] drm/rockchip: add ability to handle external dphys in mipi-dsi
2019-11-06 13:05 ` Laurent Pinchart
(?)
@ 2019-11-07 19:10 ` Heiko Stuebner
-1 siblings, 0 replies; 15+ messages in thread
From: Heiko Stuebner @ 2019-11-07 19:10 UTC (permalink / raw)
To: Laurent Pinchart
Cc: dri-devel, a.hajda, hjc, robh+dt, mark.rutland, narmstrong,
jonas, jernej.skrabec, philippe.cornu, yannick.fertre,
devicetree, linux-arm-kernel, linux-rockchip, linux-kernel,
christoph.muellner
Hi Laurent,
Am Mittwoch, 6. November 2019, 14:05:57 CET schrieb Laurent Pinchart:
> On Wed, Nov 06, 2019 at 12:26:49PM +0100, Heiko Stuebner wrote:
> > While the common case is that the dsi controller uses an internal dphy,
> > accessed through the phy registers inside the dsi controller, there is
> > also the possibility to use a separate dphy from a different vendor.
> >
> > One such case is the Rockchip px30 that uses a Innosilicon Mipi dphy,
> > so add the support for handling such a constellation, including the pll
> > also getting generated inside that external phy.
> >
> > Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> > ---
> > .../display/rockchip/dw_mipi_dsi_rockchip.txt | 7 ++-
> > .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 54 ++++++++++++++++++-
> > 2 files changed, 57 insertions(+), 4 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
> > index ce4c1fc9116c..8b25156a9dcf 100644
> > --- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
> > +++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
> > @@ -8,8 +8,9 @@ Required properties:
> > "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
> > - reg: Represent the physical address range of the controller.
> > - interrupts: Represent the controller's interrupt to the CPU(s).
> > -- clocks, clock-names: Phandles to the controller's pll reference
> > - clock(ref) and APB clock(pclk). For RK3399, a phy config clock
> > +- clocks, clock-names: Phandles to the controller's and APB clock(pclk)
> > + and either a pll reference clock(ref) (internal dphy) or pll clock(pll)
> > + (when connected to an external phy). For RK3399, a phy config clock
>
> Why does external PHY clock need to be specified here ? Shouldn't it be
> handled by the PHY instead ?
You're completely right and it seems I didn't "see the forest for the trees",
as there actually exists the phy_configure_* structs to transfer parameters
to an external phy in a correct way.
I'll revise my approach (and the phy driver) accordingly.
Thanks for the push in the right direction :-)
Heiko
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/3] drm/rockchip: add ability to handle external dphys in mipi-dsi
@ 2019-11-07 19:10 ` Heiko Stuebner
0 siblings, 0 replies; 15+ messages in thread
From: Heiko Stuebner @ 2019-11-07 19:10 UTC (permalink / raw)
To: Laurent Pinchart
Cc: mark.rutland, devicetree, jernej.skrabec, narmstrong,
linux-kernel, jonas, dri-devel, philippe.cornu, yannick.fertre,
robh+dt, linux-rockchip, linux-arm-kernel, christoph.muellner
Hi Laurent,
Am Mittwoch, 6. November 2019, 14:05:57 CET schrieb Laurent Pinchart:
> On Wed, Nov 06, 2019 at 12:26:49PM +0100, Heiko Stuebner wrote:
> > While the common case is that the dsi controller uses an internal dphy,
> > accessed through the phy registers inside the dsi controller, there is
> > also the possibility to use a separate dphy from a different vendor.
> >
> > One such case is the Rockchip px30 that uses a Innosilicon Mipi dphy,
> > so add the support for handling such a constellation, including the pll
> > also getting generated inside that external phy.
> >
> > Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> > ---
> > .../display/rockchip/dw_mipi_dsi_rockchip.txt | 7 ++-
> > .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 54 ++++++++++++++++++-
> > 2 files changed, 57 insertions(+), 4 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
> > index ce4c1fc9116c..8b25156a9dcf 100644
> > --- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
> > +++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
> > @@ -8,8 +8,9 @@ Required properties:
> > "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
> > - reg: Represent the physical address range of the controller.
> > - interrupts: Represent the controller's interrupt to the CPU(s).
> > -- clocks, clock-names: Phandles to the controller's pll reference
> > - clock(ref) and APB clock(pclk). For RK3399, a phy config clock
> > +- clocks, clock-names: Phandles to the controller's and APB clock(pclk)
> > + and either a pll reference clock(ref) (internal dphy) or pll clock(pll)
> > + (when connected to an external phy). For RK3399, a phy config clock
>
> Why does external PHY clock need to be specified here ? Shouldn't it be
> handled by the PHY instead ?
You're completely right and it seems I didn't "see the forest for the trees",
as there actually exists the phy_configure_* structs to transfer parameters
to an external phy in a correct way.
I'll revise my approach (and the phy driver) accordingly.
Thanks for the push in the right direction :-)
Heiko
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/3] drm/rockchip: add ability to handle external dphys in mipi-dsi
@ 2019-11-07 19:10 ` Heiko Stuebner
0 siblings, 0 replies; 15+ messages in thread
From: Heiko Stuebner @ 2019-11-07 19:10 UTC (permalink / raw)
To: Laurent Pinchart
Cc: mark.rutland, devicetree, jernej.skrabec, narmstrong,
linux-kernel, jonas, hjc, dri-devel, philippe.cornu,
yannick.fertre, a.hajda, robh+dt, linux-rockchip,
linux-arm-kernel, christoph.muellner
Hi Laurent,
Am Mittwoch, 6. November 2019, 14:05:57 CET schrieb Laurent Pinchart:
> On Wed, Nov 06, 2019 at 12:26:49PM +0100, Heiko Stuebner wrote:
> > While the common case is that the dsi controller uses an internal dphy,
> > accessed through the phy registers inside the dsi controller, there is
> > also the possibility to use a separate dphy from a different vendor.
> >
> > One such case is the Rockchip px30 that uses a Innosilicon Mipi dphy,
> > so add the support for handling such a constellation, including the pll
> > also getting generated inside that external phy.
> >
> > Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> > ---
> > .../display/rockchip/dw_mipi_dsi_rockchip.txt | 7 ++-
> > .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 54 ++++++++++++++++++-
> > 2 files changed, 57 insertions(+), 4 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
> > index ce4c1fc9116c..8b25156a9dcf 100644
> > --- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
> > +++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
> > @@ -8,8 +8,9 @@ Required properties:
> > "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
> > - reg: Represent the physical address range of the controller.
> > - interrupts: Represent the controller's interrupt to the CPU(s).
> > -- clocks, clock-names: Phandles to the controller's pll reference
> > - clock(ref) and APB clock(pclk). For RK3399, a phy config clock
> > +- clocks, clock-names: Phandles to the controller's and APB clock(pclk)
> > + and either a pll reference clock(ref) (internal dphy) or pll clock(pll)
> > + (when connected to an external phy). For RK3399, a phy config clock
>
> Why does external PHY clock need to be specified here ? Shouldn't it be
> handled by the PHY instead ?
You're completely right and it seems I didn't "see the forest for the trees",
as there actually exists the phy_configure_* structs to transfer parameters
to an external phy in a correct way.
I'll revise my approach (and the phy driver) accordingly.
Thanks for the push in the right direction :-)
Heiko
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 15+ messages in thread