* [PATCH] mtd: spinand: micron: add support for MT29F1G01AAADD
@ 2019-11-08 7:48 Marco Felsch
2019-11-18 10:16 ` [EXT] " Shivamurthy Shastri (sshivamurthy)
0 siblings, 1 reply; 14+ messages in thread
From: Marco Felsch @ 2019-11-08 7:48 UTC (permalink / raw)
To: miquel.raynal, frieder.schrempf, bbrezillon, richard
Cc: marek.vasut, sshivamurthy, linux-mtd, kernel, Peter Pan
The MT29F1G01AAADD is a single die, SLC based SPI NAND. It has a
capacity of 1Gb and supports 4-bit ECC. The datasheet can be found [1].
Unfortunatly the linked device is marked as EoL, but I will expect that
the MT29F1G01AAADDH4-ITX behaves the same way.
[1] https://datasheet.octopart.com/MT29F1G01AAADDH4-IT:D-Micron-datasheet-11572380.pdf
Cc: Peter Pan <peterpandong@micron.com>
Cc: sshivamurthy@micron.com
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
v2:
- Convert 0x10 into 16 for ooblayout description
- Don't break web link within commit message
drivers/mtd/nand/spi/micron.c | 68 +++++++++++++++++++++++++++++++++++
1 file changed, 68 insertions(+)
diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
index 7d7b1f7fcf71..70e278759bd3 100644
--- a/drivers/mtd/nand/spi/micron.c
+++ b/drivers/mtd/nand/spi/micron.c
@@ -34,6 +34,18 @@ static SPINAND_OP_VARIANTS(update_cache_variants,
SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
SPINAND_PROG_LOAD(false, 0, NULL, 0));
+static SPINAND_OP_VARIANTS(read_cache_variants_mt29f1g01aaadd,
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(write_cache_variants_mt29f1g01aaadd,
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(update_cache_variants_mt29f1g01aaadd,
+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
static int mt29f2g01abagd_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
@@ -90,6 +102,52 @@ static int mt29f2g01abagd_ecc_get_status(struct spinand_device *spinand,
return -EINVAL;
}
+static int mt29f1g01aaadd_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ region->offset = (section * 16) + 8;
+ region->length = 8;
+
+ return 0;
+}
+
+static int mt29f1g01aaadd_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ /* 2 bytes for the BBM + 2 bytes to skip non-ecc memory */
+ region->offset = (section * 16) + 4;
+ region->length = 4;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops mt29f1g01aaadd_ooblayout = {
+ .ecc = mt29f1g01aaadd_ooblayout_ecc,
+ .free = mt29f1g01aaadd_ooblayout_free,
+};
+
+static int mt29f1g01aaadd_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
+ switch (status & STATUS_ECC_MASK) {
+ case STATUS_ECC_NO_BITFLIPS:
+ return 0;
+ case STATUS_ECC_HAS_BITFLIPS:
+ /* 1 to 4-bit error detected and corrected */
+ return 4;
+ case STATUS_ECC_UNCOR_ERROR:
+ return -EBADMSG;
+ default:
+ return -EINVAL;
+ }
+}
+
static const struct spinand_info micron_spinand_table[] = {
SPINAND_INFO("MT29F2G01ABAGD", 0x24,
NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
@@ -100,6 +158,16 @@ static const struct spinand_info micron_spinand_table[] = {
0,
SPINAND_ECCINFO(&mt29f2g01abagd_ooblayout,
mt29f2g01abagd_ecc_get_status)),
+ SPINAND_INFO("MT29F1G01AAADD", 0x12,
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 2, 1, 1),
+ NAND_ECCREQ(4, 2048),
+ SPINAND_INFO_OP_VARIANTS(
+ &read_cache_variants_mt29f1g01aaadd,
+ &write_cache_variants_mt29f1g01aaadd,
+ &update_cache_variants_mt29f1g01aaadd),
+ 0,
+ SPINAND_ECCINFO(&mt29f1g01aaadd_ooblayout,
+ mt29f1g01aaadd_ecc_get_status)),
};
static int micron_spinand_detect(struct spinand_device *spinand)
--
2.20.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread* RE: [EXT] [PATCH] mtd: spinand: micron: add support for MT29F1G01AAADD
2019-11-08 7:48 [PATCH] mtd: spinand: micron: add support for MT29F1G01AAADD Marco Felsch
@ 2019-11-18 10:16 ` Shivamurthy Shastri (sshivamurthy)
2019-11-18 14:09 ` Marco Felsch
0 siblings, 1 reply; 14+ messages in thread
From: Shivamurthy Shastri (sshivamurthy) @ 2019-11-18 10:16 UTC (permalink / raw)
To: Marco Felsch
Cc: bbrezillon, richard, frieder.schrempf, marek.vasut, linux-mtd,
kernel, miquel.raynal
Hi Marco,
>
> The MT29F1G01AAADD is a single die, SLC based SPI NAND. It has a
> capacity of 1Gb and supports 4-bit ECC. The datasheet can be found [1].
>
> Unfortunatly the linked device is marked as EoL, but I will expect that
> the MT29F1G01AAADDH4-ITX behaves the same way.
>
> [1]
> https://nam01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fdata
> sheet.octopart.com%2FMT29F1G01AAADDH4-IT%3AD-Micron-datasheet-
> 11572380.pdf&data=02%7C01%7Csshivamurthy%40micron.com%7C21a
> da5347828461980a408d7642021a9%7Cf38a5ecd28134862b11bac1d563c806f%
> 7C0%7C1%7C637087961499818902&sdata=%2Fh%2FHfUoSnl8qqSVClVfp
> ykvi3UiDEZFTn%2BVCsAf9IaM%3D&reserved=0
>
> Cc: Peter Pan <peterpandong@micron.com>
> Cc: sshivamurthy@micron.com
> Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
> ---
> v2:
> - Convert 0x10 into 16 for ooblayout description
> - Don't break web link within commit message
>
> drivers/mtd/nand/spi/micron.c | 68
> +++++++++++++++++++++++++++++++++++
> 1 file changed, 68 insertions(+)
>
> diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
> index 7d7b1f7fcf71..70e278759bd3 100644
> --- a/drivers/mtd/nand/spi/micron.c
> +++ b/drivers/mtd/nand/spi/micron.c
> @@ -34,6 +34,18 @@ static
> SPINAND_OP_VARIANTS(update_cache_variants,
> SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
> SPINAND_PROG_LOAD(false, 0, NULL, 0));
>
> +static SPINAND_OP_VARIANTS(read_cache_variants_mt29f1g01aaadd,
> + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
> + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
> + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL,
> 0),
> + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL,
> 0));
> +
> +static SPINAND_OP_VARIANTS(write_cache_variants_mt29f1g01aaadd,
> + SPINAND_PROG_LOAD(true, 0, NULL, 0));
> +
> +static SPINAND_OP_VARIANTS(update_cache_variants_mt29f1g01aaadd,
> + SPINAND_PROG_LOAD(false, 0, NULL, 0));
> +
> static int mt29f2g01abagd_ooblayout_ecc(struct mtd_info *mtd, int section,
> struct mtd_oob_region *region)
> {
> @@ -90,6 +102,52 @@ static int mt29f2g01abagd_ecc_get_status(struct
> spinand_device *spinand,
> return -EINVAL;
> }
>
> +static int mt29f1g01aaadd_ooblayout_ecc(struct mtd_info *mtd, int
> section,
> + struct mtd_oob_region *region)
> +{
> + if (section > 3)
> + return -ERANGE;
> +
> + region->offset = (section * 16) + 8;
> + region->length = 8;
> +
> + return 0;
> +}
> +
> +static int mt29f1g01aaadd_ooblayout_free(struct mtd_info *mtd, int
> section,
> + struct mtd_oob_region *region)
> +{
> + if (section > 3)
> + return -ERANGE;
> +
> + /* 2 bytes for the BBM + 2 bytes to skip non-ecc memory */
> + region->offset = (section * 16) + 4;
> + region->length = 4;
> +
> + return 0;
> +}
> +
> +static const struct mtd_ooblayout_ops mt29f1g01aaadd_ooblayout = {
> + .ecc = mt29f1g01aaadd_ooblayout_ecc,
> + .free = mt29f1g01aaadd_ooblayout_free,
> +};
> +
> +static int mt29f1g01aaadd_ecc_get_status(struct spinand_device *spinand,
> + u8 status)
> +{
> + switch (status & STATUS_ECC_MASK) {
> + case STATUS_ECC_NO_BITFLIPS:
> + return 0;
> + case STATUS_ECC_HAS_BITFLIPS:
> + /* 1 to 4-bit error detected and corrected */
> + return 4;
> + case STATUS_ECC_UNCOR_ERROR:
> + return -EBADMSG;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> static const struct spinand_info micron_spinand_table[] = {
> SPINAND_INFO("MT29F2G01ABAGD", 0x24,
> NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
> @@ -100,6 +158,16 @@ static const struct spinand_info
> micron_spinand_table[] = {
> 0,
> SPINAND_ECCINFO(&mt29f2g01abagd_ooblayout,
> mt29f2g01abagd_ecc_get_status)),
> + SPINAND_INFO("MT29F1G01AAADD", 0x12,
> + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 2, 1, 1),
> + NAND_ECCREQ(4, 2048),
I think, this should be NAND_ECCREQ(4, 512).
> + SPINAND_INFO_OP_VARIANTS(
> +
> &read_cache_variants_mt29f1g01aaadd,
> +
> &write_cache_variants_mt29f1g01aaadd,
> +
> &update_cache_variants_mt29f1g01aaadd),
> + 0,
> + SPINAND_ECCINFO(&mt29f1g01aaadd_ooblayout,
> + mt29f1g01aaadd_ecc_get_status)),
> };
>
> static int micron_spinand_detect(struct spinand_device *spinand)
> --
> 2.20.1
Thanks,
Shiva
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Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [EXT] [PATCH] mtd: spinand: micron: add support for MT29F1G01AAADD
2019-11-18 10:16 ` [EXT] " Shivamurthy Shastri (sshivamurthy)
@ 2019-11-18 14:09 ` Marco Felsch
2019-11-18 17:39 ` Boris Brezillon
0 siblings, 1 reply; 14+ messages in thread
From: Marco Felsch @ 2019-11-18 14:09 UTC (permalink / raw)
To: Shivamurthy Shastri (sshivamurthy)
Cc: bbrezillon, richard, frieder.schrempf, marek.vasut, linux-mtd,
kernel, miquel.raynal
Hi Shiva,
On 19-11-18 10:16, Shivamurthy Shastri (sshivamurthy) wrote:
> Hi Marco,
>
> >
> > The MT29F1G01AAADD is a single die, SLC based SPI NAND. It has a
> > capacity of 1Gb and supports 4-bit ECC. The datasheet can be found [1].
> >
> > Unfortunatly the linked device is marked as EoL, but I will expect that
> > the MT29F1G01AAADDH4-ITX behaves the same way.
> >
> > [1]
> > https://nam01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fdata
> > sheet.octopart.com%2FMT29F1G01AAADDH4-IT%3AD-Micron-datasheet-
> > 11572380.pdf&data=02%7C01%7Csshivamurthy%40micron.com%7C21a
> > da5347828461980a408d7642021a9%7Cf38a5ecd28134862b11bac1d563c806f%
> > 7C0%7C1%7C637087961499818902&sdata=%2Fh%2FHfUoSnl8qqSVClVfp
> > ykvi3UiDEZFTn%2BVCsAf9IaM%3D&reserved=0
> >
> > Cc: Peter Pan <peterpandong@micron.com>
> > Cc: sshivamurthy@micron.com
> > Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
> > ---
> > v2:
> > - Convert 0x10 into 16 for ooblayout description
> > - Don't break web link within commit message
> >
> > drivers/mtd/nand/spi/micron.c | 68
> > +++++++++++++++++++++++++++++++++++
> > 1 file changed, 68 insertions(+)
> >
> > diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
> > index 7d7b1f7fcf71..70e278759bd3 100644
> > --- a/drivers/mtd/nand/spi/micron.c
> > +++ b/drivers/mtd/nand/spi/micron.c
> > @@ -34,6 +34,18 @@ static
> > SPINAND_OP_VARIANTS(update_cache_variants,
> > SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
> > SPINAND_PROG_LOAD(false, 0, NULL, 0));
> >
> > +static SPINAND_OP_VARIANTS(read_cache_variants_mt29f1g01aaadd,
> > + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
> > + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
> > + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL,
> > 0),
> > + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL,
> > 0));
> > +
> > +static SPINAND_OP_VARIANTS(write_cache_variants_mt29f1g01aaadd,
> > + SPINAND_PROG_LOAD(true, 0, NULL, 0));
> > +
> > +static SPINAND_OP_VARIANTS(update_cache_variants_mt29f1g01aaadd,
> > + SPINAND_PROG_LOAD(false, 0, NULL, 0));
> > +
> > static int mt29f2g01abagd_ooblayout_ecc(struct mtd_info *mtd, int section,
> > struct mtd_oob_region *region)
> > {
> > @@ -90,6 +102,52 @@ static int mt29f2g01abagd_ecc_get_status(struct
> > spinand_device *spinand,
> > return -EINVAL;
> > }
> >
> > +static int mt29f1g01aaadd_ooblayout_ecc(struct mtd_info *mtd, int
> > section,
> > + struct mtd_oob_region *region)
> > +{
> > + if (section > 3)
> > + return -ERANGE;
> > +
> > + region->offset = (section * 16) + 8;
> > + region->length = 8;
> > +
> > + return 0;
> > +}
> > +
> > +static int mt29f1g01aaadd_ooblayout_free(struct mtd_info *mtd, int
> > section,
> > + struct mtd_oob_region *region)
> > +{
> > + if (section > 3)
> > + return -ERANGE;
> > +
> > + /* 2 bytes for the BBM + 2 bytes to skip non-ecc memory */
> > + region->offset = (section * 16) + 4;
> > + region->length = 4;
> > +
> > + return 0;
> > +}
> > +
> > +static const struct mtd_ooblayout_ops mt29f1g01aaadd_ooblayout = {
> > + .ecc = mt29f1g01aaadd_ooblayout_ecc,
> > + .free = mt29f1g01aaadd_ooblayout_free,
> > +};
> > +
> > +static int mt29f1g01aaadd_ecc_get_status(struct spinand_device *spinand,
> > + u8 status)
> > +{
> > + switch (status & STATUS_ECC_MASK) {
> > + case STATUS_ECC_NO_BITFLIPS:
> > + return 0;
> > + case STATUS_ECC_HAS_BITFLIPS:
> > + /* 1 to 4-bit error detected and corrected */
> > + return 4;
> > + case STATUS_ECC_UNCOR_ERROR:
> > + return -EBADMSG;
> > + default:
> > + return -EINVAL;
> > + }
> > +}
> > +
> > static const struct spinand_info micron_spinand_table[] = {
> > SPINAND_INFO("MT29F2G01ABAGD", 0x24,
> > NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
> > @@ -100,6 +158,16 @@ static const struct spinand_info
> > micron_spinand_table[] = {
> > 0,
> > SPINAND_ECCINFO(&mt29f2g01abagd_ooblayout,
> > mt29f2g01abagd_ecc_get_status)),
> > + SPINAND_INFO("MT29F1G01AAADD", 0x12,
> > + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 2, 1, 1),
> > + NAND_ECCREQ(4, 2048),
>
> I think, this should be NAND_ECCREQ(4, 512).
I don't thinks so, according the datasheet [1], section ECC Protection:
8<--------------------------------------
During a PROGRAM operation, the device calculates an ECC code on the 2k
page in the cache register, before the page is written to the NAND
Flash array. The ECC code is stored in the spare area of the page.
8<--------------------------------------
[1] https://datasheet.octopart.com/MT29F1G01AAADDH4-IT:D-Micron-datasheet-11572380.pdf
Regards,
Marco
>
> > + SPINAND_INFO_OP_VARIANTS(
> > +
> > &read_cache_variants_mt29f1g01aaadd,
> > +
> > &write_cache_variants_mt29f1g01aaadd,
> > +
> > &update_cache_variants_mt29f1g01aaadd),
> > + 0,
> > + SPINAND_ECCINFO(&mt29f1g01aaadd_ooblayout,
> > + mt29f1g01aaadd_ecc_get_status)),
> > };
> >
> > static int micron_spinand_detect(struct spinand_device *spinand)
> > --
> > 2.20.1
>
> Thanks,
> Shiva
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
______________________________________________________
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^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [EXT] [PATCH] mtd: spinand: micron: add support for MT29F1G01AAADD
2019-11-18 14:09 ` Marco Felsch
@ 2019-11-18 17:39 ` Boris Brezillon
2019-11-19 9:27 ` Marco Felsch
0 siblings, 1 reply; 14+ messages in thread
From: Boris Brezillon @ 2019-11-18 17:39 UTC (permalink / raw)
To: Marco Felsch
Cc: bbrezillon, richard, frieder.schrempf, marek.vasut, linux-mtd,
kernel, miquel.raynal, Shivamurthy Shastri (sshivamurthy)
On Mon, 18 Nov 2019 15:09:51 +0100
Marco Felsch <m.felsch@pengutronix.de> wrote:
> Hi Shiva,
>
> On 19-11-18 10:16, Shivamurthy Shastri (sshivamurthy) wrote:
> > Hi Marco,
> >
> > >
> > > The MT29F1G01AAADD is a single die, SLC based SPI NAND. It has a
> > > capacity of 1Gb and supports 4-bit ECC. The datasheet can be found [1].
> > >
> > > Unfortunatly the linked device is marked as EoL, but I will expect that
> > > the MT29F1G01AAADDH4-ITX behaves the same way.
> > >
> > > [1]
> > > https://nam01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fdata
> > > sheet.octopart.com%2FMT29F1G01AAADDH4-IT%3AD-Micron-datasheet-
> > > 11572380.pdf&data=02%7C01%7Csshivamurthy%40micron.com%7C21a
> > > da5347828461980a408d7642021a9%7Cf38a5ecd28134862b11bac1d563c806f%
> > > 7C0%7C1%7C637087961499818902&sdata=%2Fh%2FHfUoSnl8qqSVClVfp
> > > ykvi3UiDEZFTn%2BVCsAf9IaM%3D&reserved=0
> > >
> > > Cc: Peter Pan <peterpandong@micron.com>
> > > Cc: sshivamurthy@micron.com
> > > Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
> > > ---
> > > v2:
> > > - Convert 0x10 into 16 for ooblayout description
> > > - Don't break web link within commit message
> > >
> > > drivers/mtd/nand/spi/micron.c | 68
> > > +++++++++++++++++++++++++++++++++++
> > > 1 file changed, 68 insertions(+)
> > >
> > > diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
> > > index 7d7b1f7fcf71..70e278759bd3 100644
> > > --- a/drivers/mtd/nand/spi/micron.c
> > > +++ b/drivers/mtd/nand/spi/micron.c
> > > @@ -34,6 +34,18 @@ static
> > > SPINAND_OP_VARIANTS(update_cache_variants,
> > > SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
> > > SPINAND_PROG_LOAD(false, 0, NULL, 0));
> > >
> > > +static SPINAND_OP_VARIANTS(read_cache_variants_mt29f1g01aaadd,
> > > + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
> > > + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
> > > + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL,
> > > 0),
> > > + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL,
> > > 0));
> > > +
> > > +static SPINAND_OP_VARIANTS(write_cache_variants_mt29f1g01aaadd,
> > > + SPINAND_PROG_LOAD(true, 0, NULL, 0));
> > > +
> > > +static SPINAND_OP_VARIANTS(update_cache_variants_mt29f1g01aaadd,
> > > + SPINAND_PROG_LOAD(false, 0, NULL, 0));
> > > +
> > > static int mt29f2g01abagd_ooblayout_ecc(struct mtd_info *mtd, int section,
> > > struct mtd_oob_region *region)
> > > {
> > > @@ -90,6 +102,52 @@ static int mt29f2g01abagd_ecc_get_status(struct
> > > spinand_device *spinand,
> > > return -EINVAL;
> > > }
> > >
> > > +static int mt29f1g01aaadd_ooblayout_ecc(struct mtd_info *mtd, int
> > > section,
> > > + struct mtd_oob_region *region)
> > > +{
> > > + if (section > 3)
> > > + return -ERANGE;
> > > +
> > > + region->offset = (section * 16) + 8;
> > > + region->length = 8;
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int mt29f1g01aaadd_ooblayout_free(struct mtd_info *mtd, int
> > > section,
> > > + struct mtd_oob_region *region)
> > > +{
> > > + if (section > 3)
> > > + return -ERANGE;
> > > +
> > > + /* 2 bytes for the BBM + 2 bytes to skip non-ecc memory */
> > > + region->offset = (section * 16) + 4;
> > > + region->length = 4;
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static const struct mtd_ooblayout_ops mt29f1g01aaadd_ooblayout = {
> > > + .ecc = mt29f1g01aaadd_ooblayout_ecc,
> > > + .free = mt29f1g01aaadd_ooblayout_free,
> > > +};
> > > +
> > > +static int mt29f1g01aaadd_ecc_get_status(struct spinand_device *spinand,
> > > + u8 status)
> > > +{
> > > + switch (status & STATUS_ECC_MASK) {
> > > + case STATUS_ECC_NO_BITFLIPS:
> > > + return 0;
> > > + case STATUS_ECC_HAS_BITFLIPS:
> > > + /* 1 to 4-bit error detected and corrected */
> > > + return 4;
> > > + case STATUS_ECC_UNCOR_ERROR:
> > > + return -EBADMSG;
> > > + default:
> > > + return -EINVAL;
> > > + }
> > > +}
> > > +
> > > static const struct spinand_info micron_spinand_table[] = {
> > > SPINAND_INFO("MT29F2G01ABAGD", 0x24,
> > > NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
> > > @@ -100,6 +158,16 @@ static const struct spinand_info
> > > micron_spinand_table[] = {
> > > 0,
> > > SPINAND_ECCINFO(&mt29f2g01abagd_ooblayout,
> > > mt29f2g01abagd_ecc_get_status)),
> > > + SPINAND_INFO("MT29F1G01AAADD", 0x12,
> > > + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 2, 1, 1),
> > > + NAND_ECCREQ(4, 2048),
> >
> > I think, this should be NAND_ECCREQ(4, 512).
>
> I don't thinks so, according the datasheet [1], section ECC Protection:
>
> 8<--------------------------------------
> During a PROGRAM operation, the device calculates an ECC code on the 2k
> page in the cache register, before the page is written to the NAND
> Flash array. The ECC code is stored in the spare area of the page.
> 8<--------------------------------------
Looking at "Table 11: ECC Protection" it really seems to be 4bit/512. I
think the sentence you quoted just means the ECC is calculated for each
512 bytes block in the page and written at once (no subpage write).
BTW, there's an easy way to know who's right => nandbiterrs.
>
> [1] https://datasheet.octopart.com/MT29F1G01AAADDH4-IT:D-Micron-datasheet-11572380.pdf
>
> Regards,
> Marco
>
> >
> > > + SPINAND_INFO_OP_VARIANTS(
> > > +
> > > &read_cache_variants_mt29f1g01aaadd,
> > > +
> > > &write_cache_variants_mt29f1g01aaadd,
> > > +
> > > &update_cache_variants_mt29f1g01aaadd),
> > > + 0,
> > > + SPINAND_ECCINFO(&mt29f1g01aaadd_ooblayout,
> > > + mt29f1g01aaadd_ecc_get_status)),
> > > };
> > >
> > > static int micron_spinand_detect(struct spinand_device *spinand)
> > > --
> > > 2.20.1
> >
> > Thanks,
> > Shiva
> >
>
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [EXT] [PATCH] mtd: spinand: micron: add support for MT29F1G01AAADD
2019-11-18 17:39 ` Boris Brezillon
@ 2019-11-19 9:27 ` Marco Felsch
2020-01-09 16:12 ` Miquel Raynal
0 siblings, 1 reply; 14+ messages in thread
From: Marco Felsch @ 2019-11-19 9:27 UTC (permalink / raw)
To: Boris Brezillon
Cc: bbrezillon, richard, frieder.schrempf, marek.vasut, linux-mtd,
kernel, miquel.raynal, Shivamurthy Shastri (sshivamurthy)
Hi Boris,
On 19-11-18 18:39, Boris Brezillon wrote:
> On Mon, 18 Nov 2019 15:09:51 +0100
> Marco Felsch <m.felsch@pengutronix.de> wrote:
>
> > Hi Shiva,
> >
> > On 19-11-18 10:16, Shivamurthy Shastri (sshivamurthy) wrote:
> > > Hi Marco,
> > >
> > > >
> > > > The MT29F1G01AAADD is a single die, SLC based SPI NAND. It has a
> > > > capacity of 1Gb and supports 4-bit ECC. The datasheet can be found [1].
> > > >
> > > > Unfortunatly the linked device is marked as EoL, but I will expect that
> > > > the MT29F1G01AAADDH4-ITX behaves the same way.
> > > >
> > > > [1]
> > > > https://nam01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fdata
> > > > sheet.octopart.com%2FMT29F1G01AAADDH4-IT%3AD-Micron-datasheet-
> > > > 11572380.pdf&data=02%7C01%7Csshivamurthy%40micron.com%7C21a
> > > > da5347828461980a408d7642021a9%7Cf38a5ecd28134862b11bac1d563c806f%
> > > > 7C0%7C1%7C637087961499818902&sdata=%2Fh%2FHfUoSnl8qqSVClVfp
> > > > ykvi3UiDEZFTn%2BVCsAf9IaM%3D&reserved=0
> > > >
> > > > Cc: Peter Pan <peterpandong@micron.com>
> > > > Cc: sshivamurthy@micron.com
> > > > Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
> > > > ---
> > > > v2:
> > > > - Convert 0x10 into 16 for ooblayout description
> > > > - Don't break web link within commit message
> > > >
> > > > drivers/mtd/nand/spi/micron.c | 68
> > > > +++++++++++++++++++++++++++++++++++
> > > > 1 file changed, 68 insertions(+)
> > > >
> > > > diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
> > > > index 7d7b1f7fcf71..70e278759bd3 100644
> > > > --- a/drivers/mtd/nand/spi/micron.c
> > > > +++ b/drivers/mtd/nand/spi/micron.c
> > > > @@ -34,6 +34,18 @@ static
> > > > SPINAND_OP_VARIANTS(update_cache_variants,
> > > > SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
> > > > SPINAND_PROG_LOAD(false, 0, NULL, 0));
> > > >
> > > > +static SPINAND_OP_VARIANTS(read_cache_variants_mt29f1g01aaadd,
> > > > + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
> > > > + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
> > > > + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL,
> > > > 0),
> > > > + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL,
> > > > 0));
> > > > +
> > > > +static SPINAND_OP_VARIANTS(write_cache_variants_mt29f1g01aaadd,
> > > > + SPINAND_PROG_LOAD(true, 0, NULL, 0));
> > > > +
> > > > +static SPINAND_OP_VARIANTS(update_cache_variants_mt29f1g01aaadd,
> > > > + SPINAND_PROG_LOAD(false, 0, NULL, 0));
> > > > +
> > > > static int mt29f2g01abagd_ooblayout_ecc(struct mtd_info *mtd, int section,
> > > > struct mtd_oob_region *region)
> > > > {
> > > > @@ -90,6 +102,52 @@ static int mt29f2g01abagd_ecc_get_status(struct
> > > > spinand_device *spinand,
> > > > return -EINVAL;
> > > > }
> > > >
> > > > +static int mt29f1g01aaadd_ooblayout_ecc(struct mtd_info *mtd, int
> > > > section,
> > > > + struct mtd_oob_region *region)
> > > > +{
> > > > + if (section > 3)
> > > > + return -ERANGE;
> > > > +
> > > > + region->offset = (section * 16) + 8;
> > > > + region->length = 8;
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static int mt29f1g01aaadd_ooblayout_free(struct mtd_info *mtd, int
> > > > section,
> > > > + struct mtd_oob_region *region)
> > > > +{
> > > > + if (section > 3)
> > > > + return -ERANGE;
> > > > +
> > > > + /* 2 bytes for the BBM + 2 bytes to skip non-ecc memory */
> > > > + region->offset = (section * 16) + 4;
> > > > + region->length = 4;
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static const struct mtd_ooblayout_ops mt29f1g01aaadd_ooblayout = {
> > > > + .ecc = mt29f1g01aaadd_ooblayout_ecc,
> > > > + .free = mt29f1g01aaadd_ooblayout_free,
> > > > +};
> > > > +
> > > > +static int mt29f1g01aaadd_ecc_get_status(struct spinand_device *spinand,
> > > > + u8 status)
> > > > +{
> > > > + switch (status & STATUS_ECC_MASK) {
> > > > + case STATUS_ECC_NO_BITFLIPS:
> > > > + return 0;
> > > > + case STATUS_ECC_HAS_BITFLIPS:
> > > > + /* 1 to 4-bit error detected and corrected */
> > > > + return 4;
> > > > + case STATUS_ECC_UNCOR_ERROR:
> > > > + return -EBADMSG;
> > > > + default:
> > > > + return -EINVAL;
> > > > + }
> > > > +}
> > > > +
> > > > static const struct spinand_info micron_spinand_table[] = {
> > > > SPINAND_INFO("MT29F2G01ABAGD", 0x24,
> > > > NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
> > > > @@ -100,6 +158,16 @@ static const struct spinand_info
> > > > micron_spinand_table[] = {
> > > > 0,
> > > > SPINAND_ECCINFO(&mt29f2g01abagd_ooblayout,
> > > > mt29f2g01abagd_ecc_get_status)),
> > > > + SPINAND_INFO("MT29F1G01AAADD", 0x12,
> > > > + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 2, 1, 1),
> > > > + NAND_ECCREQ(4, 2048),
> > >
> > > I think, this should be NAND_ECCREQ(4, 512).
> >
> > I don't thinks so, according the datasheet [1], section ECC Protection:
> >
> > 8<--------------------------------------
> > During a PROGRAM operation, the device calculates an ECC code on the 2k
> > page in the cache register, before the page is written to the NAND
> > Flash array. The ECC code is stored in the spare area of the page.
> > 8<--------------------------------------
>
> Looking at "Table 11: ECC Protection" it really seems to be 4bit/512. I
> think the sentence you quoted just means the ECC is calculated for each
> 512 bytes block in the page and written at once (no subpage write).
Yes that part confuses me a bit and than I used the description above..
I will change that, thanks for the explanation.
> BTW, there's an easy way to know who's right => nandbiterrs.
Thanks for that hint :)
Regards,
Marco
>
> >
> > [1] https://datasheet.octopart.com/MT29F1G01AAADDH4-IT:D-Micron-datasheet-11572380.pdf
> >
> > Regards,
> > Marco
> >
> > >
> > > > + SPINAND_INFO_OP_VARIANTS(
> > > > +
> > > > &read_cache_variants_mt29f1g01aaadd,
> > > > +
> > > > &write_cache_variants_mt29f1g01aaadd,
> > > > +
> > > > &update_cache_variants_mt29f1g01aaadd),
> > > > + 0,
> > > > + SPINAND_ECCINFO(&mt29f1g01aaadd_ooblayout,
> > > > + mt29f1g01aaadd_ecc_get_status)),
> > > > };
> > > >
> > > > static int micron_spinand_detect(struct spinand_device *spinand)
> > > > --
> > > > 2.20.1
> > >
> > > Thanks,
> > > Shiva
> > >
> >
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [EXT] [PATCH] mtd: spinand: micron: add support for MT29F1G01AAADD
2019-11-19 9:27 ` Marco Felsch
@ 2020-01-09 16:12 ` Miquel Raynal
2020-01-17 7:18 ` Marco Felsch
0 siblings, 1 reply; 14+ messages in thread
From: Miquel Raynal @ 2020-01-09 16:12 UTC (permalink / raw)
To: Marco Felsch
Cc: bbrezillon, richard, frieder.schrempf, marek.vasut,
Boris Brezillon, linux-mtd, kernel,
Shivamurthy Shastri (sshivamurthy)
Hi Marco,
> > > >
> > > > I think, this should be NAND_ECCREQ(4, 512).
> > >
> > > I don't thinks so, according the datasheet [1], section ECC Protection:
> > >
> > > 8<--------------------------------------
> > > During a PROGRAM operation, the device calculates an ECC code on the 2k
> > > page in the cache register, before the page is written to the NAND
> > > Flash array. The ECC code is stored in the spare area of the page.
> > > 8<--------------------------------------
> >
> > Looking at "Table 11: ECC Protection" it really seems to be 4bit/512. I
> > think the sentence you quoted just means the ECC is calculated for each
> > 512 bytes block in the page and written at once (no subpage write).
>
> Yes that part confuses me a bit and than I used the description above..
> I will change that, thanks for the explanation.
>
> > BTW, there's an easy way to know who's right => nandbiterrs.
>
> Thanks for that hint :)
>
> Regards,
> Marco
Would you mind sending an updated version of this patch please?
Thanks!
Miquèl
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [EXT] [PATCH] mtd: spinand: micron: add support for MT29F1G01AAADD
2020-01-09 16:12 ` Miquel Raynal
@ 2020-01-17 7:18 ` Marco Felsch
0 siblings, 0 replies; 14+ messages in thread
From: Marco Felsch @ 2020-01-17 7:18 UTC (permalink / raw)
To: Miquel Raynal
Cc: bbrezillon, richard, frieder.schrempf, marek.vasut,
Boris Brezillon, linux-mtd, kernel,
Shivamurthy Shastri (sshivamurthy)
Hi Miquel,
On 20-01-09 17:12, Miquel Raynal wrote:
> Hi Marco,
>
> > > > >
> > > > > I think, this should be NAND_ECCREQ(4, 512).
> > > >
> > > > I don't thinks so, according the datasheet [1], section ECC Protection:
> > > >
> > > > 8<--------------------------------------
> > > > During a PROGRAM operation, the device calculates an ECC code on the 2k
> > > > page in the cache register, before the page is written to the NAND
> > > > Flash array. The ECC code is stored in the spare area of the page.
> > > > 8<--------------------------------------
> > >
> > > Looking at "Table 11: ECC Protection" it really seems to be 4bit/512. I
> > > think the sentence you quoted just means the ECC is calculated for each
> > > 512 bytes block in the page and written at once (no subpage write).
> >
> > Yes that part confuses me a bit and than I used the description above..
> > I will change that, thanks for the explanation.
> >
> > > BTW, there's an easy way to know who's right => nandbiterrs.
> >
> > Thanks for that hint :)
> >
> > Regards,
> > Marco
>
> Would you mind sending an updated version of this patch please?
Of course, thanks for the ping.
Regards,
Marco
>
> Thanks!
> Miquèl
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH] mtd: spinand: micron: add support for MT29F1G01AAADD
@ 2019-08-14 8:22 Marco Felsch
2019-08-19 8:17 ` Miquel Raynal
0 siblings, 1 reply; 14+ messages in thread
From: Marco Felsch @ 2019-08-14 8:22 UTC (permalink / raw)
To: miquel.raynal, frieder.schrempf, bbrezillon, richard
Cc: marek.vasut, linux-mtd, kernel, Peter Pan
The MT29F1G01AAADD is a single die, SLC based SPI NAND. It has a
capacity of 1Gb and supports 4-bit ECC. The datasheet can be found [1].
Unfortunatly the linked device is marked as EoL, but I will expect that
the MT29F1G01AAADDH4-ITX behaves the same way.
[1] https://datasheet.octopart.com/ \
MT29F1G01AAADDH4-IT:D-Micron-datasheet-11572380.pdf
Cc: Peter Pan <peterpandong@micron.com>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
drivers/mtd/nand/spi/micron.c | 68 +++++++++++++++++++++++++++++++++++
1 file changed, 68 insertions(+)
diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
index 7d7b1f7fcf71..9d63450afc69 100644
--- a/drivers/mtd/nand/spi/micron.c
+++ b/drivers/mtd/nand/spi/micron.c
@@ -34,6 +34,18 @@ static SPINAND_OP_VARIANTS(update_cache_variants,
SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
SPINAND_PROG_LOAD(false, 0, NULL, 0));
+static SPINAND_OP_VARIANTS(read_cache_variants_mt29f1g01aaadd,
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(write_cache_variants_mt29f1g01aaadd,
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(update_cache_variants_mt29f1g01aaadd,
+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
static int mt29f2g01abagd_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
@@ -90,6 +102,52 @@ static int mt29f2g01abagd_ecc_get_status(struct spinand_device *spinand,
return -EINVAL;
}
+static int mt29f1g01aaadd_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ region->offset = (section * 0x10) + 8;
+ region->length = 8;
+
+ return 0;
+}
+
+static int mt29f1g01aaadd_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ /* 2 bytes for the BBM + 2 bytes to skip non-ecc memory */
+ region->offset = (section * 0x10) + 4;
+ region->length = 4;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops mt29f1g01aaadd_ooblayout = {
+ .ecc = mt29f1g01aaadd_ooblayout_ecc,
+ .free = mt29f1g01aaadd_ooblayout_free,
+};
+
+static int mt29f1g01aaadd_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
+ switch (status & STATUS_ECC_MASK) {
+ case STATUS_ECC_NO_BITFLIPS:
+ return 0;
+ case STATUS_ECC_HAS_BITFLIPS:
+ /* 1 to 4-bit error detected and corrected */
+ return 4;
+ case STATUS_ECC_UNCOR_ERROR:
+ return -EBADMSG;
+ default:
+ return -EINVAL;
+ }
+}
+
static const struct spinand_info micron_spinand_table[] = {
SPINAND_INFO("MT29F2G01ABAGD", 0x24,
NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
@@ -100,6 +158,16 @@ static const struct spinand_info micron_spinand_table[] = {
0,
SPINAND_ECCINFO(&mt29f2g01abagd_ooblayout,
mt29f2g01abagd_ecc_get_status)),
+ SPINAND_INFO("MT29F1G01AAADD", 0x12,
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 2, 1, 1),
+ NAND_ECCREQ(4, 2048),
+ SPINAND_INFO_OP_VARIANTS(
+ &read_cache_variants_mt29f1g01aaadd,
+ &write_cache_variants_mt29f1g01aaadd,
+ &update_cache_variants_mt29f1g01aaadd),
+ 0,
+ SPINAND_ECCINFO(&mt29f1g01aaadd_ooblayout,
+ mt29f1g01aaadd_ecc_get_status)),
};
static int micron_spinand_detect(struct spinand_device *spinand)
--
2.20.1
______________________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH] mtd: spinand: micron: add support for MT29F1G01AAADD
2019-08-14 8:22 Marco Felsch
@ 2019-08-19 8:17 ` Miquel Raynal
2019-08-19 13:30 ` Marco Felsch
2019-08-20 8:28 ` Uwe Kleine-König
0 siblings, 2 replies; 14+ messages in thread
From: Miquel Raynal @ 2019-08-19 8:17 UTC (permalink / raw)
To: Marco Felsch
Cc: bbrezillon, richard, frieder.schrempf, marek.vasut, linux-mtd,
kernel, Peter Pan
Hi Marco,
Marco Felsch <m.felsch@pengutronix.de> wrote on Wed, 14 Aug 2019
10:22:32 +0200:
> The MT29F1G01AAADD is a single die, SLC based SPI NAND. It has a
> capacity of 1Gb and supports 4-bit ECC. The datasheet can be found [1].
>
> Unfortunatly the linked device is marked as EoL, but I will expect that
> the MT29F1G01AAADDH4-ITX behaves the same way.
>
> [1] https://datasheet.octopart.com/ \
> MT29F1G01AAADDH4-IT:D-Micron-datasheet-11572380.pdf
>
> Cc: Peter Pan <peterpandong@micron.com>
> Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
> ---
> drivers/mtd/nand/spi/micron.c | 68 +++++++++++++++++++++++++++++++++++
> 1 file changed, 68 insertions(+)
>
> diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
> index 7d7b1f7fcf71..9d63450afc69 100644
> --- a/drivers/mtd/nand/spi/micron.c
> +++ b/drivers/mtd/nand/spi/micron.c
> @@ -34,6 +34,18 @@ static SPINAND_OP_VARIANTS(update_cache_variants,
> SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
> SPINAND_PROG_LOAD(false, 0, NULL, 0));
>
> +static SPINAND_OP_VARIANTS(read_cache_variants_mt29f1g01aaadd,
> + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
> + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
> + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
> + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
> +
> +static SPINAND_OP_VARIANTS(write_cache_variants_mt29f1g01aaadd,
> + SPINAND_PROG_LOAD(true, 0, NULL, 0));
> +
> +static SPINAND_OP_VARIANTS(update_cache_variants_mt29f1g01aaadd,
> + SPINAND_PROG_LOAD(false, 0, NULL, 0));
> +
> static int mt29f2g01abagd_ooblayout_ecc(struct mtd_info *mtd, int section,
> struct mtd_oob_region *region)
> {
> @@ -90,6 +102,52 @@ static int mt29f2g01abagd_ecc_get_status(struct spinand_device *spinand,
> return -EINVAL;
> }
>
> +static int mt29f1g01aaadd_ooblayout_ecc(struct mtd_info *mtd, int section,
> + struct mtd_oob_region *region)
> +{
> + if (section > 3)
> + return -ERANGE;
> +
> + region->offset = (section * 0x10) + 8;
Any reason to use hex here? ^
If not I would prefer decimal numbers.
Otherwise looks fine.
Thanks,
Miquèl
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH] mtd: spinand: micron: add support for MT29F1G01AAADD
2019-08-19 8:17 ` Miquel Raynal
@ 2019-08-19 13:30 ` Marco Felsch
2019-08-19 14:34 ` Miquel Raynal
2019-08-20 8:28 ` Uwe Kleine-König
1 sibling, 1 reply; 14+ messages in thread
From: Marco Felsch @ 2019-08-19 13:30 UTC (permalink / raw)
To: Miquel Raynal
Cc: bbrezillon, richard, frieder.schrempf, marek.vasut, linux-mtd,
kernel, Peter Pan
Hi Miquel,
On 19-08-19 10:17, Miquel Raynal wrote:
> Hi Marco,
>
> Marco Felsch <m.felsch@pengutronix.de> wrote on Wed, 14 Aug 2019
> 10:22:32 +0200:
>
> > The MT29F1G01AAADD is a single die, SLC based SPI NAND. It has a
> > capacity of 1Gb and supports 4-bit ECC. The datasheet can be found [1].
> >
> > Unfortunatly the linked device is marked as EoL, but I will expect that
> > the MT29F1G01AAADDH4-ITX behaves the same way.
> >
> > [1] https://datasheet.octopart.com/ \
> > MT29F1G01AAADDH4-IT:D-Micron-datasheet-11572380.pdf
> >
> > Cc: Peter Pan <peterpandong@micron.com>
> > Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
> > ---
> > drivers/mtd/nand/spi/micron.c | 68 +++++++++++++++++++++++++++++++++++
> > 1 file changed, 68 insertions(+)
> >
> > diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
> > index 7d7b1f7fcf71..9d63450afc69 100644
> > --- a/drivers/mtd/nand/spi/micron.c
> > +++ b/drivers/mtd/nand/spi/micron.c
> > @@ -34,6 +34,18 @@ static SPINAND_OP_VARIANTS(update_cache_variants,
> > SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
> > SPINAND_PROG_LOAD(false, 0, NULL, 0));
> >
> > +static SPINAND_OP_VARIANTS(read_cache_variants_mt29f1g01aaadd,
> > + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
> > + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
> > + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
> > + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
> > +
> > +static SPINAND_OP_VARIANTS(write_cache_variants_mt29f1g01aaadd,
> > + SPINAND_PROG_LOAD(true, 0, NULL, 0));
> > +
> > +static SPINAND_OP_VARIANTS(update_cache_variants_mt29f1g01aaadd,
> > + SPINAND_PROG_LOAD(false, 0, NULL, 0));
> > +
> > static int mt29f2g01abagd_ooblayout_ecc(struct mtd_info *mtd, int section,
> > struct mtd_oob_region *region)
> > {
> > @@ -90,6 +102,52 @@ static int mt29f2g01abagd_ecc_get_status(struct spinand_device *spinand,
> > return -EINVAL;
> > }
> >
> > +static int mt29f1g01aaadd_ooblayout_ecc(struct mtd_info *mtd, int section,
> > + struct mtd_oob_region *region)
> > +{
> > + if (section > 3)
> > + return -ERANGE;
> > +
> > + region->offset = (section * 0x10) + 8;
>
> Any reason to use hex here? ^
>
> If not I would prefer decimal numbers.
Since the datasheet describe it in hex to.
Can you have a look on [1] table 11? May we do something like:
region->offset = (section * 0x10) + 0x8;
[1] https://datasheet.octopart.com/MT29F1G01AAADDH4-IT:D-Micron-datasheet-11572380.pdf
>
> Otherwise looks fine.
Anyway I can change the above code to use only decimal values if you
like it more.
Regards,
Marco
>
> Thanks,
> Miquèl
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
______________________________________________________
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^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH] mtd: spinand: micron: add support for MT29F1G01AAADD
2019-08-19 13:30 ` Marco Felsch
@ 2019-08-19 14:34 ` Miquel Raynal
2019-08-20 6:39 ` Marco Felsch
0 siblings, 1 reply; 14+ messages in thread
From: Miquel Raynal @ 2019-08-19 14:34 UTC (permalink / raw)
To: Marco Felsch
Cc: bbrezillon, richard, frieder.schrempf, marek.vasut, linux-mtd,
kernel, Peter Pan
Hi Marco,
Marco Felsch <m.felsch@pengutronix.de> wrote on Mon, 19 Aug 2019
15:30:42 +0200:
> Hi Miquel,
>
> On 19-08-19 10:17, Miquel Raynal wrote:
> > Hi Marco,
> >
> > Marco Felsch <m.felsch@pengutronix.de> wrote on Wed, 14 Aug 2019
> > 10:22:32 +0200:
> >
> > > The MT29F1G01AAADD is a single die, SLC based SPI NAND. It has a
> > > capacity of 1Gb and supports 4-bit ECC. The datasheet can be found [1].
> > >
> > > Unfortunatly the linked device is marked as EoL, but I will expect that
> > > the MT29F1G01AAADDH4-ITX behaves the same way.
> > >
> > > [1] https://datasheet.octopart.com/ \
> > > MT29F1G01AAADDH4-IT:D-Micron-datasheet-11572380.pdf
> > >
> > > Cc: Peter Pan <peterpandong@micron.com>
> > > Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
> > > ---
> > > drivers/mtd/nand/spi/micron.c | 68 +++++++++++++++++++++++++++++++++++
> > > 1 file changed, 68 insertions(+)
> > >
> > > diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
> > > index 7d7b1f7fcf71..9d63450afc69 100644
> > > --- a/drivers/mtd/nand/spi/micron.c
> > > +++ b/drivers/mtd/nand/spi/micron.c
> > > @@ -34,6 +34,18 @@ static SPINAND_OP_VARIANTS(update_cache_variants,
> > > SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
> > > SPINAND_PROG_LOAD(false, 0, NULL, 0));
> > >
> > > +static SPINAND_OP_VARIANTS(read_cache_variants_mt29f1g01aaadd,
> > > + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
> > > + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
> > > + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
> > > + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
> > > +
> > > +static SPINAND_OP_VARIANTS(write_cache_variants_mt29f1g01aaadd,
> > > + SPINAND_PROG_LOAD(true, 0, NULL, 0));
> > > +
> > > +static SPINAND_OP_VARIANTS(update_cache_variants_mt29f1g01aaadd,
> > > + SPINAND_PROG_LOAD(false, 0, NULL, 0));
> > > +
> > > static int mt29f2g01abagd_ooblayout_ecc(struct mtd_info *mtd, int section,
> > > struct mtd_oob_region *region)
> > > {
> > > @@ -90,6 +102,52 @@ static int mt29f2g01abagd_ecc_get_status(struct spinand_device *spinand,
> > > return -EINVAL;
> > > }
> > >
> > > +static int mt29f1g01aaadd_ooblayout_ecc(struct mtd_info *mtd, int section,
> > > + struct mtd_oob_region *region)
> > > +{
> > > + if (section > 3)
> > > + return -ERANGE;
> > > +
> > > + region->offset = (section * 0x10) + 8;
> >
> > Any reason to use hex here? ^
> >
> > If not I would prefer decimal numbers.
>
> Since the datasheet describe it in hex to.
>
> Can you have a look on [1] table 11? May we do something like:
>
> region->offset = (section * 0x10) + 0x8;
>
> [1] https://datasheet.octopart.com/MT29F1G01AAADDH4-IT:D-Micron-datasheet-11572380.pdf
>
> >
> > Otherwise looks fine.
>
> Anyway I can change the above code to use only decimal values if you
> like it more.
I think it is better to reserve hexadecimal values to register
operations. Please translate into decimal.
Thanks,
Miquèl
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH] mtd: spinand: micron: add support for MT29F1G01AAADD
2019-08-19 14:34 ` Miquel Raynal
@ 2019-08-20 6:39 ` Marco Felsch
0 siblings, 0 replies; 14+ messages in thread
From: Marco Felsch @ 2019-08-20 6:39 UTC (permalink / raw)
To: Miquel Raynal
Cc: bbrezillon, richard, frieder.schrempf, marek.vasut, linux-mtd,
kernel, Peter Pan
Hi Miquel,
On 19-08-19 16:34, Miquel Raynal wrote:
> Hi Marco,
>
> Marco Felsch <m.felsch@pengutronix.de> wrote on Mon, 19 Aug 2019
> 15:30:42 +0200:
>
> > Hi Miquel,
> >
> > On 19-08-19 10:17, Miquel Raynal wrote:
> > > Hi Marco,
> > >
> > > Marco Felsch <m.felsch@pengutronix.de> wrote on Wed, 14 Aug 2019
> > > 10:22:32 +0200:
> > >
> > > > The MT29F1G01AAADD is a single die, SLC based SPI NAND. It has a
> > > > capacity of 1Gb and supports 4-bit ECC. The datasheet can be found [1].
> > > >
> > > > Unfortunatly the linked device is marked as EoL, but I will expect that
> > > > the MT29F1G01AAADDH4-ITX behaves the same way.
> > > >
> > > > [1] https://datasheet.octopart.com/ \
> > > > MT29F1G01AAADDH4-IT:D-Micron-datasheet-11572380.pdf
> > > >
> > > > Cc: Peter Pan <peterpandong@micron.com>
> > > > Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
> > > > ---
> > > > drivers/mtd/nand/spi/micron.c | 68 +++++++++++++++++++++++++++++++++++
> > > > 1 file changed, 68 insertions(+)
> > > >
> > > > diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
> > > > index 7d7b1f7fcf71..9d63450afc69 100644
> > > > --- a/drivers/mtd/nand/spi/micron.c
> > > > +++ b/drivers/mtd/nand/spi/micron.c
> > > > @@ -34,6 +34,18 @@ static SPINAND_OP_VARIANTS(update_cache_variants,
> > > > SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
> > > > SPINAND_PROG_LOAD(false, 0, NULL, 0));
> > > >
> > > > +static SPINAND_OP_VARIANTS(read_cache_variants_mt29f1g01aaadd,
> > > > + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
> > > > + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
> > > > + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
> > > > + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
> > > > +
> > > > +static SPINAND_OP_VARIANTS(write_cache_variants_mt29f1g01aaadd,
> > > > + SPINAND_PROG_LOAD(true, 0, NULL, 0));
> > > > +
> > > > +static SPINAND_OP_VARIANTS(update_cache_variants_mt29f1g01aaadd,
> > > > + SPINAND_PROG_LOAD(false, 0, NULL, 0));
> > > > +
> > > > static int mt29f2g01abagd_ooblayout_ecc(struct mtd_info *mtd, int section,
> > > > struct mtd_oob_region *region)
> > > > {
> > > > @@ -90,6 +102,52 @@ static int mt29f2g01abagd_ecc_get_status(struct spinand_device *spinand,
> > > > return -EINVAL;
> > > > }
> > > >
> > > > +static int mt29f1g01aaadd_ooblayout_ecc(struct mtd_info *mtd, int section,
> > > > + struct mtd_oob_region *region)
> > > > +{
> > > > + if (section > 3)
> > > > + return -ERANGE;
> > > > +
> > > > + region->offset = (section * 0x10) + 8;
> > >
> > > Any reason to use hex here? ^
> > >
> > > If not I would prefer decimal numbers.
> >
> > Since the datasheet describe it in hex to.
> >
> > Can you have a look on [1] table 11? May we do something like:
> >
> > region->offset = (section * 0x10) + 0x8;
> >
> > [1] https://datasheet.octopart.com/MT29F1G01AAADDH4-IT:D-Micron-datasheet-11572380.pdf
> >
> > >
> > > Otherwise looks fine.
> >
> > Anyway I can change the above code to use only decimal values if you
> > like it more.
>
> I think it is better to reserve hexadecimal values to register
> operations. Please translate into decimal.
Okay. Just one last question. What is the common way to go to specify
the free area? By this I mean that the NAND has two areas to store the
user metadata calling it 'user metadata I' and 'user metadata II'. 'user
metadata II' isn't ecc protected so I skip them. But the current
supported chip does not skip the user metadata area which isn't
protected [1] table 10.
[1] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m79a_2gb_3v_nand_spi.pdf
Regards,
Marco
>
> Thanks,
> Miquèl
>
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] mtd: spinand: micron: add support for MT29F1G01AAADD
2019-08-19 8:17 ` Miquel Raynal
2019-08-19 13:30 ` Marco Felsch
@ 2019-08-20 8:28 ` Uwe Kleine-König
2019-08-20 8:32 ` Miquel Raynal
1 sibling, 1 reply; 14+ messages in thread
From: Uwe Kleine-König @ 2019-08-20 8:28 UTC (permalink / raw)
To: Miquel Raynal
Cc: bbrezillon, richard, Marco Felsch, frieder.schrempf, marek.vasut,
linux-mtd, kernel, Peter Pan
Hello Miquèl,
On Mon, Aug 19, 2019 at 10:17:18AM +0200, Miquel Raynal wrote:
> Marco Felsch <m.felsch@pengutronix.de> wrote on Wed, 14 Aug 2019
> 10:22:32 +0200:
> > +static int mt29f1g01aaadd_ooblayout_ecc(struct mtd_info *mtd, int section,
> > + struct mtd_oob_region *region)
> > +{
> > + if (section > 3)
> > + return -ERANGE;
> > +
> > + region->offset = (section * 0x10) + 8;
>
> Any reason to use hex here? ^
>
> If not I would prefer decimal numbers.
IMHO it is quite common to use hexadecimal also for register offsets,
not only for register values.
I checked a few drivers (drivers/mtd/nand/raw/mxc_nand.c,
drivers/clk/meson/g12a.c, drivers/gpio/gpio-sch.c) and they all use hex
also for the offsets, so it seems to be at least usual. Also as offsets
for repeating registers are usually powers of two, hexadecimal constants
are more suitable IMHO.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | http://www.pengutronix.de/ |
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH] mtd: spinand: micron: add support for MT29F1G01AAADD
2019-08-20 8:28 ` Uwe Kleine-König
@ 2019-08-20 8:32 ` Miquel Raynal
0 siblings, 0 replies; 14+ messages in thread
From: Miquel Raynal @ 2019-08-20 8:32 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: bbrezillon, richard, Marco Felsch, frieder.schrempf, marek.vasut,
linux-mtd, kernel, Peter Pan
Hi Uwe,
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> wrote on Tue, 20 Aug
2019 10:28:37 +0200:
> Hello Miquèl,
>
> On Mon, Aug 19, 2019 at 10:17:18AM +0200, Miquel Raynal wrote:
> > Marco Felsch <m.felsch@pengutronix.de> wrote on Wed, 14 Aug 2019
> > 10:22:32 +0200:
> > > +static int mt29f1g01aaadd_ooblayout_ecc(struct mtd_info *mtd, int section,
> > > + struct mtd_oob_region *region)
> > > +{
> > > + if (section > 3)
> > > + return -ERANGE;
> > > +
> > > + region->offset = (section * 0x10) + 8;
> >
> > Any reason to use hex here? ^
> >
> > If not I would prefer decimal numbers.
>
> IMHO it is quite common to use hexadecimal also for register offsets,
> not only for register values.
>
> I checked a few drivers (drivers/mtd/nand/raw/mxc_nand.c,
> drivers/clk/meson/g12a.c, drivers/gpio/gpio-sch.c) and they all use hex
> also for the offsets, so it seems to be at least usual. Also as offsets
> for repeating registers are usually powers of two, hexadecimal constants
> are more suitable IMHO.
Absolutely. But here region->offset is not a register offset at all, it
is an indication for the upper layers of the position of an area within
a bigger buffer (here: where are the ECC bytes in my buffer in RAM). I
don't think hexadecimal numbers have any interest here.
Thanks,
Miquèl
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2020-01-17 7:18 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-08 7:48 [PATCH] mtd: spinand: micron: add support for MT29F1G01AAADD Marco Felsch
2019-11-18 10:16 ` [EXT] " Shivamurthy Shastri (sshivamurthy)
2019-11-18 14:09 ` Marco Felsch
2019-11-18 17:39 ` Boris Brezillon
2019-11-19 9:27 ` Marco Felsch
2020-01-09 16:12 ` Miquel Raynal
2020-01-17 7:18 ` Marco Felsch
-- strict thread matches above, loose matches on Subject: below --
2019-08-14 8:22 Marco Felsch
2019-08-19 8:17 ` Miquel Raynal
2019-08-19 13:30 ` Marco Felsch
2019-08-19 14:34 ` Miquel Raynal
2019-08-20 6:39 ` Marco Felsch
2019-08-20 8:28 ` Uwe Kleine-König
2019-08-20 8:32 ` Miquel Raynal
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