[igt-dev] [PATCH i-g-t v4 0/3] GEN12 render decompression

[igt-dev] [PATCH i-g-t v4 0/3] GEN12 render decompression

[Mika Kahola]

Gen-12 render decompression is supported with Y-tiled main surface.
The patch series introduces CCS support for IGT tests.

This patch series requires Imre's series

https://patchwork.freedesktop.org/series/68890/

v2: Added new subtests for each format modifier.
v3: Add IGT description for each subtest (GitLab)
v4: Fix kms_ccs errornouse subtest execution and listing

Mika Kahola (3):
  Format modifier for Intel Gen-12 render compression
  lib/igt_fb.c: Update tile sizes for GEN12 CCS
  tests/kms_ccs: Add GEN12 CCS render compression format modifiers

 include/drm-uapi/drm_fourcc.h |   1 +
 lib/igt_fb.c                  |  34 ++++++++++-
 lib/ioctl_wrappers.h          |   1 +
 tests/kms_ccs.c               | 110 ++++++++++++++++++++--------------
 4 files changed, 99 insertions(+), 47 deletions(-)

-- 
2.17.1

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[igt-dev] [PATCH i-g-t v4 1/3] Format modifier for Intel Gen-12 render compression

[Mika Kahola]

Gen-12 has a new compression format for render compression.
For this, a new modifier is needed to indicate that.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 include/drm-uapi/drm_fourcc.h | 1 +
 lib/ioctl_wrappers.h          | 1 +
 2 files changed, 2 insertions(+)

diff --git a/include/drm-uapi/drm_fourcc.h b/include/drm-uapi/drm_fourcc.h
index 3feeaa3f..b93eb2d4 100644
--- a/include/drm-uapi/drm_fourcc.h
+++ b/include/drm-uapi/drm_fourcc.h
@@ -409,6 +409,7 @@ extern "C" {
  */
 #define I915_FORMAT_MOD_Y_TILED_CCS	fourcc_mod_code(INTEL, 4)
 #define I915_FORMAT_MOD_Yf_TILED_CCS	fourcc_mod_code(INTEL, 5)
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
 
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index 03211c97..f2412d78 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -200,6 +200,7 @@ struct local_drm_mode_fb_cmd2 {
 #define LOCAL_I915_FORMAT_MOD_Yf_TILED	local_fourcc_mod_code(INTEL, 3)
 #define LOCAL_I915_FORMAT_MOD_Y_TILED_CCS	local_fourcc_mod_code(INTEL, 4)
 #define LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS	local_fourcc_mod_code(INTEL, 5)
+#define LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
 
 #define LOCAL_DRM_IOCTL_MODE_ADDFB2	DRM_IOWR(0xB8, \
 						 struct local_drm_mode_fb_cmd2)
-- 
2.17.1

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[igt-dev] [PATCH i-g-t v4 2/3] lib/igt_fb.c: Update tile sizes for GEN12 CCS

[Mika Kahola]

Update tile sizes for GEN12 CCS.

BSpec: 47709

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 lib/igt_fb.c | 34 ++++++++++++++++++++++++++++++++--
 1 file changed, 32 insertions(+), 2 deletions(-)

diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 4adca967..77030d49 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -413,6 +413,33 @@ void igt_get_fb_tile_size(int fd, uint64_t modifier, int fb_bpp,
 			*height_ret = 32;
 		}
 		break;
+	case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+		igt_require_intel(fd);
+		switch (fb_bpp) {
+		case 8:
+			*width_ret = 512;
+			*height_ret = 32;
+			break;
+		case 16:
+			*width_ret = 256;
+			*height_ret = 32;
+			break;
+		case 32:
+			*width_ret = 128;
+			*height_ret = 32;
+			break;
+		case 64:
+			*width_ret = 64;
+			*height_ret = 32;
+			break;
+		case 128:
+			*width_ret = 32;
+			*height_ret = 32;
+			break;
+		default:
+			igt_assert(false);
+		}
+		break;
 	case LOCAL_I915_FORMAT_MOD_Yf_TILED:
 	case LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS:
 		igt_require_intel(fd);
@@ -467,8 +494,10 @@ void igt_get_fb_tile_size(int fd, uint64_t modifier, int fb_bpp,
 
 static bool is_ccs_modifier(uint64_t modifier)
 {
-	return modifier == LOCAL_I915_FORMAT_MOD_Y_TILED_CCS ||
-		modifier == LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS;
+
+	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+		modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
+		modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
 }
 
 static unsigned fb_plane_width(const struct igt_fb *fb, int plane)
@@ -687,6 +716,7 @@ uint64_t igt_fb_mod_to_tiling(uint64_t modifier)
 		return I915_TILING_X;
 	case LOCAL_I915_FORMAT_MOD_Y_TILED:
 	case LOCAL_I915_FORMAT_MOD_Y_TILED_CCS:
+	case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 		return I915_TILING_Y;
 	case LOCAL_I915_FORMAT_MOD_Yf_TILED:
 	case LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS:
-- 
2.17.1

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[igt-dev] [PATCH i-g-t v4 3/3] tests/kms_ccs: Add GEN12 CCS render compression format modifiers

[Mika Kahola]

Add GEN12 CCS format modifiers for render compression. Render
compression is not supported for 90/270 rotation.

v2: Added new subtests for each format modifier.
v3: Add IGT description for each subtest (GitLab)
v4: Fix errorneous subtest execution and listing

Bspec: 49252

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 tests/kms_ccs.c | 110 ++++++++++++++++++++++++++++--------------------
 1 file changed, 65 insertions(+), 45 deletions(-)

diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c
index 1ce66cde..41916bb1 100644
--- a/tests/kms_ccs.c
+++ b/tests/kms_ccs.c
@@ -70,10 +70,14 @@ static const struct {
 	{0.0, 1.0, 0.0}
 };
 
-static const uint64_t ccs_modifiers[] = {
-	LOCAL_I915_FORMAT_MOD_Y_TILED_CCS,
-	LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS,
-};
+static const struct {
+	uint64_t modifier;
+	char name[8];
+} ccs_modifiers[3] = {
+	{LOCAL_I915_FORMAT_MOD_Y_TILED_CCS, "Y"},
+	{LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS, "Yf"},
+	{LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, "Y-rc"},
+ };
 
 /*
  * Limit maximum used sprite plane width so this test will not mistakenly
@@ -300,17 +304,14 @@ static int test_ccs(data_t *data)
 static int __test_output(data_t *data)
 {
 	igt_display_t *display = &data->display;
-	int i, valid_tests = 0;
+	int valid_tests = 0;
 
 	data->output = igt_get_single_output_for_pipe(display, data->pipe);
 	igt_require(data->output);
 
 	igt_output_set_pipe(data->output, data->pipe);
 
-	for (i = 0; i < ARRAY_SIZE(ccs_modifiers); i++) {
-		data->ccs_modifier = ccs_modifiers[i];
-		valid_tests += test_ccs(data);
-	}
+	valid_tests += test_ccs(data);
 
 	igt_output_set_pipe(data->output, PIPE_NONE);
 	igt_display_commit2(display, display->is_atomic ? COMMIT_ATOMIC : COMMIT_LEGACY);
@@ -320,7 +321,12 @@ static int __test_output(data_t *data)
 
 static void test_output(data_t *data)
 {
-	int valid_tests = __test_output(data);
+	int valid_tests;
+
+	igt_skip_on(!igt_display_has_format_mod(&data->display, DRM_FORMAT_XRGB8888,
+						data->ccs_modifier));
+
+	valid_tests = __test_output(data);
 	igt_require_f(valid_tests > 0, "CCS not supported, skipping\n");
 }
 
@@ -328,12 +334,14 @@ static data_t data;
 
 igt_main
 {
+	int i, gen;
 	enum pipe pipe;
 
 	igt_fixture {
 		data.drm_fd = drm_open_driver_master(DRIVER_INTEL);
 
-		igt_require(intel_gen(intel_get_drm_devid(data.drm_fd)) >= 9);
+		gen = intel_gen(intel_get_drm_devid(data.drm_fd));
+		igt_require(gen >= 9);
 		kmstest_set_vt_graphics_mode();
 		igt_require_pipe_crc(data.drm_fd);
 
@@ -345,51 +353,63 @@ igt_main
 
 		data.pipe = pipe;
 
-		data.flags = TEST_BAD_PIXEL_FORMAT;
-		igt_subtest_f("pipe-%s-bad-pixel-format", pipe_name)
-			test_output(&data);
+		for (i = 0; i < ARRAY_SIZE(ccs_modifiers); i++) {
+			data.ccs_modifier = ccs_modifiers[i].modifier;
 
-		data.flags = TEST_BAD_ROTATION_90;
-		igt_subtest_f("pipe-%s-bad-rotation-90", pipe_name)
-			test_output(&data);
+			data.flags = TEST_BAD_PIXEL_FORMAT;
+			igt_describe("Test bad pixel format with given CCS modifier");
+			igt_subtest_f("pipe-%s-tiling-%s-bad-pixel-format", pipe_name, ccs_modifiers[i].name)
+				test_output(&data);
 
-		data.flags = TEST_CRC;
-		igt_subtest_f("pipe-%s-crc-primary-basic", pipe_name)
-			test_output(&data);
+			data.flags = TEST_BAD_ROTATION_90;
+			igt_describe("Test 90 degree rotation with given CCS modifier");
+			igt_subtest_f("pipe-%s-tiling-%s-bad-rotation-90", pipe_name, ccs_modifiers[i].name)
+				test_output(&data);
 
-		data.flags = TEST_CRC | TEST_ROTATE_180;
-		igt_subtest_f("pipe-%s-crc-primary-rotation-180", pipe_name)
-			test_output(&data);
+			data.flags = TEST_CRC;
+			igt_describe("Test primary plane CRC compatibility with given CCS modifier");
+			igt_subtest_f("pipe-%s-tiling-%s-crc-primary-basic", pipe_name, ccs_modifiers[i].name)
+				test_output(&data);
 
-		data.flags = TEST_CRC;
-		igt_subtest_f("pipe-%s-crc-sprite-planes-basic", pipe_name) {
-			int valid_tests = 0;
+			data.flags = TEST_CRC | TEST_ROTATE_180;
+			igt_describe("Test 180 degree rotation with given CCS modifier");
+			igt_subtest_f("pipe-%s-tiling-%s-crc-primary-rotation-180", pipe_name, ccs_modifiers[i].name)
+				test_output(&data);
 
-			igt_display_require_output_on_pipe(&data.display, data.pipe);
+			data.flags = TEST_CRC;
+			igt_describe("Test sprite plane CRC compatibility with given CCS modifier");
+			igt_subtest_f("pipe-%s-tiling-%s-crc-sprite-planes-basic", pipe_name, ccs_modifiers[i].name) {
+				int valid_tests = 0;
 
-			for_each_plane_on_pipe(&data.display, data.pipe, data.plane) {
-				if (data.plane->type == DRM_PLANE_TYPE_PRIMARY)
-					continue;
-				valid_tests += __test_output(&data);
-			}
+				igt_display_require_output_on_pipe(&data.display, data.pipe);
 
-			igt_require_f(valid_tests > 0,
-				      "CCS not supported, skipping\n");
-		}
+				for_each_plane_on_pipe(&data.display, data.pipe, data.plane) {
+					if (data.plane->type == DRM_PLANE_TYPE_PRIMARY)
+						continue;
+					valid_tests += __test_output(&data);
+				}
 
-		data.plane = NULL;
+				igt_require_f(valid_tests > 0,
+					      "CCS not supported, skipping\n");
+			}
 
-		data.flags = TEST_NO_AUX_BUFFER;
-		igt_subtest_f("pipe-%s-missing-ccs-buffer", pipe_name)
-			test_output(&data);
+			data.plane = NULL;
 
-		data.flags = TEST_BAD_CCS_HANDLE;
-		igt_subtest_f("pipe-%s-ccs-on-another-bo", pipe_name)
-			test_output(&data);
+			data.flags = TEST_NO_AUX_BUFFER;
+			igt_describe("Test missing CCS buffer with given CCS modifier");
+			igt_subtest_f("pipe-%s-tiling-%s-missing-ccs-buffer", pipe_name, ccs_modifiers[i].name)
+				test_output(&data);
 
-		data.flags = TEST_BAD_AUX_STRIDE;
-		igt_subtest_f("pipe-%s-bad-aux-stride", pipe_name)
-			test_output(&data);
+			data.flags = TEST_BAD_CCS_HANDLE;
+			igt_describe("Test CCS with different BO with given modifier");
+			igt_subtest_f("pipe-%s-tiling-%s-ccs-on-another-bo", pipe_name, ccs_modifiers[i].name)
+				test_output(&data);
+
+			data.flags = TEST_BAD_AUX_STRIDE;
+			igt_describe("Test with bad AUX stride with given CCS modifier");
+			igt_subtest_f("pipe-%s-tiling-%s-bad-aux-stride", pipe_name, ccs_modifiers[i].name)
+				test_output(&data);
+		}
 	}
 
 	igt_fixture
-- 
2.17.1

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Re: [igt-dev] [PATCH i-g-t v4 1/3] Format modifier for Intel Gen-12 render compression

[Petri Latvala]

On Mon, Nov 11, 2019 at 01:00:47PM +0200, Mika Kahola wrote:
> Gen-12 has a new compression format for render compression.
> For this, a new modifier is needed to indicate that.
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
>  include/drm-uapi/drm_fourcc.h | 1 +
>  lib/ioctl_wrappers.h          | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/include/drm-uapi/drm_fourcc.h b/include/drm-uapi/drm_fourcc.h
> index 3feeaa3f..b93eb2d4 100644
> --- a/include/drm-uapi/drm_fourcc.h
> +++ b/include/drm-uapi/drm_fourcc.h
> @@ -409,6 +409,7 @@ extern "C" {
>   */
>  #define I915_FORMAT_MOD_Y_TILED_CCS	fourcc_mod_code(INTEL, 4)
>  #define I915_FORMAT_MOD_Yf_TILED_CCS	fourcc_mod_code(INTEL, 5)
> +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
>  
>  /*
>   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
> index 03211c97..f2412d78 100644
> --- a/lib/ioctl_wrappers.h
> +++ b/lib/ioctl_wrappers.h
> @@ -200,6 +200,7 @@ struct local_drm_mode_fb_cmd2 {
>  #define LOCAL_I915_FORMAT_MOD_Yf_TILED	local_fourcc_mod_code(INTEL, 3)
>  #define LOCAL_I915_FORMAT_MOD_Y_TILED_CCS	local_fourcc_mod_code(INTEL, 4)
>  #define LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS	local_fourcc_mod_code(INTEL, 5)
> +#define LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)

Why do we carry these LOCAL_ defines when we have the kernel uapi
headers copied that define them?

-- 
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Re: [igt-dev] [PATCH i-g-t v4 1/3] Format modifier for Intel Gen-12 render compression

[Kahola, Mika]

On Mon, 2019-11-11 at 13:08 +0200, Petri Latvala wrote:
> On Mon, Nov 11, 2019 at 01:00:47PM +0200, Mika Kahola wrote:
> > Gen-12 has a new compression format for render compression.
> > For this, a new modifier is needed to indicate that.
> > 
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > ---
> >  include/drm-uapi/drm_fourcc.h | 1 +
> >  lib/ioctl_wrappers.h          | 1 +
> >  2 files changed, 2 insertions(+)
> > 
> > diff --git a/include/drm-uapi/drm_fourcc.h b/include/drm-
> > uapi/drm_fourcc.h
> > index 3feeaa3f..b93eb2d4 100644
> > --- a/include/drm-uapi/drm_fourcc.h
> > +++ b/include/drm-uapi/drm_fourcc.h
> > @@ -409,6 +409,7 @@ extern "C" {
> >   */
> >  #define I915_FORMAT_MOD_Y_TILED_CCS	fourcc_mod_code(INTEL,
> > 4)
> >  #define I915_FORMAT_MOD_Yf_TILED_CCS	fourcc_mod_code(INTEL,
> > 5)
> > +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS
> > fourcc_mod_code(INTEL, 6)
> >  
> >  /*
> >   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized
> > macroblocks
> > diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
> > index 03211c97..f2412d78 100644
> > --- a/lib/ioctl_wrappers.h
> > +++ b/lib/ioctl_wrappers.h
> > @@ -200,6 +200,7 @@ struct local_drm_mode_fb_cmd2 {
> >  #define LOCAL_I915_FORMAT_MOD_Yf_TILED	local_fourcc_mod_code(I
> > NTEL, 3)
> >  #define LOCAL_I915_FORMAT_MOD_Y_TILED_CCS	local_fourcc_mod_code(I
> > NTEL, 4)
> >  #define LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS	local_fourcc_mod_code(I
> > NTEL, 5)
> > +#define LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS
> > fourcc_mod_code(INTEL, 6)
> 
> Why do we carry these LOCAL_ defines when we have the kernel uapi
> headers copied that define them?
I guess there was some historical reason to do this, which I don't
know.

Maybe we could prepare a clean up patch and drop these local
definitions altogether?


> 
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Re: [igt-dev] [PATCH i-g-t v4 1/3] Format modifier for Intel Gen-12 render compression

[Petri Latvala]

On Mon, Nov 11, 2019 at 01:36:47PM +0200, Kahola, Mika wrote:
> On Mon, 2019-11-11 at 13:08 +0200, Petri Latvala wrote:
> > On Mon, Nov 11, 2019 at 01:00:47PM +0200, Mika Kahola wrote:
> > > Gen-12 has a new compression format for render compression.
> > > For this, a new modifier is needed to indicate that.
> > > 
> > > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > > Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > > ---
> > >  include/drm-uapi/drm_fourcc.h | 1 +
> > >  lib/ioctl_wrappers.h          | 1 +
> > >  2 files changed, 2 insertions(+)
> > > 
> > > diff --git a/include/drm-uapi/drm_fourcc.h b/include/drm-
> > > uapi/drm_fourcc.h
> > > index 3feeaa3f..b93eb2d4 100644
> > > --- a/include/drm-uapi/drm_fourcc.h
> > > +++ b/include/drm-uapi/drm_fourcc.h
> > > @@ -409,6 +409,7 @@ extern "C" {
> > >   */
> > >  #define I915_FORMAT_MOD_Y_TILED_CCS	fourcc_mod_code(INTEL,
> > > 4)
> > >  #define I915_FORMAT_MOD_Yf_TILED_CCS	fourcc_mod_code(INTEL,
> > > 5)
> > > +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS
> > > fourcc_mod_code(INTEL, 6)
> > >  
> > >  /*
> > >   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized
> > > macroblocks
> > > diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
> > > index 03211c97..f2412d78 100644
> > > --- a/lib/ioctl_wrappers.h
> > > +++ b/lib/ioctl_wrappers.h
> > > @@ -200,6 +200,7 @@ struct local_drm_mode_fb_cmd2 {
> > >  #define LOCAL_I915_FORMAT_MOD_Yf_TILED	local_fourcc_mod_code(I
> > > NTEL, 3)
> > >  #define LOCAL_I915_FORMAT_MOD_Y_TILED_CCS	local_fourcc_mod_code(I
> > > NTEL, 4)
> > >  #define LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS	local_fourcc_mod_code(I
> > > NTEL, 5)
> > > +#define LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS
> > > fourcc_mod_code(INTEL, 6)
> > 
> > Why do we carry these LOCAL_ defines when we have the kernel uapi
> > headers copied that define them?
> I guess there was some historical reason to do this, which I don't
> know.

Possibly from the time before we began to copy the uapi headers.

> Maybe we could prepare a clean up patch and drop these local
> definitions altogether?

Yeah that would be nice.

Don't let it hold this series as such, though, can happen in another.


-- 
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[igt-dev] ✓ Fi.CI.BAT: success for GEN12 render decompression (rev4)

[Patchwork]

== Series Details ==

Series: GEN12 render decompression (rev4)
URL   : https://patchwork.freedesktop.org/series/68937/
State : success

== Summary ==

CI Bug Log - changes from IGT_5269 -> IGTPW_3680
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/index.html

Known issues
------------

  Here are the changes found in IGTPW_3680 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic:
    - fi-icl-u4:          [PASS][1] -> [FAIL][2] ([fdo#111699])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5269/fi-icl-u4/igt@gem_exec_suspend@basic.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/fi-icl-u4/igt@gem_exec_suspend@basic.html

  * igt@i915_selftest@live_blt:
    - fi-bsw-n3050:       [PASS][3] -> [DMESG-FAIL][4] ([fdo#112176])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5269/fi-bsw-n3050/igt@i915_selftest@live_blt.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/fi-bsw-n3050/igt@i915_selftest@live_blt.html

  * igt@kms_chamelium@dp-edid-read:
    - fi-kbl-7500u:       [PASS][5] -> [WARN][6] ([fdo#109483])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5269/fi-kbl-7500u/igt@kms_chamelium@dp-edid-read.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/fi-kbl-7500u/igt@kms_chamelium@dp-edid-read.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [PASS][7] -> [FAIL][8] ([fdo#111045] / [fdo#111096])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5269/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
#### Possible fixes ####

  * igt@i915_module_load@reload-with-fault-injection:
    - fi-bxt-dsi:         [DMESG-WARN][9] -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5269/fi-bxt-dsi/igt@i915_module_load@reload-with-fault-injection.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/fi-bxt-dsi/igt@i915_module_load@reload-with-fault-injection.html

  
  [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111699]: https://bugs.freedesktop.org/show_bug.cgi?id=111699
  [fdo#112176]: https://bugs.freedesktop.org/show_bug.cgi?id=112176


Participating hosts (48 -> 43)
------------------------------

  Missing    (5): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5269 -> IGTPW_3680

  CI-20190529: 20190529
  CI_DRM_7304: 12697c9f87a35e2cb4f002d83bde1ab52d9e8d5e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_3680: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/index.html
  IGT_5269: ad2c18fe450e99d97110db13eebf312dc0fa7b4c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools



== Testlist changes ==

+++ 144 lines
--- 48 lines

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/index.html
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Re: [igt-dev] [PATCH i-g-t v4 2/3] lib/igt_fb.c: Update tile sizes for GEN12 CCS

[Imre Deak]

Hi,

On Mon, Nov 11, 2019 at 01:00:48PM +0200, Mika Kahola wrote:
> Update tile sizes for GEN12 CCS.
> 
> BSpec: 47709
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
>  lib/igt_fb.c | 34 ++++++++++++++++++++++++++++++++--
>  1 file changed, 32 insertions(+), 2 deletions(-)
> 
> diff --git a/lib/igt_fb.c b/lib/igt_fb.c
> index 4adca967..77030d49 100644
> --- a/lib/igt_fb.c
> +++ b/lib/igt_fb.c
> @@ -413,6 +413,33 @@ void igt_get_fb_tile_size(int fd, uint64_t modifier, int fb_bpp,
>  			*height_ret = 32;
>  		}
>  		break;
> +	case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +		igt_require_intel(fd);
> +		switch (fb_bpp) {
> +		case 8:
> +			*width_ret = 512;
> +			*height_ret = 32;
> +			break;
> +		case 16:
> +			*width_ret = 256;
> +			*height_ret = 32;
> +			break;
> +		case 32:
> +			*width_ret = 128;
> +			*height_ret = 32;
> +			break;
> +		case 64:
> +			*width_ret = 64;
> +			*height_ret = 32;
> +			break;
> +		case 128:
> +			*width_ret = 32;
> +			*height_ret = 32;
> +			break;
> +		default:
> +			igt_assert(false);
> +		}
> +		break;

The above look wrong to me, tiles are always 4kB. So the GEN12 y-tiled
tile width, height (CCS or not) are the same as on other platforms.

OTOH, we should align both the main surface and AUX surface width and
height for CCS. Those are setup in igt_init_fb()->fb_plane_height() and
->fb_plane_width(). The main surface (plane 0) should be aligned to 4x4
tiles (128x128 pixels). The AUX surface (plane 1) width/height should
match this, so for that in fb_plane_width():

	return DIV_ROUND_UP(fb->width, 128) * 64;

and in fb_plane_height():

	return DIV_ROUND_UP(fb->height, 128) * 4;


>  	case LOCAL_I915_FORMAT_MOD_Yf_TILED:
>  	case LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS:
>  		igt_require_intel(fd);
> @@ -467,8 +494,10 @@ void igt_get_fb_tile_size(int fd, uint64_t modifier, int fb_bpp,
>  
>  static bool is_ccs_modifier(uint64_t modifier)
>  {
> -	return modifier == LOCAL_I915_FORMAT_MOD_Y_TILED_CCS ||
> -		modifier == LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS;
> +
> +	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> +		modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> +		modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
>  }
>  
>  static unsigned fb_plane_width(const struct igt_fb *fb, int plane)
> @@ -687,6 +716,7 @@ uint64_t igt_fb_mod_to_tiling(uint64_t modifier)
>  		return I915_TILING_X;
>  	case LOCAL_I915_FORMAT_MOD_Y_TILED:
>  	case LOCAL_I915_FORMAT_MOD_Y_TILED_CCS:
> +	case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
>  		return I915_TILING_Y;
>  	case LOCAL_I915_FORMAT_MOD_Yf_TILED:
>  	case LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS:
> -- 
> 2.17.1
> 
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Re: [igt-dev] [PATCH i-g-t v4 2/3] lib/igt_fb.c: Update tile sizes for GEN12 CCS

[Imre Deak]

On Mon, Nov 11, 2019 at 05:22:32PM +0200, Imre Deak wrote:
> Hi,
> 
> On Mon, Nov 11, 2019 at 01:00:48PM +0200, Mika Kahola wrote:
> > Update tile sizes for GEN12 CCS.
> > 
> > BSpec: 47709
> > 
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > ---
> >  lib/igt_fb.c | 34 ++++++++++++++++++++++++++++++++--
> >  1 file changed, 32 insertions(+), 2 deletions(-)
> > 
> > diff --git a/lib/igt_fb.c b/lib/igt_fb.c
> > index 4adca967..77030d49 100644
> > --- a/lib/igt_fb.c
> > +++ b/lib/igt_fb.c
> > @@ -413,6 +413,33 @@ void igt_get_fb_tile_size(int fd, uint64_t modifier, int fb_bpp,
> >  			*height_ret = 32;
> >  		}
> >  		break;
> > +	case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > +		igt_require_intel(fd);
> > +		switch (fb_bpp) {
> > +		case 8:
> > +			*width_ret = 512;
> > +			*height_ret = 32;
> > +			break;
> > +		case 16:
> > +			*width_ret = 256;
> > +			*height_ret = 32;
> > +			break;
> > +		case 32:
> > +			*width_ret = 128;
> > +			*height_ret = 32;
> > +			break;
> > +		case 64:
> > +			*width_ret = 64;
> > +			*height_ret = 32;
> > +			break;
> > +		case 128:
> > +			*width_ret = 32;
> > +			*height_ret = 32;
> > +			break;
> > +		default:
> > +			igt_assert(false);
> > +		}
> > +		break;
> 
> The above look wrong to me, tiles are always 4kB. So the GEN12 y-tiled
> tile width, height (CCS or not) are the same as on other platforms.
> 
> OTOH, we should align both the main surface and AUX surface width and
> height for CCS. Those are setup in igt_init_fb()->fb_plane_height() and
> ->fb_plane_width(). The main surface (plane 0) should be aligned to 4x4
> tiles (128x128 pixels).

and 128x128 is the case for 32bpp. For all bpps:

bpp	width	height
8	512	128
16	256	128
32	128	128
64	64	128
128	32	128

> The AUX surface (plane 1) width/height should match this, so for that
> in fb_plane_width():
> 
> 	return DIV_ROUND_UP(fb->width, 128) * 64;

and here the divisor is based on the bpp as above.

> 
> and in fb_plane_height():
> 
> 	return DIV_ROUND_UP(fb->height, 128) * 4;
> 
> 
> >  	case LOCAL_I915_FORMAT_MOD_Yf_TILED:
> >  	case LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS:
> >  		igt_require_intel(fd);
> > @@ -467,8 +494,10 @@ void igt_get_fb_tile_size(int fd, uint64_t modifier, int fb_bpp,
> >  
> >  static bool is_ccs_modifier(uint64_t modifier)
> >  {
> > -	return modifier == LOCAL_I915_FORMAT_MOD_Y_TILED_CCS ||
> > -		modifier == LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS;
> > +
> > +	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> > +		modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > +		modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> >  }
> >  
> >  static unsigned fb_plane_width(const struct igt_fb *fb, int plane)
> > @@ -687,6 +716,7 @@ uint64_t igt_fb_mod_to_tiling(uint64_t modifier)
> >  		return I915_TILING_X;
> >  	case LOCAL_I915_FORMAT_MOD_Y_TILED:
> >  	case LOCAL_I915_FORMAT_MOD_Y_TILED_CCS:
> > +	case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> >  		return I915_TILING_Y;
> >  	case LOCAL_I915_FORMAT_MOD_Yf_TILED:
> >  	case LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS:
> > -- 
> > 2.17.1
> > 
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
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[igt-dev] ✓ Fi.CI.IGT: success for GEN12 render decompression (rev4)

[Patchwork]

== Series Details ==

Series: GEN12 render decompression (rev4)
URL   : https://patchwork.freedesktop.org/series/68937/
State : success

== Summary ==

CI Bug Log - changes from IGT_5269_full -> IGTPW_3680_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_3680_full:

### IGT changes ###

#### Possible regressions ####

  * {igt@kms_ccs@pipe-c-tiling-y-rc-crc-sprite-planes-basic} (NEW):
    - shard-iclb:         NOTRUN -> [SKIP][1] +30 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/shard-iclb4/igt@kms_ccs@pipe-c-tiling-y-rc-crc-sprite-planes-basic.html

  * {igt@kms_ccs@pipe-c-tiling-yf-crc-sprite-planes-basic} (NEW):
    - shard-tglb:         NOTRUN -> [SKIP][2] +62 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/shard-tglb5/igt@kms_ccs@pipe-c-tiling-yf-crc-sprite-planes-basic.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@i915_pm_dc@dc3co-vpb-simulation}:
    - shard-iclb:         NOTRUN -> [SKIP][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/shard-iclb8/igt@i915_pm_dc@dc3co-vpb-simulation.html

  
New tests
---------

  New tests have been introduced between IGT_5269_full and IGTPW_3680_full:

### New IGT tests (96) ###

  * igt@kms_ccs@pipe-a-tiling-y-bad-aux-stride:
    - Statuses : 4 pass(s) 3 skip(s)
    - Exec time: [0.0, 0.42] s

  * igt@kms_ccs@pipe-a-tiling-y-bad-pixel-format:
    - Statuses : 3 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.24] s

  * igt@kms_ccs@pipe-a-tiling-y-bad-rotation-90:
    - Statuses : 4 pass(s) 3 skip(s)
    - Exec time: [0.0, 0.35] s

  * igt@kms_ccs@pipe-a-tiling-y-ccs-on-another-bo:
    - Statuses : 4 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.29] s

  * igt@kms_ccs@pipe-a-tiling-y-crc-primary-basic:
    - Statuses : 3 pass(s) 3 skip(s)
    - Exec time: [0.0, 0.55] s

  * igt@kms_ccs@pipe-a-tiling-y-crc-primary-rotation-180:
    - Statuses : 4 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.62] s

  * igt@kms_ccs@pipe-a-tiling-y-crc-sprite-planes-basic:
    - Statuses : 4 pass(s) 2 skip(s)
    - Exec time: [0.0, 7.60] s

  * igt@kms_ccs@pipe-a-tiling-y-missing-ccs-buffer:
    - Statuses : 4 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.31] s

  * igt@kms_ccs@pipe-a-tiling-y-rc-bad-aux-stride:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-tiling-y-rc-bad-pixel-format:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-tiling-y-rc-bad-rotation-90:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-tiling-y-rc-ccs-on-another-bo:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-tiling-y-rc-crc-primary-basic:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-tiling-y-rc-crc-primary-rotation-180:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-tiling-y-rc-crc-sprite-planes-basic:
    - Statuses : 7 skip(s)
    - Exec time: [0.0, 0.31] s

  * igt@kms_ccs@pipe-a-tiling-y-rc-missing-ccs-buffer:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-a-tiling-yf-bad-aux-stride:
    - Statuses : 4 pass(s) 3 skip(s)
    - Exec time: [0.0, 0.43] s

  * igt@kms_ccs@pipe-a-tiling-yf-bad-pixel-format:
    - Statuses : 4 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.28] s

  * igt@kms_ccs@pipe-a-tiling-yf-bad-rotation-90:
    - Statuses : 4 pass(s) 3 skip(s)
    - Exec time: [0.0, 0.34] s

  * igt@kms_ccs@pipe-a-tiling-yf-ccs-on-another-bo:
    - Statuses : 4 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.33] s

  * igt@kms_ccs@pipe-a-tiling-yf-crc-primary-basic:
    - Statuses : 4 pass(s) 3 skip(s)
    - Exec time: [0.0, 0.61] s

  * igt@kms_ccs@pipe-a-tiling-yf-crc-primary-rotation-180:
    - Statuses : 4 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.60] s

  * igt@kms_ccs@pipe-a-tiling-yf-crc-sprite-planes-basic:
    - Statuses : 4 pass(s) 3 skip(s)
    - Exec time: [0.0, 7.57] s

  * igt@kms_ccs@pipe-a-tiling-yf-missing-ccs-buffer:
    - Statuses : 4 pass(s) 3 skip(s)
    - Exec time: [0.0, 0.33] s

  * igt@kms_ccs@pipe-b-tiling-y-bad-aux-stride:
    - Statuses : 4 pass(s) 3 skip(s)
    - Exec time: [0.0, 0.42] s

  * igt@kms_ccs@pipe-b-tiling-y-bad-pixel-format:
    - Statuses : 4 pass(s) 3 skip(s)
    - Exec time: [0.0, 0.30] s

  * igt@kms_ccs@pipe-b-tiling-y-bad-rotation-90:
    - Statuses : 4 pass(s) 2 skip(s)
    - Exec time: [0.0, 1.45] s

  * igt@kms_ccs@pipe-b-tiling-y-ccs-on-another-bo:
    - Statuses : 4 pass(s) 3 skip(s)
    - Exec time: [0.0, 0.32] s

  * igt@kms_ccs@pipe-b-tiling-y-crc-primary-basic:
    - Statuses : 4 pass(s) 3 skip(s)
    - Exec time: [0.0, 1.95] s

  * igt@kms_ccs@pipe-b-tiling-y-crc-primary-rotation-180:
    - Statuses : 4 pass(s) 3 skip(s)
    - Exec time: [0.0, 1.70] s

  * igt@kms_ccs@pipe-b-tiling-y-crc-sprite-planes-basic:
    - Statuses : 4 pass(s) 2 skip(s)
    - Exec time: [0.0, 8.74] s

  * igt@kms_ccs@pipe-b-tiling-y-missing-ccs-buffer:
    - Statuses : 4 pass(s) 3 skip(s)
    - Exec time: [0.0, 0.34] s

  * igt@kms_ccs@pipe-b-tiling-y-rc-bad-aux-stride:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-tiling-y-rc-bad-pixel-format:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-tiling-y-rc-bad-rotation-90:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-tiling-y-rc-ccs-on-another-bo:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-tiling-y-rc-crc-primary-basic:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-tiling-y-rc-crc-primary-rotation-180:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-tiling-y-rc-crc-sprite-planes-basic:
    - Statuses : 7 skip(s)
    - Exec time: [0.0, 0.30] s

  * igt@kms_ccs@pipe-b-tiling-y-rc-missing-ccs-buffer:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-b-tiling-yf-bad-aux-stride:
    - Statuses : 3 pass(s) 3 skip(s)
    - Exec time: [0.0, 0.44] s

  * igt@kms_ccs@pipe-b-tiling-yf-bad-pixel-format:
    - Statuses : 4 pass(s) 3 skip(s)
    - Exec time: [0.0, 0.29] s

  * igt@kms_ccs@pipe-b-tiling-yf-bad-rotation-90:
    - Statuses : 4 pass(s) 2 skip(s)
    - Exec time: [0.0, 1.46] s

  * igt@kms_ccs@pipe-b-tiling-yf-ccs-on-another-bo:
    - Statuses : 4 pass(s) 3 skip(s)
    - Exec time: [0.0, 0.34] s

  * igt@kms_ccs@pipe-b-tiling-yf-crc-primary-basic:
    - Statuses : 4 pass(s) 2 skip(s)
    - Exec time: [0.0, 1.90] s

  * igt@kms_ccs@pipe-b-tiling-yf-crc-primary-rotation-180:
    - Statuses : 4 pass(s) 3 skip(s)
    - Exec time: [0.0, 1.68] s

  * igt@kms_ccs@pipe-b-tiling-yf-crc-sprite-planes-basic:
    - Statuses : 3 pass(s) 3 skip(s)
    - Exec time: [0.0, 1.54] s

  * igt@kms_ccs@pipe-b-tiling-yf-missing-ccs-buffer:
    - Statuses : 4 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.30] s

  * igt@kms_ccs@pipe-c-tiling-y-bad-aux-stride:
    - Statuses : 1 pass(s) 5 skip(s)
    - Exec time: [0.0, 0.36] s

  * igt@kms_ccs@pipe-c-tiling-y-bad-pixel-format:
    - Statuses : 1 pass(s) 6 skip(s)
    - Exec time: [0.0, 0.28] s

  * igt@kms_ccs@pipe-c-tiling-y-bad-rotation-90:
    - Statuses : 1 pass(s) 5 skip(s)
    - Exec time: [0.0, 1.48] s

  * igt@kms_ccs@pipe-c-tiling-y-ccs-on-another-bo:
    - Statuses : 1 pass(s) 5 skip(s)
    - Exec time: [0.0, 0.31] s

  * igt@kms_ccs@pipe-c-tiling-y-crc-primary-basic:
    - Statuses : 6 skip(s)
    - Exec time: [0.0, 0.25] s

  * igt@kms_ccs@pipe-c-tiling-y-crc-primary-rotation-180:
    - Statuses : 1 pass(s) 6 skip(s)
    - Exec time: [0.0, 1.63] s

  * igt@kms_ccs@pipe-c-tiling-y-crc-sprite-planes-basic:
    - Statuses : 1 pass(s) 6 skip(s)
    - Exec time: [0.0, 8.73] s

  * igt@kms_ccs@pipe-c-tiling-y-missing-ccs-buffer:
    - Statuses : 1 pass(s) 6 skip(s)
    - Exec time: [0.0, 0.30] s

  * igt@kms_ccs@pipe-c-tiling-y-rc-bad-aux-stride:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-tiling-y-rc-bad-pixel-format:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-tiling-y-rc-bad-rotation-90:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-tiling-y-rc-ccs-on-another-bo:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-tiling-y-rc-crc-primary-basic:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-tiling-y-rc-crc-primary-rotation-180:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-tiling-y-rc-crc-sprite-planes-basic:
    - Statuses : 7 skip(s)
    - Exec time: [0.0, 0.30] s

  * igt@kms_ccs@pipe-c-tiling-y-rc-missing-ccs-buffer:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-c-tiling-yf-bad-aux-stride:
    - Statuses : 1 pass(s) 5 skip(s)
    - Exec time: [0.0, 0.36] s

  * igt@kms_ccs@pipe-c-tiling-yf-bad-pixel-format:
    - Statuses : 1 pass(s) 6 skip(s)
    - Exec time: [0.0, 0.29] s

  * igt@kms_ccs@pipe-c-tiling-yf-bad-rotation-90:
    - Statuses : 1 pass(s) 5 skip(s)
    - Exec time: [0.0, 1.41] s

  * igt@kms_ccs@pipe-c-tiling-yf-ccs-on-another-bo:
    - Statuses : 1 pass(s) 6 skip(s)
    - Exec time: [0.0, 0.33] s

  * igt@kms_ccs@pipe-c-tiling-yf-crc-primary-basic:
    - Statuses : 1 pass(s) 6 skip(s)
    - Exec time: [0.0, 1.67] s

  * igt@kms_ccs@pipe-c-tiling-yf-crc-primary-rotation-180:
    - Statuses : 1 pass(s) 6 skip(s)
    - Exec time: [0.0, 1.66] s

  * igt@kms_ccs@pipe-c-tiling-yf-crc-sprite-planes-basic:
    - Statuses : 1 pass(s) 6 skip(s)
    - Exec time: [0.0, 8.76] s

  * igt@kms_ccs@pipe-c-tiling-yf-missing-ccs-buffer:
    - Statuses : 1 pass(s) 5 skip(s)
    - Exec time: [0.0, 0.30] s

  * igt@kms_ccs@pipe-d-tiling-y-bad-aux-stride:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-tiling-y-bad-pixel-format:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-tiling-y-bad-rotation-90:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-tiling-y-ccs-on-another-bo:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-tiling-y-crc-primary-basic:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-tiling-y-crc-primary-rotation-180:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-tiling-y-crc-sprite-planes-basic:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-tiling-y-missing-ccs-buffer:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-tiling-y-rc-bad-aux-stride:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-tiling-y-rc-bad-pixel-format:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-tiling-y-rc-bad-rotation-90:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-tiling-y-rc-ccs-on-another-bo:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-tiling-y-rc-crc-primary-basic:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-tiling-y-rc-crc-primary-rotation-180:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-tiling-y-rc-crc-sprite-planes-basic:
    - Statuses : 6 skip(s)
    - Exec time: [0.0, 0.30] s

  * igt@kms_ccs@pipe-d-tiling-y-rc-missing-ccs-buffer:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-tiling-yf-bad-aux-stride:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-tiling-yf-bad-pixel-format:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-tiling-yf-bad-rotation-90:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-tiling-yf-ccs-on-another-bo:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-tiling-yf-crc-primary-basic:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-tiling-yf-crc-primary-rotation-180:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-tiling-yf-crc-sprite-planes-basic:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_ccs@pipe-d-tiling-yf-missing-ccs-buffer:
    - Statuses : 6 skip(s)
    - Exec time: [0.0, 0.00] s

  

Known issues
------------

  Here are the changes found in IGTPW_3680_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_persistence@vcs1-mixed-process:
    - shard-iclb:         [PASS][4] -> [SKIP][5] ([fdo#109276] / [fdo#112080]) +1 similar issue
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5269/shard-iclb2/igt@gem_ctx_persistence@vcs1-mixed-process.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/shard-iclb8/igt@gem_ctx_persistence@vcs1-mixed-process.html

  * igt@gem_ctx_shared@q-smoketest-all:
    - shard-tglb:         [PASS][6] -> [INCOMPLETE][7] ([fdo#111735])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5269/shard-tglb4/igt@gem_ctx_shared@q-smoketest-all.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/shard-tglb9/igt@gem_ctx_shared@q-smoketest-all.html

  * igt@gem_eio@unwedge-stress:
    - shard-snb:          [PASS][8] -> [FAIL][9] ([fdo#109661])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5269/shard-snb2/igt@gem_eio@unwedge-stress.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/shard-snb7/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_async@concurrent-writes-bsd:
    - shard-iclb:         [PASS][10] -> [SKIP][11] ([fdo#112146]) +3 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5269/shard-iclb8/igt@gem_exec_async@concurrent-writes-bsd.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/shard-iclb2/igt@gem_exec_async@concurrent-writes-bsd.html

  * igt@gem_exec_schedule@preempt-queue-chain-vebox:
    - shard-tglb:         [PASS][12] -> [INCOMPLETE][13] ([fdo#111677])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5269/shard-tglb4/igt@gem_exec_schedule@preempt-queue-chain-vebox.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/shard-tglb6/igt@gem_exec_schedule@preempt-queue-chain-vebox.html

  * igt@gem_persistent_relocs@forked-faulting-reloc-thrashing:
    - shard-iclb:         [PASS][14] -> [TIMEOUT][15] ([fdo#112068 ])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5269/shard-iclb3/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/shard-iclb2/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html

  * igt@gem_userptr_blits@sync-unmap-cycles:
    - shard-snb:          [PASS][16] -> [DMESG-WARN][17] ([fdo#111870])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5269/shard-snb1/igt@gem_userptr_blits@sync-unmap-cycles.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/shard-snb5/igt@gem_userptr_blits@sync-unmap-cycles.html
    - shard-hsw:          [PASS][18] -> [DMESG-WARN][19] ([fdo#111870]) +1 similar issue
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5269/shard-hsw2/igt@gem_userptr_blits@sync-unmap-cycles.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/shard-hsw5/igt@gem_userptr_blits@sync-unmap-cycles.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-kbl:          [PASS][20] -> [DMESG-WARN][21] ([fdo#108566]) +3 similar issues
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5269/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/shard-kbl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-apl:          [PASS][22] -> [DMESG-WARN][23] ([fdo#108566]) +2 similar issues
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5269/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render:
    - shard-iclb:         [PASS][24] -> [FAIL][25] ([fdo#103167])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5269/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move:
    - shard-tglb:         [PASS][26] -> [FAIL][27] ([fdo#103167]) +1 similar issue
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5269/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html

  * igt@kms_plane_lowres@pipe-a-tiling-y:
    - shard-iclb:         [PASS][28] -> [FAIL][29] ([fdo#103166])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5269/shard-iclb1/igt@kms_plane_lowres@pipe-a-tiling-y.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/shard-iclb4/igt@kms_plane_lowres@pipe-a-tiling-y.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-iclb:         [PASS][30] -> [SKIP][31] ([fdo#109642] / [fdo#111068])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5269/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/shard-iclb3/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_setmode@basic:
    - shard-apl:          [PASS][32] -> [FAIL][33] ([fdo#99912])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5269/shard-apl6/igt@kms_setmode@basic.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/shard-apl3/igt@kms_setmode@basic.html
    - shard-kbl:          [PASS][34] -> [FAIL][35] ([fdo#99912])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5269/shard-kbl2/igt@kms_setmode@basic.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/shard-kbl3/igt@kms_setmode@basic.html

  * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
    - shard-tglb:         [PASS][36] -> [INCOMPLETE][37] ([fdo#111832] / [fdo#111850]) +2 similar issues
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5269/shard-tglb5/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/shard-tglb8/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html

  * igt@perf_pmu@busy-no-semaphores-vcs1:
    - shard-iclb:         [PASS][38] -> [SKIP][39] ([fdo#112080]) +12 similar issues
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5269/shard-iclb1/igt@perf_pmu@busy-no-semaphores-vcs1.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/shard-iclb8/igt@perf_pmu@busy-no-semaphores-vcs1.html

  * igt@prime_vgem@fence-wait-bsd2:
    - shard-iclb:         [PASS][40] -> [SKIP][41] ([fdo#109276]) +13 similar issues
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5269/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/shard-iclb7/igt@prime_vgem@fence-wait-bsd2.html

  
#### Possible fixes ####

  * igt@gem_ctx_exec@basic-invalid-context-vcs1:
    - shard-iclb:         [SKIP][42] ([fdo#112080]) -> [PASS][43] +12 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5269/shard-iclb7/igt@gem_ctx_exec@basic-invalid-context-vcs1.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/shard-iclb4/igt@gem_ctx_exec@basic-invalid-context-vcs1.html

  * igt@gem_ctx_isolation@vcs1-s3:
    - shard-tglb:         [INCOMPLETE][44] ([fdo#111832]) -> [PASS][45]
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5269/shard-tglb5/igt@gem_ctx_isolation@vcs1-s3.html
   [45]: https://intel-gfx-ci.01.org/tre

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3680/index.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

Re: [igt-dev] [PATCH i-g-t v4 2/3] lib/igt_fb.c: Update tile sizes for GEN12 CCS

[Kahola, Mika]

On Mon, 2019-11-11 at 17:51 +0200, Imre Deak wrote:
> On Mon, Nov 11, 2019 at 05:22:32PM +0200, Imre Deak wrote:
> > Hi,
> > 
> > On Mon, Nov 11, 2019 at 01:00:48PM +0200, Mika Kahola wrote:
> > > Update tile sizes for GEN12 CCS.
> > > 
> > > BSpec: 47709
> > > 
> > > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > > Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com
> > > >
> > > ---
> > >  lib/igt_fb.c | 34 ++++++++++++++++++++++++++++++++--
> > >  1 file changed, 32 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/lib/igt_fb.c b/lib/igt_fb.c
> > > index 4adca967..77030d49 100644
> > > --- a/lib/igt_fb.c
> > > +++ b/lib/igt_fb.c
> > > @@ -413,6 +413,33 @@ void igt_get_fb_tile_size(int fd, uint64_t
> > > modifier, int fb_bpp,
> > >  			*height_ret = 32;
> > >  		}
> > >  		break;
> > > +	case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > > +		igt_require_intel(fd);
> > > +		switch (fb_bpp) {
> > > +		case 8:
> > > +			*width_ret = 512;
> > > +			*height_ret = 32;
> > > +			break;
> > > +		case 16:
> > > +			*width_ret = 256;
> > > +			*height_ret = 32;
> > > +			break;
> > > +		case 32:
> > > +			*width_ret = 128;
> > > +			*height_ret = 32;
> > > +			break;
> > > +		case 64:
> > > +			*width_ret = 64;
> > > +			*height_ret = 32;
> > > +			break;
> > > +		case 128:
> > > +			*width_ret = 32;
> > > +			*height_ret = 32;
> > > +			break;
> > > +		default:
> > > +			igt_assert(false);
> > > +		}
> > > +		break;
> > 
> > The above look wrong to me, tiles are always 4kB. So the GEN12 y-
> > tiled
> > tile width, height (CCS or not) are the same as on other platforms.
> > 
> > OTOH, we should align both the main surface and AUX surface width
> > and
> > height for CCS. Those are setup in igt_init_fb()->fb_plane_height() 
> > and
> > ->fb_plane_width(). The main surface (plane 0) should be aligned to
> > 4x4
> > tiles (128x128 pixels).
> 
> and 128x128 is the case for 32bpp. For all bpps:
> 
> bpp	width	height
> 8	512	128
> 16	256	128
> 32	128	128
> 64	64	128
> 128	32	128
Ok, the numbers that I wrote originally above was found from BSpec.
Since the tiles are always 4kB, I could update the patch with the
numbers you provided.

> 
> > The AUX surface (plane 1) width/height should match this, so for
> > that
> > in fb_plane_width():
> > 
> > 	return DIV_ROUND_UP(fb->width, 128) * 64;
> 
> and here the divisor is based on the bpp as above.
> 
> > 
> > and in fb_plane_height():
> > 
> > 	return DIV_ROUND_UP(fb->height, 128) * 4;
> > 
> > 
> > >  	case LOCAL_I915_FORMAT_MOD_Yf_TILED:
> > >  	case LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS:
> > >  		igt_require_intel(fd);
> > > @@ -467,8 +494,10 @@ void igt_get_fb_tile_size(int fd, uint64_t
> > > modifier, int fb_bpp,
> > >  
> > >  static bool is_ccs_modifier(uint64_t modifier)
> > >  {
> > > -	return modifier == LOCAL_I915_FORMAT_MOD_Y_TILED_CCS ||
> > > -		modifier == LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS;
> > > +
> > > +	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> > > +		modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > > +		modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > >  }
> > >  
> > >  static unsigned fb_plane_width(const struct igt_fb *fb, int
> > > plane)
> > > @@ -687,6 +716,7 @@ uint64_t igt_fb_mod_to_tiling(uint64_t
> > > modifier)
> > >  		return I915_TILING_X;
> > >  	case LOCAL_I915_FORMAT_MOD_Y_TILED:
> > >  	case LOCAL_I915_FORMAT_MOD_Y_TILED_CCS:
> > > +	case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > >  		return I915_TILING_Y;
> > >  	case LOCAL_I915_FORMAT_MOD_Yf_TILED:
> > >  	case LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS:
> > > -- 
> > > 2.17.1
> > > 
> > 
> > _______________________________________________
> > igt-dev mailing list
> > igt-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/igt-dev
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Re: [igt-dev] [PATCH i-g-t v4 2/3] lib/igt_fb.c: Update tile sizes for GEN12 CCS

[Imre Deak]

On Tue, Nov 12, 2019 at 09:40:10AM +0200, Kahola, Mika wrote:
> On Mon, 2019-11-11 at 17:51 +0200, Imre Deak wrote:
> > On Mon, Nov 11, 2019 at 05:22:32PM +0200, Imre Deak wrote:
> > > Hi,
> > > 
> > > On Mon, Nov 11, 2019 at 01:00:48PM +0200, Mika Kahola wrote:
> > > > Update tile sizes for GEN12 CCS.
> > > > 
> > > > BSpec: 47709
> > > > 
> > > > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > > > Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com
> > > > >
> > > > ---
> > > >  lib/igt_fb.c | 34 ++++++++++++++++++++++++++++++++--
> > > >  1 file changed, 32 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/lib/igt_fb.c b/lib/igt_fb.c
> > > > index 4adca967..77030d49 100644
> > > > --- a/lib/igt_fb.c
> > > > +++ b/lib/igt_fb.c
> > > > @@ -413,6 +413,33 @@ void igt_get_fb_tile_size(int fd, uint64_t
> > > > modifier, int fb_bpp,
> > > >  			*height_ret = 32;
> > > >  		}
> > > >  		break;
> > > > +	case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > > > +		igt_require_intel(fd);
> > > > +		switch (fb_bpp) {
> > > > +		case 8:
> > > > +			*width_ret = 512;
> > > > +			*height_ret = 32;
> > > > +			break;
> > > > +		case 16:
> > > > +			*width_ret = 256;
> > > > +			*height_ret = 32;
> > > > +			break;
> > > > +		case 32:
> > > > +			*width_ret = 128;
> > > > +			*height_ret = 32;
> > > > +			break;
> > > > +		case 64:
> > > > +			*width_ret = 64;
> > > > +			*height_ret = 32;
> > > > +			break;
> > > > +		case 128:
> > > > +			*width_ret = 32;
> > > > +			*height_ret = 32;
> > > > +			break;
> > > > +		default:
> > > > +			igt_assert(false);
> > > > +		}
> > > > +		break;
> > > 
> > > The above look wrong to me, tiles are always 4kB. So the GEN12 y-
> > > tiled tile width, height (CCS or not) are the same as on other
> > > platforms.
>
> > > OTOH, we should align both the main surface and AUX surface width
> > > and height for CCS. Those are setup in
> > > igt_init_fb()->fb_plane_height() and ->fb_plane_width(). The main
> > > surface (plane 0) should be aligned to 4x4 tiles (128x128 pixels).
> > 
> > and 128x128 is the case for 32bpp. For all bpps:
> > 
> > bpp	width	height
> > 8	512	128
> > 16	256	128
> > 32	128	128
> > 64	64	128
> > 128	32	128
>
> Ok, the numbers that I wrote originally above was found from BSpec.
> Since the tiles are always 4kB, I could update the patch with the
> numbers you provided.

The BSpec list is correct, but it's about the plane size alignment not
about tile sizes and it specifies width in pixels not in bytes as
igt_get_fb_tile_size(). I think we should keep the tile size what it
actually is (so 4kB or 128 bytes x 32 rows) and enforce the plane size
alignment in calc_plane_stride() and calc_plane_size().

> > > The AUX surface (plane 1) width/height should match this, so for
> > > that
> > > in fb_plane_width():
> > > 
> > > 	return DIV_ROUND_UP(fb->width, 128) * 64;
> > 
> > and here the divisor is based on the bpp as above.
> > 
> > > 
> > > and in fb_plane_height():
> > > 
> > > 	return DIV_ROUND_UP(fb->height, 128) * 4;
> > > 
> > > 
> > > >  	case LOCAL_I915_FORMAT_MOD_Yf_TILED:
> > > >  	case LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS:
> > > >  		igt_require_intel(fd);
> > > > @@ -467,8 +494,10 @@ void igt_get_fb_tile_size(int fd, uint64_t
> > > > modifier, int fb_bpp,
> > > >  
> > > >  static bool is_ccs_modifier(uint64_t modifier)
> > > >  {
> > > > -	return modifier == LOCAL_I915_FORMAT_MOD_Y_TILED_CCS ||
> > > > -		modifier == LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS;
> > > > +
> > > > +	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> > > > +		modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > > > +		modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > > >  }
> > > >  
> > > >  static unsigned fb_plane_width(const struct igt_fb *fb, int
> > > > plane)
> > > > @@ -687,6 +716,7 @@ uint64_t igt_fb_mod_to_tiling(uint64_t
> > > > modifier)
> > > >  		return I915_TILING_X;
> > > >  	case LOCAL_I915_FORMAT_MOD_Y_TILED:
> > > >  	case LOCAL_I915_FORMAT_MOD_Y_TILED_CCS:
> > > > +	case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > > >  		return I915_TILING_Y;
> > > >  	case LOCAL_I915_FORMAT_MOD_Yf_TILED:
> > > >  	case LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS:
> > > > -- 
> > > > 2.17.1
> > > > 
> > > 
> > > _______________________________________________
> > > igt-dev mailing list
> > > igt-dev@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/igt-dev
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[igt-dev] [PATCH i-g-t v4 0/3] GEN12 render decompression

[Mika Kahola]

Gen-12 render decompression is supported with Y-tiled main surface.
The patch series introduces CCS support for IGT tests.

This patch series requires Imre's series

https://patchwork.freedesktop.org/series/68890/

v2: Added new subtests for each format modifier.
v3: Add IGT description for each subtest (GitLab)
v4: Fix kms_ccs errornouse subtest execution and listing

Mika Kahola (3):
  Format modifier for Intel Gen-12 render compression
  lib/igt_fb.c: Update tile sizes for GEN12 CCS
  tests/kms_ccs: Add GEN12 CCS render compression format modifiers

 include/drm-uapi/drm_fourcc.h |   1 +
 lib/igt_fb.c                  |  34 ++++++++++-
 lib/ioctl_wrappers.h          |   1 +
 tests/kms_ccs.c               | 107 ++++++++++++++++++++--------------
 4 files changed, 97 insertions(+), 46 deletions(-)

-- 
2.17.1

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