[PATCH 0/2] ARM: dts: ls1021a: define and use external interrupt lines

[PATCH 0/2] ARM: dts: ls1021a: define and use external interrupt lines

[Rasmus Villemoes]

A device tree binding documentation as well as a driver implementing
support for the external interrupt lines on the ls1021a has been
merged into irqchip-next, so will very likely appear in v5.5. See

87cd38dfd9e6 dt/bindings: Add bindings for Layerscape external irqs
0dcd9f872769 irqchip: Add support for Layerscape external interrupt lines

present in next-20191112.

These patches simply add the extirq node to the ls1021a.dtsi and make
use of it on the LS1021A-TSN board. I hope these can be picked up so
they also land in v5.5, so we don't have to wait a full extra release
cycle.

Rasmus Villemoes (1):
  ARM: dts: ls1021a: add node describing external interrupt lines

Vladimir Oltean (1):
  ARM: dts: ls1021a-tsn: Use interrupts for the SGMII PHYs

 arch/arm/boot/dts/ls1021a-tsn.dts |  4 ++++
 arch/arm/boot/dts/ls1021a.dtsi    | 19 +++++++++++++++++++
 2 files changed, 23 insertions(+)

-- 
2.23.0

[PATCH 0/2] ARM: dts: ls1021a: define and use external interrupt lines

[Rasmus Villemoes]

A device tree binding documentation as well as a driver implementing
support for the external interrupt lines on the ls1021a has been
merged into irqchip-next, so will very likely appear in v5.5. See

87cd38dfd9e6 dt/bindings: Add bindings for Layerscape external irqs
0dcd9f872769 irqchip: Add support for Layerscape external interrupt lines

present in next-20191112.

These patches simply add the extirq node to the ls1021a.dtsi and make
use of it on the LS1021A-TSN board. I hope these can be picked up so
they also land in v5.5, so we don't have to wait a full extra release
cycle.

Rasmus Villemoes (1):
  ARM: dts: ls1021a: add node describing external interrupt lines

Vladimir Oltean (1):
  ARM: dts: ls1021a-tsn: Use interrupts for the SGMII PHYs

 arch/arm/boot/dts/ls1021a-tsn.dts |  4 ++++
 arch/arm/boot/dts/ls1021a.dtsi    | 19 +++++++++++++++++++
 2 files changed, 23 insertions(+)

-- 
2.23.0


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[PATCH 1/2] ARM: dts: ls1021a: add node describing external interrupt lines

[Rasmus Villemoes]

This adds a node describing the six external interrupt lines IRQ0-IRQ5
with configurable polarity.

Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
 arch/arm/boot/dts/ls1021a.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 2f6977ada447..0855b1fe98e0 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -216,6 +216,25 @@
 			compatible = "fsl,ls1021a-scfg", "syscon";
 			reg = <0x0 0x1570000 0x0 0x10000>;
 			big-endian;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x0 0x1570000 0x10000>;
+
+			extirq: interrupt-controller@1ac {
+				compatible = "fsl,ls1021a-extirq";
+				#interrupt-cells = <2>;
+				#address-cells = <0>;
+				interrupt-controller;
+				reg = <0x1ac 4>;
+				interrupt-map =
+					<0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+					<1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+					<2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+					<3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+					<4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+					<5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-map-mask = <0xffffffff 0x0>;
+			};
 		};
 
 		crypto: crypto@1700000 {
-- 
2.23.0

[PATCH 1/2] ARM: dts: ls1021a: add node describing external interrupt lines

[Rasmus Villemoes]

This adds a node describing the six external interrupt lines IRQ0-IRQ5
with configurable polarity.

Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
 arch/arm/boot/dts/ls1021a.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 2f6977ada447..0855b1fe98e0 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -216,6 +216,25 @@
 			compatible = "fsl,ls1021a-scfg", "syscon";
 			reg = <0x0 0x1570000 0x0 0x10000>;
 			big-endian;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x0 0x1570000 0x10000>;
+
+			extirq: interrupt-controller@1ac {
+				compatible = "fsl,ls1021a-extirq";
+				#interrupt-cells = <2>;
+				#address-cells = <0>;
+				interrupt-controller;
+				reg = <0x1ac 4>;
+				interrupt-map =
+					<0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+					<1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+					<2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+					<3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+					<4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+					<5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-map-mask = <0xffffffff 0x0>;
+			};
 		};
 
 		crypto: crypto@1700000 {
-- 
2.23.0


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[PATCH 2/2] ARM: dts: ls1021a-tsn: Use interrupts for the SGMII PHYs

[Rasmus Villemoes]

From: Vladimir Oltean <olteanv@gmail.com>

On the LS1021A-TSN board, the 2 Atheros AR8031 PHYs for eth0 and eth1
have interrupt lines connected to the shared IRQ2_B LS1021A pin.

Switching to interrupts offloads the PHY library from the task of
polling the MDIO status and AN registers (1, 4, 5) every second.

Unfortunately, the BCM5464R quad PHY connected to the switch does not
appear to have an interrupt line routed to the SoC.

Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
 arch/arm/boot/dts/ls1021a-tsn.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/ls1021a-tsn.dts b/arch/arm/boot/dts/ls1021a-tsn.dts
index 5b7689094b70..135d36461af4 100644
--- a/arch/arm/boot/dts/ls1021a-tsn.dts
+++ b/arch/arm/boot/dts/ls1021a-tsn.dts
@@ -203,11 +203,15 @@
 	/* AR8031 */
 	sgmii_phy1: ethernet-phy@1 {
 		reg = <0x1>;
+		/* SGMII1_PHY_INT_B: connected to IRQ2, active low */
+		interrupts-extended = <&extirq 2 IRQ_TYPE_EDGE_FALLING>;
 	};
 
 	/* AR8031 */
 	sgmii_phy2: ethernet-phy@2 {
 		reg = <0x2>;
+		/* SGMII2_PHY_INT_B: connected to IRQ2, active low */
+		interrupts-extended = <&extirq 2 IRQ_TYPE_EDGE_FALLING>;
 	};
 
 	/* BCM5464 quad PHY */
-- 
2.23.0

[PATCH 2/2] ARM: dts: ls1021a-tsn: Use interrupts for the SGMII PHYs

[Rasmus Villemoes]

From: Vladimir Oltean <olteanv@gmail.com>

On the LS1021A-TSN board, the 2 Atheros AR8031 PHYs for eth0 and eth1
have interrupt lines connected to the shared IRQ2_B LS1021A pin.

Switching to interrupts offloads the PHY library from the task of
polling the MDIO status and AN registers (1, 4, 5) every second.

Unfortunately, the BCM5464R quad PHY connected to the switch does not
appear to have an interrupt line routed to the SoC.

Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
 arch/arm/boot/dts/ls1021a-tsn.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/ls1021a-tsn.dts b/arch/arm/boot/dts/ls1021a-tsn.dts
index 5b7689094b70..135d36461af4 100644
--- a/arch/arm/boot/dts/ls1021a-tsn.dts
+++ b/arch/arm/boot/dts/ls1021a-tsn.dts
@@ -203,11 +203,15 @@
 	/* AR8031 */
 	sgmii_phy1: ethernet-phy@1 {
 		reg = <0x1>;
+		/* SGMII1_PHY_INT_B: connected to IRQ2, active low */
+		interrupts-extended = <&extirq 2 IRQ_TYPE_EDGE_FALLING>;
 	};
 
 	/* AR8031 */
 	sgmii_phy2: ethernet-phy@2 {
 		reg = <0x2>;
+		/* SGMII2_PHY_INT_B: connected to IRQ2, active low */
+		interrupts-extended = <&extirq 2 IRQ_TYPE_EDGE_FALLING>;
 	};
 
 	/* BCM5464 quad PHY */
-- 
2.23.0


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Re: [PATCH 2/2] ARM: dts: ls1021a-tsn: Use interrupts for the SGMII PHYs

[Vladimir Oltean]

On Tue, 12 Nov 2019 at 15:20, Rasmus Villemoes <linux@rasmusvillemoes.dk> wrote:
>
> From: Vladimir Oltean <olteanv@gmail.com>
>
> On the LS1021A-TSN board, the 2 Atheros AR8031 PHYs for eth0 and eth1
> have interrupt lines connected to the shared IRQ2_B LS1021A pin.
>
> Switching to interrupts offloads the PHY library from the task of
> polling the MDIO status and AN registers (1, 4, 5) every second.
>
> Unfortunately, the BCM5464R quad PHY connected to the switch does not
> appear to have an interrupt line routed to the SoC.
>
> Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
> Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
> ---
>  arch/arm/boot/dts/ls1021a-tsn.dts | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/boot/dts/ls1021a-tsn.dts b/arch/arm/boot/dts/ls1021a-tsn.dts
> index 5b7689094b70..135d36461af4 100644
> --- a/arch/arm/boot/dts/ls1021a-tsn.dts
> +++ b/arch/arm/boot/dts/ls1021a-tsn.dts
> @@ -203,11 +203,15 @@
>         /* AR8031 */
>         sgmii_phy1: ethernet-phy@1 {
>                 reg = <0x1>;
> +               /* SGMII1_PHY_INT_B: connected to IRQ2, active low */
> +               interrupts-extended = <&extirq 2 IRQ_TYPE_EDGE_FALLING>;
>         };
>
>         /* AR8031 */
>         sgmii_phy2: ethernet-phy@2 {
>                 reg = <0x2>;
> +               /* SGMII2_PHY_INT_B: connected to IRQ2, active low */
> +               interrupts-extended = <&extirq 2 IRQ_TYPE_EDGE_FALLING>;
>         };
>
>         /* BCM5464 quad PHY */
> --
> 2.23.0
>

+netdev and Andrew for this patch, since the interrupt polarity caught
his attention in v1.

Re: [PATCH 2/2] ARM: dts: ls1021a-tsn: Use interrupts for the SGMII PHYs

[Vladimir Oltean]

On Tue, 12 Nov 2019 at 15:20, Rasmus Villemoes <linux@rasmusvillemoes.dk> wrote:
>
> From: Vladimir Oltean <olteanv@gmail.com>
>
> On the LS1021A-TSN board, the 2 Atheros AR8031 PHYs for eth0 and eth1
> have interrupt lines connected to the shared IRQ2_B LS1021A pin.
>
> Switching to interrupts offloads the PHY library from the task of
> polling the MDIO status and AN registers (1, 4, 5) every second.
>
> Unfortunately, the BCM5464R quad PHY connected to the switch does not
> appear to have an interrupt line routed to the SoC.
>
> Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
> Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
> ---
>  arch/arm/boot/dts/ls1021a-tsn.dts | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/boot/dts/ls1021a-tsn.dts b/arch/arm/boot/dts/ls1021a-tsn.dts
> index 5b7689094b70..135d36461af4 100644
> --- a/arch/arm/boot/dts/ls1021a-tsn.dts
> +++ b/arch/arm/boot/dts/ls1021a-tsn.dts
> @@ -203,11 +203,15 @@
>         /* AR8031 */
>         sgmii_phy1: ethernet-phy@1 {
>                 reg = <0x1>;
> +               /* SGMII1_PHY_INT_B: connected to IRQ2, active low */
> +               interrupts-extended = <&extirq 2 IRQ_TYPE_EDGE_FALLING>;
>         };
>
>         /* AR8031 */
>         sgmii_phy2: ethernet-phy@2 {
>                 reg = <0x2>;
> +               /* SGMII2_PHY_INT_B: connected to IRQ2, active low */
> +               interrupts-extended = <&extirq 2 IRQ_TYPE_EDGE_FALLING>;
>         };
>
>         /* BCM5464 quad PHY */
> --
> 2.23.0
>

+netdev and Andrew for this patch, since the interrupt polarity caught
his attention in v1.

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Re: [PATCH 2/2] ARM: dts: ls1021a-tsn: Use interrupts for the SGMII PHYs

[Marc Zyngier]

On 2019-11-12 14:53, Vladimir Oltean wrote:
> On Tue, 12 Nov 2019 at 15:20, Rasmus Villemoes
> <linux@rasmusvillemoes.dk> wrote:
>>
>> From: Vladimir Oltean <olteanv@gmail.com>
>>
>> On the LS1021A-TSN board, the 2 Atheros AR8031 PHYs for eth0 and 
>> eth1
>> have interrupt lines connected to the shared IRQ2_B LS1021A pin.
>>
>> Switching to interrupts offloads the PHY library from the task of
>> polling the MDIO status and AN registers (1, 4, 5) every second.
>>
>> Unfortunately, the BCM5464R quad PHY connected to the switch does 
>> not
>> appear to have an interrupt line routed to the SoC.
>>
>> Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
>> Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
>> ---
>>  arch/arm/boot/dts/ls1021a-tsn.dts | 4 ++++
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/ls1021a-tsn.dts 
>> b/arch/arm/boot/dts/ls1021a-tsn.dts
>> index 5b7689094b70..135d36461af4 100644
>> --- a/arch/arm/boot/dts/ls1021a-tsn.dts
>> +++ b/arch/arm/boot/dts/ls1021a-tsn.dts
>> @@ -203,11 +203,15 @@
>>         /* AR8031 */
>>         sgmii_phy1: ethernet-phy@1 {
>>                 reg = <0x1>;
>> +               /* SGMII1_PHY_INT_B: connected to IRQ2, active low 
>> */
>> +               interrupts-extended = <&extirq 2 
>> IRQ_TYPE_EDGE_FALLING>;
>>         };
>>
>>         /* AR8031 */
>>         sgmii_phy2: ethernet-phy@2 {
>>                 reg = <0x2>;
>> +               /* SGMII2_PHY_INT_B: connected to IRQ2, active low 
>> */
>> +               interrupts-extended = <&extirq 2 
>> IRQ_TYPE_EDGE_FALLING>;
>>         };
>>
>>         /* BCM5464 quad PHY */
>> --
>> 2.23.0
>>
>
> +netdev and Andrew for this patch, since the interrupt polarity 
> caught
> his attention in v1.

Certainly, the comments and the interrupt specifier do not match.
Which one is true?

         M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH 2/2] ARM: dts: ls1021a-tsn: Use interrupts for the SGMII PHYs

[Marc Zyngier]

On 2019-11-12 14:53, Vladimir Oltean wrote:
> On Tue, 12 Nov 2019 at 15:20, Rasmus Villemoes
> <linux@rasmusvillemoes.dk> wrote:
>>
>> From: Vladimir Oltean <olteanv@gmail.com>
>>
>> On the LS1021A-TSN board, the 2 Atheros AR8031 PHYs for eth0 and 
>> eth1
>> have interrupt lines connected to the shared IRQ2_B LS1021A pin.
>>
>> Switching to interrupts offloads the PHY library from the task of
>> polling the MDIO status and AN registers (1, 4, 5) every second.
>>
>> Unfortunately, the BCM5464R quad PHY connected to the switch does 
>> not
>> appear to have an interrupt line routed to the SoC.
>>
>> Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
>> Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
>> ---
>>  arch/arm/boot/dts/ls1021a-tsn.dts | 4 ++++
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/ls1021a-tsn.dts 
>> b/arch/arm/boot/dts/ls1021a-tsn.dts
>> index 5b7689094b70..135d36461af4 100644
>> --- a/arch/arm/boot/dts/ls1021a-tsn.dts
>> +++ b/arch/arm/boot/dts/ls1021a-tsn.dts
>> @@ -203,11 +203,15 @@
>>         /* AR8031 */
>>         sgmii_phy1: ethernet-phy@1 {
>>                 reg = <0x1>;
>> +               /* SGMII1_PHY_INT_B: connected to IRQ2, active low 
>> */
>> +               interrupts-extended = <&extirq 2 
>> IRQ_TYPE_EDGE_FALLING>;
>>         };
>>
>>         /* AR8031 */
>>         sgmii_phy2: ethernet-phy@2 {
>>                 reg = <0x2>;
>> +               /* SGMII2_PHY_INT_B: connected to IRQ2, active low 
>> */
>> +               interrupts-extended = <&extirq 2 
>> IRQ_TYPE_EDGE_FALLING>;
>>         };
>>
>>         /* BCM5464 quad PHY */
>> --
>> 2.23.0
>>
>
> +netdev and Andrew for this patch, since the interrupt polarity 
> caught
> his attention in v1.

Certainly, the comments and the interrupt specifier do not match.
Which one is true?

         M.
-- 
Jazz is not dead. It just smells funny...

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Re: [PATCH 2/2] ARM: dts: ls1021a-tsn: Use interrupts for the SGMII PHYs

[Vladimir Oltean]

On Tue, 12 Nov 2019 at 15:49, Marc Zyngier <maz@kernel.org> wrote:
>
> On 2019-11-12 14:53, Vladimir Oltean wrote:
> > On Tue, 12 Nov 2019 at 15:20, Rasmus Villemoes
> > <linux@rasmusvillemoes.dk> wrote:
> >>
> >> From: Vladimir Oltean <olteanv@gmail.com>
> >>
> >> On the LS1021A-TSN board, the 2 Atheros AR8031 PHYs for eth0 and
> >> eth1
> >> have interrupt lines connected to the shared IRQ2_B LS1021A pin.
> >>
> >> Switching to interrupts offloads the PHY library from the task of
> >> polling the MDIO status and AN registers (1, 4, 5) every second.
> >>
> >> Unfortunately, the BCM5464R quad PHY connected to the switch does
> >> not
> >> appear to have an interrupt line routed to the SoC.
> >>
> >> Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
> >> Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
> >> ---
> >>  arch/arm/boot/dts/ls1021a-tsn.dts | 4 ++++
> >>  1 file changed, 4 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/ls1021a-tsn.dts
> >> b/arch/arm/boot/dts/ls1021a-tsn.dts
> >> index 5b7689094b70..135d36461af4 100644
> >> --- a/arch/arm/boot/dts/ls1021a-tsn.dts
> >> +++ b/arch/arm/boot/dts/ls1021a-tsn.dts
> >> @@ -203,11 +203,15 @@
> >>         /* AR8031 */
> >>         sgmii_phy1: ethernet-phy@1 {
> >>                 reg = <0x1>;
> >> +               /* SGMII1_PHY_INT_B: connected to IRQ2, active low
> >> */
> >> +               interrupts-extended = <&extirq 2
> >> IRQ_TYPE_EDGE_FALLING>;
> >>         };
> >>
> >>         /* AR8031 */
> >>         sgmii_phy2: ethernet-phy@2 {
> >>                 reg = <0x2>;
> >> +               /* SGMII2_PHY_INT_B: connected to IRQ2, active low
> >> */
> >> +               interrupts-extended = <&extirq 2
> >> IRQ_TYPE_EDGE_FALLING>;
> >>         };
> >>
> >>         /* BCM5464 quad PHY */
> >> --
> >> 2.23.0
> >>
> >
> > +netdev and Andrew for this patch, since the interrupt polarity
> > caught
> > his attention in v1.
>
> Certainly, the comments and the interrupt specifier do not match.
> Which one is true?
>
>          M.
> --
> Jazz is not dead. It just smells funny...

The interrupt specifier certainly works. So that points to an issue
with the description. What do you mean, exactly? Does "active low"
mean "level-triggered"? How would you have described this?

Re: [PATCH 2/2] ARM: dts: ls1021a-tsn: Use interrupts for the SGMII PHYs

[Vladimir Oltean]

On Tue, 12 Nov 2019 at 15:49, Marc Zyngier <maz@kernel.org> wrote:
>
> On 2019-11-12 14:53, Vladimir Oltean wrote:
> > On Tue, 12 Nov 2019 at 15:20, Rasmus Villemoes
> > <linux@rasmusvillemoes.dk> wrote:
> >>
> >> From: Vladimir Oltean <olteanv@gmail.com>
> >>
> >> On the LS1021A-TSN board, the 2 Atheros AR8031 PHYs for eth0 and
> >> eth1
> >> have interrupt lines connected to the shared IRQ2_B LS1021A pin.
> >>
> >> Switching to interrupts offloads the PHY library from the task of
> >> polling the MDIO status and AN registers (1, 4, 5) every second.
> >>
> >> Unfortunately, the BCM5464R quad PHY connected to the switch does
> >> not
> >> appear to have an interrupt line routed to the SoC.
> >>
> >> Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
> >> Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
> >> ---
> >>  arch/arm/boot/dts/ls1021a-tsn.dts | 4 ++++
> >>  1 file changed, 4 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/ls1021a-tsn.dts
> >> b/arch/arm/boot/dts/ls1021a-tsn.dts
> >> index 5b7689094b70..135d36461af4 100644
> >> --- a/arch/arm/boot/dts/ls1021a-tsn.dts
> >> +++ b/arch/arm/boot/dts/ls1021a-tsn.dts
> >> @@ -203,11 +203,15 @@
> >>         /* AR8031 */
> >>         sgmii_phy1: ethernet-phy@1 {
> >>                 reg = <0x1>;
> >> +               /* SGMII1_PHY_INT_B: connected to IRQ2, active low
> >> */
> >> +               interrupts-extended = <&extirq 2
> >> IRQ_TYPE_EDGE_FALLING>;
> >>         };
> >>
> >>         /* AR8031 */
> >>         sgmii_phy2: ethernet-phy@2 {
> >>                 reg = <0x2>;
> >> +               /* SGMII2_PHY_INT_B: connected to IRQ2, active low
> >> */
> >> +               interrupts-extended = <&extirq 2
> >> IRQ_TYPE_EDGE_FALLING>;
> >>         };
> >>
> >>         /* BCM5464 quad PHY */
> >> --
> >> 2.23.0
> >>
> >
> > +netdev and Andrew for this patch, since the interrupt polarity
> > caught
> > his attention in v1.
>
> Certainly, the comments and the interrupt specifier do not match.
> Which one is true?
>
>          M.
> --
> Jazz is not dead. It just smells funny...

The interrupt specifier certainly works. So that points to an issue
with the description. What do you mean, exactly? Does "active low"
mean "level-triggered"? How would you have described this?

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Re: [PATCH 2/2] ARM: dts: ls1021a-tsn: Use interrupts for the SGMII PHYs

[Andrew Lunn]

> > >> +               /* SGMII2_PHY_INT_B: connected to IRQ2, active low
> > >> */
> > >> +               interrupts-extended = <&extirq 2
> > >> IRQ_TYPE_EDGE_FALLING>;

> The interrupt specifier certainly works. So that points to an issue
> with the description. What do you mean, exactly? Does "active low"
> mean "level-triggered"? How would you have described this?

I would expect IRQ_TYPE_ACTIVE_LOW, or whatever it is called. Since
this is a shared interrupt, going on the edge i think opens up a race
condition and interrupts can be missed.

	  Andrew

Re: [PATCH 2/2] ARM: dts: ls1021a-tsn: Use interrupts for the SGMII PHYs

[Andrew Lunn]

> > >> +               /* SGMII2_PHY_INT_B: connected to IRQ2, active low
> > >> */
> > >> +               interrupts-extended = <&extirq 2
> > >> IRQ_TYPE_EDGE_FALLING>;

> The interrupt specifier certainly works. So that points to an issue
> with the description. What do you mean, exactly? Does "active low"
> mean "level-triggered"? How would you have described this?

I would expect IRQ_TYPE_ACTIVE_LOW, or whatever it is called. Since
this is a shared interrupt, going on the edge i think opens up a race
condition and interrupts can be missed.

	  Andrew

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Re: [PATCH 2/2] ARM: dts: ls1021a-tsn: Use interrupts for the SGMII PHYs

[Marc Zyngier]

On 2019-11-12 15:03, Vladimir Oltean wrote:
> On Tue, 12 Nov 2019 at 15:49, Marc Zyngier <maz@kernel.org> wrote:
>>
>> On 2019-11-12 14:53, Vladimir Oltean wrote:
>> > On Tue, 12 Nov 2019 at 15:20, Rasmus Villemoes
>> > <linux@rasmusvillemoes.dk> wrote:
>> >>
>> >> From: Vladimir Oltean <olteanv@gmail.com>
>> >>
>> >> On the LS1021A-TSN board, the 2 Atheros AR8031 PHYs for eth0 and
>> >> eth1
>> >> have interrupt lines connected to the shared IRQ2_B LS1021A pin.
>> >>
>> >> Switching to interrupts offloads the PHY library from the task of
>> >> polling the MDIO status and AN registers (1, 4, 5) every second.
>> >>
>> >> Unfortunately, the BCM5464R quad PHY connected to the switch does
>> >> not
>> >> appear to have an interrupt line routed to the SoC.
>> >>
>> >> Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
>> >> Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
>> >> ---
>> >>  arch/arm/boot/dts/ls1021a-tsn.dts | 4 ++++
>> >>  1 file changed, 4 insertions(+)
>> >>
>> >> diff --git a/arch/arm/boot/dts/ls1021a-tsn.dts
>> >> b/arch/arm/boot/dts/ls1021a-tsn.dts
>> >> index 5b7689094b70..135d36461af4 100644
>> >> --- a/arch/arm/boot/dts/ls1021a-tsn.dts
>> >> +++ b/arch/arm/boot/dts/ls1021a-tsn.dts
>> >> @@ -203,11 +203,15 @@
>> >>         /* AR8031 */
>> >>         sgmii_phy1: ethernet-phy@1 {
>> >>                 reg = <0x1>;
>> >> +               /* SGMII1_PHY_INT_B: connected to IRQ2, active 
>> low
>> >> */
>> >> +               interrupts-extended = <&extirq 2
>> >> IRQ_TYPE_EDGE_FALLING>;
>> >>         };
>> >>
>> >>         /* AR8031 */
>> >>         sgmii_phy2: ethernet-phy@2 {
>> >>                 reg = <0x2>;
>> >> +               /* SGMII2_PHY_INT_B: connected to IRQ2, active 
>> low
>> >> */
>> >> +               interrupts-extended = <&extirq 2
>> >> IRQ_TYPE_EDGE_FALLING>;
>> >>         };
>> >>
>> >>         /* BCM5464 quad PHY */
>> >> --
>> >> 2.23.0
>> >>
>> >
>> > +netdev and Andrew for this patch, since the interrupt polarity
>> > caught
>> > his attention in v1.
>>
>> Certainly, the comments and the interrupt specifier do not match.
>> Which one is true?
>>
>>          M.
>> --
>> Jazz is not dead. It just smells funny...
>
> The interrupt specifier certainly works. So that points to an issue
> with the description. What do you mean, exactly? Does "active low"
> mean "level-triggered"? How would you have described this?

Active Low definitely implies level triggered. And if that's how it
is described in the TRM, than the interrupt specifier is wrong, and
just *seem to work* because the level goes back to high between two
interrupts.

Also, shared *edge* interrupts do not work, full stop. So I'm pretty
convinced that what you have here is just wrong.

         M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH 2/2] ARM: dts: ls1021a-tsn: Use interrupts for the SGMII PHYs

[Marc Zyngier]

On 2019-11-12 15:03, Vladimir Oltean wrote:
> On Tue, 12 Nov 2019 at 15:49, Marc Zyngier <maz@kernel.org> wrote:
>>
>> On 2019-11-12 14:53, Vladimir Oltean wrote:
>> > On Tue, 12 Nov 2019 at 15:20, Rasmus Villemoes
>> > <linux@rasmusvillemoes.dk> wrote:
>> >>
>> >> From: Vladimir Oltean <olteanv@gmail.com>
>> >>
>> >> On the LS1021A-TSN board, the 2 Atheros AR8031 PHYs for eth0 and
>> >> eth1
>> >> have interrupt lines connected to the shared IRQ2_B LS1021A pin.
>> >>
>> >> Switching to interrupts offloads the PHY library from the task of
>> >> polling the MDIO status and AN registers (1, 4, 5) every second.
>> >>
>> >> Unfortunately, the BCM5464R quad PHY connected to the switch does
>> >> not
>> >> appear to have an interrupt line routed to the SoC.
>> >>
>> >> Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
>> >> Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
>> >> ---
>> >>  arch/arm/boot/dts/ls1021a-tsn.dts | 4 ++++
>> >>  1 file changed, 4 insertions(+)
>> >>
>> >> diff --git a/arch/arm/boot/dts/ls1021a-tsn.dts
>> >> b/arch/arm/boot/dts/ls1021a-tsn.dts
>> >> index 5b7689094b70..135d36461af4 100644
>> >> --- a/arch/arm/boot/dts/ls1021a-tsn.dts
>> >> +++ b/arch/arm/boot/dts/ls1021a-tsn.dts
>> >> @@ -203,11 +203,15 @@
>> >>         /* AR8031 */
>> >>         sgmii_phy1: ethernet-phy@1 {
>> >>                 reg = <0x1>;
>> >> +               /* SGMII1_PHY_INT_B: connected to IRQ2, active 
>> low
>> >> */
>> >> +               interrupts-extended = <&extirq 2
>> >> IRQ_TYPE_EDGE_FALLING>;
>> >>         };
>> >>
>> >>         /* AR8031 */
>> >>         sgmii_phy2: ethernet-phy@2 {
>> >>                 reg = <0x2>;
>> >> +               /* SGMII2_PHY_INT_B: connected to IRQ2, active 
>> low
>> >> */
>> >> +               interrupts-extended = <&extirq 2
>> >> IRQ_TYPE_EDGE_FALLING>;
>> >>         };
>> >>
>> >>         /* BCM5464 quad PHY */
>> >> --
>> >> 2.23.0
>> >>
>> >
>> > +netdev and Andrew for this patch, since the interrupt polarity
>> > caught
>> > his attention in v1.
>>
>> Certainly, the comments and the interrupt specifier do not match.
>> Which one is true?
>>
>>          M.
>> --
>> Jazz is not dead. It just smells funny...
>
> The interrupt specifier certainly works. So that points to an issue
> with the description. What do you mean, exactly? Does "active low"
> mean "level-triggered"? How would you have described this?

Active Low definitely implies level triggered. And if that's how it
is described in the TRM, than the interrupt specifier is wrong, and
just *seem to work* because the level goes back to high between two
interrupts.

Also, shared *edge* interrupts do not work, full stop. So I'm pretty
convinced that what you have here is just wrong.

         M.
-- 
Jazz is not dead. It just smells funny...

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Re: [PATCH 2/2] ARM: dts: ls1021a-tsn: Use interrupts for the SGMII PHYs

[Vladimir Oltean]

On Tue, 12 Nov 2019 at 16:04, Marc Zyngier <maz@kernel.org> wrote:
>
> On 2019-11-12 15:03, Vladimir Oltean wrote:
> > On Tue, 12 Nov 2019 at 15:49, Marc Zyngier <maz@kernel.org> wrote:
> >>
> >> On 2019-11-12 14:53, Vladimir Oltean wrote:
> >> > On Tue, 12 Nov 2019 at 15:20, Rasmus Villemoes
> >> > <linux@rasmusvillemoes.dk> wrote:
> >> >>
> >> >> From: Vladimir Oltean <olteanv@gmail.com>
> >> >>
> >> >> On the LS1021A-TSN board, the 2 Atheros AR8031 PHYs for eth0 and
> >> >> eth1
> >> >> have interrupt lines connected to the shared IRQ2_B LS1021A pin.
> >> >>
> >> >> Switching to interrupts offloads the PHY library from the task of
> >> >> polling the MDIO status and AN registers (1, 4, 5) every second.
> >> >>
> >> >> Unfortunately, the BCM5464R quad PHY connected to the switch does
> >> >> not
> >> >> appear to have an interrupt line routed to the SoC.
> >> >>
> >> >> Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
> >> >> Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
> >> >> ---
> >> >>  arch/arm/boot/dts/ls1021a-tsn.dts | 4 ++++
> >> >>  1 file changed, 4 insertions(+)
> >> >>
> >> >> diff --git a/arch/arm/boot/dts/ls1021a-tsn.dts
> >> >> b/arch/arm/boot/dts/ls1021a-tsn.dts
> >> >> index 5b7689094b70..135d36461af4 100644
> >> >> --- a/arch/arm/boot/dts/ls1021a-tsn.dts
> >> >> +++ b/arch/arm/boot/dts/ls1021a-tsn.dts
> >> >> @@ -203,11 +203,15 @@
> >> >>         /* AR8031 */
> >> >>         sgmii_phy1: ethernet-phy@1 {
> >> >>                 reg = <0x1>;
> >> >> +               /* SGMII1_PHY_INT_B: connected to IRQ2, active
> >> low
> >> >> */
> >> >> +               interrupts-extended = <&extirq 2
> >> >> IRQ_TYPE_EDGE_FALLING>;
> >> >>         };
> >> >>
> >> >>         /* AR8031 */
> >> >>         sgmii_phy2: ethernet-phy@2 {
> >> >>                 reg = <0x2>;
> >> >> +               /* SGMII2_PHY_INT_B: connected to IRQ2, active
> >> low
> >> >> */
> >> >> +               interrupts-extended = <&extirq 2
> >> >> IRQ_TYPE_EDGE_FALLING>;
> >> >>         };
> >> >>
> >> >>         /* BCM5464 quad PHY */
> >> >> --
> >> >> 2.23.0
> >> >>
> >> >
> >> > +netdev and Andrew for this patch, since the interrupt polarity
> >> > caught
> >> > his attention in v1.
> >>
> >> Certainly, the comments and the interrupt specifier do not match.
> >> Which one is true?
> >>
> >>          M.
> >> --
> >> Jazz is not dead. It just smells funny...
> >
> > The interrupt specifier certainly works. So that points to an issue
> > with the description. What do you mean, exactly? Does "active low"
> > mean "level-triggered"? How would you have described this?
>
> Active Low definitely implies level triggered. And if that's how it
> is described in the TRM, than the interrupt specifier is wrong, and
> just *seem to work* because the level goes back to high between two
> interrupts.
>
> Also, shared *edge* interrupts do not work, full stop. So I'm pretty
> convinced that what you have here is just wrong.
>
>          M.
> --
> Jazz is not dead. It just smells funny...

Ok, I've tested both interrupts with IRQ_TYPE_LEVEL_LOW and they still
work. I'll let Rasmus re-send if there is no trouble with the dtsi
patch. Sorry for the trouble and thanks for teaching me something new.

Cheers,
-Vladimir

Re: [PATCH 2/2] ARM: dts: ls1021a-tsn: Use interrupts for the SGMII PHYs

[Vladimir Oltean]

On Tue, 12 Nov 2019 at 16:04, Marc Zyngier <maz@kernel.org> wrote:
>
> On 2019-11-12 15:03, Vladimir Oltean wrote:
> > On Tue, 12 Nov 2019 at 15:49, Marc Zyngier <maz@kernel.org> wrote:
> >>
> >> On 2019-11-12 14:53, Vladimir Oltean wrote:
> >> > On Tue, 12 Nov 2019 at 15:20, Rasmus Villemoes
> >> > <linux@rasmusvillemoes.dk> wrote:
> >> >>
> >> >> From: Vladimir Oltean <olteanv@gmail.com>
> >> >>
> >> >> On the LS1021A-TSN board, the 2 Atheros AR8031 PHYs for eth0 and
> >> >> eth1
> >> >> have interrupt lines connected to the shared IRQ2_B LS1021A pin.
> >> >>
> >> >> Switching to interrupts offloads the PHY library from the task of
> >> >> polling the MDIO status and AN registers (1, 4, 5) every second.
> >> >>
> >> >> Unfortunately, the BCM5464R quad PHY connected to the switch does
> >> >> not
> >> >> appear to have an interrupt line routed to the SoC.
> >> >>
> >> >> Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
> >> >> Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
> >> >> ---
> >> >>  arch/arm/boot/dts/ls1021a-tsn.dts | 4 ++++
> >> >>  1 file changed, 4 insertions(+)
> >> >>
> >> >> diff --git a/arch/arm/boot/dts/ls1021a-tsn.dts
> >> >> b/arch/arm/boot/dts/ls1021a-tsn.dts
> >> >> index 5b7689094b70..135d36461af4 100644
> >> >> --- a/arch/arm/boot/dts/ls1021a-tsn.dts
> >> >> +++ b/arch/arm/boot/dts/ls1021a-tsn.dts
> >> >> @@ -203,11 +203,15 @@
> >> >>         /* AR8031 */
> >> >>         sgmii_phy1: ethernet-phy@1 {
> >> >>                 reg = <0x1>;
> >> >> +               /* SGMII1_PHY_INT_B: connected to IRQ2, active
> >> low
> >> >> */
> >> >> +               interrupts-extended = <&extirq 2
> >> >> IRQ_TYPE_EDGE_FALLING>;
> >> >>         };
> >> >>
> >> >>         /* AR8031 */
> >> >>         sgmii_phy2: ethernet-phy@2 {
> >> >>                 reg = <0x2>;
> >> >> +               /* SGMII2_PHY_INT_B: connected to IRQ2, active
> >> low
> >> >> */
> >> >> +               interrupts-extended = <&extirq 2
> >> >> IRQ_TYPE_EDGE_FALLING>;
> >> >>         };
> >> >>
> >> >>         /* BCM5464 quad PHY */
> >> >> --
> >> >> 2.23.0
> >> >>
> >> >
> >> > +netdev and Andrew for this patch, since the interrupt polarity
> >> > caught
> >> > his attention in v1.
> >>
> >> Certainly, the comments and the interrupt specifier do not match.
> >> Which one is true?
> >>
> >>          M.
> >> --
> >> Jazz is not dead. It just smells funny...
> >
> > The interrupt specifier certainly works. So that points to an issue
> > with the description. What do you mean, exactly? Does "active low"
> > mean "level-triggered"? How would you have described this?
>
> Active Low definitely implies level triggered. And if that's how it
> is described in the TRM, than the interrupt specifier is wrong, and
> just *seem to work* because the level goes back to high between two
> interrupts.
>
> Also, shared *edge* interrupts do not work, full stop. So I'm pretty
> convinced that what you have here is just wrong.
>
>          M.
> --
> Jazz is not dead. It just smells funny...

Ok, I've tested both interrupts with IRQ_TYPE_LEVEL_LOW and they still
work. I'll let Rasmus re-send if there is no trouble with the dtsi
patch. Sorry for the trouble and thanks for teaching me something new.

Cheers,
-Vladimir

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