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From: Lucas De Marchi <lucas.demarchi@intel.com>
To: "José Roberto de Souza" <jose.souza@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/3] drm/i915/display/dsi: Add support to pipe D
Date: Wed, 13 Nov 2019 10:58:53 -0800	[thread overview]
Message-ID: <20191113185853.7ktkehtpim42xda5@ldmartin-desk1> (raw)
In-Reply-To: <20191107214559.77087-2-jose.souza@intel.com>

On Thu, Nov 07, 2019 at 01:45:58PM -0800, Jose Souza wrote:
>Adding pipe D support to DSI transcoder.
>Not adding it for EDP transcoder code paths as only TGL has 4 pipes
>and it do not have a EDP transcoder.
>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Signed-off-by: José Roberto de Souza <jose.souza@intel.com>

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>---
> drivers/gpu/drm/i915/display/icl_dsi.c | 6 ++++++
> drivers/gpu/drm/i915/i915_reg.h        | 1 +
> 2 files changed, 7 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
>index 8eb2d7f29c82..f688207932e0 100644
>--- a/drivers/gpu/drm/i915/display/icl_dsi.c
>+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>@@ -745,6 +745,9 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
> 		case PIPE_C:
> 			tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
> 			break;
>+		case PIPE_D:
>+			tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF;
>+			break;
> 		}
>
> 		/* enable DDI buffer */
>@@ -1325,6 +1328,9 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
> 		case TRANS_DDI_EDP_INPUT_C_ONOFF:
> 			*pipe = PIPE_C;
> 			break;
>+		case TRANS_DDI_EDP_INPUT_D_ONOFF:
>+			*pipe = PIPE_D;
>+			break;
> 		default:
> 			DRM_ERROR("Invalid PIPE input\n");
> 			goto out;
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 70459a3d93e3..88d1430a6800 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -9665,6 +9665,7 @@ enum skl_power_gate {
> #define  TRANS_DDI_EDP_INPUT_A_ONOFF	(4 << 12)
> #define  TRANS_DDI_EDP_INPUT_B_ONOFF	(5 << 12)
> #define  TRANS_DDI_EDP_INPUT_C_ONOFF	(6 << 12)
>+#define  TRANS_DDI_EDP_INPUT_D_ONOFF	(7 << 12)
> #define  TRANS_DDI_MST_TRANSPORT_SELECT_MASK	REG_GENMASK(11, 10)
> #define  TRANS_DDI_MST_TRANSPORT_SELECT(trans)	\
> 	REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
>-- 
>2.24.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: Lucas De Marchi <lucas.demarchi@intel.com>
To: "José Roberto de Souza" <jose.souza@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 2/3] drm/i915/display/dsi: Add support to pipe D
Date: Wed, 13 Nov 2019 10:58:53 -0800	[thread overview]
Message-ID: <20191113185853.7ktkehtpim42xda5@ldmartin-desk1> (raw)
Message-ID: <20191113185853.8NSgzImDErO9gXfyKrz8QJ8Iw6T4kQiEfWYqrho2Gak@z> (raw)
In-Reply-To: <20191107214559.77087-2-jose.souza@intel.com>

On Thu, Nov 07, 2019 at 01:45:58PM -0800, Jose Souza wrote:
>Adding pipe D support to DSI transcoder.
>Not adding it for EDP transcoder code paths as only TGL has 4 pipes
>and it do not have a EDP transcoder.
>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Signed-off-by: José Roberto de Souza <jose.souza@intel.com>

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>---
> drivers/gpu/drm/i915/display/icl_dsi.c | 6 ++++++
> drivers/gpu/drm/i915/i915_reg.h        | 1 +
> 2 files changed, 7 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
>index 8eb2d7f29c82..f688207932e0 100644
>--- a/drivers/gpu/drm/i915/display/icl_dsi.c
>+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>@@ -745,6 +745,9 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
> 		case PIPE_C:
> 			tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
> 			break;
>+		case PIPE_D:
>+			tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF;
>+			break;
> 		}
>
> 		/* enable DDI buffer */
>@@ -1325,6 +1328,9 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
> 		case TRANS_DDI_EDP_INPUT_C_ONOFF:
> 			*pipe = PIPE_C;
> 			break;
>+		case TRANS_DDI_EDP_INPUT_D_ONOFF:
>+			*pipe = PIPE_D;
>+			break;
> 		default:
> 			DRM_ERROR("Invalid PIPE input\n");
> 			goto out;
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 70459a3d93e3..88d1430a6800 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -9665,6 +9665,7 @@ enum skl_power_gate {
> #define  TRANS_DDI_EDP_INPUT_A_ONOFF	(4 << 12)
> #define  TRANS_DDI_EDP_INPUT_B_ONOFF	(5 << 12)
> #define  TRANS_DDI_EDP_INPUT_C_ONOFF	(6 << 12)
>+#define  TRANS_DDI_EDP_INPUT_D_ONOFF	(7 << 12)
> #define  TRANS_DDI_MST_TRANSPORT_SELECT_MASK	REG_GENMASK(11, 10)
> #define  TRANS_DDI_MST_TRANSPORT_SELECT(trans)	\
> 	REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
>-- 
>2.24.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2019-11-13 18:59 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-07 21:45 [PATCH 1/3] drm/i915/display: Fix TRANS_DDI_MST_TRANSPORT_SELECT definition José Roberto de Souza
2019-11-07 21:45 ` [Intel-gfx] " José Roberto de Souza
2019-11-07 21:45 ` [PATCH 2/3] drm/i915/display/dsi: Add support to pipe D José Roberto de Souza
2019-11-07 21:45   ` [Intel-gfx] " José Roberto de Souza
2019-11-13 18:58   ` Lucas De Marchi [this message]
2019-11-13 18:58     ` Lucas De Marchi
2019-11-07 21:45 ` [PATCH 3/3] drm/i915/display/mst: Enable virtual channel payload allocation earlier José Roberto de Souza
2019-11-07 21:45   ` [Intel-gfx] " José Roberto de Souza
2019-11-07 22:44   ` Lucas De Marchi
2019-11-07 22:44     ` [Intel-gfx] " Lucas De Marchi
2019-11-07 22:56     ` Souza, Jose
2019-11-07 22:56       ` [Intel-gfx] " Souza, Jose
2019-11-07 23:10       ` Lucas De Marchi
2019-11-07 23:10         ` [Intel-gfx] " Lucas De Marchi
2019-11-07 23:18         ` Souza, Jose
2019-11-07 23:18           ` [Intel-gfx] " Souza, Jose
2019-11-13 18:59           ` Lucas De Marchi
2019-11-13 18:59             ` [Intel-gfx] " Lucas De Marchi
2019-11-07 22:29 ` [PATCH 1/3] drm/i915/display: Fix TRANS_DDI_MST_TRANSPORT_SELECT definition Lucas De Marchi
2019-11-07 22:29   ` [Intel-gfx] " Lucas De Marchi
2019-11-08  1:14 ` ✓ Fi.CI.BAT: success for series starting with [1/3] " Patchwork
2019-11-08  1:14   ` [Intel-gfx] " Patchwork
2019-11-09 10:47 ` ✓ Fi.CI.IGT: " Patchwork
2019-11-09 10:47   ` [Intel-gfx] " Patchwork
2019-11-13 21:13   ` Souza, Jose
2019-11-13 21:13     ` [Intel-gfx] " Souza, Jose

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