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From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915/ehl: Update voltage level checks
Date: Mon, 18 Nov 2019 08:50:31 -0800	[thread overview]
Message-ID: <20191118165031.GF21445@mdroper-desk1.amr.corp.intel.com> (raw)
In-Reply-To: <20191118164412.26216-1-matthew.d.roper@intel.com>

On Mon, Nov 18, 2019 at 08:44:12AM -0800, Matt Roper wrote:
> The bspec was recently updated with new cdclk -> voltage level tables to
> accomodate the new 324/326.4 cdclk values.
> 
> Bspec: 21809
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Vivek Kasireddy <vivek.kasireddy@intel.com>
> Cc: Bob Paauwe <bob.j.paauwe@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

And

Fixes: 63c9dae71dc5 ("drm/i915/ehl: Add voltage level requirement table")

since using the old table could result in us requesting too low a
voltage level for the highest cdclk values.


Matt

> ---
> There are some platform tagging issues on this bspec page and multiple
> tables are actually tagged with the EHL label, but the bspec changelog
> makes it pretty clear which table we're supposed to be using (plus the
> other tables don't match the set of cdclks supported by the platform).
> 
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 8b702317557e..7d1ab1e5b7c3 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1273,7 +1273,9 @@ static u8 icl_calc_voltage_level(int cdclk)
>  
>  static u8 ehl_calc_voltage_level(int cdclk)
>  {
> -	if (cdclk > 312000)
> +	if (cdclk > 326400)
> +		return 3;
> +	else if (cdclk > 312000)
>  		return 2;
>  	else if (cdclk > 180000)
>  		return 1;
> -- 
> 2.21.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915/ehl: Update voltage level checks
Date: Mon, 18 Nov 2019 08:50:31 -0800	[thread overview]
Message-ID: <20191118165031.GF21445@mdroper-desk1.amr.corp.intel.com> (raw)
Message-ID: <20191118165031.SB9_eKdkRkz7o8paRZw4gdMADLnaIPvwWcn0mfnGYig@z> (raw)
In-Reply-To: <20191118164412.26216-1-matthew.d.roper@intel.com>

On Mon, Nov 18, 2019 at 08:44:12AM -0800, Matt Roper wrote:
> The bspec was recently updated with new cdclk -> voltage level tables to
> accomodate the new 324/326.4 cdclk values.
> 
> Bspec: 21809
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Vivek Kasireddy <vivek.kasireddy@intel.com>
> Cc: Bob Paauwe <bob.j.paauwe@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

And

Fixes: 63c9dae71dc5 ("drm/i915/ehl: Add voltage level requirement table")

since using the old table could result in us requesting too low a
voltage level for the highest cdclk values.


Matt

> ---
> There are some platform tagging issues on this bspec page and multiple
> tables are actually tagged with the EHL label, but the bspec changelog
> makes it pretty clear which table we're supposed to be using (plus the
> other tables don't match the set of cdclks supported by the platform).
> 
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 8b702317557e..7d1ab1e5b7c3 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1273,7 +1273,9 @@ static u8 icl_calc_voltage_level(int cdclk)
>  
>  static u8 ehl_calc_voltage_level(int cdclk)
>  {
> -	if (cdclk > 312000)
> +	if (cdclk > 326400)
> +		return 3;
> +	else if (cdclk > 312000)
>  		return 2;
>  	else if (cdclk > 180000)
>  		return 1;
> -- 
> 2.21.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2019-11-18 16:49 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-18 16:44 [PATCH] drm/i915/ehl: Update voltage level checks Matt Roper
2019-11-18 16:44 ` [Intel-gfx] " Matt Roper
2019-11-18 16:50 ` Matt Roper [this message]
2019-11-18 16:50   ` Matt Roper
2019-11-18 19:02   ` Souza, Jose
2019-11-18 19:02     ` [Intel-gfx] " Souza, Jose
2019-11-18 19:11 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2019-11-18 19:11   ` [Intel-gfx] " Patchwork
2019-11-18 19:33 ` ✓ Fi.CI.BAT: success " Patchwork
2019-11-18 19:33   ` [Intel-gfx] " Patchwork
2019-11-19  4:37 ` ✓ Fi.CI.IGT: " Patchwork
2019-11-19  4:37   ` [Intel-gfx] " Patchwork
2019-11-19  5:08   ` Matt Roper
2019-11-19  5:08     ` [Intel-gfx] " Matt Roper

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