[V3 0/8] Add support for mipi dsi cmd mode

[V3 0/8] Add support for mipi dsi cmd mode

[Vandita Kulkarni]

Addressed comments on RFC-v2 from Jani, thanks.

Vandita Kulkarni (8):
  drm/i915/dsi: Configure transcoder operation for command mode.
  drm/i915/dsi: Add vblank calculation for command mode
  drm/i915/dsi: Add cmd mode flags in display mode private flags
  drm/i915/dsi: Add check for periodic command mode
  drm/i915/dsi: Use private flags to indicate TE in cmd mode
  drm/i915/dsi: Configure TE interrupt for cmd mode
  drm/i915/dsi: Add TE handler for dsi cmd mode.
  drm/i915/dsi: Initiate fame request in cmd mode

 drivers/gpu/drm/i915/display/icl_dsi.c        | 150 ++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_display.c  |  10 ++
 .../drm/i915/display/intel_display_types.h    |  10 ++
 drivers/gpu/drm/i915/display/intel_dsi.h      |   3 +
 drivers/gpu/drm/i915/i915_irq.c               | 119 +++++++++++++-
 5 files changed, 277 insertions(+), 15 deletions(-)

-- 
2.21.0.5.gaeb582a

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[Intel-gfx] [V3 0/8] Add support for mipi dsi cmd mode

[Vandita Kulkarni]

Addressed comments on RFC-v2 from Jani, thanks.

Vandita Kulkarni (8):
  drm/i915/dsi: Configure transcoder operation for command mode.
  drm/i915/dsi: Add vblank calculation for command mode
  drm/i915/dsi: Add cmd mode flags in display mode private flags
  drm/i915/dsi: Add check for periodic command mode
  drm/i915/dsi: Use private flags to indicate TE in cmd mode
  drm/i915/dsi: Configure TE interrupt for cmd mode
  drm/i915/dsi: Add TE handler for dsi cmd mode.
  drm/i915/dsi: Initiate fame request in cmd mode

 drivers/gpu/drm/i915/display/icl_dsi.c        | 150 ++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_display.c  |  10 ++
 .../drm/i915/display/intel_display_types.h    |  10 ++
 drivers/gpu/drm/i915/display/intel_dsi.h      |   3 +
 drivers/gpu/drm/i915/i915_irq.c               | 119 +++++++++++++-
 5 files changed, 277 insertions(+), 15 deletions(-)

-- 
2.21.0.5.gaeb582a

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[V3 1/8] drm/i915/dsi: Configure transcoder operation for command mode.

[Vandita Kulkarni]

Configure the transcoder to operate in TE GATE command mode
and  take TE events from GPIO.
Also disable the periodic command mode, that GOP would have
programmed.

v2: Disable util pin (Jani)

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 52 ++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index f688207932e0..089c630526bc 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -704,6 +704,18 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 				tmp |= VIDEO_MODE_SYNC_PULSE;
 				break;
 			}
+		} else {
+			/*
+			 * FIXME: Retrieve this info from VBT.
+			 * As per the spec when dsi transcoder is operating
+			 * in TE GATE mode, TE comes from GPIO
+			 * which is UTIL PIN for DSI 0.
+			 * Also this GPIO would not be used for other
+			 * purposes is an assumption.
+			 */
+			tmp &= ~OP_MODE_MASK;
+			tmp |= CMD_MODE_TE_GATE;
+			tmp |= TE_SOURCE_GPIO;
 		}
 
 		I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
@@ -956,6 +968,32 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
 	}
 }
 
+static void gen11_dsi_config_util_pin(struct intel_encoder *encoder,
+				      bool enable)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	u32 tmp;
+
+	/*
+	 * used as TE i/p for DSI0,
+	 * for dual link/DSI1 TE is from slave DSI1
+	 * through GPIO.
+	 */
+	if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B)))
+		return;
+
+	tmp = I915_READ(UTIL_PIN_CTL);
+
+	if (enable) {
+		tmp |= UTIL_PIN_DIRECTION_INPUT;
+		tmp |= UTIL_PIN_ENABLE;
+	} else
+		tmp &= ~UTIL_PIN_ENABLE;
+
+	I915_WRITE(UTIL_PIN_CTL, tmp);
+}
+
 static void
 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *pipe_config)
@@ -977,6 +1015,9 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
 	/* setup D-PHY timings */
 	gen11_dsi_setup_dphy_timings(encoder);
 
+	/* Since transcoder is configured to take events from GPIO */
+	gen11_dsi_config_util_pin(encoder, true);
+
 	/* step 4h: setup DSI protocol timeouts */
 	gen11_dsi_setup_timeouts(encoder);
 
@@ -1107,6 +1148,15 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
 	enum transcoder dsi_trans;
 	u32 tmp;
 
+	/* disable periodic update mode */
+	if (is_cmd_mode(intel_dsi)) {
+		for_each_dsi_port(port, intel_dsi->ports) {
+			tmp = I915_READ(DSI_CMD_FRMCTL(port));
+			tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE;
+			I915_WRITE(DSI_CMD_FRMCTL(port), tmp);
+		}
+	}
+
 	/* put dsi link in ULPS */
 	for_each_dsi_port(port, intel_dsi->ports) {
 		dsi_trans = dsi_port_to_transcoder(port);
@@ -1210,6 +1260,8 @@ static void gen11_dsi_disable(struct intel_encoder *encoder,
 	/* step3: disable port */
 	gen11_dsi_disable_port(encoder);
 
+	gen11_dsi_config_util_pin(encoder, false);
+
 	/* step4: disable IO power */
 	gen11_dsi_disable_io_power(encoder);
 }
-- 
2.21.0.5.gaeb582a

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[Intel-gfx] [V3 1/8] drm/i915/dsi: Configure transcoder operation for command mode.

[Vandita Kulkarni]

Configure the transcoder to operate in TE GATE command mode
and  take TE events from GPIO.
Also disable the periodic command mode, that GOP would have
programmed.

v2: Disable util pin (Jani)

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 52 ++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index f688207932e0..089c630526bc 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -704,6 +704,18 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 				tmp |= VIDEO_MODE_SYNC_PULSE;
 				break;
 			}
+		} else {
+			/*
+			 * FIXME: Retrieve this info from VBT.
+			 * As per the spec when dsi transcoder is operating
+			 * in TE GATE mode, TE comes from GPIO
+			 * which is UTIL PIN for DSI 0.
+			 * Also this GPIO would not be used for other
+			 * purposes is an assumption.
+			 */
+			tmp &= ~OP_MODE_MASK;
+			tmp |= CMD_MODE_TE_GATE;
+			tmp |= TE_SOURCE_GPIO;
 		}
 
 		I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
@@ -956,6 +968,32 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
 	}
 }
 
+static void gen11_dsi_config_util_pin(struct intel_encoder *encoder,
+				      bool enable)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	u32 tmp;
+
+	/*
+	 * used as TE i/p for DSI0,
+	 * for dual link/DSI1 TE is from slave DSI1
+	 * through GPIO.
+	 */
+	if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B)))
+		return;
+
+	tmp = I915_READ(UTIL_PIN_CTL);
+
+	if (enable) {
+		tmp |= UTIL_PIN_DIRECTION_INPUT;
+		tmp |= UTIL_PIN_ENABLE;
+	} else
+		tmp &= ~UTIL_PIN_ENABLE;
+
+	I915_WRITE(UTIL_PIN_CTL, tmp);
+}
+
 static void
 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *pipe_config)
@@ -977,6 +1015,9 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
 	/* setup D-PHY timings */
 	gen11_dsi_setup_dphy_timings(encoder);
 
+	/* Since transcoder is configured to take events from GPIO */
+	gen11_dsi_config_util_pin(encoder, true);
+
 	/* step 4h: setup DSI protocol timeouts */
 	gen11_dsi_setup_timeouts(encoder);
 
@@ -1107,6 +1148,15 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
 	enum transcoder dsi_trans;
 	u32 tmp;
 
+	/* disable periodic update mode */
+	if (is_cmd_mode(intel_dsi)) {
+		for_each_dsi_port(port, intel_dsi->ports) {
+			tmp = I915_READ(DSI_CMD_FRMCTL(port));
+			tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE;
+			I915_WRITE(DSI_CMD_FRMCTL(port), tmp);
+		}
+	}
+
 	/* put dsi link in ULPS */
 	for_each_dsi_port(port, intel_dsi->ports) {
 		dsi_trans = dsi_port_to_transcoder(port);
@@ -1210,6 +1260,8 @@ static void gen11_dsi_disable(struct intel_encoder *encoder,
 	/* step3: disable port */
 	gen11_dsi_disable_port(encoder);
 
+	gen11_dsi_config_util_pin(encoder, false);
+
 	/* step4: disable IO power */
 	gen11_dsi_disable_io_power(encoder);
 }
-- 
2.21.0.5.gaeb582a

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[V3 2/8] drm/i915/dsi: Add vblank calculation for command mode

[Vandita Kulkarni]

Transcoder timing calculation differ for command mode.

v2: Use is_vid_mode, and use same I915_WRITE (Jani)

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 39 +++++++++++++++++---------
 1 file changed, 26 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 089c630526bc..96f912b153e9 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -791,6 +791,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 	u16 hback_porch;
 	/* vertical timings */
 	u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
+	int bpp, line_time_us, byte_clk_period_ns;
 
 	hactive = adjusted_mode->crtc_hdisplay;
 	htotal = adjusted_mode->crtc_htotal;
@@ -828,7 +829,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 	}
 
 	/* TRANS_HSYNC register to be programmed only for video mode */
-	if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
+	if (is_vid_mode(intel_dsi)) {
 		if (intel_dsi->video_mode_format ==
 		    VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) {
 			/* BSPEC: hsync size should be atleast 16 pixels */
@@ -852,12 +853,20 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 	}
 
 	/* program TRANS_VTOTAL register */
+	if (is_cmd_mode(intel_dsi)) {
+		bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
+		byte_clk_period_ns = 8 * 1000000 / intel_dsi->pclk;
+		htotal = hactive + 160;
+		line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count);
+		vtotal = vactive + DIV_ROUND_UP(460, line_time_us);
+	}
+
 	for_each_dsi_port(port, intel_dsi->ports) {
 		dsi_trans = dsi_port_to_transcoder(port);
 		/*
-		 * FIXME: Programing this by assuming progressive mode, since
-		 * non-interlaced info from VBT is not saved inside
-		 * struct drm_display_mode.
+		 * FIXME: Programing this by assuming progressive mode,
+		 * since non-interlaced info from VBT is not saved
+		 * inside struct drm_display_mode.
 		 * For interlace mode: program required pixel minus 2
 		 */
 		I915_WRITE(VTOTAL(dsi_trans),
@@ -870,22 +879,26 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 	if (vsync_start < vactive)
 		DRM_ERROR("vsync_start less than vactive\n");
 
-	/* program TRANS_VSYNC register */
-	for_each_dsi_port(port, intel_dsi->ports) {
-		dsi_trans = dsi_port_to_transcoder(port);
-		I915_WRITE(VSYNC(dsi_trans),
-			   (vsync_start - 1) | ((vsync_end - 1) << 16));
+	/* program TRANS_VSYNC register for video mode only */
+	if (is_vid_mode(intel_dsi)) {
+		for_each_dsi_port(port, intel_dsi->ports) {
+			dsi_trans = dsi_port_to_transcoder(port);
+			I915_WRITE(VSYNC(dsi_trans),
+				   (vsync_start - 1) | ((vsync_end - 1) << 16));
+		}
 	}
 
 	/*
-	 * FIXME: It has to be programmed only for interlaced
+	 * FIXME: It has to be programmed only for video modes and interlaced
 	 * modes. Put the check condition here once interlaced
 	 * info available as described above.
 	 * program TRANS_VSYNCSHIFT register
 	 */
-	for_each_dsi_port(port, intel_dsi->ports) {
-		dsi_trans = dsi_port_to_transcoder(port);
-		I915_WRITE(VSYNCSHIFT(dsi_trans), vsync_shift);
+	if (is_vid_mode(intel_dsi)) {
+		for_each_dsi_port(port, intel_dsi->ports) {
+			dsi_trans = dsi_port_to_transcoder(port);
+			I915_WRITE(VSYNCSHIFT(dsi_trans), vsync_shift);
+		}
 	}
 
 	/* program TRANS_VBLANK register, should be same as vtotal programmed */
-- 
2.21.0.5.gaeb582a

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[Intel-gfx] [V3 2/8] drm/i915/dsi: Add vblank calculation for command mode

[Vandita Kulkarni]

Transcoder timing calculation differ for command mode.

v2: Use is_vid_mode, and use same I915_WRITE (Jani)

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 39 +++++++++++++++++---------
 1 file changed, 26 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 089c630526bc..96f912b153e9 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -791,6 +791,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 	u16 hback_porch;
 	/* vertical timings */
 	u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
+	int bpp, line_time_us, byte_clk_period_ns;
 
 	hactive = adjusted_mode->crtc_hdisplay;
 	htotal = adjusted_mode->crtc_htotal;
@@ -828,7 +829,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 	}
 
 	/* TRANS_HSYNC register to be programmed only for video mode */
-	if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
+	if (is_vid_mode(intel_dsi)) {
 		if (intel_dsi->video_mode_format ==
 		    VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) {
 			/* BSPEC: hsync size should be atleast 16 pixels */
@@ -852,12 +853,20 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 	}
 
 	/* program TRANS_VTOTAL register */
+	if (is_cmd_mode(intel_dsi)) {
+		bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
+		byte_clk_period_ns = 8 * 1000000 / intel_dsi->pclk;
+		htotal = hactive + 160;
+		line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count);
+		vtotal = vactive + DIV_ROUND_UP(460, line_time_us);
+	}
+
 	for_each_dsi_port(port, intel_dsi->ports) {
 		dsi_trans = dsi_port_to_transcoder(port);
 		/*
-		 * FIXME: Programing this by assuming progressive mode, since
-		 * non-interlaced info from VBT is not saved inside
-		 * struct drm_display_mode.
+		 * FIXME: Programing this by assuming progressive mode,
+		 * since non-interlaced info from VBT is not saved
+		 * inside struct drm_display_mode.
 		 * For interlace mode: program required pixel minus 2
 		 */
 		I915_WRITE(VTOTAL(dsi_trans),
@@ -870,22 +879,26 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 	if (vsync_start < vactive)
 		DRM_ERROR("vsync_start less than vactive\n");
 
-	/* program TRANS_VSYNC register */
-	for_each_dsi_port(port, intel_dsi->ports) {
-		dsi_trans = dsi_port_to_transcoder(port);
-		I915_WRITE(VSYNC(dsi_trans),
-			   (vsync_start - 1) | ((vsync_end - 1) << 16));
+	/* program TRANS_VSYNC register for video mode only */
+	if (is_vid_mode(intel_dsi)) {
+		for_each_dsi_port(port, intel_dsi->ports) {
+			dsi_trans = dsi_port_to_transcoder(port);
+			I915_WRITE(VSYNC(dsi_trans),
+				   (vsync_start - 1) | ((vsync_end - 1) << 16));
+		}
 	}
 
 	/*
-	 * FIXME: It has to be programmed only for interlaced
+	 * FIXME: It has to be programmed only for video modes and interlaced
 	 * modes. Put the check condition here once interlaced
 	 * info available as described above.
 	 * program TRANS_VSYNCSHIFT register
 	 */
-	for_each_dsi_port(port, intel_dsi->ports) {
-		dsi_trans = dsi_port_to_transcoder(port);
-		I915_WRITE(VSYNCSHIFT(dsi_trans), vsync_shift);
+	if (is_vid_mode(intel_dsi)) {
+		for_each_dsi_port(port, intel_dsi->ports) {
+			dsi_trans = dsi_port_to_transcoder(port);
+			I915_WRITE(VSYNCSHIFT(dsi_trans), vsync_shift);
+		}
 	}
 
 	/* program TRANS_VBLANK register, should be same as vtotal programmed */
-- 
2.21.0.5.gaeb582a

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[V3 3/8] drm/i915/dsi: Add cmd mode flags in display mode private flags

[Vandita Kulkarni]

Adding TE flags and periodic command mode flags
as part of private flags to indicate what TE interrupts
we would be getting instead of vblanks in case of mipi dsi
command mode.

v2: Add TE flag description (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_types.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 83ea04149b77..1e071cfb3ff7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -656,6 +656,16 @@ struct intel_crtc_scaler_state {
 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
 /* Flag to use the scanline counter instead of the pixel counter */
 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
+/*
+ * TE0 or TE1 flag is set if the crtc has a DSI encoder which
+ * is operating in command mode.
+ * Flag to use TE from DSI0 instead of VBI in command mode
+ */
+#define I915_MODE_FLAG_DSI_USE_TE0 (1<<3)
+/* Flag to use TE from DSI1 instead of VBI in command mode */
+#define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)
+/* Flag to indicate mipi dsi periodic command mode where we do not get TE */
+#define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
 
 struct intel_pipe_wm {
 	struct intel_wm_level wm[5];
-- 
2.21.0.5.gaeb582a

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[Intel-gfx] [V3 3/8] drm/i915/dsi: Add cmd mode flags in display mode private flags

[Vandita Kulkarni]

Adding TE flags and periodic command mode flags
as part of private flags to indicate what TE interrupts
we would be getting instead of vblanks in case of mipi dsi
command mode.

v2: Add TE flag description (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_types.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 83ea04149b77..1e071cfb3ff7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -656,6 +656,16 @@ struct intel_crtc_scaler_state {
 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
 /* Flag to use the scanline counter instead of the pixel counter */
 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
+/*
+ * TE0 or TE1 flag is set if the crtc has a DSI encoder which
+ * is operating in command mode.
+ * Flag to use TE from DSI0 instead of VBI in command mode
+ */
+#define I915_MODE_FLAG_DSI_USE_TE0 (1<<3)
+/* Flag to use TE from DSI1 instead of VBI in command mode */
+#define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)
+/* Flag to indicate mipi dsi periodic command mode where we do not get TE */
+#define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
 
 struct intel_pipe_wm {
 	struct intel_wm_level wm[5];
-- 
2.21.0.5.gaeb582a

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[V3 4/8] drm/i915/dsi: Add check for periodic command mode

[Vandita Kulkarni]

If the GOP has programmed periodic command mode,
we need to disable that which would need a
deconfigure and configure sequence.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 96f912b153e9..5bbaac5980ca 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1306,6 +1306,21 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
 	adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
 }
 
+bool gen11_dsi_is_periodic_cmd_mode(struct drm_i915_private *dev_priv,
+				    struct intel_dsi *intel_dsi)
+{
+	u32 val;
+	enum transcoder dsi_trans;
+
+	if (intel_dsi->ports == BIT(PORT_B))
+		dsi_trans = TRANSCODER_DSI_1;
+	else
+		dsi_trans = TRANSCODER_DSI_0;
+
+	val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
+	return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE);
+}
+
 static void gen11_dsi_get_config(struct intel_encoder *encoder,
 				 struct intel_crtc_state *pipe_config)
 {
@@ -1324,6 +1339,10 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
 	gen11_dsi_get_timings(encoder, pipe_config);
 	pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
 	pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
+
+	if (gen11_dsi_is_periodic_cmd_mode(dev_priv, intel_dsi))
+		pipe_config->hw.adjusted_mode.private_flags |=
+					I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
 }
 
 static int gen11_dsi_compute_config(struct intel_encoder *encoder,
@@ -1354,6 +1373,9 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
 	pipe_config->clock_set = true;
 	pipe_config->port_clock = intel_dsi_bitrate(intel_dsi) / 5;
 
+	/* We would not opereate in peridoc command mode */
+	pipe_config->hw.adjusted_mode.private_flags &=
+					~I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
 	return 0;
 }
 
-- 
2.21.0.5.gaeb582a

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[Intel-gfx] [V3 4/8] drm/i915/dsi: Add check for periodic command mode

[Vandita Kulkarni]

If the GOP has programmed periodic command mode,
we need to disable that which would need a
deconfigure and configure sequence.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 96f912b153e9..5bbaac5980ca 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1306,6 +1306,21 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
 	adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
 }
 
+bool gen11_dsi_is_periodic_cmd_mode(struct drm_i915_private *dev_priv,
+				    struct intel_dsi *intel_dsi)
+{
+	u32 val;
+	enum transcoder dsi_trans;
+
+	if (intel_dsi->ports == BIT(PORT_B))
+		dsi_trans = TRANSCODER_DSI_1;
+	else
+		dsi_trans = TRANSCODER_DSI_0;
+
+	val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
+	return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE);
+}
+
 static void gen11_dsi_get_config(struct intel_encoder *encoder,
 				 struct intel_crtc_state *pipe_config)
 {
@@ -1324,6 +1339,10 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
 	gen11_dsi_get_timings(encoder, pipe_config);
 	pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
 	pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
+
+	if (gen11_dsi_is_periodic_cmd_mode(dev_priv, intel_dsi))
+		pipe_config->hw.adjusted_mode.private_flags |=
+					I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
 }
 
 static int gen11_dsi_compute_config(struct intel_encoder *encoder,
@@ -1354,6 +1373,9 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
 	pipe_config->clock_set = true;
 	pipe_config->port_clock = intel_dsi_bitrate(intel_dsi) / 5;
 
+	/* We would not opereate in peridoc command mode */
+	pipe_config->hw.adjusted_mode.private_flags &=
+					~I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
 	return 0;
 }
 
-- 
2.21.0.5.gaeb582a

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[V3 5/8] drm/i915/dsi: Use private flags to indicate TE in cmd mode

[Vandita Kulkarni]

On dsi cmd mode we do not receive vblanks instead
we would get TE and these flags indicate TE is expected on
which port.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 5bbaac5980ca..8db3a0f48c39 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1376,6 +1376,21 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
 	/* We would not opereate in peridoc command mode */
 	pipe_config->hw.adjusted_mode.private_flags &=
 					~I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
+
+	/*
+	 * In case of TE GATE cmd mode, we
+	 * receive TE from the slave if
+	 * dual link is enabled
+	 */
+	if (is_cmd_mode(intel_dsi)) {
+		if (intel_dsi->ports == BIT(PORT_B))
+			pipe_config->hw.adjusted_mode.private_flags |=
+						I915_MODE_FLAG_DSI_USE_TE1;
+		else
+			pipe_config->hw.adjusted_mode.private_flags |=
+						I915_MODE_FLAG_DSI_USE_TE0;
+	}
+
 	return 0;
 }
 
-- 
2.21.0.5.gaeb582a

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[Intel-gfx] [V3 5/8] drm/i915/dsi: Use private flags to indicate TE in cmd mode

[Vandita Kulkarni]

On dsi cmd mode we do not receive vblanks instead
we would get TE and these flags indicate TE is expected on
which port.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 5bbaac5980ca..8db3a0f48c39 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1376,6 +1376,21 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
 	/* We would not opereate in peridoc command mode */
 	pipe_config->hw.adjusted_mode.private_flags &=
 					~I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
+
+	/*
+	 * In case of TE GATE cmd mode, we
+	 * receive TE from the slave if
+	 * dual link is enabled
+	 */
+	if (is_cmd_mode(intel_dsi)) {
+		if (intel_dsi->ports == BIT(PORT_B))
+			pipe_config->hw.adjusted_mode.private_flags |=
+						I915_MODE_FLAG_DSI_USE_TE1;
+		else
+			pipe_config->hw.adjusted_mode.private_flags |=
+						I915_MODE_FLAG_DSI_USE_TE0;
+	}
+
 	return 0;
 }
 
-- 
2.21.0.5.gaeb582a

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[V3 6/8] drm/i915/dsi: Configure TE interrupt for cmd mode

[Vandita Kulkarni]

We need to configure TE interrupt in two places.
Port interrupt and DSI interrupt mask registers.

v2: Hide the private flags check inside configure_te (Jani)

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 55 +++++++++++++++++++++++++++++++--
 1 file changed, 53 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index dae00f7dd7df..a3d1fc0bfb56 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -41,6 +41,7 @@
 #include "display/intel_hotplug.h"
 #include "display/intel_lpe_audio.h"
 #include "display/intel_psr.h"
+#include "display/intel_dsi.h"
 
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_irq.h"
@@ -2571,12 +2572,46 @@ int ilk_enable_vblank(struct drm_crtc *crtc)
 	return 0;
 }
 
+static bool gen11_dsi_configure_te(struct drm_i915_private *dev_priv,
+				   struct drm_display_mode *mode, bool enable)
+{
+	enum port port;
+	u32 tmp;
+
+	if (!(mode->private_flags &
+	    (I915_MODE_FLAG_DSI_USE_TE1 | I915_MODE_FLAG_DSI_USE_TE0)))
+		return false;
+
+	if (mode->private_flags & I915_MODE_FLAG_DSI_USE_TE1)
+		port = PORT_B;
+	else
+		port = PORT_A;
+
+	tmp =  I915_READ(DSI_INTR_MASK_REG(port));
+	if (enable)
+		tmp &= ~DSI_TE_EVENT;
+	else
+		tmp |= DSI_TE_EVENT;
+
+	I915_WRITE(DSI_INTR_MASK_REG(port), tmp);
+	return true;
+}
+
 int bdw_enable_vblank(struct drm_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
-	enum pipe pipe = to_intel_crtc(crtc)->pipe;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	enum pipe pipe = intel_crtc->pipe;
+	struct drm_vblank_crtc *vblank;
+	struct drm_display_mode *mode;
 	unsigned long irqflags;
 
+	vblank = &crtc->dev->vblank[drm_crtc_index(crtc)];
+	mode = &vblank->hwmode;
+
+	if (gen11_dsi_configure_te(dev_priv, mode, true))
+		return 0;
+
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 	bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
@@ -2642,9 +2677,18 @@ void ilk_disable_vblank(struct drm_crtc *crtc)
 void bdw_disable_vblank(struct drm_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
-	enum pipe pipe = to_intel_crtc(crtc)->pipe;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	enum pipe pipe = intel_crtc->pipe;
+	struct drm_vblank_crtc *vblank;
+	struct drm_display_mode *mode;
 	unsigned long irqflags;
 
+	vblank = &crtc->dev->vblank[drm_crtc_index(crtc)];
+	mode = &vblank->hwmode;
+
+	if (gen11_dsi_configure_te(dev_priv, mode, false))
+		return;
+
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 	bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
@@ -3350,6 +3394,13 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 		gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
 	}
 
+	if (INTEL_GEN(dev_priv) >= 11) {
+		enum port port;
+
+		if (intel_bios_is_dsi_present(dev_priv, &port))
+			de_port_masked |= DSI0_TE | DSI1_TE;
+	}
+
 	for_each_pipe(dev_priv, pipe) {
 		dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
 
-- 
2.21.0.5.gaeb582a

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[Intel-gfx] [V3 6/8] drm/i915/dsi: Configure TE interrupt for cmd mode

[Vandita Kulkarni]

We need to configure TE interrupt in two places.
Port interrupt and DSI interrupt mask registers.

v2: Hide the private flags check inside configure_te (Jani)

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 55 +++++++++++++++++++++++++++++++--
 1 file changed, 53 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index dae00f7dd7df..a3d1fc0bfb56 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -41,6 +41,7 @@
 #include "display/intel_hotplug.h"
 #include "display/intel_lpe_audio.h"
 #include "display/intel_psr.h"
+#include "display/intel_dsi.h"
 
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_irq.h"
@@ -2571,12 +2572,46 @@ int ilk_enable_vblank(struct drm_crtc *crtc)
 	return 0;
 }
 
+static bool gen11_dsi_configure_te(struct drm_i915_private *dev_priv,
+				   struct drm_display_mode *mode, bool enable)
+{
+	enum port port;
+	u32 tmp;
+
+	if (!(mode->private_flags &
+	    (I915_MODE_FLAG_DSI_USE_TE1 | I915_MODE_FLAG_DSI_USE_TE0)))
+		return false;
+
+	if (mode->private_flags & I915_MODE_FLAG_DSI_USE_TE1)
+		port = PORT_B;
+	else
+		port = PORT_A;
+
+	tmp =  I915_READ(DSI_INTR_MASK_REG(port));
+	if (enable)
+		tmp &= ~DSI_TE_EVENT;
+	else
+		tmp |= DSI_TE_EVENT;
+
+	I915_WRITE(DSI_INTR_MASK_REG(port), tmp);
+	return true;
+}
+
 int bdw_enable_vblank(struct drm_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
-	enum pipe pipe = to_intel_crtc(crtc)->pipe;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	enum pipe pipe = intel_crtc->pipe;
+	struct drm_vblank_crtc *vblank;
+	struct drm_display_mode *mode;
 	unsigned long irqflags;
 
+	vblank = &crtc->dev->vblank[drm_crtc_index(crtc)];
+	mode = &vblank->hwmode;
+
+	if (gen11_dsi_configure_te(dev_priv, mode, true))
+		return 0;
+
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 	bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
@@ -2642,9 +2677,18 @@ void ilk_disable_vblank(struct drm_crtc *crtc)
 void bdw_disable_vblank(struct drm_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
-	enum pipe pipe = to_intel_crtc(crtc)->pipe;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	enum pipe pipe = intel_crtc->pipe;
+	struct drm_vblank_crtc *vblank;
+	struct drm_display_mode *mode;
 	unsigned long irqflags;
 
+	vblank = &crtc->dev->vblank[drm_crtc_index(crtc)];
+	mode = &vblank->hwmode;
+
+	if (gen11_dsi_configure_te(dev_priv, mode, false))
+		return;
+
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 	bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
@@ -3350,6 +3394,13 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 		gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
 	}
 
+	if (INTEL_GEN(dev_priv) >= 11) {
+		enum port port;
+
+		if (intel_bios_is_dsi_present(dev_priv, &port))
+			de_port_masked |= DSI0_TE | DSI1_TE;
+	}
+
 	for_each_pipe(dev_priv, pipe) {
 		dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
 
-- 
2.21.0.5.gaeb582a

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[V3 7/8] drm/i915/dsi: Add TE handler for dsi cmd mode.

[Vandita Kulkarni]

In case of dual link, we get the TE on slave.
So clear the TE on slave DSI IIR.

v2: Pass only relevant masked bits to the handler (Jani)

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 64 +++++++++++++++++++++++++++++++++
 1 file changed, 64 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a3d1fc0bfb56..a8c7043640db 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2230,6 +2230,62 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
 		DRM_ERROR("Unexpected DE Misc interrupt\n");
 }
 
+void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
+				    u32 te_trigger)
+{
+	enum pipe pipe = INVALID_PIPE;
+	enum transcoder dsi_trans;
+	enum port port;
+	u32 val, tmp;
+
+	/*
+	 * Incase of dual link, TE comes from DSI_1
+	 * this is to check if dual link is enabled
+	 */
+	val = I915_READ(TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0));
+	val &= PORT_SYNC_MODE_ENABLE;
+
+	/*
+	 * if dual link is enabled, then read DSI_0
+	 * transcoder registers
+	 */
+	port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ?
+						  PORT_A : PORT_B;
+	dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1;
+
+	/* Check if DSI configured in command mode */
+	val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
+	val = (val & OP_MODE_MASK) >> 28;
+
+	if (val) {
+		DRM_ERROR("DSI trancoder not configured in command mode\n");
+		return;
+	}
+
+	/* Get PIPE for handling VBLANK event */
+	val = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
+	switch (val & TRANS_DDI_EDP_INPUT_MASK) {
+	case TRANS_DDI_EDP_INPUT_A_ON:
+		pipe = PIPE_A;
+		break;
+	case TRANS_DDI_EDP_INPUT_B_ONOFF:
+		pipe = PIPE_B;
+		break;
+	case TRANS_DDI_EDP_INPUT_C_ONOFF:
+		pipe = PIPE_C;
+		break;
+	default:
+		DRM_ERROR("Invalid PIPE\n");
+	}
+
+	/* clear TE in dsi IIR */
+	port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A;
+	tmp = I915_READ(DSI_INTR_IDENT_REG(port));
+	I915_WRITE(DSI_INTR_IDENT_REG(port), tmp);
+
+	drm_handle_vblank(&dev_priv->drm, pipe);
+}
+
 static irqreturn_t
 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 {
@@ -2294,6 +2350,14 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 				found = true;
 			}
 
+			if (INTEL_GEN(dev_priv) >= 11) {
+				tmp_mask = iir & (DSI0_TE | DSI1_TE);
+				if (tmp_mask) {
+					gen11_dsi_te_interrupt_handler(dev_priv, tmp_mask);
+					found = true;
+				}
+			}
+
 			if (!found)
 				DRM_ERROR("Unexpected DE Port interrupt\n");
 		}
-- 
2.21.0.5.gaeb582a

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[Intel-gfx] [V3 7/8] drm/i915/dsi: Add TE handler for dsi cmd mode.

[Vandita Kulkarni]

In case of dual link, we get the TE on slave.
So clear the TE on slave DSI IIR.

v2: Pass only relevant masked bits to the handler (Jani)

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 64 +++++++++++++++++++++++++++++++++
 1 file changed, 64 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a3d1fc0bfb56..a8c7043640db 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2230,6 +2230,62 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
 		DRM_ERROR("Unexpected DE Misc interrupt\n");
 }
 
+void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
+				    u32 te_trigger)
+{
+	enum pipe pipe = INVALID_PIPE;
+	enum transcoder dsi_trans;
+	enum port port;
+	u32 val, tmp;
+
+	/*
+	 * Incase of dual link, TE comes from DSI_1
+	 * this is to check if dual link is enabled
+	 */
+	val = I915_READ(TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0));
+	val &= PORT_SYNC_MODE_ENABLE;
+
+	/*
+	 * if dual link is enabled, then read DSI_0
+	 * transcoder registers
+	 */
+	port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ?
+						  PORT_A : PORT_B;
+	dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1;
+
+	/* Check if DSI configured in command mode */
+	val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
+	val = (val & OP_MODE_MASK) >> 28;
+
+	if (val) {
+		DRM_ERROR("DSI trancoder not configured in command mode\n");
+		return;
+	}
+
+	/* Get PIPE for handling VBLANK event */
+	val = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
+	switch (val & TRANS_DDI_EDP_INPUT_MASK) {
+	case TRANS_DDI_EDP_INPUT_A_ON:
+		pipe = PIPE_A;
+		break;
+	case TRANS_DDI_EDP_INPUT_B_ONOFF:
+		pipe = PIPE_B;
+		break;
+	case TRANS_DDI_EDP_INPUT_C_ONOFF:
+		pipe = PIPE_C;
+		break;
+	default:
+		DRM_ERROR("Invalid PIPE\n");
+	}
+
+	/* clear TE in dsi IIR */
+	port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A;
+	tmp = I915_READ(DSI_INTR_IDENT_REG(port));
+	I915_WRITE(DSI_INTR_IDENT_REG(port), tmp);
+
+	drm_handle_vblank(&dev_priv->drm, pipe);
+}
+
 static irqreturn_t
 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 {
@@ -2294,6 +2350,14 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 				found = true;
 			}
 
+			if (INTEL_GEN(dev_priv) >= 11) {
+				tmp_mask = iir & (DSI0_TE | DSI1_TE);
+				if (tmp_mask) {
+					gen11_dsi_te_interrupt_handler(dev_priv, tmp_mask);
+					found = true;
+				}
+			}
+
 			if (!found)
 				DRM_ERROR("Unexpected DE Port interrupt\n");
 		}
-- 
2.21.0.5.gaeb582a

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[V3 8/8] drm/i915/dsi: Initiate fame request in cmd mode

[Vandita Kulkarni]

In TE Gate mode, on every flip we need to set the
frame update request bit. After this  bit is set
transcoder hardware will automatically send the
frame data to the panel when it receives the TE event.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c       | 22 ++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_display.c | 10 +++++++++
 drivers/gpu/drm/i915/display/intel_dsi.h     |  3 +++
 3 files changed, 35 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 8db3a0f48c39..78fc32065661 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -198,6 +198,28 @@ static int dsi_send_pkt_payld(struct intel_dsi_host *host,
 	return 0;
 }
 
+void gen11_dsi_frame_update(struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	u32 tmp, private_flags;
+	enum port port;
+
+	private_flags = crtc_state->hw.adjusted_mode.private_flags;
+
+	/* case 1 also covers dual link */
+	if (private_flags & I915_MODE_FLAG_DSI_USE_TE0)
+		port = PORT_A;
+	else if (private_flags & I915_MODE_FLAG_DSI_USE_TE1)
+		port = PORT_B;
+	else
+		return;
+
+	tmp = I915_READ(DSI_CMD_FRMCTL(port));
+	tmp |= DSI_FRAME_UPDATE_REQUEST;
+	I915_WRITE(DSI_CMD_FRMCTL(port), tmp);
+}
+
 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index dccb94b24d14..5fc42689087a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14886,6 +14886,16 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 			intel_color_load_luts(new_crtc_state);
 	}
 
+	/*
+	 * Incase of mipi dsi command mode, we need to set frame update
+	 * for every commit
+	 */
+	if ((INTEL_GEN(dev_priv) >= 11) &&
+	    (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))) {
+		if (new_crtc_state->hw.active)
+			gen11_dsi_frame_update(new_crtc_state);
+	}
+
 	/*
 	 * Now that the vblank has passed, we can go ahead and program the
 	 * optimal watermarks on platforms that need two-step watermark
diff --git a/drivers/gpu/drm/i915/display/intel_dsi.h b/drivers/gpu/drm/i915/display/intel_dsi.h
index b15be5814599..0c5366e23feb 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi.h
+++ b/drivers/gpu/drm/i915/display/intel_dsi.h
@@ -201,6 +201,9 @@ u32 bxt_dsi_get_pclk(struct intel_encoder *encoder,
 		     struct intel_crtc_state *config);
 void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port);
 
+/* icl_dsi.c */
+void gen11_dsi_frame_update(struct intel_crtc_state *crtc_state);
+
 /* intel_dsi_vbt.c */
 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id);
 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
-- 
2.21.0.5.gaeb582a

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[Intel-gfx] [V3 8/8] drm/i915/dsi: Initiate fame request in cmd mode

[Vandita Kulkarni]

In TE Gate mode, on every flip we need to set the
frame update request bit. After this  bit is set
transcoder hardware will automatically send the
frame data to the panel when it receives the TE event.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c       | 22 ++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_display.c | 10 +++++++++
 drivers/gpu/drm/i915/display/intel_dsi.h     |  3 +++
 3 files changed, 35 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 8db3a0f48c39..78fc32065661 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -198,6 +198,28 @@ static int dsi_send_pkt_payld(struct intel_dsi_host *host,
 	return 0;
 }
 
+void gen11_dsi_frame_update(struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	u32 tmp, private_flags;
+	enum port port;
+
+	private_flags = crtc_state->hw.adjusted_mode.private_flags;
+
+	/* case 1 also covers dual link */
+	if (private_flags & I915_MODE_FLAG_DSI_USE_TE0)
+		port = PORT_A;
+	else if (private_flags & I915_MODE_FLAG_DSI_USE_TE1)
+		port = PORT_B;
+	else
+		return;
+
+	tmp = I915_READ(DSI_CMD_FRMCTL(port));
+	tmp |= DSI_FRAME_UPDATE_REQUEST;
+	I915_WRITE(DSI_CMD_FRMCTL(port), tmp);
+}
+
 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index dccb94b24d14..5fc42689087a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14886,6 +14886,16 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 			intel_color_load_luts(new_crtc_state);
 	}
 
+	/*
+	 * Incase of mipi dsi command mode, we need to set frame update
+	 * for every commit
+	 */
+	if ((INTEL_GEN(dev_priv) >= 11) &&
+	    (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))) {
+		if (new_crtc_state->hw.active)
+			gen11_dsi_frame_update(new_crtc_state);
+	}
+
 	/*
 	 * Now that the vblank has passed, we can go ahead and program the
 	 * optimal watermarks on platforms that need two-step watermark
diff --git a/drivers/gpu/drm/i915/display/intel_dsi.h b/drivers/gpu/drm/i915/display/intel_dsi.h
index b15be5814599..0c5366e23feb 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi.h
+++ b/drivers/gpu/drm/i915/display/intel_dsi.h
@@ -201,6 +201,9 @@ u32 bxt_dsi_get_pclk(struct intel_encoder *encoder,
 		     struct intel_crtc_state *config);
 void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port);
 
+/* icl_dsi.c */
+void gen11_dsi_frame_update(struct intel_crtc_state *crtc_state);
+
 /* intel_dsi_vbt.c */
 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id);
 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
-- 
2.21.0.5.gaeb582a

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✗ Fi.CI.CHECKPATCH: warning for Add support for mipi dsi cmd mode (rev2)

[Patchwork]

== Series Details ==

Series: Add support for mipi dsi cmd mode (rev2)
URL   : https://patchwork.freedesktop.org/series/69290/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
fdc21d81bb9e drm/i915/dsi: Configure transcoder operation for command mode.
-:60: CHECK:BRACES: braces {} should be used on all arms of this statement
#60: FILE: drivers/gpu/drm/i915/display/icl_dsi.c:988:
+	if (enable) {
[...]
+	} else
[...]

-:63: CHECK:BRACES: Unbalanced braces around else statement
#63: FILE: drivers/gpu/drm/i915/display/icl_dsi.c:991:
+	} else

total: 0 errors, 0 warnings, 2 checks, 82 lines checked
14ef58b82e3d drm/i915/dsi: Add vblank calculation for command mode
-:41: WARNING:LONG_LINE: line over 100 characters
#41: FILE: drivers/gpu/drm/i915/display/icl_dsi.c:860:
+		line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count);

total: 0 errors, 1 warnings, 0 checks, 73 lines checked
efeb2e076cc1 drm/i915/dsi: Add cmd mode flags in display mode private flags
-:30: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#30: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:664:
+#define I915_MODE_FLAG_DSI_USE_TE0 (1<<3)
                                      ^

-:32: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#32: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:666:
+#define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)
                                      ^

-:34: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#34: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:668:
+#define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
                                                ^

total: 0 errors, 0 warnings, 3 checks, 16 lines checked
ef45ca1a8eed drm/i915/dsi: Add check for periodic command mode
41fd924cda49 drm/i915/dsi: Use private flags to indicate TE in cmd mode
6222c0176bcb drm/i915/dsi: Configure TE interrupt for cmd mode
c61d2184cd7b drm/i915/dsi: Add TE handler for dsi cmd mode.
8d1db9bddfa7 drm/i915/dsi: Initiate fame request in cmd mode

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for mipi dsi cmd mode (rev2)

[Patchwork]

== Series Details ==

Series: Add support for mipi dsi cmd mode (rev2)
URL   : https://patchwork.freedesktop.org/series/69290/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
fdc21d81bb9e drm/i915/dsi: Configure transcoder operation for command mode.
-:60: CHECK:BRACES: braces {} should be used on all arms of this statement
#60: FILE: drivers/gpu/drm/i915/display/icl_dsi.c:988:
+	if (enable) {
[...]
+	} else
[...]

-:63: CHECK:BRACES: Unbalanced braces around else statement
#63: FILE: drivers/gpu/drm/i915/display/icl_dsi.c:991:
+	} else

total: 0 errors, 0 warnings, 2 checks, 82 lines checked
14ef58b82e3d drm/i915/dsi: Add vblank calculation for command mode
-:41: WARNING:LONG_LINE: line over 100 characters
#41: FILE: drivers/gpu/drm/i915/display/icl_dsi.c:860:
+		line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count);

total: 0 errors, 1 warnings, 0 checks, 73 lines checked
efeb2e076cc1 drm/i915/dsi: Add cmd mode flags in display mode private flags
-:30: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#30: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:664:
+#define I915_MODE_FLAG_DSI_USE_TE0 (1<<3)
                                      ^

-:32: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#32: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:666:
+#define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)
                                      ^

-:34: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#34: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:668:
+#define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
                                                ^

total: 0 errors, 0 warnings, 3 checks, 16 lines checked
ef45ca1a8eed drm/i915/dsi: Add check for periodic command mode
41fd924cda49 drm/i915/dsi: Use private flags to indicate TE in cmd mode
6222c0176bcb drm/i915/dsi: Configure TE interrupt for cmd mode
c61d2184cd7b drm/i915/dsi: Add TE handler for dsi cmd mode.
8d1db9bddfa7 drm/i915/dsi: Initiate fame request in cmd mode

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✗ Fi.CI.SPARSE: warning for Add support for mipi dsi cmd mode (rev2)

[Patchwork]

== Series Details ==

Series: Add support for mipi dsi cmd mode (rev2)
URL   : https://patchwork.freedesktop.org/series/69290/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/dsi: Configure transcoder operation for command mode.
Okay!

Commit: drm/i915/dsi: Add vblank calculation for command mode
Okay!

Commit: drm/i915/dsi: Add cmd mode flags in display mode private flags
Okay!

Commit: drm/i915/dsi: Add check for periodic command mode
-
+drivers/gpu/drm/i915/display/icl_dsi.c:1309:6: warning: symbol 'gen11_dsi_is_periodic_cmd_mode' was not declared. Should it be static?

Commit: drm/i915/dsi: Use private flags to indicate TE in cmd mode
Okay!

Commit: drm/i915/dsi: Configure TE interrupt for cmd mode
Okay!

Commit: drm/i915/dsi: Add TE handler for dsi cmd mode.
-
+drivers/gpu/drm/i915/i915_irq.c:2233:6: warning: symbol 'gen11_dsi_te_interrupt_handler' was not declared. Should it be static?

Commit: drm/i915/dsi: Initiate fame request in cmd mode
Okay!

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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add support for mipi dsi cmd mode (rev2)

[Patchwork]

== Series Details ==

Series: Add support for mipi dsi cmd mode (rev2)
URL   : https://patchwork.freedesktop.org/series/69290/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/dsi: Configure transcoder operation for command mode.
Okay!

Commit: drm/i915/dsi: Add vblank calculation for command mode
Okay!

Commit: drm/i915/dsi: Add cmd mode flags in display mode private flags
Okay!

Commit: drm/i915/dsi: Add check for periodic command mode
-
+drivers/gpu/drm/i915/display/icl_dsi.c:1309:6: warning: symbol 'gen11_dsi_is_periodic_cmd_mode' was not declared. Should it be static?

Commit: drm/i915/dsi: Use private flags to indicate TE in cmd mode
Okay!

Commit: drm/i915/dsi: Configure TE interrupt for cmd mode
Okay!

Commit: drm/i915/dsi: Add TE handler for dsi cmd mode.
-
+drivers/gpu/drm/i915/i915_irq.c:2233:6: warning: symbol 'gen11_dsi_te_interrupt_handler' was not declared. Should it be static?

Commit: drm/i915/dsi: Initiate fame request in cmd mode
Okay!

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✓ Fi.CI.BAT: success for Add support for mipi dsi cmd mode (rev2)

[Patchwork]

== Series Details ==

Series: Add support for mipi dsi cmd mode (rev2)
URL   : https://patchwork.freedesktop.org/series/69290/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7370 -> Patchwork_15328
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/index.html

Known issues
------------

  Here are the changes found in Patchwork_15328 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@read_all_entries:
    - fi-icl-u3:          [PASS][1] -> [INCOMPLETE][2] ([fdo#107713])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/fi-icl-u3/igt@debugfs_test@read_all_entries.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/fi-icl-u3/igt@debugfs_test@read_all_entries.html
    - fi-icl-u2:          [PASS][3] -> [INCOMPLETE][4] ([fdo#107713])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/fi-icl-u2/igt@debugfs_test@read_all_entries.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/fi-icl-u2/igt@debugfs_test@read_all_entries.html
    - fi-icl-y:           [PASS][5] -> [INCOMPLETE][6] ([fdo#107713])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/fi-icl-y/igt@debugfs_test@read_all_entries.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/fi-icl-y/igt@debugfs_test@read_all_entries.html
    - fi-icl-dsi:         [PASS][7] -> [INCOMPLETE][8] ([fdo#107713])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/fi-icl-dsi/igt@debugfs_test@read_all_entries.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/fi-icl-dsi/igt@debugfs_test@read_all_entries.html
    - fi-icl-guc:         [PASS][9] -> [INCOMPLETE][10] ([fdo#107713])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/fi-icl-guc/igt@debugfs_test@read_all_entries.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/fi-icl-guc/igt@debugfs_test@read_all_entries.html

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6770hq:      [PASS][11] -> [FAIL][12] ([fdo#108511])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live_gem_contexts:
    - fi-bsw-kefka:       [PASS][13] -> [INCOMPLETE][14] ([fdo# 111542])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/fi-bsw-kefka/igt@i915_selftest@live_gem_contexts.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/fi-bsw-kefka/igt@i915_selftest@live_gem_contexts.html

  
#### Possible fixes ####

  * igt@i915_pm_rpm@module-reload:
    - {fi-kbl-7560u}:     [FAIL][15] ([fdo#112269]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/fi-kbl-7560u/igt@i915_pm_rpm@module-reload.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/fi-kbl-7560u/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live_blt:
    - fi-hsw-peppy:       [DMESG-FAIL][17] ([fdo#112147]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/fi-hsw-peppy/igt@i915_selftest@live_blt.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/fi-hsw-peppy/igt@i915_selftest@live_blt.html

  * igt@i915_selftest@live_gem_contexts:
    - fi-skl-lmem:        [DMESG-FAIL][19] -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/fi-skl-lmem/igt@i915_selftest@live_gem_contexts.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/fi-skl-lmem/igt@i915_selftest@live_gem_contexts.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][21] ([fdo#111407]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@kms_flip@basic-flip-vs-dpms:
    - fi-skl-6770hq:      [SKIP][23] ([fdo#109271]) -> [PASS][24] +27 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/fi-skl-6770hq/igt@kms_flip@basic-flip-vs-dpms.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/fi-skl-6770hq/igt@kms_flip@basic-flip-vs-dpms.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-hsw-peppy:       [DMESG-WARN][25] ([fdo#102614]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo# 111542]: https://bugs.freedesktop.org/show_bug.cgi?id= 111542
  [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
  [fdo#112147]: https://bugs.freedesktop.org/show_bug.cgi?id=112147
  [fdo#112269]: https://bugs.freedesktop.org/show_bug.cgi?id=112269


Participating hosts (49 -> 44)
------------------------------

  Additional (1): fi-hsw-4770r 
  Missing    (6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7370 -> Patchwork_15328

  CI-20190529: 20190529
  CI_DRM_7370: d2db945edccfe34bc3cc1d0accafac2036ad4e66 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5293: 4bb46f08f7cb6485642c4351cecdad93072d27a0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15328: 8d1db9bddfa74fd98434fde513734ccd952a6b22 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

8d1db9bddfa7 drm/i915/dsi: Initiate fame request in cmd mode
c61d2184cd7b drm/i915/dsi: Add TE handler for dsi cmd mode.
6222c0176bcb drm/i915/dsi: Configure TE interrupt for cmd mode
41fd924cda49 drm/i915/dsi: Use private flags to indicate TE in cmd mode
ef45ca1a8eed drm/i915/dsi: Add check for periodic command mode
efeb2e076cc1 drm/i915/dsi: Add cmd mode flags in display mode private flags
14ef58b82e3d drm/i915/dsi: Add vblank calculation for command mode
fdc21d81bb9e drm/i915/dsi: Configure transcoder operation for command mode.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for Add support for mipi dsi cmd mode (rev2)

[Patchwork]

== Series Details ==

Series: Add support for mipi dsi cmd mode (rev2)
URL   : https://patchwork.freedesktop.org/series/69290/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7370 -> Patchwork_15328
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/index.html

Known issues
------------

  Here are the changes found in Patchwork_15328 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@read_all_entries:
    - fi-icl-u3:          [PASS][1] -> [INCOMPLETE][2] ([fdo#107713])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/fi-icl-u3/igt@debugfs_test@read_all_entries.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/fi-icl-u3/igt@debugfs_test@read_all_entries.html
    - fi-icl-u2:          [PASS][3] -> [INCOMPLETE][4] ([fdo#107713])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/fi-icl-u2/igt@debugfs_test@read_all_entries.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/fi-icl-u2/igt@debugfs_test@read_all_entries.html
    - fi-icl-y:           [PASS][5] -> [INCOMPLETE][6] ([fdo#107713])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/fi-icl-y/igt@debugfs_test@read_all_entries.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/fi-icl-y/igt@debugfs_test@read_all_entries.html
    - fi-icl-dsi:         [PASS][7] -> [INCOMPLETE][8] ([fdo#107713])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/fi-icl-dsi/igt@debugfs_test@read_all_entries.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/fi-icl-dsi/igt@debugfs_test@read_all_entries.html
    - fi-icl-guc:         [PASS][9] -> [INCOMPLETE][10] ([fdo#107713])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/fi-icl-guc/igt@debugfs_test@read_all_entries.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/fi-icl-guc/igt@debugfs_test@read_all_entries.html

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6770hq:      [PASS][11] -> [FAIL][12] ([fdo#108511])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live_gem_contexts:
    - fi-bsw-kefka:       [PASS][13] -> [INCOMPLETE][14] ([fdo# 111542])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/fi-bsw-kefka/igt@i915_selftest@live_gem_contexts.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/fi-bsw-kefka/igt@i915_selftest@live_gem_contexts.html

  
#### Possible fixes ####

  * igt@i915_pm_rpm@module-reload:
    - {fi-kbl-7560u}:     [FAIL][15] ([fdo#112269]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/fi-kbl-7560u/igt@i915_pm_rpm@module-reload.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/fi-kbl-7560u/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live_blt:
    - fi-hsw-peppy:       [DMESG-FAIL][17] ([fdo#112147]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/fi-hsw-peppy/igt@i915_selftest@live_blt.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/fi-hsw-peppy/igt@i915_selftest@live_blt.html

  * igt@i915_selftest@live_gem_contexts:
    - fi-skl-lmem:        [DMESG-FAIL][19] -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/fi-skl-lmem/igt@i915_selftest@live_gem_contexts.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/fi-skl-lmem/igt@i915_selftest@live_gem_contexts.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][21] ([fdo#111407]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@kms_flip@basic-flip-vs-dpms:
    - fi-skl-6770hq:      [SKIP][23] ([fdo#109271]) -> [PASS][24] +27 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/fi-skl-6770hq/igt@kms_flip@basic-flip-vs-dpms.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/fi-skl-6770hq/igt@kms_flip@basic-flip-vs-dpms.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-hsw-peppy:       [DMESG-WARN][25] ([fdo#102614]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo# 111542]: https://bugs.freedesktop.org/show_bug.cgi?id= 111542
  [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
  [fdo#112147]: https://bugs.freedesktop.org/show_bug.cgi?id=112147
  [fdo#112269]: https://bugs.freedesktop.org/show_bug.cgi?id=112269


Participating hosts (49 -> 44)
------------------------------

  Additional (1): fi-hsw-4770r 
  Missing    (6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7370 -> Patchwork_15328

  CI-20190529: 20190529
  CI_DRM_7370: d2db945edccfe34bc3cc1d0accafac2036ad4e66 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5293: 4bb46f08f7cb6485642c4351cecdad93072d27a0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15328: 8d1db9bddfa74fd98434fde513734ccd952a6b22 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

8d1db9bddfa7 drm/i915/dsi: Initiate fame request in cmd mode
c61d2184cd7b drm/i915/dsi: Add TE handler for dsi cmd mode.
6222c0176bcb drm/i915/dsi: Configure TE interrupt for cmd mode
41fd924cda49 drm/i915/dsi: Use private flags to indicate TE in cmd mode
ef45ca1a8eed drm/i915/dsi: Add check for periodic command mode
efeb2e076cc1 drm/i915/dsi: Add cmd mode flags in display mode private flags
14ef58b82e3d drm/i915/dsi: Add vblank calculation for command mode
fdc21d81bb9e drm/i915/dsi: Configure transcoder operation for command mode.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.IGT: failure for Add support for mipi dsi cmd mode (rev2)

[Patchwork]

== Series Details ==

Series: Add support for mipi dsi cmd mode (rev2)
URL   : https://patchwork.freedesktop.org/series/69290/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7370_full -> Patchwork_15328_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_15328_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_15328_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_15328_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_cursor_crc@pipe-c-cursor-dpms:
    - shard-tglb:         [PASS][1] -> [INCOMPLETE][2] +13 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-tglb4/igt@kms_cursor_crc@pipe-c-cursor-dpms.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-tglb3/igt@kms_cursor_crc@pipe-c-cursor-dpms.html

  
Known issues
------------

  Here are the changes found in Patchwork_15328_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_exec@basic-invalid-context-vcs1:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([fdo#112080])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-iclb1/igt@gem_ctx_exec@basic-invalid-context-vcs1.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-iclb6/igt@gem_ctx_exec@basic-invalid-context-vcs1.html

  * igt@gem_ctx_isolation@vcs0-s3:
    - shard-tglb:         [PASS][5] -> [INCOMPLETE][6] ([fdo#111832])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-tglb9/igt@gem_ctx_isolation@vcs0-s3.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-tglb2/igt@gem_ctx_isolation@vcs0-s3.html

  * igt@gem_exec_schedule@out-order-bsd2:
    - shard-iclb:         [PASS][7] -> [SKIP][8] ([fdo#109276]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-iclb1/igt@gem_exec_schedule@out-order-bsd2.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-iclb7/igt@gem_exec_schedule@out-order-bsd2.html

  * igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive:
    - shard-apl:          [PASS][9] -> [DMESG-FAIL][10] ([fdo#112309]) +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-apl3/igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-apl8/igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive.html

  * igt@gem_persistent_relocs@forked-thrash-inactive:
    - shard-kbl:          [PASS][11] -> [TIMEOUT][12] ([fdo#112068 ])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-kbl1/igt@gem_persistent_relocs@forked-thrash-inactive.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-kbl6/igt@gem_persistent_relocs@forked-thrash-inactive.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy:
    - shard-hsw:          [PASS][13] -> [DMESG-WARN][14] ([fdo#111870]) +1 similar issue
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-hsw8/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-hsw8/igt@gem_userptr_blits@map-fixed-invalidate-busy.html

  * igt@gem_userptr_blits@sync-unmap-cycles:
    - shard-snb:          [PASS][15] -> [DMESG-WARN][16] ([fdo#111870]) +2 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-snb1/igt@gem_userptr_blits@sync-unmap-cycles.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-snb5/igt@gem_userptr_blits@sync-unmap-cycles.html

  * igt@i915_selftest@mock_requests:
    - shard-glk:          [PASS][17] -> [DMESG-WARN][18] ([fdo#112158])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-glk5/igt@i915_selftest@mock_requests.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-glk7/igt@i915_selftest@mock_requests.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
    - shard-hsw:          [PASS][19] -> [FAIL][20] ([fdo#105767])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-hsw5/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-hsw8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html

  * igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
    - shard-tglb:         [PASS][21] -> [INCOMPLETE][22] ([fdo#112035 ])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-tglb6/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-tglb6/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
    - shard-hsw:          [PASS][23] -> [SKIP][24] ([fdo#109271])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-hsw5/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-hsw1/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-toggle:
    - shard-skl:          [PASS][25] -> [FAIL][26] ([fdo#102670] / [fdo#106081])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html

  * igt@kms_flip@bo-too-big-interruptible:
    - shard-iclb:         [PASS][27] -> [INCOMPLETE][28] ([fdo#107713] / [fdo#110384])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-iclb3/igt@kms_flip@bo-too-big-interruptible.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-iclb6/igt@kms_flip@bo-too-big-interruptible.html

  * igt@kms_flip@busy-flip:
    - shard-tglb:         [PASS][29] -> [INCOMPLETE][30] ([fdo#112031]) +2 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-tglb9/igt@kms_flip@busy-flip.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-tglb1/igt@kms_flip@busy-flip.html

  * igt@kms_flip@dpms-off-confusion:
    - shard-iclb:         [PASS][31] -> [INCOMPLETE][32] ([fdo#107713]) +25 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-iclb7/igt@kms_flip@dpms-off-confusion.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-iclb8/igt@kms_flip@dpms-off-confusion.html

  * igt@kms_flip_tiling@flip-y-tiled:
    - shard-tglb:         [PASS][33] -> [INCOMPLETE][34] ([fdo#111747] / [fdo#112031]) +1 similar issue
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-tglb8/igt@kms_flip_tiling@flip-y-tiled.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-tglb1/igt@kms_flip_tiling@flip-y-tiled.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-kbl:          [PASS][35] -> [DMESG-WARN][36] ([fdo#108566]) +3 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render:
    - shard-iclb:         [PASS][37] -> [INCOMPLETE][38] ([fdo#106978] / [fdo#107713]) +2 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-tglb:         [PASS][39] -> [INCOMPLETE][40] ([fdo#111884]) +2 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-tglb9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-iclb:         [PASS][41] -> [INCOMPLETE][42] ([fdo#107713] / [fdo#110042])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-iclb5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-iclb2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_plane@plane-panning-top-left-pipe-d-planes:
    - shard-tglb:         [PASS][43] -> [INCOMPLETE][44] ([fdo#111747]) +6 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-tglb5/igt@kms_plane@plane-panning-top-left-pipe-d-planes.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-tglb2/igt@kms_plane@plane-panning-top-left-pipe-d-planes.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][45] -> [FAIL][46] ([fdo#108145] / [fdo#110403])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_rotation_crc@primary-x-tiled-reflect-x-0:
    - shard-iclb:         [PASS][47] -> [INCOMPLETE][48] ([fdo#107713] / [fdo#110026])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-iclb3/igt@kms_rotation_crc@primary-x-tiled-reflect-x-0.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-iclb6/igt@kms_rotation_crc@primary-x-tiled-reflect-x-0.html

  * igt@kms_vblank@pipe-b-ts-continuation-suspend:
    - shard-apl:          [PASS][49] -> [DMESG-WARN][50] ([fdo#108566]) +1 similar issue
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-apl1/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-apl6/igt@kms_vblank@pipe-b-ts-continuation-suspend.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@rcs0-s3:
    - shard-kbl:          [DMESG-WARN][51] ([fdo#108566]) -> [PASS][52] +1 similar issue
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-kbl1/igt@gem_ctx_isolation@rcs0-s3.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-kbl2/igt@gem_ctx_isolation@rcs0-s3.html

  * igt@gem_ctx_persistence@vcs1-mixed:
    - shard-iclb:         [SKIP][53] ([fdo#109276] / [fdo#112080]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-iclb3/igt@gem_ctx_persistence@vcs1-mixed.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-iclb1/igt@gem_ctx_persistence@vcs1-mixed.html

  * igt@gem_exec_schedule@preempt-contexts-bsd1:
    - shard-iclb:         [SKIP][55] ([fdo#109276]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-iclb3/igt@gem_exec_schedule@preempt-contexts-bsd1.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-iclb1/igt@gem_exec_schedule@preempt-contexts-bsd1.html

  * igt@gem_mmap_wc@set-cache-level:
    - shard-snb:          [SKIP][57] ([fdo#109271]) -> [PASS][58] +6 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-snb5/igt@gem_mmap_wc@set-cache-level.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-snb4/igt@gem_mmap_wc@set-cache-level.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-snb:          [DMESG-WARN][59] ([fdo#111870]) -> [PASS][60] +1 similar issue
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-snb2/igt@gem_userptr_blits@dmabuf-sync.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-snb6/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@sync-unmap:
    - shard-hsw:          [DMESG-WARN][61] ([fdo#111870]) -> [PASS][62] +1 similar issue
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-hsw5/igt@gem_userptr_blits@sync-unmap.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-hsw8/igt@gem_userptr_blits@sync-unmap.html

  * igt@kms_cursor_crc@pipe-b-cursor-128x128-offscreen:
    - shard-skl:          [FAIL][63] ([fdo#103232]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-skl10/igt@kms_cursor_crc@pipe-b-cursor-128x128-offscreen.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-skl9/igt@kms_cursor_crc@pipe-b-cursor-128x128-offscreen.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-apl:          [DMESG-WARN][65] ([fdo#108566]) -> [PASS][66] +1 similar issue
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-apl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-apl8/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-skl:          [INCOMPLETE][67] ([fdo#104108] / [fdo#107773]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-skl4/igt@kms_fbcon_fbt@psr-suspend.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-skl7/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_flip@2x-flip-vs-suspend:
    - shard-hsw:          [INCOMPLETE][69] ([fdo#103540]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-hsw5/igt@kms_flip@2x-flip-vs-suspend.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-hsw1/igt@kms_flip@2x-flip-vs-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-skl:          [INCOMPLETE][71] ([fdo#109507]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-skl6/igt@kms_flip@flip-vs-suspend-interruptible.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-skl10/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [FAIL][73] ([fdo#108145]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_setmode@basic:
    - shard-hsw:          [FAIL][75] ([fdo#99912]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-hsw6/igt@kms_setmode@basic.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-hsw1/igt@kms_setmode@basic.html

  
#### Warnings ####

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
    - shard-tglb:         [FAIL][77] ([fdo#103167]) -> [INCOMPLETE][78] ([fdo#111884]) +1 similar issue
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-tglb9/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
    - shard-iclb:         [FAIL][79] ([fdo#103167]) -> [INCOMPLETE][80] ([fdo#106978] / [fdo#107713]) +1 similar issue
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-tglb:         [INCOMPLETE][81] ([fdo#111832] / [fdo#111850]) -> [INCOMPLETE][82] ([fdo#111850])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-tglb1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-tglb8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  
  [fdo#102670]: https://bugs.freedesktop.org/show_bug.cgi?id=102670
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
  [fdo#106081]: https://bugs.freedesktop.org/show_bug.cgi?id=106081
  [fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
  [fdo#110026]: https://bugs.freedesktop.org/show_bug.cgi?id=110026
  [fdo#110042]: https://bugs.freedesktop.org/show_bug.cgi?id=110042
  [fdo#110384]: https://bugs.freedesktop.org/show_bug.cgi?id=110384
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
  [fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832
  [fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
  [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
  [fdo#111884]: https://bugs.freedesktop.org/show_bug.cgi?id=111884
  [fdo#112031]: https://bugs.freedesktop.org/show_bug.cgi?id=112031
  [fdo#112035 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112035 
  [fdo#112068 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112068 
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#112158]: https://bugs.freedesktop.org/show_bug.cgi?id=112158
  [fdo#112309]: https://bugs.freedesktop.org/show_bug.cgi?id=112309
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7370 -> Patchwork_15328

  CI-20190529: 20190529
  CI_DRM_7370: d2db945edccfe34bc3cc1d0accafac2036ad4e66 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5293: 4bb46f08f7cb6485642c4351cecdad93072d27a0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15328: 8d1db9bddfa74fd98434fde513734ccd952a6b22 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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[Intel-gfx] ✗ Fi.CI.IGT: failure for Add support for mipi dsi cmd mode (rev2)

[Patchwork]

== Series Details ==

Series: Add support for mipi dsi cmd mode (rev2)
URL   : https://patchwork.freedesktop.org/series/69290/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7370_full -> Patchwork_15328_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_15328_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_15328_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_15328_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_cursor_crc@pipe-c-cursor-dpms:
    - shard-tglb:         [PASS][1] -> [INCOMPLETE][2] +13 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-tglb4/igt@kms_cursor_crc@pipe-c-cursor-dpms.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-tglb3/igt@kms_cursor_crc@pipe-c-cursor-dpms.html

  
Known issues
------------

  Here are the changes found in Patchwork_15328_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_exec@basic-invalid-context-vcs1:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([fdo#112080])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-iclb1/igt@gem_ctx_exec@basic-invalid-context-vcs1.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-iclb6/igt@gem_ctx_exec@basic-invalid-context-vcs1.html

  * igt@gem_ctx_isolation@vcs0-s3:
    - shard-tglb:         [PASS][5] -> [INCOMPLETE][6] ([fdo#111832])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-tglb9/igt@gem_ctx_isolation@vcs0-s3.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-tglb2/igt@gem_ctx_isolation@vcs0-s3.html

  * igt@gem_exec_schedule@out-order-bsd2:
    - shard-iclb:         [PASS][7] -> [SKIP][8] ([fdo#109276]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-iclb1/igt@gem_exec_schedule@out-order-bsd2.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-iclb7/igt@gem_exec_schedule@out-order-bsd2.html

  * igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive:
    - shard-apl:          [PASS][9] -> [DMESG-FAIL][10] ([fdo#112309]) +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-apl3/igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-apl8/igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive.html

  * igt@gem_persistent_relocs@forked-thrash-inactive:
    - shard-kbl:          [PASS][11] -> [TIMEOUT][12] ([fdo#112068 ])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-kbl1/igt@gem_persistent_relocs@forked-thrash-inactive.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-kbl6/igt@gem_persistent_relocs@forked-thrash-inactive.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy:
    - shard-hsw:          [PASS][13] -> [DMESG-WARN][14] ([fdo#111870]) +1 similar issue
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-hsw8/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-hsw8/igt@gem_userptr_blits@map-fixed-invalidate-busy.html

  * igt@gem_userptr_blits@sync-unmap-cycles:
    - shard-snb:          [PASS][15] -> [DMESG-WARN][16] ([fdo#111870]) +2 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-snb1/igt@gem_userptr_blits@sync-unmap-cycles.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-snb5/igt@gem_userptr_blits@sync-unmap-cycles.html

  * igt@i915_selftest@mock_requests:
    - shard-glk:          [PASS][17] -> [DMESG-WARN][18] ([fdo#112158])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-glk5/igt@i915_selftest@mock_requests.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-glk7/igt@i915_selftest@mock_requests.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
    - shard-hsw:          [PASS][19] -> [FAIL][20] ([fdo#105767])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-hsw5/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-hsw8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html

  * igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
    - shard-tglb:         [PASS][21] -> [INCOMPLETE][22] ([fdo#112035 ])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-tglb6/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-tglb6/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
    - shard-hsw:          [PASS][23] -> [SKIP][24] ([fdo#109271])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-hsw5/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-hsw1/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-toggle:
    - shard-skl:          [PASS][25] -> [FAIL][26] ([fdo#102670] / [fdo#106081])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html

  * igt@kms_flip@bo-too-big-interruptible:
    - shard-iclb:         [PASS][27] -> [INCOMPLETE][28] ([fdo#107713] / [fdo#110384])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-iclb3/igt@kms_flip@bo-too-big-interruptible.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-iclb6/igt@kms_flip@bo-too-big-interruptible.html

  * igt@kms_flip@busy-flip:
    - shard-tglb:         [PASS][29] -> [INCOMPLETE][30] ([fdo#112031]) +2 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-tglb9/igt@kms_flip@busy-flip.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-tglb1/igt@kms_flip@busy-flip.html

  * igt@kms_flip@dpms-off-confusion:
    - shard-iclb:         [PASS][31] -> [INCOMPLETE][32] ([fdo#107713]) +25 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-iclb7/igt@kms_flip@dpms-off-confusion.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-iclb8/igt@kms_flip@dpms-off-confusion.html

  * igt@kms_flip_tiling@flip-y-tiled:
    - shard-tglb:         [PASS][33] -> [INCOMPLETE][34] ([fdo#111747] / [fdo#112031]) +1 similar issue
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-tglb8/igt@kms_flip_tiling@flip-y-tiled.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-tglb1/igt@kms_flip_tiling@flip-y-tiled.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-kbl:          [PASS][35] -> [DMESG-WARN][36] ([fdo#108566]) +3 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render:
    - shard-iclb:         [PASS][37] -> [INCOMPLETE][38] ([fdo#106978] / [fdo#107713]) +2 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-tglb:         [PASS][39] -> [INCOMPLETE][40] ([fdo#111884]) +2 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-tglb9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-iclb:         [PASS][41] -> [INCOMPLETE][42] ([fdo#107713] / [fdo#110042])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-iclb5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-iclb2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_plane@plane-panning-top-left-pipe-d-planes:
    - shard-tglb:         [PASS][43] -> [INCOMPLETE][44] ([fdo#111747]) +6 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-tglb5/igt@kms_plane@plane-panning-top-left-pipe-d-planes.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-tglb2/igt@kms_plane@plane-panning-top-left-pipe-d-planes.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][45] -> [FAIL][46] ([fdo#108145] / [fdo#110403])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_rotation_crc@primary-x-tiled-reflect-x-0:
    - shard-iclb:         [PASS][47] -> [INCOMPLETE][48] ([fdo#107713] / [fdo#110026])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-iclb3/igt@kms_rotation_crc@primary-x-tiled-reflect-x-0.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-iclb6/igt@kms_rotation_crc@primary-x-tiled-reflect-x-0.html

  * igt@kms_vblank@pipe-b-ts-continuation-suspend:
    - shard-apl:          [PASS][49] -> [DMESG-WARN][50] ([fdo#108566]) +1 similar issue
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-apl1/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-apl6/igt@kms_vblank@pipe-b-ts-continuation-suspend.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@rcs0-s3:
    - shard-kbl:          [DMESG-WARN][51] ([fdo#108566]) -> [PASS][52] +1 similar issue
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-kbl1/igt@gem_ctx_isolation@rcs0-s3.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-kbl2/igt@gem_ctx_isolation@rcs0-s3.html

  * igt@gem_ctx_persistence@vcs1-mixed:
    - shard-iclb:         [SKIP][53] ([fdo#109276] / [fdo#112080]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-iclb3/igt@gem_ctx_persistence@vcs1-mixed.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-iclb1/igt@gem_ctx_persistence@vcs1-mixed.html

  * igt@gem_exec_schedule@preempt-contexts-bsd1:
    - shard-iclb:         [SKIP][55] ([fdo#109276]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-iclb3/igt@gem_exec_schedule@preempt-contexts-bsd1.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-iclb1/igt@gem_exec_schedule@preempt-contexts-bsd1.html

  * igt@gem_mmap_wc@set-cache-level:
    - shard-snb:          [SKIP][57] ([fdo#109271]) -> [PASS][58] +6 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-snb5/igt@gem_mmap_wc@set-cache-level.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-snb4/igt@gem_mmap_wc@set-cache-level.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-snb:          [DMESG-WARN][59] ([fdo#111870]) -> [PASS][60] +1 similar issue
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-snb2/igt@gem_userptr_blits@dmabuf-sync.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-snb6/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@sync-unmap:
    - shard-hsw:          [DMESG-WARN][61] ([fdo#111870]) -> [PASS][62] +1 similar issue
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-hsw5/igt@gem_userptr_blits@sync-unmap.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-hsw8/igt@gem_userptr_blits@sync-unmap.html

  * igt@kms_cursor_crc@pipe-b-cursor-128x128-offscreen:
    - shard-skl:          [FAIL][63] ([fdo#103232]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-skl10/igt@kms_cursor_crc@pipe-b-cursor-128x128-offscreen.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-skl9/igt@kms_cursor_crc@pipe-b-cursor-128x128-offscreen.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-apl:          [DMESG-WARN][65] ([fdo#108566]) -> [PASS][66] +1 similar issue
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-apl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-apl8/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-skl:          [INCOMPLETE][67] ([fdo#104108] / [fdo#107773]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-skl4/igt@kms_fbcon_fbt@psr-suspend.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-skl7/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_flip@2x-flip-vs-suspend:
    - shard-hsw:          [INCOMPLETE][69] ([fdo#103540]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-hsw5/igt@kms_flip@2x-flip-vs-suspend.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-hsw1/igt@kms_flip@2x-flip-vs-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-skl:          [INCOMPLETE][71] ([fdo#109507]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-skl6/igt@kms_flip@flip-vs-suspend-interruptible.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-skl10/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [FAIL][73] ([fdo#108145]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_setmode@basic:
    - shard-hsw:          [FAIL][75] ([fdo#99912]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-hsw6/igt@kms_setmode@basic.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-hsw1/igt@kms_setmode@basic.html

  
#### Warnings ####

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
    - shard-tglb:         [FAIL][77] ([fdo#103167]) -> [INCOMPLETE][78] ([fdo#111884]) +1 similar issue
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-tglb9/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
    - shard-iclb:         [FAIL][79] ([fdo#103167]) -> [INCOMPLETE][80] ([fdo#106978] / [fdo#107713]) +1 similar issue
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-tglb:         [INCOMPLETE][81] ([fdo#111832] / [fdo#111850]) -> [INCOMPLETE][82] ([fdo#111850])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7370/shard-tglb1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/shard-tglb8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  
  [fdo#102670]: https://bugs.freedesktop.org/show_bug.cgi?id=102670
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
  [fdo#106081]: https://bugs.freedesktop.org/show_bug.cgi?id=106081
  [fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
  [fdo#110026]: https://bugs.freedesktop.org/show_bug.cgi?id=110026
  [fdo#110042]: https://bugs.freedesktop.org/show_bug.cgi?id=110042
  [fdo#110384]: https://bugs.freedesktop.org/show_bug.cgi?id=110384
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
  [fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832
  [fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
  [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
  [fdo#111884]: https://bugs.freedesktop.org/show_bug.cgi?id=111884
  [fdo#112031]: https://bugs.freedesktop.org/show_bug.cgi?id=112031
  [fdo#112035 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112035 
  [fdo#112068 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112068 
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#112158]: https://bugs.freedesktop.org/show_bug.cgi?id=112158
  [fdo#112309]: https://bugs.freedesktop.org/show_bug.cgi?id=112309
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7370 -> Patchwork_15328

  CI-20190529: 20190529
  CI_DRM_7370: d2db945edccfe34bc3cc1d0accafac2036ad4e66 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5293: 4bb46f08f7cb6485642c4351cecdad93072d27a0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15328: 8d1db9bddfa74fd98434fde513734ccd952a6b22 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15328/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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Re: [V3 1/8] drm/i915/dsi: Configure transcoder operation for command mode.

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 11500 bytes --]

Hi Vandita,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v5.4-rc8 next-20191118]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Vandita-Kulkarni/Add-support-for-mipi-dsi-cmd-mode/20191120-015713
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-defconfig (attached as .config)
compiler: gcc-7 (Debian 7.4.0-14) 7.4.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All error/warnings (new ones prefixed by >>):

   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_configure_transcoder':
>> drivers/gpu/drm/i915/display/icl_dsi.c:718:11: error: 'TE_SOURCE_GPIO' undeclared (first use in this function); did you mean 'DP_SOURCE_OUI'?
       tmp |= TE_SOURCE_GPIO;
              ^~~~~~~~~~~~~~
              DP_SOURCE_OUI
   drivers/gpu/drm/i915/display/icl_dsi.c:718:11: note: each undeclared identifier is reported only once for each function it appears in
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_config_util_pin':
>> drivers/gpu/drm/i915/display/icl_dsi.c:986:10: error: 'UTIL_PIN_DIRECTION_INPUT' undeclared (first use in this function); did you mean 'UTIL_PIN_PIPE_MASK'?
      tmp |= UTIL_PIN_DIRECTION_INPUT;
             ^~~~~~~~~~~~~~~~~~~~~~~~
             UTIL_PIN_PIPE_MASK
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_deconfigure_trancoder':
>> drivers/gpu/drm/i915/display/icl_dsi.c:1151:20: error: implicit declaration of function 'DSI_CMD_FRMCTL'; did you mean 'DSI_CMD_RXCTL'? [-Werror=implicit-function-declaration]
       tmp = I915_READ(DSI_CMD_FRMCTL(port));
                       ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
>> drivers/gpu/drm/i915/display/icl_dsi.c:1151:10: note: in expansion of macro 'I915_READ'
       tmp = I915_READ(DSI_CMD_FRMCTL(port));
             ^~~~~~~~~
>> drivers/gpu/drm/i915/i915_drv.h:1981:57: error: incompatible type for argument 2 of 'intel_uncore_read'
    #define I915_READ(reg__)  __I915_REG_OP(read, dev_priv, (reg__))
                                                            ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
>> drivers/gpu/drm/i915/display/icl_dsi.c:1151:10: note: in expansion of macro 'I915_READ'
       tmp = I915_READ(DSI_CMD_FRMCTL(port));
             ^~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/intel_uncore.h:287:22: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
                         ^
>> drivers/gpu/drm/i915/intel_uncore.h:302:1: note: in expansion of macro '__uncore_read'
    __uncore_read(read, 32, l, true)
    ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/icl_dsi.c:1152:12: error: 'DSI_PERIODIC_FRAME_UPDATE_ENABLE' undeclared (first use in this function); did you mean 'GEN6_MBCTL_BME_UPDATE_ENABLE'?
       tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE;
               ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
               GEN6_MBCTL_BME_UPDATE_ENABLE
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
>> drivers/gpu/drm/i915/i915_drv.h:1982:65: error: incompatible type for argument 2 of 'intel_uncore_write'
    #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
                                                                    ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
>> drivers/gpu/drm/i915/display/icl_dsi.c:1153:4: note: in expansion of macro 'I915_WRITE'
       I915_WRITE(DSI_CMD_FRMCTL(port), tmp);
       ^~~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/intel_uncore.h:294:20: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline void intel_uncore_##name__(struct intel_uncore *uncore, \
                       ^
>> drivers/gpu/drm/i915/intel_uncore.h:308:1: note: in expansion of macro '__uncore_write'
    __uncore_write(write, 32, l, true)
    ^~~~~~~~~~~~~~
   cc1: some warnings being treated as errors

vim +718 drivers/gpu/drm/i915/display/icl_dsi.c

   621	
   622	static void
   623	gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
   624				       const struct intel_crtc_state *pipe_config)
   625	{
   626		struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
   627		struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
   628		struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
   629		enum pipe pipe = intel_crtc->pipe;
   630		u32 tmp;
   631		enum port port;
   632		enum transcoder dsi_trans;
   633	
   634		for_each_dsi_port(port, intel_dsi->ports) {
   635			dsi_trans = dsi_port_to_transcoder(port);
   636			tmp = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
   637	
   638			if (intel_dsi->eotp_pkt)
   639				tmp &= ~EOTP_DISABLED;
   640			else
   641				tmp |= EOTP_DISABLED;
   642	
   643			/* enable link calibration if freq > 1.5Gbps */
   644			if (intel_dsi_bitrate(intel_dsi) >= 1500 * 1000) {
   645				tmp &= ~LINK_CALIBRATION_MASK;
   646				tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
   647			}
   648	
   649			/* configure continuous clock */
   650			tmp &= ~CONTINUOUS_CLK_MASK;
   651			if (intel_dsi->clock_stop)
   652				tmp |= CLK_ENTER_LP_AFTER_DATA;
   653			else
   654				tmp |= CLK_HS_CONTINUOUS;
   655	
   656			/* configure buffer threshold limit to minimum */
   657			tmp &= ~PIX_BUF_THRESHOLD_MASK;
   658			tmp |= PIX_BUF_THRESHOLD_1_4;
   659	
   660			/* set virtual channel to '0' */
   661			tmp &= ~PIX_VIRT_CHAN_MASK;
   662			tmp |= PIX_VIRT_CHAN(0);
   663	
   664			/* program BGR transmission */
   665			if (intel_dsi->bgr_enabled)
   666				tmp |= BGR_TRANSMISSION;
   667	
   668			/* select pixel format */
   669			tmp &= ~PIX_FMT_MASK;
   670			switch (intel_dsi->pixel_format) {
   671			default:
   672				MISSING_CASE(intel_dsi->pixel_format);
   673				/* fallthrough */
   674			case MIPI_DSI_FMT_RGB565:
   675				tmp |= PIX_FMT_RGB565;
   676				break;
   677			case MIPI_DSI_FMT_RGB666_PACKED:
   678				tmp |= PIX_FMT_RGB666_PACKED;
   679				break;
   680			case MIPI_DSI_FMT_RGB666:
   681				tmp |= PIX_FMT_RGB666_LOOSE;
   682				break;
   683			case MIPI_DSI_FMT_RGB888:
   684				tmp |= PIX_FMT_RGB888;
   685				break;
   686			}
   687	
   688			if (INTEL_GEN(dev_priv) >= 12) {
   689				if (is_vid_mode(intel_dsi))
   690					tmp |= BLANKING_PACKET_ENABLE;
   691			}
   692	
   693			/* program DSI operation mode */
   694			if (is_vid_mode(intel_dsi)) {
   695				tmp &= ~OP_MODE_MASK;
   696				switch (intel_dsi->video_mode_format) {
   697				default:
   698					MISSING_CASE(intel_dsi->video_mode_format);
   699					/* fallthrough */
   700				case VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS:
   701					tmp |= VIDEO_MODE_SYNC_EVENT;
   702					break;
   703				case VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE:
   704					tmp |= VIDEO_MODE_SYNC_PULSE;
   705					break;
   706				}
   707			} else {
   708				/*
   709				 * FIXME: Retrieve this info from VBT.
   710				 * As per the spec when dsi transcoder is operating
   711				 * in TE GATE mode, TE comes from GPIO
   712				 * which is UTIL PIN for DSI 0.
   713				 * Also this GPIO would not be used for other
   714				 * purposes is an assumption.
   715				 */
   716				tmp &= ~OP_MODE_MASK;
   717				tmp |= CMD_MODE_TE_GATE;
 > 718				tmp |= TE_SOURCE_GPIO;
   719			}
   720	
   721			I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
   722		}
   723	
   724		/* enable port sync mode if dual link */
   725		if (intel_dsi->dual_link) {
   726			for_each_dsi_port(port, intel_dsi->ports) {
   727				dsi_trans = dsi_port_to_transcoder(port);
   728				tmp = I915_READ(TRANS_DDI_FUNC_CTL2(dsi_trans));
   729				tmp |= PORT_SYNC_MODE_ENABLE;
   730				I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
   731			}
   732	
   733			/* configure stream splitting */
   734			configure_dual_link_mode(encoder, pipe_config);
   735		}
   736	
   737		for_each_dsi_port(port, intel_dsi->ports) {
   738			dsi_trans = dsi_port_to_transcoder(port);
   739	
   740			/* select data lane width */
   741			tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
   742			tmp &= ~DDI_PORT_WIDTH_MASK;
   743			tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
   744	
   745			/* select input pipe */
   746			tmp &= ~TRANS_DDI_EDP_INPUT_MASK;
   747			switch (pipe) {
   748			default:
   749				MISSING_CASE(pipe);
   750				/* fallthrough */
   751			case PIPE_A:
   752				tmp |= TRANS_DDI_EDP_INPUT_A_ON;
   753				break;
   754			case PIPE_B:
   755				tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
   756				break;
   757			case PIPE_C:
   758				tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
   759				break;
   760			}
   761	
   762			/* enable DDI buffer */
   763			tmp |= TRANS_DDI_FUNC_ENABLE;
   764			I915_WRITE(TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
   765		}
   766	
   767		/* wait for link ready */
   768		for_each_dsi_port(port, intel_dsi->ports) {
   769			dsi_trans = dsi_port_to_transcoder(port);
   770			if (wait_for_us((I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans)) &
   771					LINK_READY), 2500))
   772				DRM_ERROR("DSI link not ready\n");
   773		}
   774	}
   775	

---
0-DAY kernel test infrastructure                 Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org Intel Corporation

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [V3 1/8] drm/i915/dsi: Configure transcoder operation for command mode.

[kbuild test robot]

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Hi Vandita,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v5.4-rc8 next-20191118]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Vandita-Kulkarni/Add-support-for-mipi-dsi-cmd-mode/20191120-015713
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-defconfig (attached as .config)
compiler: gcc-7 (Debian 7.4.0-14) 7.4.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All error/warnings (new ones prefixed by >>):

   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_configure_transcoder':
>> drivers/gpu/drm/i915/display/icl_dsi.c:718:11: error: 'TE_SOURCE_GPIO' undeclared (first use in this function); did you mean 'DP_SOURCE_OUI'?
       tmp |= TE_SOURCE_GPIO;
              ^~~~~~~~~~~~~~
              DP_SOURCE_OUI
   drivers/gpu/drm/i915/display/icl_dsi.c:718:11: note: each undeclared identifier is reported only once for each function it appears in
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_config_util_pin':
>> drivers/gpu/drm/i915/display/icl_dsi.c:986:10: error: 'UTIL_PIN_DIRECTION_INPUT' undeclared (first use in this function); did you mean 'UTIL_PIN_PIPE_MASK'?
      tmp |= UTIL_PIN_DIRECTION_INPUT;
             ^~~~~~~~~~~~~~~~~~~~~~~~
             UTIL_PIN_PIPE_MASK
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_deconfigure_trancoder':
>> drivers/gpu/drm/i915/display/icl_dsi.c:1151:20: error: implicit declaration of function 'DSI_CMD_FRMCTL'; did you mean 'DSI_CMD_RXCTL'? [-Werror=implicit-function-declaration]
       tmp = I915_READ(DSI_CMD_FRMCTL(port));
                       ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
>> drivers/gpu/drm/i915/display/icl_dsi.c:1151:10: note: in expansion of macro 'I915_READ'
       tmp = I915_READ(DSI_CMD_FRMCTL(port));
             ^~~~~~~~~
>> drivers/gpu/drm/i915/i915_drv.h:1981:57: error: incompatible type for argument 2 of 'intel_uncore_read'
    #define I915_READ(reg__)  __I915_REG_OP(read, dev_priv, (reg__))
                                                            ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
>> drivers/gpu/drm/i915/display/icl_dsi.c:1151:10: note: in expansion of macro 'I915_READ'
       tmp = I915_READ(DSI_CMD_FRMCTL(port));
             ^~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/intel_uncore.h:287:22: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
                         ^
>> drivers/gpu/drm/i915/intel_uncore.h:302:1: note: in expansion of macro '__uncore_read'
    __uncore_read(read, 32, l, true)
    ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/icl_dsi.c:1152:12: error: 'DSI_PERIODIC_FRAME_UPDATE_ENABLE' undeclared (first use in this function); did you mean 'GEN6_MBCTL_BME_UPDATE_ENABLE'?
       tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE;
               ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
               GEN6_MBCTL_BME_UPDATE_ENABLE
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
>> drivers/gpu/drm/i915/i915_drv.h:1982:65: error: incompatible type for argument 2 of 'intel_uncore_write'
    #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
                                                                    ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
>> drivers/gpu/drm/i915/display/icl_dsi.c:1153:4: note: in expansion of macro 'I915_WRITE'
       I915_WRITE(DSI_CMD_FRMCTL(port), tmp);
       ^~~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/intel_uncore.h:294:20: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline void intel_uncore_##name__(struct intel_uncore *uncore, \
                       ^
>> drivers/gpu/drm/i915/intel_uncore.h:308:1: note: in expansion of macro '__uncore_write'
    __uncore_write(write, 32, l, true)
    ^~~~~~~~~~~~~~
   cc1: some warnings being treated as errors

vim +718 drivers/gpu/drm/i915/display/icl_dsi.c

   621	
   622	static void
   623	gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
   624				       const struct intel_crtc_state *pipe_config)
   625	{
   626		struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
   627		struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
   628		struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
   629		enum pipe pipe = intel_crtc->pipe;
   630		u32 tmp;
   631		enum port port;
   632		enum transcoder dsi_trans;
   633	
   634		for_each_dsi_port(port, intel_dsi->ports) {
   635			dsi_trans = dsi_port_to_transcoder(port);
   636			tmp = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
   637	
   638			if (intel_dsi->eotp_pkt)
   639				tmp &= ~EOTP_DISABLED;
   640			else
   641				tmp |= EOTP_DISABLED;
   642	
   643			/* enable link calibration if freq > 1.5Gbps */
   644			if (intel_dsi_bitrate(intel_dsi) >= 1500 * 1000) {
   645				tmp &= ~LINK_CALIBRATION_MASK;
   646				tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
   647			}
   648	
   649			/* configure continuous clock */
   650			tmp &= ~CONTINUOUS_CLK_MASK;
   651			if (intel_dsi->clock_stop)
   652				tmp |= CLK_ENTER_LP_AFTER_DATA;
   653			else
   654				tmp |= CLK_HS_CONTINUOUS;
   655	
   656			/* configure buffer threshold limit to minimum */
   657			tmp &= ~PIX_BUF_THRESHOLD_MASK;
   658			tmp |= PIX_BUF_THRESHOLD_1_4;
   659	
   660			/* set virtual channel to '0' */
   661			tmp &= ~PIX_VIRT_CHAN_MASK;
   662			tmp |= PIX_VIRT_CHAN(0);
   663	
   664			/* program BGR transmission */
   665			if (intel_dsi->bgr_enabled)
   666				tmp |= BGR_TRANSMISSION;
   667	
   668			/* select pixel format */
   669			tmp &= ~PIX_FMT_MASK;
   670			switch (intel_dsi->pixel_format) {
   671			default:
   672				MISSING_CASE(intel_dsi->pixel_format);
   673				/* fallthrough */
   674			case MIPI_DSI_FMT_RGB565:
   675				tmp |= PIX_FMT_RGB565;
   676				break;
   677			case MIPI_DSI_FMT_RGB666_PACKED:
   678				tmp |= PIX_FMT_RGB666_PACKED;
   679				break;
   680			case MIPI_DSI_FMT_RGB666:
   681				tmp |= PIX_FMT_RGB666_LOOSE;
   682				break;
   683			case MIPI_DSI_FMT_RGB888:
   684				tmp |= PIX_FMT_RGB888;
   685				break;
   686			}
   687	
   688			if (INTEL_GEN(dev_priv) >= 12) {
   689				if (is_vid_mode(intel_dsi))
   690					tmp |= BLANKING_PACKET_ENABLE;
   691			}
   692	
   693			/* program DSI operation mode */
   694			if (is_vid_mode(intel_dsi)) {
   695				tmp &= ~OP_MODE_MASK;
   696				switch (intel_dsi->video_mode_format) {
   697				default:
   698					MISSING_CASE(intel_dsi->video_mode_format);
   699					/* fallthrough */
   700				case VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS:
   701					tmp |= VIDEO_MODE_SYNC_EVENT;
   702					break;
   703				case VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE:
   704					tmp |= VIDEO_MODE_SYNC_PULSE;
   705					break;
   706				}
   707			} else {
   708				/*
   709				 * FIXME: Retrieve this info from VBT.
   710				 * As per the spec when dsi transcoder is operating
   711				 * in TE GATE mode, TE comes from GPIO
   712				 * which is UTIL PIN for DSI 0.
   713				 * Also this GPIO would not be used for other
   714				 * purposes is an assumption.
   715				 */
   716				tmp &= ~OP_MODE_MASK;
   717				tmp |= CMD_MODE_TE_GATE;
 > 718				tmp |= TE_SOURCE_GPIO;
   719			}
   720	
   721			I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
   722		}
   723	
   724		/* enable port sync mode if dual link */
   725		if (intel_dsi->dual_link) {
   726			for_each_dsi_port(port, intel_dsi->ports) {
   727				dsi_trans = dsi_port_to_transcoder(port);
   728				tmp = I915_READ(TRANS_DDI_FUNC_CTL2(dsi_trans));
   729				tmp |= PORT_SYNC_MODE_ENABLE;
   730				I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
   731			}
   732	
   733			/* configure stream splitting */
   734			configure_dual_link_mode(encoder, pipe_config);
   735		}
   736	
   737		for_each_dsi_port(port, intel_dsi->ports) {
   738			dsi_trans = dsi_port_to_transcoder(port);
   739	
   740			/* select data lane width */
   741			tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
   742			tmp &= ~DDI_PORT_WIDTH_MASK;
   743			tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
   744	
   745			/* select input pipe */
   746			tmp &= ~TRANS_DDI_EDP_INPUT_MASK;
   747			switch (pipe) {
   748			default:
   749				MISSING_CASE(pipe);
   750				/* fallthrough */
   751			case PIPE_A:
   752				tmp |= TRANS_DDI_EDP_INPUT_A_ON;
   753				break;
   754			case PIPE_B:
   755				tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
   756				break;
   757			case PIPE_C:
   758				tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
   759				break;
   760			}
   761	
   762			/* enable DDI buffer */
   763			tmp |= TRANS_DDI_FUNC_ENABLE;
   764			I915_WRITE(TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
   765		}
   766	
   767		/* wait for link ready */
   768		for_each_dsi_port(port, intel_dsi->ports) {
   769			dsi_trans = dsi_port_to_transcoder(port);
   770			if (wait_for_us((I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans)) &
   771					LINK_READY), 2500))
   772				DRM_ERROR("DSI link not ready\n");
   773		}
   774	}
   775	

---
0-DAY kernel test infrastructure                 Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org Intel Corporation

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[-- Attachment #3: Type: text/plain, Size: 159 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [V3 1/8] drm/i915/dsi: Configure transcoder operation for command mode.

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 11763 bytes --]

Hi Vandita,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v5.4-rc8 next-20191118]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Vandita-Kulkarni/Add-support-for-mipi-dsi-cmd-mode/20191120-015713
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-defconfig (attached as .config)
compiler: gcc-7 (Debian 7.4.0-14) 7.4.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All error/warnings (new ones prefixed by >>):

   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_configure_transcoder':
>> drivers/gpu/drm/i915/display/icl_dsi.c:718:11: error: 'TE_SOURCE_GPIO' undeclared (first use in this function); did you mean 'DP_SOURCE_OUI'?
       tmp |= TE_SOURCE_GPIO;
              ^~~~~~~~~~~~~~
              DP_SOURCE_OUI
   drivers/gpu/drm/i915/display/icl_dsi.c:718:11: note: each undeclared identifier is reported only once for each function it appears in
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_config_util_pin':
>> drivers/gpu/drm/i915/display/icl_dsi.c:986:10: error: 'UTIL_PIN_DIRECTION_INPUT' undeclared (first use in this function); did you mean 'UTIL_PIN_PIPE_MASK'?
      tmp |= UTIL_PIN_DIRECTION_INPUT;
             ^~~~~~~~~~~~~~~~~~~~~~~~
             UTIL_PIN_PIPE_MASK
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_deconfigure_trancoder':
>> drivers/gpu/drm/i915/display/icl_dsi.c:1151:20: error: implicit declaration of function 'DSI_CMD_FRMCTL'; did you mean 'DSI_CMD_RXCTL'? [-Werror=implicit-function-declaration]
       tmp = I915_READ(DSI_CMD_FRMCTL(port));
                       ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
>> drivers/gpu/drm/i915/display/icl_dsi.c:1151:10: note: in expansion of macro 'I915_READ'
       tmp = I915_READ(DSI_CMD_FRMCTL(port));
             ^~~~~~~~~
>> drivers/gpu/drm/i915/i915_drv.h:1981:57: error: incompatible type for argument 2 of 'intel_uncore_read'
    #define I915_READ(reg__)  __I915_REG_OP(read, dev_priv, (reg__))
                                                            ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
>> drivers/gpu/drm/i915/display/icl_dsi.c:1151:10: note: in expansion of macro 'I915_READ'
       tmp = I915_READ(DSI_CMD_FRMCTL(port));
             ^~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/intel_uncore.h:287:22: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
                         ^
>> drivers/gpu/drm/i915/intel_uncore.h:302:1: note: in expansion of macro '__uncore_read'
    __uncore_read(read, 32, l, true)
    ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/icl_dsi.c:1152:12: error: 'DSI_PERIODIC_FRAME_UPDATE_ENABLE' undeclared (first use in this function); did you mean 'GEN6_MBCTL_BME_UPDATE_ENABLE'?
       tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE;
               ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
               GEN6_MBCTL_BME_UPDATE_ENABLE
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
>> drivers/gpu/drm/i915/i915_drv.h:1982:65: error: incompatible type for argument 2 of 'intel_uncore_write'
    #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
                                                                    ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
>> drivers/gpu/drm/i915/display/icl_dsi.c:1153:4: note: in expansion of macro 'I915_WRITE'
       I915_WRITE(DSI_CMD_FRMCTL(port), tmp);
       ^~~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/intel_uncore.h:294:20: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline void intel_uncore_##name__(struct intel_uncore *uncore, \
                       ^
>> drivers/gpu/drm/i915/intel_uncore.h:308:1: note: in expansion of macro '__uncore_write'
    __uncore_write(write, 32, l, true)
    ^~~~~~~~~~~~~~
   cc1: some warnings being treated as errors

vim +718 drivers/gpu/drm/i915/display/icl_dsi.c

   621	
   622	static void
   623	gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
   624				       const struct intel_crtc_state *pipe_config)
   625	{
   626		struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
   627		struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
   628		struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
   629		enum pipe pipe = intel_crtc->pipe;
   630		u32 tmp;
   631		enum port port;
   632		enum transcoder dsi_trans;
   633	
   634		for_each_dsi_port(port, intel_dsi->ports) {
   635			dsi_trans = dsi_port_to_transcoder(port);
   636			tmp = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
   637	
   638			if (intel_dsi->eotp_pkt)
   639				tmp &= ~EOTP_DISABLED;
   640			else
   641				tmp |= EOTP_DISABLED;
   642	
   643			/* enable link calibration if freq > 1.5Gbps */
   644			if (intel_dsi_bitrate(intel_dsi) >= 1500 * 1000) {
   645				tmp &= ~LINK_CALIBRATION_MASK;
   646				tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
   647			}
   648	
   649			/* configure continuous clock */
   650			tmp &= ~CONTINUOUS_CLK_MASK;
   651			if (intel_dsi->clock_stop)
   652				tmp |= CLK_ENTER_LP_AFTER_DATA;
   653			else
   654				tmp |= CLK_HS_CONTINUOUS;
   655	
   656			/* configure buffer threshold limit to minimum */
   657			tmp &= ~PIX_BUF_THRESHOLD_MASK;
   658			tmp |= PIX_BUF_THRESHOLD_1_4;
   659	
   660			/* set virtual channel to '0' */
   661			tmp &= ~PIX_VIRT_CHAN_MASK;
   662			tmp |= PIX_VIRT_CHAN(0);
   663	
   664			/* program BGR transmission */
   665			if (intel_dsi->bgr_enabled)
   666				tmp |= BGR_TRANSMISSION;
   667	
   668			/* select pixel format */
   669			tmp &= ~PIX_FMT_MASK;
   670			switch (intel_dsi->pixel_format) {
   671			default:
   672				MISSING_CASE(intel_dsi->pixel_format);
   673				/* fallthrough */
   674			case MIPI_DSI_FMT_RGB565:
   675				tmp |= PIX_FMT_RGB565;
   676				break;
   677			case MIPI_DSI_FMT_RGB666_PACKED:
   678				tmp |= PIX_FMT_RGB666_PACKED;
   679				break;
   680			case MIPI_DSI_FMT_RGB666:
   681				tmp |= PIX_FMT_RGB666_LOOSE;
   682				break;
   683			case MIPI_DSI_FMT_RGB888:
   684				tmp |= PIX_FMT_RGB888;
   685				break;
   686			}
   687	
   688			if (INTEL_GEN(dev_priv) >= 12) {
   689				if (is_vid_mode(intel_dsi))
   690					tmp |= BLANKING_PACKET_ENABLE;
   691			}
   692	
   693			/* program DSI operation mode */
   694			if (is_vid_mode(intel_dsi)) {
   695				tmp &= ~OP_MODE_MASK;
   696				switch (intel_dsi->video_mode_format) {
   697				default:
   698					MISSING_CASE(intel_dsi->video_mode_format);
   699					/* fallthrough */
   700				case VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS:
   701					tmp |= VIDEO_MODE_SYNC_EVENT;
   702					break;
   703				case VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE:
   704					tmp |= VIDEO_MODE_SYNC_PULSE;
   705					break;
   706				}
   707			} else {
   708				/*
   709				 * FIXME: Retrieve this info from VBT.
   710				 * As per the spec when dsi transcoder is operating
   711				 * in TE GATE mode, TE comes from GPIO
   712				 * which is UTIL PIN for DSI 0.
   713				 * Also this GPIO would not be used for other
   714				 * purposes is an assumption.
   715				 */
   716				tmp &= ~OP_MODE_MASK;
   717				tmp |= CMD_MODE_TE_GATE;
 > 718				tmp |= TE_SOURCE_GPIO;
   719			}
   720	
   721			I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
   722		}
   723	
   724		/* enable port sync mode if dual link */
   725		if (intel_dsi->dual_link) {
   726			for_each_dsi_port(port, intel_dsi->ports) {
   727				dsi_trans = dsi_port_to_transcoder(port);
   728				tmp = I915_READ(TRANS_DDI_FUNC_CTL2(dsi_trans));
   729				tmp |= PORT_SYNC_MODE_ENABLE;
   730				I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
   731			}
   732	
   733			/* configure stream splitting */
   734			configure_dual_link_mode(encoder, pipe_config);
   735		}
   736	
   737		for_each_dsi_port(port, intel_dsi->ports) {
   738			dsi_trans = dsi_port_to_transcoder(port);
   739	
   740			/* select data lane width */
   741			tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
   742			tmp &= ~DDI_PORT_WIDTH_MASK;
   743			tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
   744	
   745			/* select input pipe */
   746			tmp &= ~TRANS_DDI_EDP_INPUT_MASK;
   747			switch (pipe) {
   748			default:
   749				MISSING_CASE(pipe);
   750				/* fallthrough */
   751			case PIPE_A:
   752				tmp |= TRANS_DDI_EDP_INPUT_A_ON;
   753				break;
   754			case PIPE_B:
   755				tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
   756				break;
   757			case PIPE_C:
   758				tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
   759				break;
   760			}
   761	
   762			/* enable DDI buffer */
   763			tmp |= TRANS_DDI_FUNC_ENABLE;
   764			I915_WRITE(TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
   765		}
   766	
   767		/* wait for link ready */
   768		for_each_dsi_port(port, intel_dsi->ports) {
   769			dsi_trans = dsi_port_to_transcoder(port);
   770			if (wait_for_us((I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans)) &
   771					LINK_READY), 2500))
   772				DRM_ERROR("DSI link not ready\n");
   773		}
   774	}
   775	

---
0-DAY kernel test infrastructure                 Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org Intel Corporation

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Re: [V3 4/8] drm/i915/dsi: Add check for periodic command mode

[kbuild test robot]

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Hi Vandita,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[cannot apply to v5.4-rc8 next-20191118]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Vandita-Kulkarni/Add-support-for-mipi-dsi-cmd-mode/20191120-015713
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-defconfig (attached as .config)
compiler: gcc-7 (Debian 7.4.0-14) 7.4.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_configure_transcoder':
   drivers/gpu/drm/i915/display/icl_dsi.c:718:11: error: 'TE_SOURCE_GPIO' undeclared (first use in this function); did you mean 'DP_SOURCE_OUI'?
       tmp |= TE_SOURCE_GPIO;
              ^~~~~~~~~~~~~~
              DP_SOURCE_OUI
   drivers/gpu/drm/i915/display/icl_dsi.c:718:11: note: each undeclared identifier is reported only once for each function it appears in
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_config_util_pin':
   drivers/gpu/drm/i915/display/icl_dsi.c:999:10: error: 'UTIL_PIN_DIRECTION_INPUT' undeclared (first use in this function); did you mean 'UTIL_PIN_PIPE_MASK'?
      tmp |= UTIL_PIN_DIRECTION_INPUT;
             ^~~~~~~~~~~~~~~~~~~~~~~~
             UTIL_PIN_PIPE_MASK
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_deconfigure_trancoder':
   drivers/gpu/drm/i915/display/icl_dsi.c:1164:20: error: implicit declaration of function 'DSI_CMD_FRMCTL'; did you mean 'DSI_CMD_RXCTL'? [-Werror=implicit-function-declaration]
       tmp = I915_READ(DSI_CMD_FRMCTL(port));
                       ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:1164:10: note: in expansion of macro 'I915_READ'
       tmp = I915_READ(DSI_CMD_FRMCTL(port));
             ^~~~~~~~~
   drivers/gpu/drm/i915/i915_drv.h:1981:57: error: incompatible type for argument 2 of 'intel_uncore_read'
    #define I915_READ(reg__)  __I915_REG_OP(read, dev_priv, (reg__))
                                                            ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:1164:10: note: in expansion of macro 'I915_READ'
       tmp = I915_READ(DSI_CMD_FRMCTL(port));
             ^~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/intel_uncore.h:287:22: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
                         ^
   drivers/gpu/drm/i915/intel_uncore.h:302:1: note: in expansion of macro '__uncore_read'
    __uncore_read(read, 32, l, true)
    ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:1165:12: error: 'DSI_PERIODIC_FRAME_UPDATE_ENABLE' undeclared (first use in this function); did you mean 'GEN6_MBCTL_BME_UPDATE_ENABLE'?
       tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE;
               ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
               GEN6_MBCTL_BME_UPDATE_ENABLE
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/i915_drv.h:1982:65: error: incompatible type for argument 2 of 'intel_uncore_write'
    #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
                                                                    ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:1166:4: note: in expansion of macro 'I915_WRITE'
       I915_WRITE(DSI_CMD_FRMCTL(port), tmp);
       ^~~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/intel_uncore.h:294:20: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline void intel_uncore_##name__(struct intel_uncore *uncore, \
                       ^
   drivers/gpu/drm/i915/intel_uncore.h:308:1: note: in expansion of macro '__uncore_write'
    __uncore_write(write, 32, l, true)
    ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_is_periodic_cmd_mode':
   drivers/gpu/drm/i915/display/icl_dsi.c:1318:16: error: 'DSI_PERIODIC_FRAME_UPDATE_ENABLE' undeclared (first use in this function); did you mean 'GEN6_MBCTL_BME_UPDATE_ENABLE'?
     return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE);
                   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                   GEN6_MBCTL_BME_UPDATE_ENABLE
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_get_config':
   drivers/gpu/drm/i915/display/icl_dsi.c:1341:14: error: 'struct intel_crtc_state' has no member named 'hw'
      pipe_config->hw.adjusted_mode.private_flags |=
                 ^~
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_compute_config':
   drivers/gpu/drm/i915/display/icl_dsi.c:1374:13: error: 'struct intel_crtc_state' has no member named 'hw'
     pipe_config->hw.adjusted_mode.private_flags &=
                ^~
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_is_periodic_cmd_mode':
>> drivers/gpu/drm/i915/display/icl_dsi.c:1319:1: warning: control reaches end of non-void function [-Wreturn-type]
    }
    ^
   cc1: some warnings being treated as errors

vim +1319 drivers/gpu/drm/i915/display/icl_dsi.c

  1305	
  1306	bool gen11_dsi_is_periodic_cmd_mode(struct drm_i915_private *dev_priv,
  1307					    struct intel_dsi *intel_dsi)
  1308	{
  1309		u32 val;
  1310		enum transcoder dsi_trans;
  1311	
  1312		if (intel_dsi->ports == BIT(PORT_B))
  1313			dsi_trans = TRANSCODER_DSI_1;
  1314		else
  1315			dsi_trans = TRANSCODER_DSI_0;
  1316	
  1317		val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
  1318		return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE);
> 1319	}
  1320	
  1321	static void gen11_dsi_get_config(struct intel_encoder *encoder,
  1322					 struct intel_crtc_state *pipe_config)
  1323	{
  1324		struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  1325		struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
  1326		struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
  1327	
  1328		/* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
  1329		pipe_config->port_clock =
  1330			cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state);
  1331	
  1332		pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
  1333		if (intel_dsi->dual_link)
  1334			pipe_config->base.adjusted_mode.crtc_clock *= 2;
  1335	
  1336		gen11_dsi_get_timings(encoder, pipe_config);
  1337		pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
  1338		pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
  1339	
  1340		if (gen11_dsi_is_periodic_cmd_mode(dev_priv, intel_dsi))
> 1341			pipe_config->hw.adjusted_mode.private_flags |=
  1342						I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
  1343	}
  1344	

---
0-DAY kernel test infrastructure                 Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org Intel Corporation

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[-- Attachment #3: Type: text/plain, Size: 159 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [V3 4/8] drm/i915/dsi: Add check for periodic command mode

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 9112 bytes --]

Hi Vandita,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[cannot apply to v5.4-rc8 next-20191118]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Vandita-Kulkarni/Add-support-for-mipi-dsi-cmd-mode/20191120-015713
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-defconfig (attached as .config)
compiler: gcc-7 (Debian 7.4.0-14) 7.4.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_configure_transcoder':
   drivers/gpu/drm/i915/display/icl_dsi.c:718:11: error: 'TE_SOURCE_GPIO' undeclared (first use in this function); did you mean 'DP_SOURCE_OUI'?
       tmp |= TE_SOURCE_GPIO;
              ^~~~~~~~~~~~~~
              DP_SOURCE_OUI
   drivers/gpu/drm/i915/display/icl_dsi.c:718:11: note: each undeclared identifier is reported only once for each function it appears in
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_config_util_pin':
   drivers/gpu/drm/i915/display/icl_dsi.c:999:10: error: 'UTIL_PIN_DIRECTION_INPUT' undeclared (first use in this function); did you mean 'UTIL_PIN_PIPE_MASK'?
      tmp |= UTIL_PIN_DIRECTION_INPUT;
             ^~~~~~~~~~~~~~~~~~~~~~~~
             UTIL_PIN_PIPE_MASK
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_deconfigure_trancoder':
   drivers/gpu/drm/i915/display/icl_dsi.c:1164:20: error: implicit declaration of function 'DSI_CMD_FRMCTL'; did you mean 'DSI_CMD_RXCTL'? [-Werror=implicit-function-declaration]
       tmp = I915_READ(DSI_CMD_FRMCTL(port));
                       ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:1164:10: note: in expansion of macro 'I915_READ'
       tmp = I915_READ(DSI_CMD_FRMCTL(port));
             ^~~~~~~~~
   drivers/gpu/drm/i915/i915_drv.h:1981:57: error: incompatible type for argument 2 of 'intel_uncore_read'
    #define I915_READ(reg__)  __I915_REG_OP(read, dev_priv, (reg__))
                                                            ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:1164:10: note: in expansion of macro 'I915_READ'
       tmp = I915_READ(DSI_CMD_FRMCTL(port));
             ^~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/intel_uncore.h:287:22: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
                         ^
   drivers/gpu/drm/i915/intel_uncore.h:302:1: note: in expansion of macro '__uncore_read'
    __uncore_read(read, 32, l, true)
    ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:1165:12: error: 'DSI_PERIODIC_FRAME_UPDATE_ENABLE' undeclared (first use in this function); did you mean 'GEN6_MBCTL_BME_UPDATE_ENABLE'?
       tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE;
               ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
               GEN6_MBCTL_BME_UPDATE_ENABLE
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/i915_drv.h:1982:65: error: incompatible type for argument 2 of 'intel_uncore_write'
    #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
                                                                    ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:1166:4: note: in expansion of macro 'I915_WRITE'
       I915_WRITE(DSI_CMD_FRMCTL(port), tmp);
       ^~~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/intel_uncore.h:294:20: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline void intel_uncore_##name__(struct intel_uncore *uncore, \
                       ^
   drivers/gpu/drm/i915/intel_uncore.h:308:1: note: in expansion of macro '__uncore_write'
    __uncore_write(write, 32, l, true)
    ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_is_periodic_cmd_mode':
   drivers/gpu/drm/i915/display/icl_dsi.c:1318:16: error: 'DSI_PERIODIC_FRAME_UPDATE_ENABLE' undeclared (first use in this function); did you mean 'GEN6_MBCTL_BME_UPDATE_ENABLE'?
     return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE);
                   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                   GEN6_MBCTL_BME_UPDATE_ENABLE
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_get_config':
   drivers/gpu/drm/i915/display/icl_dsi.c:1341:14: error: 'struct intel_crtc_state' has no member named 'hw'
      pipe_config->hw.adjusted_mode.private_flags |=
                 ^~
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_compute_config':
   drivers/gpu/drm/i915/display/icl_dsi.c:1374:13: error: 'struct intel_crtc_state' has no member named 'hw'
     pipe_config->hw.adjusted_mode.private_flags &=
                ^~
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_is_periodic_cmd_mode':
>> drivers/gpu/drm/i915/display/icl_dsi.c:1319:1: warning: control reaches end of non-void function [-Wreturn-type]
    }
    ^
   cc1: some warnings being treated as errors

vim +1319 drivers/gpu/drm/i915/display/icl_dsi.c

  1305	
  1306	bool gen11_dsi_is_periodic_cmd_mode(struct drm_i915_private *dev_priv,
  1307					    struct intel_dsi *intel_dsi)
  1308	{
  1309		u32 val;
  1310		enum transcoder dsi_trans;
  1311	
  1312		if (intel_dsi->ports == BIT(PORT_B))
  1313			dsi_trans = TRANSCODER_DSI_1;
  1314		else
  1315			dsi_trans = TRANSCODER_DSI_0;
  1316	
  1317		val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
  1318		return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE);
> 1319	}
  1320	
  1321	static void gen11_dsi_get_config(struct intel_encoder *encoder,
  1322					 struct intel_crtc_state *pipe_config)
  1323	{
  1324		struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  1325		struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
  1326		struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
  1327	
  1328		/* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
  1329		pipe_config->port_clock =
  1330			cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state);
  1331	
  1332		pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
  1333		if (intel_dsi->dual_link)
  1334			pipe_config->base.adjusted_mode.crtc_clock *= 2;
  1335	
  1336		gen11_dsi_get_timings(encoder, pipe_config);
  1337		pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
  1338		pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
  1339	
  1340		if (gen11_dsi_is_periodic_cmd_mode(dev_priv, intel_dsi))
> 1341			pipe_config->hw.adjusted_mode.private_flags |=
  1342						I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
  1343	}
  1344	

---
0-DAY kernel test infrastructure                 Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org Intel Corporation

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[-- Attachment #3: Type: text/plain, Size: 159 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [V3 4/8] drm/i915/dsi: Add check for periodic command mode

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 9277 bytes --]

Hi Vandita,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[cannot apply to v5.4-rc8 next-20191118]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Vandita-Kulkarni/Add-support-for-mipi-dsi-cmd-mode/20191120-015713
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-defconfig (attached as .config)
compiler: gcc-7 (Debian 7.4.0-14) 7.4.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_configure_transcoder':
   drivers/gpu/drm/i915/display/icl_dsi.c:718:11: error: 'TE_SOURCE_GPIO' undeclared (first use in this function); did you mean 'DP_SOURCE_OUI'?
       tmp |= TE_SOURCE_GPIO;
              ^~~~~~~~~~~~~~
              DP_SOURCE_OUI
   drivers/gpu/drm/i915/display/icl_dsi.c:718:11: note: each undeclared identifier is reported only once for each function it appears in
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_config_util_pin':
   drivers/gpu/drm/i915/display/icl_dsi.c:999:10: error: 'UTIL_PIN_DIRECTION_INPUT' undeclared (first use in this function); did you mean 'UTIL_PIN_PIPE_MASK'?
      tmp |= UTIL_PIN_DIRECTION_INPUT;
             ^~~~~~~~~~~~~~~~~~~~~~~~
             UTIL_PIN_PIPE_MASK
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_deconfigure_trancoder':
   drivers/gpu/drm/i915/display/icl_dsi.c:1164:20: error: implicit declaration of function 'DSI_CMD_FRMCTL'; did you mean 'DSI_CMD_RXCTL'? [-Werror=implicit-function-declaration]
       tmp = I915_READ(DSI_CMD_FRMCTL(port));
                       ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:1164:10: note: in expansion of macro 'I915_READ'
       tmp = I915_READ(DSI_CMD_FRMCTL(port));
             ^~~~~~~~~
   drivers/gpu/drm/i915/i915_drv.h:1981:57: error: incompatible type for argument 2 of 'intel_uncore_read'
    #define I915_READ(reg__)  __I915_REG_OP(read, dev_priv, (reg__))
                                                            ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:1164:10: note: in expansion of macro 'I915_READ'
       tmp = I915_READ(DSI_CMD_FRMCTL(port));
             ^~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/intel_uncore.h:287:22: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
                         ^
   drivers/gpu/drm/i915/intel_uncore.h:302:1: note: in expansion of macro '__uncore_read'
    __uncore_read(read, 32, l, true)
    ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:1165:12: error: 'DSI_PERIODIC_FRAME_UPDATE_ENABLE' undeclared (first use in this function); did you mean 'GEN6_MBCTL_BME_UPDATE_ENABLE'?
       tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE;
               ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
               GEN6_MBCTL_BME_UPDATE_ENABLE
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/i915_drv.h:1982:65: error: incompatible type for argument 2 of 'intel_uncore_write'
    #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
                                                                    ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:1166:4: note: in expansion of macro 'I915_WRITE'
       I915_WRITE(DSI_CMD_FRMCTL(port), tmp);
       ^~~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/intel_uncore.h:294:20: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline void intel_uncore_##name__(struct intel_uncore *uncore, \
                       ^
   drivers/gpu/drm/i915/intel_uncore.h:308:1: note: in expansion of macro '__uncore_write'
    __uncore_write(write, 32, l, true)
    ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_is_periodic_cmd_mode':
   drivers/gpu/drm/i915/display/icl_dsi.c:1318:16: error: 'DSI_PERIODIC_FRAME_UPDATE_ENABLE' undeclared (first use in this function); did you mean 'GEN6_MBCTL_BME_UPDATE_ENABLE'?
     return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE);
                   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                   GEN6_MBCTL_BME_UPDATE_ENABLE
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_get_config':
   drivers/gpu/drm/i915/display/icl_dsi.c:1341:14: error: 'struct intel_crtc_state' has no member named 'hw'
      pipe_config->hw.adjusted_mode.private_flags |=
                 ^~
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_compute_config':
   drivers/gpu/drm/i915/display/icl_dsi.c:1374:13: error: 'struct intel_crtc_state' has no member named 'hw'
     pipe_config->hw.adjusted_mode.private_flags &=
                ^~
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_is_periodic_cmd_mode':
>> drivers/gpu/drm/i915/display/icl_dsi.c:1319:1: warning: control reaches end of non-void function [-Wreturn-type]
    }
    ^
   cc1: some warnings being treated as errors

vim +1319 drivers/gpu/drm/i915/display/icl_dsi.c

  1305	
  1306	bool gen11_dsi_is_periodic_cmd_mode(struct drm_i915_private *dev_priv,
  1307					    struct intel_dsi *intel_dsi)
  1308	{
  1309		u32 val;
  1310		enum transcoder dsi_trans;
  1311	
  1312		if (intel_dsi->ports == BIT(PORT_B))
  1313			dsi_trans = TRANSCODER_DSI_1;
  1314		else
  1315			dsi_trans = TRANSCODER_DSI_0;
  1316	
  1317		val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
  1318		return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE);
> 1319	}
  1320	
  1321	static void gen11_dsi_get_config(struct intel_encoder *encoder,
  1322					 struct intel_crtc_state *pipe_config)
  1323	{
  1324		struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  1325		struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
  1326		struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
  1327	
  1328		/* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
  1329		pipe_config->port_clock =
  1330			cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state);
  1331	
  1332		pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
  1333		if (intel_dsi->dual_link)
  1334			pipe_config->base.adjusted_mode.crtc_clock *= 2;
  1335	
  1336		gen11_dsi_get_timings(encoder, pipe_config);
  1337		pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
  1338		pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
  1339	
  1340		if (gen11_dsi_is_periodic_cmd_mode(dev_priv, intel_dsi))
> 1341			pipe_config->hw.adjusted_mode.private_flags |=
  1342						I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
  1343	}
  1344	

---
0-DAY kernel test infrastructure                 Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org Intel Corporation

[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 28187 bytes --]

Re: [V3 6/8] drm/i915/dsi: Configure TE interrupt for cmd mode

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 6485 bytes --]

Hi Vandita,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v5.4-rc8 next-20191118]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Vandita-Kulkarni/Add-support-for-mipi-dsi-cmd-mode/20191120-015713
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-defconfig (attached as .config)
compiler: gcc-7 (Debian 7.4.0-14) 7.4.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All error/warnings (new ones prefixed by >>):

   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
   drivers/gpu/drm/i915/i915_irq.c: In function 'gen11_dsi_configure_te':
>> drivers/gpu/drm/i915/i915_irq.c:2590:19: error: implicit declaration of function 'DSI_INTR_MASK_REG'; did you mean 'TSFS_INTR_MASK'? [-Werror=implicit-function-declaration]
     tmp =  I915_READ(DSI_INTR_MASK_REG(port));
                      ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
>> drivers/gpu/drm/i915/i915_irq.c:2590:9: note: in expansion of macro 'I915_READ'
     tmp =  I915_READ(DSI_INTR_MASK_REG(port));
            ^~~~~~~~~
   drivers/gpu/drm/i915/i915_drv.h:1981:57: error: incompatible type for argument 2 of 'intel_uncore_read'
    #define I915_READ(reg__)  __I915_REG_OP(read, dev_priv, (reg__))
                                                            ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
>> drivers/gpu/drm/i915/i915_irq.c:2590:9: note: in expansion of macro 'I915_READ'
     tmp =  I915_READ(DSI_INTR_MASK_REG(port));
            ^~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
   drivers/gpu/drm/i915/intel_uncore.h:287:22: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
                         ^
   drivers/gpu/drm/i915/intel_uncore.h:302:1: note: in expansion of macro '__uncore_read'
    __uncore_read(read, 32, l, true)
    ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/i915_irq.c:2592:11: error: 'DSI_TE_EVENT' undeclared (first use in this function); did you mean 'DEFINE_EVENT'?
      tmp &= ~DSI_TE_EVENT;
              ^~~~~~~~~~~~
              DEFINE_EVENT
   drivers/gpu/drm/i915/i915_irq.c:2592:11: note: each undeclared identifier is reported only once for each function it appears in
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
   drivers/gpu/drm/i915/i915_drv.h:1982:65: error: incompatible type for argument 2 of 'intel_uncore_write'
    #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
                                                                    ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
>> drivers/gpu/drm/i915/i915_irq.c:2596:2: note: in expansion of macro 'I915_WRITE'
     I915_WRITE(DSI_INTR_MASK_REG(port), tmp);
     ^~~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
   drivers/gpu/drm/i915/intel_uncore.h:294:20: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline void intel_uncore_##name__(struct intel_uncore *uncore, \
                       ^
   drivers/gpu/drm/i915/intel_uncore.h:308:1: note: in expansion of macro '__uncore_write'
    __uncore_write(write, 32, l, true)
    ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_irq.c: In function 'gen8_de_irq_postinstall':
>> drivers/gpu/drm/i915/i915_irq.c:3401:22: error: 'DSI0_TE' undeclared (first use in this function)
       de_port_masked |= DSI0_TE | DSI1_TE;
                         ^~~~~~~
>> drivers/gpu/drm/i915/i915_irq.c:3401:32: error: 'DSI1_TE' undeclared (first use in this function); did you mean 'DSI0_TE'?
       de_port_masked |= DSI0_TE | DSI1_TE;
                                   ^~~~~~~
                                   DSI0_TE
   cc1: some warnings being treated as errors

vim +2590 drivers/gpu/drm/i915/i915_irq.c

  2574	
  2575	static bool gen11_dsi_configure_te(struct drm_i915_private *dev_priv,
  2576					   struct drm_display_mode *mode, bool enable)
  2577	{
  2578		enum port port;
  2579		u32 tmp;
  2580	
  2581		if (!(mode->private_flags &
  2582		    (I915_MODE_FLAG_DSI_USE_TE1 | I915_MODE_FLAG_DSI_USE_TE0)))
  2583			return false;
  2584	
  2585		if (mode->private_flags & I915_MODE_FLAG_DSI_USE_TE1)
  2586			port = PORT_B;
  2587		else
  2588			port = PORT_A;
  2589	
> 2590		tmp =  I915_READ(DSI_INTR_MASK_REG(port));
  2591		if (enable)
> 2592			tmp &= ~DSI_TE_EVENT;
  2593		else
  2594			tmp |= DSI_TE_EVENT;
  2595	
> 2596		I915_WRITE(DSI_INTR_MASK_REG(port), tmp);
  2597		return true;
  2598	}
  2599	

---
0-DAY kernel test infrastructure                 Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org Intel Corporation

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [V3 6/8] drm/i915/dsi: Configure TE interrupt for cmd mode

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 6485 bytes --]

Hi Vandita,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v5.4-rc8 next-20191118]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Vandita-Kulkarni/Add-support-for-mipi-dsi-cmd-mode/20191120-015713
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-defconfig (attached as .config)
compiler: gcc-7 (Debian 7.4.0-14) 7.4.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All error/warnings (new ones prefixed by >>):

   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
   drivers/gpu/drm/i915/i915_irq.c: In function 'gen11_dsi_configure_te':
>> drivers/gpu/drm/i915/i915_irq.c:2590:19: error: implicit declaration of function 'DSI_INTR_MASK_REG'; did you mean 'TSFS_INTR_MASK'? [-Werror=implicit-function-declaration]
     tmp =  I915_READ(DSI_INTR_MASK_REG(port));
                      ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
>> drivers/gpu/drm/i915/i915_irq.c:2590:9: note: in expansion of macro 'I915_READ'
     tmp =  I915_READ(DSI_INTR_MASK_REG(port));
            ^~~~~~~~~
   drivers/gpu/drm/i915/i915_drv.h:1981:57: error: incompatible type for argument 2 of 'intel_uncore_read'
    #define I915_READ(reg__)  __I915_REG_OP(read, dev_priv, (reg__))
                                                            ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
>> drivers/gpu/drm/i915/i915_irq.c:2590:9: note: in expansion of macro 'I915_READ'
     tmp =  I915_READ(DSI_INTR_MASK_REG(port));
            ^~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
   drivers/gpu/drm/i915/intel_uncore.h:287:22: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
                         ^
   drivers/gpu/drm/i915/intel_uncore.h:302:1: note: in expansion of macro '__uncore_read'
    __uncore_read(read, 32, l, true)
    ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/i915_irq.c:2592:11: error: 'DSI_TE_EVENT' undeclared (first use in this function); did you mean 'DEFINE_EVENT'?
      tmp &= ~DSI_TE_EVENT;
              ^~~~~~~~~~~~
              DEFINE_EVENT
   drivers/gpu/drm/i915/i915_irq.c:2592:11: note: each undeclared identifier is reported only once for each function it appears in
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
   drivers/gpu/drm/i915/i915_drv.h:1982:65: error: incompatible type for argument 2 of 'intel_uncore_write'
    #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
                                                                    ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
>> drivers/gpu/drm/i915/i915_irq.c:2596:2: note: in expansion of macro 'I915_WRITE'
     I915_WRITE(DSI_INTR_MASK_REG(port), tmp);
     ^~~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
   drivers/gpu/drm/i915/intel_uncore.h:294:20: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline void intel_uncore_##name__(struct intel_uncore *uncore, \
                       ^
   drivers/gpu/drm/i915/intel_uncore.h:308:1: note: in expansion of macro '__uncore_write'
    __uncore_write(write, 32, l, true)
    ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_irq.c: In function 'gen8_de_irq_postinstall':
>> drivers/gpu/drm/i915/i915_irq.c:3401:22: error: 'DSI0_TE' undeclared (first use in this function)
       de_port_masked |= DSI0_TE | DSI1_TE;
                         ^~~~~~~
>> drivers/gpu/drm/i915/i915_irq.c:3401:32: error: 'DSI1_TE' undeclared (first use in this function); did you mean 'DSI0_TE'?
       de_port_masked |= DSI0_TE | DSI1_TE;
                                   ^~~~~~~
                                   DSI0_TE
   cc1: some warnings being treated as errors

vim +2590 drivers/gpu/drm/i915/i915_irq.c

  2574	
  2575	static bool gen11_dsi_configure_te(struct drm_i915_private *dev_priv,
  2576					   struct drm_display_mode *mode, bool enable)
  2577	{
  2578		enum port port;
  2579		u32 tmp;
  2580	
  2581		if (!(mode->private_flags &
  2582		    (I915_MODE_FLAG_DSI_USE_TE1 | I915_MODE_FLAG_DSI_USE_TE0)))
  2583			return false;
  2584	
  2585		if (mode->private_flags & I915_MODE_FLAG_DSI_USE_TE1)
  2586			port = PORT_B;
  2587		else
  2588			port = PORT_A;
  2589	
> 2590		tmp =  I915_READ(DSI_INTR_MASK_REG(port));
  2591		if (enable)
> 2592			tmp &= ~DSI_TE_EVENT;
  2593		else
  2594			tmp |= DSI_TE_EVENT;
  2595	
> 2596		I915_WRITE(DSI_INTR_MASK_REG(port), tmp);
  2597		return true;
  2598	}
  2599	

---
0-DAY kernel test infrastructure                 Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org Intel Corporation

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [V3 6/8] drm/i915/dsi: Configure TE interrupt for cmd mode

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 6613 bytes --]

Hi Vandita,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v5.4-rc8 next-20191118]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Vandita-Kulkarni/Add-support-for-mipi-dsi-cmd-mode/20191120-015713
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-defconfig (attached as .config)
compiler: gcc-7 (Debian 7.4.0-14) 7.4.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All error/warnings (new ones prefixed by >>):

   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
   drivers/gpu/drm/i915/i915_irq.c: In function 'gen11_dsi_configure_te':
>> drivers/gpu/drm/i915/i915_irq.c:2590:19: error: implicit declaration of function 'DSI_INTR_MASK_REG'; did you mean 'TSFS_INTR_MASK'? [-Werror=implicit-function-declaration]
     tmp =  I915_READ(DSI_INTR_MASK_REG(port));
                      ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
>> drivers/gpu/drm/i915/i915_irq.c:2590:9: note: in expansion of macro 'I915_READ'
     tmp =  I915_READ(DSI_INTR_MASK_REG(port));
            ^~~~~~~~~
   drivers/gpu/drm/i915/i915_drv.h:1981:57: error: incompatible type for argument 2 of 'intel_uncore_read'
    #define I915_READ(reg__)  __I915_REG_OP(read, dev_priv, (reg__))
                                                            ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
>> drivers/gpu/drm/i915/i915_irq.c:2590:9: note: in expansion of macro 'I915_READ'
     tmp =  I915_READ(DSI_INTR_MASK_REG(port));
            ^~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
   drivers/gpu/drm/i915/intel_uncore.h:287:22: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
                         ^
   drivers/gpu/drm/i915/intel_uncore.h:302:1: note: in expansion of macro '__uncore_read'
    __uncore_read(read, 32, l, true)
    ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/i915_irq.c:2592:11: error: 'DSI_TE_EVENT' undeclared (first use in this function); did you mean 'DEFINE_EVENT'?
      tmp &= ~DSI_TE_EVENT;
              ^~~~~~~~~~~~
              DEFINE_EVENT
   drivers/gpu/drm/i915/i915_irq.c:2592:11: note: each undeclared identifier is reported only once for each function it appears in
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
   drivers/gpu/drm/i915/i915_drv.h:1982:65: error: incompatible type for argument 2 of 'intel_uncore_write'
    #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
                                                                    ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
>> drivers/gpu/drm/i915/i915_irq.c:2596:2: note: in expansion of macro 'I915_WRITE'
     I915_WRITE(DSI_INTR_MASK_REG(port), tmp);
     ^~~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
   drivers/gpu/drm/i915/intel_uncore.h:294:20: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline void intel_uncore_##name__(struct intel_uncore *uncore, \
                       ^
   drivers/gpu/drm/i915/intel_uncore.h:308:1: note: in expansion of macro '__uncore_write'
    __uncore_write(write, 32, l, true)
    ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_irq.c: In function 'gen8_de_irq_postinstall':
>> drivers/gpu/drm/i915/i915_irq.c:3401:22: error: 'DSI0_TE' undeclared (first use in this function)
       de_port_masked |= DSI0_TE | DSI1_TE;
                         ^~~~~~~
>> drivers/gpu/drm/i915/i915_irq.c:3401:32: error: 'DSI1_TE' undeclared (first use in this function); did you mean 'DSI0_TE'?
       de_port_masked |= DSI0_TE | DSI1_TE;
                                   ^~~~~~~
                                   DSI0_TE
   cc1: some warnings being treated as errors

vim +2590 drivers/gpu/drm/i915/i915_irq.c

  2574	
  2575	static bool gen11_dsi_configure_te(struct drm_i915_private *dev_priv,
  2576					   struct drm_display_mode *mode, bool enable)
  2577	{
  2578		enum port port;
  2579		u32 tmp;
  2580	
  2581		if (!(mode->private_flags &
  2582		    (I915_MODE_FLAG_DSI_USE_TE1 | I915_MODE_FLAG_DSI_USE_TE0)))
  2583			return false;
  2584	
  2585		if (mode->private_flags & I915_MODE_FLAG_DSI_USE_TE1)
  2586			port = PORT_B;
  2587		else
  2588			port = PORT_A;
  2589	
> 2590		tmp =  I915_READ(DSI_INTR_MASK_REG(port));
  2591		if (enable)
> 2592			tmp &= ~DSI_TE_EVENT;
  2593		else
  2594			tmp |= DSI_TE_EVENT;
  2595	
> 2596		I915_WRITE(DSI_INTR_MASK_REG(port), tmp);
  2597		return true;
  2598	}
  2599	

---
0-DAY kernel test infrastructure                 Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org Intel Corporation

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Re: [V3 7/8] drm/i915/dsi: Add TE handler for dsi cmd mode.

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 10569 bytes --]

Hi Vandita,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v5.4-rc8 next-20191118]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Vandita-Kulkarni/Add-support-for-mipi-dsi-cmd-mode/20191120-015713
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-defconfig (attached as .config)
compiler: gcc-7 (Debian 7.4.0-14) 7.4.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/i915_irq.c: In function 'gen11_dsi_te_interrupt_handler':
>> drivers/gpu/drm/i915/i915_irq.c:2252:24: error: 'DSI1_TE' undeclared (first use in this function)
     port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ?
                           ^~~~~~~
   drivers/gpu/drm/i915/i915_irq.c:2252:24: note: each undeclared identifier is reported only once for each function it appears in
>> drivers/gpu/drm/i915/i915_irq.c:2252:57: error: 'DSI0_TE' undeclared (first use in this function); did you mean 'DSI1_TE'?
     port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ?
                                                            ^~~~~~~
                                                            DSI1_TE
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
>> drivers/gpu/drm/i915/i915_irq.c:2283:18: error: implicit declaration of function 'DSI_INTR_IDENT_REG'; did you mean 'GEN11_INTR_IDENTITY_REG'? [-Werror=implicit-function-declaration]
     tmp = I915_READ(DSI_INTR_IDENT_REG(port));
                     ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/i915_irq.c:2283:8: note: in expansion of macro 'I915_READ'
     tmp = I915_READ(DSI_INTR_IDENT_REG(port));
           ^~~~~~~~~
   drivers/gpu/drm/i915/i915_drv.h:1981:57: error: incompatible type for argument 2 of 'intel_uncore_read'
    #define I915_READ(reg__)  __I915_REG_OP(read, dev_priv, (reg__))
                                                            ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/i915_irq.c:2283:8: note: in expansion of macro 'I915_READ'
     tmp = I915_READ(DSI_INTR_IDENT_REG(port));
           ^~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
   drivers/gpu/drm/i915/intel_uncore.h:287:22: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
                         ^
   drivers/gpu/drm/i915/intel_uncore.h:302:1: note: in expansion of macro '__uncore_read'
    __uncore_read(read, 32, l, true)
    ^~~~~~~~~~~~~
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
   drivers/gpu/drm/i915/i915_drv.h:1982:65: error: incompatible type for argument 2 of 'intel_uncore_write'
    #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
                                                                    ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/i915_irq.c:2284:2: note: in expansion of macro 'I915_WRITE'
     I915_WRITE(DSI_INTR_IDENT_REG(port), tmp);
     ^~~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
   drivers/gpu/drm/i915/intel_uncore.h:294:20: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline void intel_uncore_##name__(struct intel_uncore *uncore, \
                       ^
   drivers/gpu/drm/i915/intel_uncore.h:308:1: note: in expansion of macro '__uncore_write'
    __uncore_write(write, 32, l, true)
    ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_irq.c: In function 'gen8_de_irq_handler':
   drivers/gpu/drm/i915/i915_irq.c:2354:23: error: 'DSI0_TE' undeclared (first use in this function)
        tmp_mask = iir & (DSI0_TE | DSI1_TE);
                          ^~~~~~~
   drivers/gpu/drm/i915/i915_irq.c:2354:33: error: 'DSI1_TE' undeclared (first use in this function); did you mean 'DSI0_TE'?
        tmp_mask = iir & (DSI0_TE | DSI1_TE);
                                    ^~~~~~~
                                    DSI0_TE
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
   drivers/gpu/drm/i915/i915_irq.c: In function 'gen11_dsi_configure_te':
   drivers/gpu/drm/i915/i915_irq.c:2654:19: error: implicit declaration of function 'DSI_INTR_MASK_REG'; did you mean 'TSFS_INTR_MASK'? [-Werror=implicit-function-declaration]
     tmp =  I915_READ(DSI_INTR_MASK_REG(port));
                      ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/i915_irq.c:2654:9: note: in expansion of macro 'I915_READ'
     tmp =  I915_READ(DSI_INTR_MASK_REG(port));
            ^~~~~~~~~
   drivers/gpu/drm/i915/i915_drv.h:1981:57: error: incompatible type for argument 2 of 'intel_uncore_read'
    #define I915_READ(reg__)  __I915_REG_OP(read, dev_priv, (reg__))
                                                            ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/i915_irq.c:2654:9: note: in expansion of macro 'I915_READ'
     tmp =  I915_READ(DSI_INTR_MASK_REG(port));
            ^~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
   drivers/gpu/drm/i915/intel_uncore.h:287:22: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
                         ^
   drivers/gpu/drm/i915/intel_uncore.h:302:1: note: in expansion of macro '__uncore_read'
    __uncore_read(read, 32, l, true)
    ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_irq.c:2656:11: error: 'DSI_TE_EVENT' undeclared (first use in this function); did you mean 'DEFINE_EVENT'?
      tmp &= ~DSI_TE_EVENT;
              ^~~~~~~~~~~~
              DEFINE_EVENT
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
   drivers/gpu/drm/i915/i915_drv.h:1982:65: error: incompatible type for argument 2 of 'intel_uncore_write'

vim +/DSI1_TE +2252 drivers/gpu/drm/i915/i915_irq.c

  2232	
  2233	void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
  2234					    u32 te_trigger)
  2235	{
  2236		enum pipe pipe = INVALID_PIPE;
  2237		enum transcoder dsi_trans;
  2238		enum port port;
  2239		u32 val, tmp;
  2240	
  2241		/*
  2242		 * Incase of dual link, TE comes from DSI_1
  2243		 * this is to check if dual link is enabled
  2244		 */
  2245		val = I915_READ(TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0));
  2246		val &= PORT_SYNC_MODE_ENABLE;
  2247	
  2248		/*
  2249		 * if dual link is enabled, then read DSI_0
  2250		 * transcoder registers
  2251		 */
> 2252		port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ?
  2253							  PORT_A : PORT_B;
  2254		dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1;
  2255	
  2256		/* Check if DSI configured in command mode */
  2257		val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
  2258		val = (val & OP_MODE_MASK) >> 28;
  2259	
  2260		if (val) {
  2261			DRM_ERROR("DSI trancoder not configured in command mode\n");
  2262			return;
  2263		}
  2264	
  2265		/* Get PIPE for handling VBLANK event */
  2266		val = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
  2267		switch (val & TRANS_DDI_EDP_INPUT_MASK) {
  2268		case TRANS_DDI_EDP_INPUT_A_ON:
  2269			pipe = PIPE_A;
  2270			break;
  2271		case TRANS_DDI_EDP_INPUT_B_ONOFF:
  2272			pipe = PIPE_B;
  2273			break;
  2274		case TRANS_DDI_EDP_INPUT_C_ONOFF:
  2275			pipe = PIPE_C;
  2276			break;
  2277		default:
  2278			DRM_ERROR("Invalid PIPE\n");
  2279		}
  2280	
  2281		/* clear TE in dsi IIR */
  2282		port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A;
> 2283		tmp = I915_READ(DSI_INTR_IDENT_REG(port));
  2284		I915_WRITE(DSI_INTR_IDENT_REG(port), tmp);
  2285	
  2286		drm_handle_vblank(&dev_priv->drm, pipe);
  2287	}
  2288	

---
0-DAY kernel test infrastructure                 Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 28187 bytes --]

[-- Attachment #3: Type: text/plain, Size: 159 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [V3 7/8] drm/i915/dsi: Add TE handler for dsi cmd mode.

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 10569 bytes --]

Hi Vandita,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v5.4-rc8 next-20191118]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Vandita-Kulkarni/Add-support-for-mipi-dsi-cmd-mode/20191120-015713
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-defconfig (attached as .config)
compiler: gcc-7 (Debian 7.4.0-14) 7.4.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/i915_irq.c: In function 'gen11_dsi_te_interrupt_handler':
>> drivers/gpu/drm/i915/i915_irq.c:2252:24: error: 'DSI1_TE' undeclared (first use in this function)
     port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ?
                           ^~~~~~~
   drivers/gpu/drm/i915/i915_irq.c:2252:24: note: each undeclared identifier is reported only once for each function it appears in
>> drivers/gpu/drm/i915/i915_irq.c:2252:57: error: 'DSI0_TE' undeclared (first use in this function); did you mean 'DSI1_TE'?
     port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ?
                                                            ^~~~~~~
                                                            DSI1_TE
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
>> drivers/gpu/drm/i915/i915_irq.c:2283:18: error: implicit declaration of function 'DSI_INTR_IDENT_REG'; did you mean 'GEN11_INTR_IDENTITY_REG'? [-Werror=implicit-function-declaration]
     tmp = I915_READ(DSI_INTR_IDENT_REG(port));
                     ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/i915_irq.c:2283:8: note: in expansion of macro 'I915_READ'
     tmp = I915_READ(DSI_INTR_IDENT_REG(port));
           ^~~~~~~~~
   drivers/gpu/drm/i915/i915_drv.h:1981:57: error: incompatible type for argument 2 of 'intel_uncore_read'
    #define I915_READ(reg__)  __I915_REG_OP(read, dev_priv, (reg__))
                                                            ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/i915_irq.c:2283:8: note: in expansion of macro 'I915_READ'
     tmp = I915_READ(DSI_INTR_IDENT_REG(port));
           ^~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
   drivers/gpu/drm/i915/intel_uncore.h:287:22: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
                         ^
   drivers/gpu/drm/i915/intel_uncore.h:302:1: note: in expansion of macro '__uncore_read'
    __uncore_read(read, 32, l, true)
    ^~~~~~~~~~~~~
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
   drivers/gpu/drm/i915/i915_drv.h:1982:65: error: incompatible type for argument 2 of 'intel_uncore_write'
    #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
                                                                    ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/i915_irq.c:2284:2: note: in expansion of macro 'I915_WRITE'
     I915_WRITE(DSI_INTR_IDENT_REG(port), tmp);
     ^~~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
   drivers/gpu/drm/i915/intel_uncore.h:294:20: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline void intel_uncore_##name__(struct intel_uncore *uncore, \
                       ^
   drivers/gpu/drm/i915/intel_uncore.h:308:1: note: in expansion of macro '__uncore_write'
    __uncore_write(write, 32, l, true)
    ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_irq.c: In function 'gen8_de_irq_handler':
   drivers/gpu/drm/i915/i915_irq.c:2354:23: error: 'DSI0_TE' undeclared (first use in this function)
        tmp_mask = iir & (DSI0_TE | DSI1_TE);
                          ^~~~~~~
   drivers/gpu/drm/i915/i915_irq.c:2354:33: error: 'DSI1_TE' undeclared (first use in this function); did you mean 'DSI0_TE'?
        tmp_mask = iir & (DSI0_TE | DSI1_TE);
                                    ^~~~~~~
                                    DSI0_TE
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
   drivers/gpu/drm/i915/i915_irq.c: In function 'gen11_dsi_configure_te':
   drivers/gpu/drm/i915/i915_irq.c:2654:19: error: implicit declaration of function 'DSI_INTR_MASK_REG'; did you mean 'TSFS_INTR_MASK'? [-Werror=implicit-function-declaration]
     tmp =  I915_READ(DSI_INTR_MASK_REG(port));
                      ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/i915_irq.c:2654:9: note: in expansion of macro 'I915_READ'
     tmp =  I915_READ(DSI_INTR_MASK_REG(port));
            ^~~~~~~~~
   drivers/gpu/drm/i915/i915_drv.h:1981:57: error: incompatible type for argument 2 of 'intel_uncore_read'
    #define I915_READ(reg__)  __I915_REG_OP(read, dev_priv, (reg__))
                                                            ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/i915_irq.c:2654:9: note: in expansion of macro 'I915_READ'
     tmp =  I915_READ(DSI_INTR_MASK_REG(port));
            ^~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
   drivers/gpu/drm/i915/intel_uncore.h:287:22: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
                         ^
   drivers/gpu/drm/i915/intel_uncore.h:302:1: note: in expansion of macro '__uncore_read'
    __uncore_read(read, 32, l, true)
    ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_irq.c:2656:11: error: 'DSI_TE_EVENT' undeclared (first use in this function); did you mean 'DEFINE_EVENT'?
      tmp &= ~DSI_TE_EVENT;
              ^~~~~~~~~~~~
              DEFINE_EVENT
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
   drivers/gpu/drm/i915/i915_drv.h:1982:65: error: incompatible type for argument 2 of 'intel_uncore_write'

vim +/DSI1_TE +2252 drivers/gpu/drm/i915/i915_irq.c

  2232	
  2233	void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
  2234					    u32 te_trigger)
  2235	{
  2236		enum pipe pipe = INVALID_PIPE;
  2237		enum transcoder dsi_trans;
  2238		enum port port;
  2239		u32 val, tmp;
  2240	
  2241		/*
  2242		 * Incase of dual link, TE comes from DSI_1
  2243		 * this is to check if dual link is enabled
  2244		 */
  2245		val = I915_READ(TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0));
  2246		val &= PORT_SYNC_MODE_ENABLE;
  2247	
  2248		/*
  2249		 * if dual link is enabled, then read DSI_0
  2250		 * transcoder registers
  2251		 */
> 2252		port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ?
  2253							  PORT_A : PORT_B;
  2254		dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1;
  2255	
  2256		/* Check if DSI configured in command mode */
  2257		val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
  2258		val = (val & OP_MODE_MASK) >> 28;
  2259	
  2260		if (val) {
  2261			DRM_ERROR("DSI trancoder not configured in command mode\n");
  2262			return;
  2263		}
  2264	
  2265		/* Get PIPE for handling VBLANK event */
  2266		val = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
  2267		switch (val & TRANS_DDI_EDP_INPUT_MASK) {
  2268		case TRANS_DDI_EDP_INPUT_A_ON:
  2269			pipe = PIPE_A;
  2270			break;
  2271		case TRANS_DDI_EDP_INPUT_B_ONOFF:
  2272			pipe = PIPE_B;
  2273			break;
  2274		case TRANS_DDI_EDP_INPUT_C_ONOFF:
  2275			pipe = PIPE_C;
  2276			break;
  2277		default:
  2278			DRM_ERROR("Invalid PIPE\n");
  2279		}
  2280	
  2281		/* clear TE in dsi IIR */
  2282		port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A;
> 2283		tmp = I915_READ(DSI_INTR_IDENT_REG(port));
  2284		I915_WRITE(DSI_INTR_IDENT_REG(port), tmp);
  2285	
  2286		drm_handle_vblank(&dev_priv->drm, pipe);
  2287	}
  2288	

---
0-DAY kernel test infrastructure                 Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org Intel Corporation

[-- Attachment #2: .config.gz --]
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[-- Attachment #3: Type: text/plain, Size: 159 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [V3 7/8] drm/i915/dsi: Add TE handler for dsi cmd mode.

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 10770 bytes --]

Hi Vandita,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v5.4-rc8 next-20191118]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Vandita-Kulkarni/Add-support-for-mipi-dsi-cmd-mode/20191120-015713
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-defconfig (attached as .config)
compiler: gcc-7 (Debian 7.4.0-14) 7.4.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/i915_irq.c: In function 'gen11_dsi_te_interrupt_handler':
>> drivers/gpu/drm/i915/i915_irq.c:2252:24: error: 'DSI1_TE' undeclared (first use in this function)
     port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ?
                           ^~~~~~~
   drivers/gpu/drm/i915/i915_irq.c:2252:24: note: each undeclared identifier is reported only once for each function it appears in
>> drivers/gpu/drm/i915/i915_irq.c:2252:57: error: 'DSI0_TE' undeclared (first use in this function); did you mean 'DSI1_TE'?
     port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ?
                                                            ^~~~~~~
                                                            DSI1_TE
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
>> drivers/gpu/drm/i915/i915_irq.c:2283:18: error: implicit declaration of function 'DSI_INTR_IDENT_REG'; did you mean 'GEN11_INTR_IDENTITY_REG'? [-Werror=implicit-function-declaration]
     tmp = I915_READ(DSI_INTR_IDENT_REG(port));
                     ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/i915_irq.c:2283:8: note: in expansion of macro 'I915_READ'
     tmp = I915_READ(DSI_INTR_IDENT_REG(port));
           ^~~~~~~~~
   drivers/gpu/drm/i915/i915_drv.h:1981:57: error: incompatible type for argument 2 of 'intel_uncore_read'
    #define I915_READ(reg__)  __I915_REG_OP(read, dev_priv, (reg__))
                                                            ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/i915_irq.c:2283:8: note: in expansion of macro 'I915_READ'
     tmp = I915_READ(DSI_INTR_IDENT_REG(port));
           ^~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
   drivers/gpu/drm/i915/intel_uncore.h:287:22: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
                         ^
   drivers/gpu/drm/i915/intel_uncore.h:302:1: note: in expansion of macro '__uncore_read'
    __uncore_read(read, 32, l, true)
    ^~~~~~~~~~~~~
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
   drivers/gpu/drm/i915/i915_drv.h:1982:65: error: incompatible type for argument 2 of 'intel_uncore_write'
    #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
                                                                    ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/i915_irq.c:2284:2: note: in expansion of macro 'I915_WRITE'
     I915_WRITE(DSI_INTR_IDENT_REG(port), tmp);
     ^~~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
   drivers/gpu/drm/i915/intel_uncore.h:294:20: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline void intel_uncore_##name__(struct intel_uncore *uncore, \
                       ^
   drivers/gpu/drm/i915/intel_uncore.h:308:1: note: in expansion of macro '__uncore_write'
    __uncore_write(write, 32, l, true)
    ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_irq.c: In function 'gen8_de_irq_handler':
   drivers/gpu/drm/i915/i915_irq.c:2354:23: error: 'DSI0_TE' undeclared (first use in this function)
        tmp_mask = iir & (DSI0_TE | DSI1_TE);
                          ^~~~~~~
   drivers/gpu/drm/i915/i915_irq.c:2354:33: error: 'DSI1_TE' undeclared (first use in this function); did you mean 'DSI0_TE'?
        tmp_mask = iir & (DSI0_TE | DSI1_TE);
                                    ^~~~~~~
                                    DSI0_TE
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
   drivers/gpu/drm/i915/i915_irq.c: In function 'gen11_dsi_configure_te':
   drivers/gpu/drm/i915/i915_irq.c:2654:19: error: implicit declaration of function 'DSI_INTR_MASK_REG'; did you mean 'TSFS_INTR_MASK'? [-Werror=implicit-function-declaration]
     tmp =  I915_READ(DSI_INTR_MASK_REG(port));
                      ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/i915_irq.c:2654:9: note: in expansion of macro 'I915_READ'
     tmp =  I915_READ(DSI_INTR_MASK_REG(port));
            ^~~~~~~~~
   drivers/gpu/drm/i915/i915_drv.h:1981:57: error: incompatible type for argument 2 of 'intel_uncore_read'
    #define I915_READ(reg__)  __I915_REG_OP(read, dev_priv, (reg__))
                                                            ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/i915_irq.c:2654:9: note: in expansion of macro 'I915_READ'
     tmp =  I915_READ(DSI_INTR_MASK_REG(port));
            ^~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
   drivers/gpu/drm/i915/intel_uncore.h:287:22: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
                         ^
   drivers/gpu/drm/i915/intel_uncore.h:302:1: note: in expansion of macro '__uncore_read'
    __uncore_read(read, 32, l, true)
    ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/i915_irq.c:2656:11: error: 'DSI_TE_EVENT' undeclared (first use in this function); did you mean 'DEFINE_EVENT'?
      tmp &= ~DSI_TE_EVENT;
              ^~~~~~~~~~~~
              DEFINE_EVENT
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/i915_irq.c:39:
   drivers/gpu/drm/i915/i915_drv.h:1982:65: error: incompatible type for argument 2 of 'intel_uncore_write'

vim +/DSI1_TE +2252 drivers/gpu/drm/i915/i915_irq.c

  2232	
  2233	void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
  2234					    u32 te_trigger)
  2235	{
  2236		enum pipe pipe = INVALID_PIPE;
  2237		enum transcoder dsi_trans;
  2238		enum port port;
  2239		u32 val, tmp;
  2240	
  2241		/*
  2242		 * Incase of dual link, TE comes from DSI_1
  2243		 * this is to check if dual link is enabled
  2244		 */
  2245		val = I915_READ(TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0));
  2246		val &= PORT_SYNC_MODE_ENABLE;
  2247	
  2248		/*
  2249		 * if dual link is enabled, then read DSI_0
  2250		 * transcoder registers
  2251		 */
> 2252		port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ?
  2253							  PORT_A : PORT_B;
  2254		dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1;
  2255	
  2256		/* Check if DSI configured in command mode */
  2257		val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
  2258		val = (val & OP_MODE_MASK) >> 28;
  2259	
  2260		if (val) {
  2261			DRM_ERROR("DSI trancoder not configured in command mode\n");
  2262			return;
  2263		}
  2264	
  2265		/* Get PIPE for handling VBLANK event */
  2266		val = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
  2267		switch (val & TRANS_DDI_EDP_INPUT_MASK) {
  2268		case TRANS_DDI_EDP_INPUT_A_ON:
  2269			pipe = PIPE_A;
  2270			break;
  2271		case TRANS_DDI_EDP_INPUT_B_ONOFF:
  2272			pipe = PIPE_B;
  2273			break;
  2274		case TRANS_DDI_EDP_INPUT_C_ONOFF:
  2275			pipe = PIPE_C;
  2276			break;
  2277		default:
  2278			DRM_ERROR("Invalid PIPE\n");
  2279		}
  2280	
  2281		/* clear TE in dsi IIR */
  2282		port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A;
> 2283		tmp = I915_READ(DSI_INTR_IDENT_REG(port));
  2284		I915_WRITE(DSI_INTR_IDENT_REG(port), tmp);
  2285	
  2286		drm_handle_vblank(&dev_priv->drm, pipe);
  2287	}
  2288	

---
0-DAY kernel test infrastructure                 Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org Intel Corporation

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Re: [V3 8/8] drm/i915/dsi: Initiate fame request in cmd mode

[kbuild test robot]

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Hi Vandita,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v5.4-rc8 next-20191118]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Vandita-Kulkarni/Add-support-for-mipi-dsi-cmd-mode/20191120-015713
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-defconfig (attached as .config)
compiler: gcc-7 (Debian 7.4.0-14) 7.4.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/display/icl_dsi.c:203:52: error: 'struct intel_crtc_state' has no member named 'uapi'
     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
                                                       ^
   include/linux/kernel.h:993:26: note: in definition of macro 'container_of'
     void *__mptr = (void *)(ptr);     \
                             ^~~
   drivers/gpu/drm/i915/display/icl_dsi.c:203:28: note: in expansion of macro 'to_intel_crtc'
     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
                               ^~~~~~~~~~~~~
   In file included from include/linux/ioport.h:13:0,
                    from include/linux/acpi.h:12,
                    from include/linux/i2c.h:13,
                    from include/drm/drm_crtc.h:28,
                    from include/drm/drm_atomic_helper.h:31,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:28:
   drivers/gpu/drm/i915/display/icl_dsi.c:203:52: error: 'struct intel_crtc_state' has no member named 'uapi'
     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
                                                       ^
   include/linux/compiler.h:330:9: note: in definition of macro '__compiletime_assert'
      if (!(condition))     \
            ^~~~~~~~~
   include/linux/compiler.h:350:2: note: in expansion of macro '_compiletime_assert'
     _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)
     ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
    #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
                                        ^~~~~~~~~~~~~~~~~~
   include/linux/kernel.h:994:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
     BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \
     ^~~~~~~~~~~~~~~~
   include/linux/kernel.h:994:20: note: in expansion of macro '__same_type'
     BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \
                       ^~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_display_types.h:1125:26: note: in expansion of macro 'container_of'
    #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
                             ^~~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:203:28: note: in expansion of macro 'to_intel_crtc'
     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
                               ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:203:52: error: 'struct intel_crtc_state' has no member named 'uapi'
     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
                                                       ^
   include/linux/compiler.h:330:9: note: in definition of macro '__compiletime_assert'
      if (!(condition))     \
            ^~~~~~~~~
   include/linux/compiler.h:350:2: note: in expansion of macro '_compiletime_assert'
     _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)
     ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
    #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
                                        ^~~~~~~~~~~~~~~~~~
   include/linux/kernel.h:994:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
     BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \
     ^~~~~~~~~~~~~~~~
   include/linux/kernel.h:995:6: note: in expansion of macro '__same_type'
        !__same_type(*(ptr), void),   \
         ^~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_display_types.h:1125:26: note: in expansion of macro 'container_of'
    #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
                             ^~~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:203:28: note: in expansion of macro 'to_intel_crtc'
     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
                               ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:208:28: error: 'struct intel_crtc_state' has no member named 'hw'
     private_flags = crtc_state->hw.adjusted_mode.private_flags;
                               ^~
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/display/icl_dsi.c:218:18: error: implicit declaration of function 'DSI_CMD_FRMCTL'; did you mean 'DSI_CMD_RXCTL'? [-Werror=implicit-function-declaration]
     tmp = I915_READ(DSI_CMD_FRMCTL(port));
                     ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:218:8: note: in expansion of macro 'I915_READ'
     tmp = I915_READ(DSI_CMD_FRMCTL(port));
           ^~~~~~~~~
   drivers/gpu/drm/i915/i915_drv.h:1981:57: error: incompatible type for argument 2 of 'intel_uncore_read'
    #define I915_READ(reg__)  __I915_REG_OP(read, dev_priv, (reg__))
                                                            ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:218:8: note: in expansion of macro 'I915_READ'
     tmp = I915_READ(DSI_CMD_FRMCTL(port));
           ^~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/intel_uncore.h:287:22: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
                         ^
   drivers/gpu/drm/i915/intel_uncore.h:302:1: note: in expansion of macro '__uncore_read'
    __uncore_read(read, 32, l, true)
    ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/icl_dsi.c:219:9: error: 'DSI_FRAME_UPDATE_REQUEST' undeclared (first use in this function); did you mean 'HDCP_REAUTH_REQUEST'?
     tmp |= DSI_FRAME_UPDATE_REQUEST;
            ^~~~~~~~~~~~~~~~~~~~~~~~
            HDCP_REAUTH_REQUEST
   drivers/gpu/drm/i915/display/icl_dsi.c:219:9: note: each undeclared identifier is reported only once for each function it appears in
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/i915_drv.h:1982:65: error: incompatible type for argument 2 of 'intel_uncore_write'
    #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
                                                                    ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:220:2: note: in expansion of macro 'I915_WRITE'
     I915_WRITE(DSI_CMD_FRMCTL(port), tmp);
     ^~~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/intel_uncore.h:294:20: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline void intel_uncore_##name__(struct intel_uncore *uncore, \
                       ^
   drivers/gpu/drm/i915/intel_uncore.h:308:1: note: in expansion of macro '__uncore_write'
    __uncore_write(write, 32, l, true)
    ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_configure_transcoder':
   drivers/gpu/drm/i915/display/icl_dsi.c:740:11: error: 'TE_SOURCE_GPIO' undeclared (first use in this function); did you mean 'DP_SOURCE_OUI'?
       tmp |= TE_SOURCE_GPIO;
              ^~~~~~~~~~~~~~
              DP_SOURCE_OUI
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_config_util_pin':
   drivers/gpu/drm/i915/display/icl_dsi.c:1021:10: error: 'UTIL_PIN_DIRECTION_INPUT' undeclared (first use in this function); did you mean 'UTIL_PIN_PIPE_MASK'?
      tmp |= UTIL_PIN_DIRECTION_INPUT;
             ^~~~~~~~~~~~~~~~~~~~~~~~
             UTIL_PIN_PIPE_MASK
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_deconfigure_trancoder':
   drivers/gpu/drm/i915/i915_drv.h:1981:57: error: incompatible type for argument 2 of 'intel_uncore_read'
    #define I915_READ(reg__)  __I915_REG_OP(read, dev_priv, (reg__))
                                                            ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:1186:10: note: in expansion of macro 'I915_READ'
       tmp = I915_READ(DSI_CMD_FRMCTL(port));
             ^~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/intel_uncore.h:287:22: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
                         ^
   drivers/gpu/drm/i915/intel_uncore.h:302:1: note: in expansion of macro '__uncore_read'
    __uncore_read(read, 32, l, true)
    ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:1187:12: error: 'DSI_PERIODIC_FRAME_UPDATE_ENABLE' undeclared (first use in this function); did you mean 'GEN6_MBCTL_BME_UPDATE_ENABLE'?
       tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE;
               ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
               GEN6_MBCTL_BME_UPDATE_ENABLE
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/i915_drv.h:1982:65: error: incompatible type for argument 2 of 'intel_uncore_write'
    #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
                                                                    ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:1188:4: note: in expansion of macro 'I915_WRITE'
       I915_WRITE(DSI_CMD_FRMCTL(port), tmp);
       ^~~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/intel_uncore.h:294:20: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline void intel_uncore_##name__(struct intel_uncore *uncore, \
                       ^
   drivers/gpu/drm/i915/intel_uncore.h:308:1: note: in expansion of macro '__uncore_write'
    __uncore_write(write, 32, l, true)
    ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_is_periodic_cmd_mode':
   drivers/gpu/drm/i915/display/icl_dsi.c:1340:16: error: 'DSI_PERIODIC_FRAME_UPDATE_ENABLE' undeclared (first use in this function); did you mean 'GEN6_MBCTL_BME_UPDATE_ENABLE'?
     return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE);
                   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                   GEN6_MBCTL_BME_UPDATE_ENABLE
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_get_config':

vim +219 drivers/gpu/drm/i915/display/icl_dsi.c

    30	
    31	#include "intel_atomic.h"
    32	#include "intel_combo_phy.h"
    33	#include "intel_connector.h"
    34	#include "intel_ddi.h"
  > 35	#include "intel_dsi.h"
    36	#include "intel_panel.h"
    37	
    38	static inline int header_credits_available(struct drm_i915_private *dev_priv,
    39						   enum transcoder dsi_trans)
    40	{
    41		return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
    42			>> FREE_HEADER_CREDIT_SHIFT;
    43	}
    44	
    45	static inline int payload_credits_available(struct drm_i915_private *dev_priv,
    46						    enum transcoder dsi_trans)
    47	{
    48		return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
    49			>> FREE_PLOAD_CREDIT_SHIFT;
    50	}
    51	
    52	static void wait_for_header_credits(struct drm_i915_private *dev_priv,
    53					    enum transcoder dsi_trans)
    54	{
    55		if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >=
    56				MAX_HEADER_CREDIT, 100))
    57			DRM_ERROR("DSI header credits not released\n");
    58	}
    59	
    60	static void wait_for_payload_credits(struct drm_i915_private *dev_priv,
    61					     enum transcoder dsi_trans)
    62	{
    63		if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >=
    64				MAX_PLOAD_CREDIT, 100))
    65			DRM_ERROR("DSI payload credits not released\n");
    66	}
    67	
    68	static enum transcoder dsi_port_to_transcoder(enum port port)
    69	{
    70		if (port == PORT_A)
    71			return TRANSCODER_DSI_0;
    72		else
    73			return TRANSCODER_DSI_1;
    74	}
    75	
    76	static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
    77	{
    78		struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
    79		struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
    80		struct mipi_dsi_device *dsi;
    81		enum port port;
    82		enum transcoder dsi_trans;
    83		int ret;
    84	
    85		/* wait for header/payload credits to be released */
    86		for_each_dsi_port(port, intel_dsi->ports) {
    87			dsi_trans = dsi_port_to_transcoder(port);
    88			wait_for_header_credits(dev_priv, dsi_trans);
    89			wait_for_payload_credits(dev_priv, dsi_trans);
    90		}
    91	
    92		/* send nop DCS command */
    93		for_each_dsi_port(port, intel_dsi->ports) {
    94			dsi = intel_dsi->dsi_hosts[port]->device;
    95			dsi->mode_flags |= MIPI_DSI_MODE_LPM;
    96			dsi->channel = 0;
    97			ret = mipi_dsi_dcs_nop(dsi);
    98			if (ret < 0)
    99				DRM_ERROR("error sending DCS NOP command\n");
   100		}
   101	
   102		/* wait for header credits to be released */
   103		for_each_dsi_port(port, intel_dsi->ports) {
   104			dsi_trans = dsi_port_to_transcoder(port);
   105			wait_for_header_credits(dev_priv, dsi_trans);
   106		}
   107	
   108		/* wait for LP TX in progress bit to be cleared */
   109		for_each_dsi_port(port, intel_dsi->ports) {
   110			dsi_trans = dsi_port_to_transcoder(port);
   111			if (wait_for_us(!(I915_READ(DSI_LP_MSG(dsi_trans)) &
   112					  LPTX_IN_PROGRESS), 20))
   113				DRM_ERROR("LPTX bit not cleared\n");
   114		}
   115	}
   116	
   117	static bool add_payld_to_queue(struct intel_dsi_host *host, const u8 *data,
   118				       u32 len)
   119	{
   120		struct intel_dsi *intel_dsi = host->intel_dsi;
   121		struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
   122		enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
   123		int free_credits;
   124		int i, j;
   125	
   126		for (i = 0; i < len; i += 4) {
   127			u32 tmp = 0;
   128	
   129			free_credits = payload_credits_available(dev_priv, dsi_trans);
   130			if (free_credits < 1) {
   131				DRM_ERROR("Payload credit not available\n");
   132				return false;
   133			}
   134	
   135			for (j = 0; j < min_t(u32, len - i, 4); j++)
   136				tmp |= *data++ << 8 * j;
   137	
   138			I915_WRITE(DSI_CMD_TXPYLD(dsi_trans), tmp);
   139		}
   140	
   141		return true;
   142	}
   143	
   144	static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
   145				    struct mipi_dsi_packet pkt, bool enable_lpdt)
   146	{
   147		struct intel_dsi *intel_dsi = host->intel_dsi;
   148		struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
   149		enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
   150		u32 tmp;
   151		int free_credits;
   152	
   153		/* check if header credit available */
   154		free_credits = header_credits_available(dev_priv, dsi_trans);
   155		if (free_credits < 1) {
   156			DRM_ERROR("send pkt header failed, not enough hdr credits\n");
   157			return -1;
   158		}
   159	
   160		tmp = I915_READ(DSI_CMD_TXHDR(dsi_trans));
   161	
   162		if (pkt.payload)
   163			tmp |= PAYLOAD_PRESENT;
   164		else
   165			tmp &= ~PAYLOAD_PRESENT;
   166	
   167		tmp &= ~VBLANK_FENCE;
   168	
   169		if (enable_lpdt)
   170			tmp |= LP_DATA_TRANSFER;
   171	
   172		tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK);
   173		tmp |= ((pkt.header[0] & VC_MASK) << VC_SHIFT);
   174		tmp |= ((pkt.header[0] & DT_MASK) << DT_SHIFT);
   175		tmp |= (pkt.header[1] << PARAM_WC_LOWER_SHIFT);
   176		tmp |= (pkt.header[2] << PARAM_WC_UPPER_SHIFT);
   177		I915_WRITE(DSI_CMD_TXHDR(dsi_trans), tmp);
   178	
   179		return 0;
   180	}
   181	
   182	static int dsi_send_pkt_payld(struct intel_dsi_host *host,
   183				      struct mipi_dsi_packet pkt)
   184	{
   185		/* payload queue can accept *256 bytes*, check limit */
   186		if (pkt.payload_length > MAX_PLOAD_CREDIT * 4) {
   187			DRM_ERROR("payload size exceeds max queue limit\n");
   188			return -1;
   189		}
   190	
   191		/* load data into command payload queue */
   192		if (!add_payld_to_queue(host, pkt.payload,
   193					pkt.payload_length)) {
   194			DRM_ERROR("adding payload to queue failed\n");
   195			return -1;
   196		}
   197	
   198		return 0;
   199	}
   200	
   201	void gen11_dsi_frame_update(struct intel_crtc_state *crtc_state)
   202	{
   203		struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
   204		struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
   205		u32 tmp, private_flags;
   206		enum port port;
   207	
   208		private_flags = crtc_state->hw.adjusted_mode.private_flags;
   209	
   210		/* case 1 also covers dual link */
   211		if (private_flags & I915_MODE_FLAG_DSI_USE_TE0)
   212			port = PORT_A;
   213		else if (private_flags & I915_MODE_FLAG_DSI_USE_TE1)
   214			port = PORT_B;
   215		else
   216			return;
   217	
   218		tmp = I915_READ(DSI_CMD_FRMCTL(port));
 > 219		tmp |= DSI_FRAME_UPDATE_REQUEST;
   220		I915_WRITE(DSI_CMD_FRMCTL(port), tmp);
   221	}
   222	

---
0-DAY kernel test infrastructure                 Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org Intel Corporation

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [V3 8/8] drm/i915/dsi: Initiate fame request in cmd mode

[kbuild test robot]

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Hi Vandita,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v5.4-rc8 next-20191118]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Vandita-Kulkarni/Add-support-for-mipi-dsi-cmd-mode/20191120-015713
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-defconfig (attached as .config)
compiler: gcc-7 (Debian 7.4.0-14) 7.4.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/display/icl_dsi.c:203:52: error: 'struct intel_crtc_state' has no member named 'uapi'
     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
                                                       ^
   include/linux/kernel.h:993:26: note: in definition of macro 'container_of'
     void *__mptr = (void *)(ptr);     \
                             ^~~
   drivers/gpu/drm/i915/display/icl_dsi.c:203:28: note: in expansion of macro 'to_intel_crtc'
     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
                               ^~~~~~~~~~~~~
   In file included from include/linux/ioport.h:13:0,
                    from include/linux/acpi.h:12,
                    from include/linux/i2c.h:13,
                    from include/drm/drm_crtc.h:28,
                    from include/drm/drm_atomic_helper.h:31,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:28:
   drivers/gpu/drm/i915/display/icl_dsi.c:203:52: error: 'struct intel_crtc_state' has no member named 'uapi'
     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
                                                       ^
   include/linux/compiler.h:330:9: note: in definition of macro '__compiletime_assert'
      if (!(condition))     \
            ^~~~~~~~~
   include/linux/compiler.h:350:2: note: in expansion of macro '_compiletime_assert'
     _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)
     ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
    #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
                                        ^~~~~~~~~~~~~~~~~~
   include/linux/kernel.h:994:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
     BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \
     ^~~~~~~~~~~~~~~~
   include/linux/kernel.h:994:20: note: in expansion of macro '__same_type'
     BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \
                       ^~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_display_types.h:1125:26: note: in expansion of macro 'container_of'
    #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
                             ^~~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:203:28: note: in expansion of macro 'to_intel_crtc'
     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
                               ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:203:52: error: 'struct intel_crtc_state' has no member named 'uapi'
     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
                                                       ^
   include/linux/compiler.h:330:9: note: in definition of macro '__compiletime_assert'
      if (!(condition))     \
            ^~~~~~~~~
   include/linux/compiler.h:350:2: note: in expansion of macro '_compiletime_assert'
     _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)
     ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
    #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
                                        ^~~~~~~~~~~~~~~~~~
   include/linux/kernel.h:994:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
     BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \
     ^~~~~~~~~~~~~~~~
   include/linux/kernel.h:995:6: note: in expansion of macro '__same_type'
        !__same_type(*(ptr), void),   \
         ^~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_display_types.h:1125:26: note: in expansion of macro 'container_of'
    #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
                             ^~~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:203:28: note: in expansion of macro 'to_intel_crtc'
     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
                               ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:208:28: error: 'struct intel_crtc_state' has no member named 'hw'
     private_flags = crtc_state->hw.adjusted_mode.private_flags;
                               ^~
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/display/icl_dsi.c:218:18: error: implicit declaration of function 'DSI_CMD_FRMCTL'; did you mean 'DSI_CMD_RXCTL'? [-Werror=implicit-function-declaration]
     tmp = I915_READ(DSI_CMD_FRMCTL(port));
                     ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:218:8: note: in expansion of macro 'I915_READ'
     tmp = I915_READ(DSI_CMD_FRMCTL(port));
           ^~~~~~~~~
   drivers/gpu/drm/i915/i915_drv.h:1981:57: error: incompatible type for argument 2 of 'intel_uncore_read'
    #define I915_READ(reg__)  __I915_REG_OP(read, dev_priv, (reg__))
                                                            ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:218:8: note: in expansion of macro 'I915_READ'
     tmp = I915_READ(DSI_CMD_FRMCTL(port));
           ^~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/intel_uncore.h:287:22: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
                         ^
   drivers/gpu/drm/i915/intel_uncore.h:302:1: note: in expansion of macro '__uncore_read'
    __uncore_read(read, 32, l, true)
    ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/icl_dsi.c:219:9: error: 'DSI_FRAME_UPDATE_REQUEST' undeclared (first use in this function); did you mean 'HDCP_REAUTH_REQUEST'?
     tmp |= DSI_FRAME_UPDATE_REQUEST;
            ^~~~~~~~~~~~~~~~~~~~~~~~
            HDCP_REAUTH_REQUEST
   drivers/gpu/drm/i915/display/icl_dsi.c:219:9: note: each undeclared identifier is reported only once for each function it appears in
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/i915_drv.h:1982:65: error: incompatible type for argument 2 of 'intel_uncore_write'
    #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
                                                                    ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:220:2: note: in expansion of macro 'I915_WRITE'
     I915_WRITE(DSI_CMD_FRMCTL(port), tmp);
     ^~~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/intel_uncore.h:294:20: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline void intel_uncore_##name__(struct intel_uncore *uncore, \
                       ^
   drivers/gpu/drm/i915/intel_uncore.h:308:1: note: in expansion of macro '__uncore_write'
    __uncore_write(write, 32, l, true)
    ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_configure_transcoder':
   drivers/gpu/drm/i915/display/icl_dsi.c:740:11: error: 'TE_SOURCE_GPIO' undeclared (first use in this function); did you mean 'DP_SOURCE_OUI'?
       tmp |= TE_SOURCE_GPIO;
              ^~~~~~~~~~~~~~
              DP_SOURCE_OUI
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_config_util_pin':
   drivers/gpu/drm/i915/display/icl_dsi.c:1021:10: error: 'UTIL_PIN_DIRECTION_INPUT' undeclared (first use in this function); did you mean 'UTIL_PIN_PIPE_MASK'?
      tmp |= UTIL_PIN_DIRECTION_INPUT;
             ^~~~~~~~~~~~~~~~~~~~~~~~
             UTIL_PIN_PIPE_MASK
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_deconfigure_trancoder':
   drivers/gpu/drm/i915/i915_drv.h:1981:57: error: incompatible type for argument 2 of 'intel_uncore_read'
    #define I915_READ(reg__)  __I915_REG_OP(read, dev_priv, (reg__))
                                                            ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:1186:10: note: in expansion of macro 'I915_READ'
       tmp = I915_READ(DSI_CMD_FRMCTL(port));
             ^~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/intel_uncore.h:287:22: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
                         ^
   drivers/gpu/drm/i915/intel_uncore.h:302:1: note: in expansion of macro '__uncore_read'
    __uncore_read(read, 32, l, true)
    ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:1187:12: error: 'DSI_PERIODIC_FRAME_UPDATE_ENABLE' undeclared (first use in this function); did you mean 'GEN6_MBCTL_BME_UPDATE_ENABLE'?
       tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE;
               ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
               GEN6_MBCTL_BME_UPDATE_ENABLE
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/i915_drv.h:1982:65: error: incompatible type for argument 2 of 'intel_uncore_write'
    #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
                                                                    ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:1188:4: note: in expansion of macro 'I915_WRITE'
       I915_WRITE(DSI_CMD_FRMCTL(port), tmp);
       ^~~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/intel_uncore.h:294:20: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline void intel_uncore_##name__(struct intel_uncore *uncore, \
                       ^
   drivers/gpu/drm/i915/intel_uncore.h:308:1: note: in expansion of macro '__uncore_write'
    __uncore_write(write, 32, l, true)
    ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_is_periodic_cmd_mode':
   drivers/gpu/drm/i915/display/icl_dsi.c:1340:16: error: 'DSI_PERIODIC_FRAME_UPDATE_ENABLE' undeclared (first use in this function); did you mean 'GEN6_MBCTL_BME_UPDATE_ENABLE'?
     return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE);
                   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                   GEN6_MBCTL_BME_UPDATE_ENABLE
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_get_config':

vim +219 drivers/gpu/drm/i915/display/icl_dsi.c

    30	
    31	#include "intel_atomic.h"
    32	#include "intel_combo_phy.h"
    33	#include "intel_connector.h"
    34	#include "intel_ddi.h"
  > 35	#include "intel_dsi.h"
    36	#include "intel_panel.h"
    37	
    38	static inline int header_credits_available(struct drm_i915_private *dev_priv,
    39						   enum transcoder dsi_trans)
    40	{
    41		return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
    42			>> FREE_HEADER_CREDIT_SHIFT;
    43	}
    44	
    45	static inline int payload_credits_available(struct drm_i915_private *dev_priv,
    46						    enum transcoder dsi_trans)
    47	{
    48		return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
    49			>> FREE_PLOAD_CREDIT_SHIFT;
    50	}
    51	
    52	static void wait_for_header_credits(struct drm_i915_private *dev_priv,
    53					    enum transcoder dsi_trans)
    54	{
    55		if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >=
    56				MAX_HEADER_CREDIT, 100))
    57			DRM_ERROR("DSI header credits not released\n");
    58	}
    59	
    60	static void wait_for_payload_credits(struct drm_i915_private *dev_priv,
    61					     enum transcoder dsi_trans)
    62	{
    63		if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >=
    64				MAX_PLOAD_CREDIT, 100))
    65			DRM_ERROR("DSI payload credits not released\n");
    66	}
    67	
    68	static enum transcoder dsi_port_to_transcoder(enum port port)
    69	{
    70		if (port == PORT_A)
    71			return TRANSCODER_DSI_0;
    72		else
    73			return TRANSCODER_DSI_1;
    74	}
    75	
    76	static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
    77	{
    78		struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
    79		struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
    80		struct mipi_dsi_device *dsi;
    81		enum port port;
    82		enum transcoder dsi_trans;
    83		int ret;
    84	
    85		/* wait for header/payload credits to be released */
    86		for_each_dsi_port(port, intel_dsi->ports) {
    87			dsi_trans = dsi_port_to_transcoder(port);
    88			wait_for_header_credits(dev_priv, dsi_trans);
    89			wait_for_payload_credits(dev_priv, dsi_trans);
    90		}
    91	
    92		/* send nop DCS command */
    93		for_each_dsi_port(port, intel_dsi->ports) {
    94			dsi = intel_dsi->dsi_hosts[port]->device;
    95			dsi->mode_flags |= MIPI_DSI_MODE_LPM;
    96			dsi->channel = 0;
    97			ret = mipi_dsi_dcs_nop(dsi);
    98			if (ret < 0)
    99				DRM_ERROR("error sending DCS NOP command\n");
   100		}
   101	
   102		/* wait for header credits to be released */
   103		for_each_dsi_port(port, intel_dsi->ports) {
   104			dsi_trans = dsi_port_to_transcoder(port);
   105			wait_for_header_credits(dev_priv, dsi_trans);
   106		}
   107	
   108		/* wait for LP TX in progress bit to be cleared */
   109		for_each_dsi_port(port, intel_dsi->ports) {
   110			dsi_trans = dsi_port_to_transcoder(port);
   111			if (wait_for_us(!(I915_READ(DSI_LP_MSG(dsi_trans)) &
   112					  LPTX_IN_PROGRESS), 20))
   113				DRM_ERROR("LPTX bit not cleared\n");
   114		}
   115	}
   116	
   117	static bool add_payld_to_queue(struct intel_dsi_host *host, const u8 *data,
   118				       u32 len)
   119	{
   120		struct intel_dsi *intel_dsi = host->intel_dsi;
   121		struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
   122		enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
   123		int free_credits;
   124		int i, j;
   125	
   126		for (i = 0; i < len; i += 4) {
   127			u32 tmp = 0;
   128	
   129			free_credits = payload_credits_available(dev_priv, dsi_trans);
   130			if (free_credits < 1) {
   131				DRM_ERROR("Payload credit not available\n");
   132				return false;
   133			}
   134	
   135			for (j = 0; j < min_t(u32, len - i, 4); j++)
   136				tmp |= *data++ << 8 * j;
   137	
   138			I915_WRITE(DSI_CMD_TXPYLD(dsi_trans), tmp);
   139		}
   140	
   141		return true;
   142	}
   143	
   144	static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
   145				    struct mipi_dsi_packet pkt, bool enable_lpdt)
   146	{
   147		struct intel_dsi *intel_dsi = host->intel_dsi;
   148		struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
   149		enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
   150		u32 tmp;
   151		int free_credits;
   152	
   153		/* check if header credit available */
   154		free_credits = header_credits_available(dev_priv, dsi_trans);
   155		if (free_credits < 1) {
   156			DRM_ERROR("send pkt header failed, not enough hdr credits\n");
   157			return -1;
   158		}
   159	
   160		tmp = I915_READ(DSI_CMD_TXHDR(dsi_trans));
   161	
   162		if (pkt.payload)
   163			tmp |= PAYLOAD_PRESENT;
   164		else
   165			tmp &= ~PAYLOAD_PRESENT;
   166	
   167		tmp &= ~VBLANK_FENCE;
   168	
   169		if (enable_lpdt)
   170			tmp |= LP_DATA_TRANSFER;
   171	
   172		tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK);
   173		tmp |= ((pkt.header[0] & VC_MASK) << VC_SHIFT);
   174		tmp |= ((pkt.header[0] & DT_MASK) << DT_SHIFT);
   175		tmp |= (pkt.header[1] << PARAM_WC_LOWER_SHIFT);
   176		tmp |= (pkt.header[2] << PARAM_WC_UPPER_SHIFT);
   177		I915_WRITE(DSI_CMD_TXHDR(dsi_trans), tmp);
   178	
   179		return 0;
   180	}
   181	
   182	static int dsi_send_pkt_payld(struct intel_dsi_host *host,
   183				      struct mipi_dsi_packet pkt)
   184	{
   185		/* payload queue can accept *256 bytes*, check limit */
   186		if (pkt.payload_length > MAX_PLOAD_CREDIT * 4) {
   187			DRM_ERROR("payload size exceeds max queue limit\n");
   188			return -1;
   189		}
   190	
   191		/* load data into command payload queue */
   192		if (!add_payld_to_queue(host, pkt.payload,
   193					pkt.payload_length)) {
   194			DRM_ERROR("adding payload to queue failed\n");
   195			return -1;
   196		}
   197	
   198		return 0;
   199	}
   200	
   201	void gen11_dsi_frame_update(struct intel_crtc_state *crtc_state)
   202	{
   203		struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
   204		struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
   205		u32 tmp, private_flags;
   206		enum port port;
   207	
   208		private_flags = crtc_state->hw.adjusted_mode.private_flags;
   209	
   210		/* case 1 also covers dual link */
   211		if (private_flags & I915_MODE_FLAG_DSI_USE_TE0)
   212			port = PORT_A;
   213		else if (private_flags & I915_MODE_FLAG_DSI_USE_TE1)
   214			port = PORT_B;
   215		else
   216			return;
   217	
   218		tmp = I915_READ(DSI_CMD_FRMCTL(port));
 > 219		tmp |= DSI_FRAME_UPDATE_REQUEST;
   220		I915_WRITE(DSI_CMD_FRMCTL(port), tmp);
   221	}
   222	

---
0-DAY kernel test infrastructure                 Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org Intel Corporation

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [V3 8/8] drm/i915/dsi: Initiate fame request in cmd mode

[kbuild test robot]

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Hi Vandita,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v5.4-rc8 next-20191118]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Vandita-Kulkarni/Add-support-for-mipi-dsi-cmd-mode/20191120-015713
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-defconfig (attached as .config)
compiler: gcc-7 (Debian 7.4.0-14) 7.4.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/display/icl_dsi.c:203:52: error: 'struct intel_crtc_state' has no member named 'uapi'
     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
                                                       ^
   include/linux/kernel.h:993:26: note: in definition of macro 'container_of'
     void *__mptr = (void *)(ptr);     \
                             ^~~
   drivers/gpu/drm/i915/display/icl_dsi.c:203:28: note: in expansion of macro 'to_intel_crtc'
     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
                               ^~~~~~~~~~~~~
   In file included from include/linux/ioport.h:13:0,
                    from include/linux/acpi.h:12,
                    from include/linux/i2c.h:13,
                    from include/drm/drm_crtc.h:28,
                    from include/drm/drm_atomic_helper.h:31,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:28:
   drivers/gpu/drm/i915/display/icl_dsi.c:203:52: error: 'struct intel_crtc_state' has no member named 'uapi'
     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
                                                       ^
   include/linux/compiler.h:330:9: note: in definition of macro '__compiletime_assert'
      if (!(condition))     \
            ^~~~~~~~~
   include/linux/compiler.h:350:2: note: in expansion of macro '_compiletime_assert'
     _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)
     ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
    #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
                                        ^~~~~~~~~~~~~~~~~~
   include/linux/kernel.h:994:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
     BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \
     ^~~~~~~~~~~~~~~~
   include/linux/kernel.h:994:20: note: in expansion of macro '__same_type'
     BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \
                       ^~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_display_types.h:1125:26: note: in expansion of macro 'container_of'
    #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
                             ^~~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:203:28: note: in expansion of macro 'to_intel_crtc'
     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
                               ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:203:52: error: 'struct intel_crtc_state' has no member named 'uapi'
     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
                                                       ^
   include/linux/compiler.h:330:9: note: in definition of macro '__compiletime_assert'
      if (!(condition))     \
            ^~~~~~~~~
   include/linux/compiler.h:350:2: note: in expansion of macro '_compiletime_assert'
     _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)
     ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
    #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
                                        ^~~~~~~~~~~~~~~~~~
   include/linux/kernel.h:994:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
     BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \
     ^~~~~~~~~~~~~~~~
   include/linux/kernel.h:995:6: note: in expansion of macro '__same_type'
        !__same_type(*(ptr), void),   \
         ^~~~~~~~~~~
   drivers/gpu/drm/i915/display/intel_display_types.h:1125:26: note: in expansion of macro 'container_of'
    #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
                             ^~~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:203:28: note: in expansion of macro 'to_intel_crtc'
     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
                               ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:208:28: error: 'struct intel_crtc_state' has no member named 'hw'
     private_flags = crtc_state->hw.adjusted_mode.private_flags;
                               ^~
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/display/icl_dsi.c:218:18: error: implicit declaration of function 'DSI_CMD_FRMCTL'; did you mean 'DSI_CMD_RXCTL'? [-Werror=implicit-function-declaration]
     tmp = I915_READ(DSI_CMD_FRMCTL(port));
                     ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:218:8: note: in expansion of macro 'I915_READ'
     tmp = I915_READ(DSI_CMD_FRMCTL(port));
           ^~~~~~~~~
   drivers/gpu/drm/i915/i915_drv.h:1981:57: error: incompatible type for argument 2 of 'intel_uncore_read'
    #define I915_READ(reg__)  __I915_REG_OP(read, dev_priv, (reg__))
                                                            ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:218:8: note: in expansion of macro 'I915_READ'
     tmp = I915_READ(DSI_CMD_FRMCTL(port));
           ^~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/intel_uncore.h:287:22: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
                         ^
   drivers/gpu/drm/i915/intel_uncore.h:302:1: note: in expansion of macro '__uncore_read'
    __uncore_read(read, 32, l, true)
    ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/icl_dsi.c:219:9: error: 'DSI_FRAME_UPDATE_REQUEST' undeclared (first use in this function); did you mean 'HDCP_REAUTH_REQUEST'?
     tmp |= DSI_FRAME_UPDATE_REQUEST;
            ^~~~~~~~~~~~~~~~~~~~~~~~
            HDCP_REAUTH_REQUEST
   drivers/gpu/drm/i915/display/icl_dsi.c:219:9: note: each undeclared identifier is reported only once for each function it appears in
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/i915_drv.h:1982:65: error: incompatible type for argument 2 of 'intel_uncore_write'
    #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
                                                                    ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:220:2: note: in expansion of macro 'I915_WRITE'
     I915_WRITE(DSI_CMD_FRMCTL(port), tmp);
     ^~~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/intel_uncore.h:294:20: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline void intel_uncore_##name__(struct intel_uncore *uncore, \
                       ^
   drivers/gpu/drm/i915/intel_uncore.h:308:1: note: in expansion of macro '__uncore_write'
    __uncore_write(write, 32, l, true)
    ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_configure_transcoder':
   drivers/gpu/drm/i915/display/icl_dsi.c:740:11: error: 'TE_SOURCE_GPIO' undeclared (first use in this function); did you mean 'DP_SOURCE_OUI'?
       tmp |= TE_SOURCE_GPIO;
              ^~~~~~~~~~~~~~
              DP_SOURCE_OUI
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_config_util_pin':
   drivers/gpu/drm/i915/display/icl_dsi.c:1021:10: error: 'UTIL_PIN_DIRECTION_INPUT' undeclared (first use in this function); did you mean 'UTIL_PIN_PIPE_MASK'?
      tmp |= UTIL_PIN_DIRECTION_INPUT;
             ^~~~~~~~~~~~~~~~~~~~~~~~
             UTIL_PIN_PIPE_MASK
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_deconfigure_trancoder':
   drivers/gpu/drm/i915/i915_drv.h:1981:57: error: incompatible type for argument 2 of 'intel_uncore_read'
    #define I915_READ(reg__)  __I915_REG_OP(read, dev_priv, (reg__))
                                                            ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:1186:10: note: in expansion of macro 'I915_READ'
       tmp = I915_READ(DSI_CMD_FRMCTL(port));
             ^~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/intel_uncore.h:287:22: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
                         ^
   drivers/gpu/drm/i915/intel_uncore.h:302:1: note: in expansion of macro '__uncore_read'
    __uncore_read(read, 32, l, true)
    ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:1187:12: error: 'DSI_PERIODIC_FRAME_UPDATE_ENABLE' undeclared (first use in this function); did you mean 'GEN6_MBCTL_BME_UPDATE_ENABLE'?
       tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE;
               ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
               GEN6_MBCTL_BME_UPDATE_ENABLE
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/i915_drv.h:1982:65: error: incompatible type for argument 2 of 'intel_uncore_write'
    #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
                                                                    ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c:1188:4: note: in expansion of macro 'I915_WRITE'
       I915_WRITE(DSI_CMD_FRMCTL(port), tmp);
       ^~~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/intel_uncore.h:294:20: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline void intel_uncore_##name__(struct intel_uncore *uncore, \
                       ^
   drivers/gpu/drm/i915/intel_uncore.h:308:1: note: in expansion of macro '__uncore_write'
    __uncore_write(write, 32, l, true)
    ^~~~~~~~~~~~~~
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_is_periodic_cmd_mode':
   drivers/gpu/drm/i915/display/icl_dsi.c:1340:16: error: 'DSI_PERIODIC_FRAME_UPDATE_ENABLE' undeclared (first use in this function); did you mean 'GEN6_MBCTL_BME_UPDATE_ENABLE'?
     return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE);
                   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                   GEN6_MBCTL_BME_UPDATE_ENABLE
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_get_config':

vim +219 drivers/gpu/drm/i915/display/icl_dsi.c

    30	
    31	#include "intel_atomic.h"
    32	#include "intel_combo_phy.h"
    33	#include "intel_connector.h"
    34	#include "intel_ddi.h"
  > 35	#include "intel_dsi.h"
    36	#include "intel_panel.h"
    37	
    38	static inline int header_credits_available(struct drm_i915_private *dev_priv,
    39						   enum transcoder dsi_trans)
    40	{
    41		return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
    42			>> FREE_HEADER_CREDIT_SHIFT;
    43	}
    44	
    45	static inline int payload_credits_available(struct drm_i915_private *dev_priv,
    46						    enum transcoder dsi_trans)
    47	{
    48		return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
    49			>> FREE_PLOAD_CREDIT_SHIFT;
    50	}
    51	
    52	static void wait_for_header_credits(struct drm_i915_private *dev_priv,
    53					    enum transcoder dsi_trans)
    54	{
    55		if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >=
    56				MAX_HEADER_CREDIT, 100))
    57			DRM_ERROR("DSI header credits not released\n");
    58	}
    59	
    60	static void wait_for_payload_credits(struct drm_i915_private *dev_priv,
    61					     enum transcoder dsi_trans)
    62	{
    63		if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >=
    64				MAX_PLOAD_CREDIT, 100))
    65			DRM_ERROR("DSI payload credits not released\n");
    66	}
    67	
    68	static enum transcoder dsi_port_to_transcoder(enum port port)
    69	{
    70		if (port == PORT_A)
    71			return TRANSCODER_DSI_0;
    72		else
    73			return TRANSCODER_DSI_1;
    74	}
    75	
    76	static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
    77	{
    78		struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
    79		struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
    80		struct mipi_dsi_device *dsi;
    81		enum port port;
    82		enum transcoder dsi_trans;
    83		int ret;
    84	
    85		/* wait for header/payload credits to be released */
    86		for_each_dsi_port(port, intel_dsi->ports) {
    87			dsi_trans = dsi_port_to_transcoder(port);
    88			wait_for_header_credits(dev_priv, dsi_trans);
    89			wait_for_payload_credits(dev_priv, dsi_trans);
    90		}
    91	
    92		/* send nop DCS command */
    93		for_each_dsi_port(port, intel_dsi->ports) {
    94			dsi = intel_dsi->dsi_hosts[port]->device;
    95			dsi->mode_flags |= MIPI_DSI_MODE_LPM;
    96			dsi->channel = 0;
    97			ret = mipi_dsi_dcs_nop(dsi);
    98			if (ret < 0)
    99				DRM_ERROR("error sending DCS NOP command\n");
   100		}
   101	
   102		/* wait for header credits to be released */
   103		for_each_dsi_port(port, intel_dsi->ports) {
   104			dsi_trans = dsi_port_to_transcoder(port);
   105			wait_for_header_credits(dev_priv, dsi_trans);
   106		}
   107	
   108		/* wait for LP TX in progress bit to be cleared */
   109		for_each_dsi_port(port, intel_dsi->ports) {
   110			dsi_trans = dsi_port_to_transcoder(port);
   111			if (wait_for_us(!(I915_READ(DSI_LP_MSG(dsi_trans)) &
   112					  LPTX_IN_PROGRESS), 20))
   113				DRM_ERROR("LPTX bit not cleared\n");
   114		}
   115	}
   116	
   117	static bool add_payld_to_queue(struct intel_dsi_host *host, const u8 *data,
   118				       u32 len)
   119	{
   120		struct intel_dsi *intel_dsi = host->intel_dsi;
   121		struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
   122		enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
   123		int free_credits;
   124		int i, j;
   125	
   126		for (i = 0; i < len; i += 4) {
   127			u32 tmp = 0;
   128	
   129			free_credits = payload_credits_available(dev_priv, dsi_trans);
   130			if (free_credits < 1) {
   131				DRM_ERROR("Payload credit not available\n");
   132				return false;
   133			}
   134	
   135			for (j = 0; j < min_t(u32, len - i, 4); j++)
   136				tmp |= *data++ << 8 * j;
   137	
   138			I915_WRITE(DSI_CMD_TXPYLD(dsi_trans), tmp);
   139		}
   140	
   141		return true;
   142	}
   143	
   144	static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
   145				    struct mipi_dsi_packet pkt, bool enable_lpdt)
   146	{
   147		struct intel_dsi *intel_dsi = host->intel_dsi;
   148		struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
   149		enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
   150		u32 tmp;
   151		int free_credits;
   152	
   153		/* check if header credit available */
   154		free_credits = header_credits_available(dev_priv, dsi_trans);
   155		if (free_credits < 1) {
   156			DRM_ERROR("send pkt header failed, not enough hdr credits\n");
   157			return -1;
   158		}
   159	
   160		tmp = I915_READ(DSI_CMD_TXHDR(dsi_trans));
   161	
   162		if (pkt.payload)
   163			tmp |= PAYLOAD_PRESENT;
   164		else
   165			tmp &= ~PAYLOAD_PRESENT;
   166	
   167		tmp &= ~VBLANK_FENCE;
   168	
   169		if (enable_lpdt)
   170			tmp |= LP_DATA_TRANSFER;
   171	
   172		tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK);
   173		tmp |= ((pkt.header[0] & VC_MASK) << VC_SHIFT);
   174		tmp |= ((pkt.header[0] & DT_MASK) << DT_SHIFT);
   175		tmp |= (pkt.header[1] << PARAM_WC_LOWER_SHIFT);
   176		tmp |= (pkt.header[2] << PARAM_WC_UPPER_SHIFT);
   177		I915_WRITE(DSI_CMD_TXHDR(dsi_trans), tmp);
   178	
   179		return 0;
   180	}
   181	
   182	static int dsi_send_pkt_payld(struct intel_dsi_host *host,
   183				      struct mipi_dsi_packet pkt)
   184	{
   185		/* payload queue can accept *256 bytes*, check limit */
   186		if (pkt.payload_length > MAX_PLOAD_CREDIT * 4) {
   187			DRM_ERROR("payload size exceeds max queue limit\n");
   188			return -1;
   189		}
   190	
   191		/* load data into command payload queue */
   192		if (!add_payld_to_queue(host, pkt.payload,
   193					pkt.payload_length)) {
   194			DRM_ERROR("adding payload to queue failed\n");
   195			return -1;
   196		}
   197	
   198		return 0;
   199	}
   200	
   201	void gen11_dsi_frame_update(struct intel_crtc_state *crtc_state)
   202	{
   203		struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
   204		struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
   205		u32 tmp, private_flags;
   206		enum port port;
   207	
   208		private_flags = crtc_state->hw.adjusted_mode.private_flags;
   209	
   210		/* case 1 also covers dual link */
   211		if (private_flags & I915_MODE_FLAG_DSI_USE_TE0)
   212			port = PORT_A;
   213		else if (private_flags & I915_MODE_FLAG_DSI_USE_TE1)
   214			port = PORT_B;
   215		else
   216			return;
   217	
   218		tmp = I915_READ(DSI_CMD_FRMCTL(port));
 > 219		tmp |= DSI_FRAME_UPDATE_REQUEST;
   220		I915_WRITE(DSI_CMD_FRMCTL(port), tmp);
   221	}
   222	

---
0-DAY kernel test infrastructure                 Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org Intel Corporation

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