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* [PATCH 1/3] drm/i915/display: Refactor intel_commit_modeset_disables()
@ 2019-11-20 23:48 ` José Roberto de Souza
  0 siblings, 0 replies; 16+ messages in thread
From: José Roberto de Souza @ 2019-11-20 23:48 UTC (permalink / raw)
  To: intel-gfx

Commit 9c722e17c1b9 ("drm/i915: Disable pipes in reverse order")
reverted the order that pipes gets disabled because of TGL
master/slave relationship between transcoders in MST mode.

But as stated in a comment in skl_commit_modeset_enables() the
enabling order is not always crescent, possibly causing previously
selected slave transcoder being enabled before master so another
approach will be needed to select a transcoder to master in MST mode.
It will be similar to the approach taken in port sync.

But instead of implement something like
intel_trans_port_sync_modeset_disables() to MST lets simply it and
iterate over all pipes 2 times, the first one disabling any slave and
then disabling everything else.
The MST bits will be added in another patch.

Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 79 ++++++--------------
 1 file changed, 22 insertions(+), 57 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 53dc310a5f6d..1b1fbb6d8acc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14443,53 +14443,16 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
 		dev_priv->display.initial_watermarks(state, crtc);
 }
 
-static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state *state,
-						   struct intel_crtc *crtc,
-						   struct intel_crtc_state *old_crtc_state,
-						   struct intel_crtc_state *new_crtc_state)
-{
-	struct intel_crtc *slave_crtc = intel_get_slave_crtc(new_crtc_state);
-	struct intel_crtc_state *new_slave_crtc_state =
-		intel_atomic_get_new_crtc_state(state, slave_crtc);
-	struct intel_crtc_state *old_slave_crtc_state =
-		intel_atomic_get_old_crtc_state(state, slave_crtc);
-
-	WARN_ON(!slave_crtc || !new_slave_crtc_state ||
-		!old_slave_crtc_state);
-
-	/* Disable Slave first */
-	intel_pre_plane_update(old_slave_crtc_state, new_slave_crtc_state);
-	if (old_slave_crtc_state->hw.active)
-		intel_old_crtc_state_disables(state,
-					      old_slave_crtc_state,
-					      new_slave_crtc_state,
-					      slave_crtc);
-
-	/* Disable Master */
-	intel_pre_plane_update(old_crtc_state, new_crtc_state);
-	if (old_crtc_state->hw.active)
-		intel_old_crtc_state_disables(state,
-					      old_crtc_state,
-					      new_crtc_state,
-					      crtc);
-}
-
 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
 {
 	struct intel_crtc_state *new_crtc_state, *old_crtc_state;
 	struct intel_crtc *crtc;
 	int i;
 
-	/*
-	 * Disable CRTC/pipes in reverse order because some features(MST in
-	 * TGL+) requires master and slave relationship between pipes, so it
-	 * should always pick the lowest pipe as master as it will be enabled
-	 * first and disable in the reverse order so the master will be the
-	 * last one to be disabled.
-	 */
-	for_each_oldnew_intel_crtc_in_state_reverse(state, crtc, old_crtc_state,
-						    new_crtc_state, i) {
-		if (!needs_modeset(new_crtc_state))
+	/* Only disable port sync slaves */
+	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+					    new_crtc_state, i) {
+		if (!needs_modeset(new_crtc_state) || !crtc->active)
 			continue;
 
 		/* In case of Transcoder port Sync master slave CRTCs can be
@@ -14497,23 +14460,25 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
 		 * slave CRTCs are disabled first and then master CRTC since
 		 * Slave vblanks are masked till Master Vblanks.
 		 */
-		if (is_trans_port_sync_mode(new_crtc_state)) {
-			if (is_trans_port_sync_master(new_crtc_state))
-				intel_trans_port_sync_modeset_disables(state,
-								       crtc,
-								       old_crtc_state,
-								       new_crtc_state);
-			else
-				continue;
-		} else {
-			intel_pre_plane_update(old_crtc_state, new_crtc_state);
+		if (!is_trans_port_sync_mode(new_crtc_state))
+			continue;
+		if (is_trans_port_sync_master(new_crtc_state))
+			continue;
 
-			if (old_crtc_state->hw.active)
-				intel_old_crtc_state_disables(state,
-							      old_crtc_state,
-							      new_crtc_state,
-							      crtc);
-		}
+		intel_pre_plane_update(old_crtc_state, new_crtc_state);
+		intel_old_crtc_state_disables(state, old_crtc_state,
+					      new_crtc_state, crtc);
+	}
+
+	/* Disable everything else left on */
+	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+					    new_crtc_state, i) {
+		if (!needs_modeset(new_crtc_state) || !crtc->active)
+			continue;
+
+		intel_pre_plane_update(old_crtc_state, new_crtc_state);
+		intel_old_crtc_state_disables(state, old_crtc_state,
+					      new_crtc_state, crtc);
 	}
 }
 
-- 
2.24.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 16+ messages in thread

* [Intel-gfx] [PATCH 1/3] drm/i915/display: Refactor intel_commit_modeset_disables()
@ 2019-11-20 23:48 ` José Roberto de Souza
  0 siblings, 0 replies; 16+ messages in thread
From: José Roberto de Souza @ 2019-11-20 23:48 UTC (permalink / raw)
  To: intel-gfx

Commit 9c722e17c1b9 ("drm/i915: Disable pipes in reverse order")
reverted the order that pipes gets disabled because of TGL
master/slave relationship between transcoders in MST mode.

But as stated in a comment in skl_commit_modeset_enables() the
enabling order is not always crescent, possibly causing previously
selected slave transcoder being enabled before master so another
approach will be needed to select a transcoder to master in MST mode.
It will be similar to the approach taken in port sync.

But instead of implement something like
intel_trans_port_sync_modeset_disables() to MST lets simply it and
iterate over all pipes 2 times, the first one disabling any slave and
then disabling everything else.
The MST bits will be added in another patch.

Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 79 ++++++--------------
 1 file changed, 22 insertions(+), 57 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 53dc310a5f6d..1b1fbb6d8acc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14443,53 +14443,16 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
 		dev_priv->display.initial_watermarks(state, crtc);
 }
 
-static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state *state,
-						   struct intel_crtc *crtc,
-						   struct intel_crtc_state *old_crtc_state,
-						   struct intel_crtc_state *new_crtc_state)
-{
-	struct intel_crtc *slave_crtc = intel_get_slave_crtc(new_crtc_state);
-	struct intel_crtc_state *new_slave_crtc_state =
-		intel_atomic_get_new_crtc_state(state, slave_crtc);
-	struct intel_crtc_state *old_slave_crtc_state =
-		intel_atomic_get_old_crtc_state(state, slave_crtc);
-
-	WARN_ON(!slave_crtc || !new_slave_crtc_state ||
-		!old_slave_crtc_state);
-
-	/* Disable Slave first */
-	intel_pre_plane_update(old_slave_crtc_state, new_slave_crtc_state);
-	if (old_slave_crtc_state->hw.active)
-		intel_old_crtc_state_disables(state,
-					      old_slave_crtc_state,
-					      new_slave_crtc_state,
-					      slave_crtc);
-
-	/* Disable Master */
-	intel_pre_plane_update(old_crtc_state, new_crtc_state);
-	if (old_crtc_state->hw.active)
-		intel_old_crtc_state_disables(state,
-					      old_crtc_state,
-					      new_crtc_state,
-					      crtc);
-}
-
 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
 {
 	struct intel_crtc_state *new_crtc_state, *old_crtc_state;
 	struct intel_crtc *crtc;
 	int i;
 
-	/*
-	 * Disable CRTC/pipes in reverse order because some features(MST in
-	 * TGL+) requires master and slave relationship between pipes, so it
-	 * should always pick the lowest pipe as master as it will be enabled
-	 * first and disable in the reverse order so the master will be the
-	 * last one to be disabled.
-	 */
-	for_each_oldnew_intel_crtc_in_state_reverse(state, crtc, old_crtc_state,
-						    new_crtc_state, i) {
-		if (!needs_modeset(new_crtc_state))
+	/* Only disable port sync slaves */
+	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+					    new_crtc_state, i) {
+		if (!needs_modeset(new_crtc_state) || !crtc->active)
 			continue;
 
 		/* In case of Transcoder port Sync master slave CRTCs can be
@@ -14497,23 +14460,25 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
 		 * slave CRTCs are disabled first and then master CRTC since
 		 * Slave vblanks are masked till Master Vblanks.
 		 */
-		if (is_trans_port_sync_mode(new_crtc_state)) {
-			if (is_trans_port_sync_master(new_crtc_state))
-				intel_trans_port_sync_modeset_disables(state,
-								       crtc,
-								       old_crtc_state,
-								       new_crtc_state);
-			else
-				continue;
-		} else {
-			intel_pre_plane_update(old_crtc_state, new_crtc_state);
+		if (!is_trans_port_sync_mode(new_crtc_state))
+			continue;
+		if (is_trans_port_sync_master(new_crtc_state))
+			continue;
 
-			if (old_crtc_state->hw.active)
-				intel_old_crtc_state_disables(state,
-							      old_crtc_state,
-							      new_crtc_state,
-							      crtc);
-		}
+		intel_pre_plane_update(old_crtc_state, new_crtc_state);
+		intel_old_crtc_state_disables(state, old_crtc_state,
+					      new_crtc_state, crtc);
+	}
+
+	/* Disable everything else left on */
+	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+					    new_crtc_state, i) {
+		if (!needs_modeset(new_crtc_state) || !crtc->active)
+			continue;
+
+		intel_pre_plane_update(old_crtc_state, new_crtc_state);
+		intel_old_crtc_state_disables(state, old_crtc_state,
+					      new_crtc_state, crtc);
 	}
 }
 
-- 
2.24.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 16+ messages in thread

* [PATCH 2/3] drm/i915/display: Check the old state to find port sync slave
@ 2019-11-20 23:48   ` José Roberto de Souza
  0 siblings, 0 replies; 16+ messages in thread
From: José Roberto de Souza @ 2019-11-20 23:48 UTC (permalink / raw)
  To: intel-gfx

If the CRTC is going from enabled to disabled and it is a port sync
slave, it needs to check to the old state to be disabled before the
port sync master.

Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1b1fbb6d8acc..801b975c7d39 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14460,9 +14460,9 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
 		 * slave CRTCs are disabled first and then master CRTC since
 		 * Slave vblanks are masked till Master Vblanks.
 		 */
-		if (!is_trans_port_sync_mode(new_crtc_state))
+		if (!is_trans_port_sync_mode(old_crtc_state))
 			continue;
-		if (is_trans_port_sync_master(new_crtc_state))
+		if (is_trans_port_sync_master(old_crtc_state))
 			continue;
 
 		intel_pre_plane_update(old_crtc_state, new_crtc_state);
-- 
2.24.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 16+ messages in thread

* [Intel-gfx] [PATCH 2/3] drm/i915/display: Check the old state to find port sync slave
@ 2019-11-20 23:48   ` José Roberto de Souza
  0 siblings, 0 replies; 16+ messages in thread
From: José Roberto de Souza @ 2019-11-20 23:48 UTC (permalink / raw)
  To: intel-gfx

If the CRTC is going from enabled to disabled and it is a port sync
slave, it needs to check to the old state to be disabled before the
port sync master.

Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1b1fbb6d8acc..801b975c7d39 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14460,9 +14460,9 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
 		 * slave CRTCs are disabled first and then master CRTC since
 		 * Slave vblanks are masked till Master Vblanks.
 		 */
-		if (!is_trans_port_sync_mode(new_crtc_state))
+		if (!is_trans_port_sync_mode(old_crtc_state))
 			continue;
-		if (is_trans_port_sync_master(new_crtc_state))
+		if (is_trans_port_sync_master(old_crtc_state))
 			continue;
 
 		intel_pre_plane_update(old_crtc_state, new_crtc_state);
-- 
2.24.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 16+ messages in thread

* [PATCH 3/3] drm/i915/tgl: Select master trasconder for MST stream
@ 2019-11-20 23:48   ` José Roberto de Souza
  0 siblings, 0 replies; 16+ messages in thread
From: José Roberto de Souza @ 2019-11-20 23:48 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

On TGL the blending of all the streams have moved from DDI to
transcoder, so now every transcoder working over the same MST port must
send its stream to a master transcoder and master will send to DDI
respecting the time slots.

A previous approach was using the lowest pipe/transcoder as master
transcoder but as the comment in skl_commit_modeset_enables() states,
that is not always true.

So here promoting the first pipe/transcoder of the stream as master.
That caused several other problems as during the commit phase the
state computed should not be changed.

So the master transcoder is store into intel_dp and the modeset in
slave pipes/transcoders is forced using mst_master_trans_pending.

BSpec: 50493
BSpec: 49190
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      |   9 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  58 +++++++++-
 .../drm/i915/display/intel_display_types.h    |   3 +
 drivers/gpu/drm/i915/display/intel_dp.c       |   1 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 109 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp_mst.h   |   2 +
 6 files changed, 175 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a976606d21c7..5d076c84f253 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -35,6 +35,7 @@
 #include "intel_display_types.h"
 #include "intel_dp.h"
 #include "intel_dp_link_training.h"
+#include "intel_dp_mst.h"
 #include "intel_dpio_phy.h"
 #include "intel_dsi.h"
 #include "intel_fifo_underrun.h"
@@ -1903,8 +1904,12 @@ intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
 		temp |= TRANS_DDI_MODE_SELECT_DP_MST;
 		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
 
-		if (INTEL_GEN(dev_priv) >= 12)
-			temp |= TRANS_DDI_MST_TRANSPORT_SELECT(crtc_state->cpu_transcoder);
+		if (INTEL_GEN(dev_priv) >= 12) {
+			enum transcoder master;
+
+			master = intel_dp_mst_master_trans_get(encoder);
+			temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
+		}
 	} else {
 		temp |= TRANS_DDI_MODE_SELECT_DP_SST;
 		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 801b975c7d39..35a59108194e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -46,6 +46,7 @@
 #include "display/intel_crt.h"
 #include "display/intel_ddi.h"
 #include "display/intel_dp.h"
+#include "display/intel_dp_mst.h"
 #include "display/intel_dsi.h"
 #include "display/intel_dvo.h"
 #include "display/intel_gmbus.h"
@@ -5365,6 +5366,36 @@ intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
 	return encoder;
 }
 
+/*
+ * Finds the encoder associated with the given CRTC. This can only be
+ * used when we know that the CRTC isn't feeding multiple encoders!
+ */
+static struct intel_encoder *
+intel_get_crtc_old_encoder(const struct intel_atomic_state *state,
+			   const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	const struct drm_connector_state *connector_state;
+	const struct drm_connector *connector;
+	struct intel_encoder *encoder = NULL;
+	int num_encoders = 0;
+	int i;
+
+	for_each_old_connector_in_state(&state->base, connector,
+					connector_state, i) {
+		if (connector_state->crtc != &crtc->base)
+			continue;
+
+		encoder = to_intel_encoder(connector_state->best_encoder);
+		num_encoders++;
+	}
+
+	WARN(num_encoders != 1, "%d encoders for pipe %c\n",
+	     num_encoders, pipe_name(crtc->pipe));
+
+	return encoder;
+}
+
 /*
  * Enable PCH resources required for PCH ports:
  *   - PCH PLLs
@@ -13365,6 +13396,12 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 #undef PIPE_CONF_CHECK_COLOR_LUT
 #undef PIPE_CONF_QUIRK
 
+	if (fastset && pipe_config->mst_master_trans_pending) {
+		DRM_DEBUG_KMS("[CRTC:%d:%s] fastset mismatch in mst_master_trans\n",
+			      crtc->base.base.id, crtc->base.name);
+		ret = false;
+	}
+
 	return ret;
 }
 
@@ -14449,22 +14486,35 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
 	struct intel_crtc *crtc;
 	int i;
 
-	/* Only disable port sync slaves */
+	/* Only disable port sync and MST slaves */
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
 					    new_crtc_state, i) {
 		if (!needs_modeset(new_crtc_state) || !crtc->active)
 			continue;
 
+		if (!is_trans_port_sync_mode(new_crtc_state) &&
+		    !intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
+			continue;
+
 		/* In case of Transcoder port Sync master slave CRTCs can be
 		 * assigned in any order and we need to make sure that
 		 * slave CRTCs are disabled first and then master CRTC since
 		 * Slave vblanks are masked till Master Vblanks.
 		 */
-		if (!is_trans_port_sync_mode(old_crtc_state))
-			continue;
-		if (is_trans_port_sync_master(old_crtc_state))
+		if (is_trans_port_sync_mode(new_crtc_state) &&
+		    is_trans_port_sync_master(new_crtc_state))
 			continue;
 
+		if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) {
+			struct intel_encoder *encoder;
+
+			encoder = intel_get_crtc_old_encoder(state,
+							     old_crtc_state);
+			if (intel_dp_mst_master_trans_get(encoder) ==
+			    old_crtc_state->cpu_transcoder)
+				continue;
+		}
+
 		intel_pre_plane_update(old_crtc_state, new_crtc_state);
 		intel_old_crtc_state_disables(state, old_crtc_state,
 					      new_crtc_state, crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 83ea04149b77..23d747cdca64 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1052,6 +1052,8 @@ struct intel_crtc_state {
 	/* Pointer to master transcoder in case of tiled displays */
 	enum transcoder master_transcoder;
 
+	bool mst_master_trans_pending;
+
 	/* Bitmask to indicate slaves attached */
 	u8 sync_mode_slaves_mask;
 };
@@ -1284,6 +1286,7 @@ struct intel_dp {
 	bool can_mst; /* this port supports mst */
 	bool is_mst;
 	int active_mst_links;
+	enum transcoder mst_master_transcoder; /* Only used in TGL+ */
 
 	/*
 	 * DP_TP_* registers may be either on port or transcoder register space.
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3123958e2081..ceff6901451a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7424,6 +7424,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 	intel_dp->reset_link_params = true;
 	intel_dp->pps_pipe = INVALID_PIPE;
 	intel_dp->active_pipe = INVALID_PIPE;
+	intel_dp->mst_master_transcoder = INVALID_TRANSCODER;
 
 	/* Preserve the current hw state. */
 	intel_dp->DP = I915_READ(intel_dp->output_reg);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index f8a350359346..38739d565751 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -157,6 +157,95 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
 	return 0;
 }
 
+static int
+intel_dp_mst_atomic_master_trans_check(struct drm_connector *connector,
+				       struct drm_atomic_state *state)
+{
+	struct drm_i915_private *dev_priv = to_i915(connector->dev);
+	struct intel_connector *intel_conn = to_intel_connector(connector);
+	struct drm_connector_state *new_conn_state, *old_conn_state;
+	struct drm_connector_list_iter conn_list_iter;
+	struct intel_crtc_state *intel_crtc_state;
+	struct drm_crtc_state *crtc_state;
+	struct drm_connector *conn_iter;
+
+	if (INTEL_GEN(dev_priv) < 12)
+		return 0;
+
+	new_conn_state = drm_atomic_get_new_connector_state(state, connector);
+	old_conn_state = drm_atomic_get_old_connector_state(state, connector);
+
+	if (!old_conn_state->crtc && !new_conn_state->crtc)
+		return 0;
+
+	/*
+	 * 3 cases that needs be handled here:
+	 * - connector going from disabled to enabled
+	 * - connector going from enabled to disabled:
+	 * if this transcoder was the master, all slaves needs a modeset
+	 * - connector going from enabled to enabled but it needs a modeset:
+	 * if this transcoder was the master, all slaves also needs a modeset
+	 */
+
+	/* disabled -> enabled */
+	if (!old_conn_state->crtc && new_conn_state->crtc) {
+		crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
+		intel_crtc_state = to_intel_crtc_state(crtc_state);
+		intel_crtc_state->mst_master_trans_pending = true;
+		return 0;
+	}
+
+	/* enabled -> enabled(modeset)? */
+	if (new_conn_state->crtc) {
+		crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
+		if (!drm_atomic_crtc_needs_modeset(crtc_state))
+			return 0;
+	}
+
+	/* handling enabled -> enabled(modeset) and enabled -> disabled */
+	crtc_state = drm_atomic_get_old_crtc_state(state, old_conn_state->crtc);
+	intel_crtc_state = to_intel_crtc_state(crtc_state);
+
+	/* If not master, nothing else needs to be handled */
+	if (intel_conn->mst_port->mst_master_transcoder !=
+	    intel_crtc_state->cpu_transcoder)
+		return 0;
+
+	/* Is master, mark all other CRTCs as needing a modeset */
+	drm_connector_list_iter_begin(state->dev, &conn_list_iter);
+	drm_for_each_connector_iter(conn_iter, &conn_list_iter) {
+		struct intel_connector *intel_conn_iter;
+		struct drm_connector_state *conn_iter_state;
+
+		intel_conn_iter = to_intel_connector(conn_iter);
+		if (intel_conn_iter->mst_port != intel_conn->mst_port)
+			continue;
+
+		conn_iter_state = drm_atomic_get_connector_state(state,
+								 conn_iter);
+		if (IS_ERR(conn_iter_state)) {
+			drm_connector_list_iter_end(&conn_list_iter);
+			return PTR_ERR(conn_iter_state);
+		}
+
+		if (!conn_iter_state->crtc)
+			continue;
+
+		crtc_state = drm_atomic_get_crtc_state(state, conn_iter_state->crtc);
+		if (IS_ERR(crtc_state)) {
+			drm_connector_list_iter_end(&conn_list_iter);
+			return PTR_ERR(conn_iter_state);
+		}
+
+		intel_crtc_state = to_intel_crtc_state(crtc_state);
+		intel_crtc_state->mst_master_trans_pending = true;
+		crtc_state->mode_changed = true;
+	}
+	drm_connector_list_iter_end(&conn_list_iter);
+
+	return 0;
+}
+
 static int
 intel_dp_mst_atomic_check(struct drm_connector *connector,
 			  struct drm_atomic_state *state)
@@ -175,6 +264,10 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
 	if (ret)
 		return ret;
 
+	ret = intel_dp_mst_atomic_master_trans_check(connector, state);
+	if (ret)
+		return ret;
+
 	if (!old_conn_state->crtc)
 		return 0;
 
@@ -259,6 +352,7 @@ static void intel_mst_post_disable_dp(struct intel_encoder *encoder,
 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
 		intel_dig_port->base.post_disable(&intel_dig_port->base,
 						  old_crtc_state, NULL);
+		intel_dp->mst_master_transcoder = INVALID_TRANSCODER;
 	}
 
 	DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
@@ -314,8 +408,11 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
 
 	DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
 
-	if (first_mst_stream)
+	if (first_mst_stream) {
+		WARN_ON(intel_dp->mst_master_transcoder != INVALID_TRANSCODER);
+		intel_dp->mst_master_transcoder = pipe_config->cpu_transcoder;
 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+	}
 
 	drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
 
@@ -717,3 +814,13 @@ intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port)
 	drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr);
 	/* encoders will get killed by normal cleanup */
 }
+
+enum transcoder
+intel_dp_mst_master_trans_get(struct intel_encoder *encoder)
+{
+	struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
+	struct intel_dp *intel_dp = &intel_mst->primary->dp;
+
+	WARN_ON(intel_dp->mst_master_transcoder == INVALID_TRANSCODER);
+	return intel_dp->mst_master_transcoder;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.h b/drivers/gpu/drm/i915/display/intel_dp_mst.h
index f660ad80db04..e6f28a517182 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.h
@@ -7,9 +7,11 @@
 #define __INTEL_DP_MST_H__
 
 struct intel_digital_port;
+struct intel_encoder;
 
 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
 int intel_dp_mst_encoder_active_links(struct intel_digital_port *intel_dig_port);
+enum transcoder intel_dp_mst_master_trans_get(struct intel_encoder *encoder);
 
 #endif /* __INTEL_DP_MST_H__ */
-- 
2.24.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 16+ messages in thread

* [Intel-gfx] [PATCH 3/3] drm/i915/tgl: Select master trasconder for MST stream
@ 2019-11-20 23:48   ` José Roberto de Souza
  0 siblings, 0 replies; 16+ messages in thread
From: José Roberto de Souza @ 2019-11-20 23:48 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

On TGL the blending of all the streams have moved from DDI to
transcoder, so now every transcoder working over the same MST port must
send its stream to a master transcoder and master will send to DDI
respecting the time slots.

A previous approach was using the lowest pipe/transcoder as master
transcoder but as the comment in skl_commit_modeset_enables() states,
that is not always true.

So here promoting the first pipe/transcoder of the stream as master.
That caused several other problems as during the commit phase the
state computed should not be changed.

So the master transcoder is store into intel_dp and the modeset in
slave pipes/transcoders is forced using mst_master_trans_pending.

BSpec: 50493
BSpec: 49190
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      |   9 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  58 +++++++++-
 .../drm/i915/display/intel_display_types.h    |   3 +
 drivers/gpu/drm/i915/display/intel_dp.c       |   1 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 109 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp_mst.h   |   2 +
 6 files changed, 175 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a976606d21c7..5d076c84f253 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -35,6 +35,7 @@
 #include "intel_display_types.h"
 #include "intel_dp.h"
 #include "intel_dp_link_training.h"
+#include "intel_dp_mst.h"
 #include "intel_dpio_phy.h"
 #include "intel_dsi.h"
 #include "intel_fifo_underrun.h"
@@ -1903,8 +1904,12 @@ intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
 		temp |= TRANS_DDI_MODE_SELECT_DP_MST;
 		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
 
-		if (INTEL_GEN(dev_priv) >= 12)
-			temp |= TRANS_DDI_MST_TRANSPORT_SELECT(crtc_state->cpu_transcoder);
+		if (INTEL_GEN(dev_priv) >= 12) {
+			enum transcoder master;
+
+			master = intel_dp_mst_master_trans_get(encoder);
+			temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
+		}
 	} else {
 		temp |= TRANS_DDI_MODE_SELECT_DP_SST;
 		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 801b975c7d39..35a59108194e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -46,6 +46,7 @@
 #include "display/intel_crt.h"
 #include "display/intel_ddi.h"
 #include "display/intel_dp.h"
+#include "display/intel_dp_mst.h"
 #include "display/intel_dsi.h"
 #include "display/intel_dvo.h"
 #include "display/intel_gmbus.h"
@@ -5365,6 +5366,36 @@ intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
 	return encoder;
 }
 
+/*
+ * Finds the encoder associated with the given CRTC. This can only be
+ * used when we know that the CRTC isn't feeding multiple encoders!
+ */
+static struct intel_encoder *
+intel_get_crtc_old_encoder(const struct intel_atomic_state *state,
+			   const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	const struct drm_connector_state *connector_state;
+	const struct drm_connector *connector;
+	struct intel_encoder *encoder = NULL;
+	int num_encoders = 0;
+	int i;
+
+	for_each_old_connector_in_state(&state->base, connector,
+					connector_state, i) {
+		if (connector_state->crtc != &crtc->base)
+			continue;
+
+		encoder = to_intel_encoder(connector_state->best_encoder);
+		num_encoders++;
+	}
+
+	WARN(num_encoders != 1, "%d encoders for pipe %c\n",
+	     num_encoders, pipe_name(crtc->pipe));
+
+	return encoder;
+}
+
 /*
  * Enable PCH resources required for PCH ports:
  *   - PCH PLLs
@@ -13365,6 +13396,12 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 #undef PIPE_CONF_CHECK_COLOR_LUT
 #undef PIPE_CONF_QUIRK
 
+	if (fastset && pipe_config->mst_master_trans_pending) {
+		DRM_DEBUG_KMS("[CRTC:%d:%s] fastset mismatch in mst_master_trans\n",
+			      crtc->base.base.id, crtc->base.name);
+		ret = false;
+	}
+
 	return ret;
 }
 
@@ -14449,22 +14486,35 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
 	struct intel_crtc *crtc;
 	int i;
 
-	/* Only disable port sync slaves */
+	/* Only disable port sync and MST slaves */
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
 					    new_crtc_state, i) {
 		if (!needs_modeset(new_crtc_state) || !crtc->active)
 			continue;
 
+		if (!is_trans_port_sync_mode(new_crtc_state) &&
+		    !intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
+			continue;
+
 		/* In case of Transcoder port Sync master slave CRTCs can be
 		 * assigned in any order and we need to make sure that
 		 * slave CRTCs are disabled first and then master CRTC since
 		 * Slave vblanks are masked till Master Vblanks.
 		 */
-		if (!is_trans_port_sync_mode(old_crtc_state))
-			continue;
-		if (is_trans_port_sync_master(old_crtc_state))
+		if (is_trans_port_sync_mode(new_crtc_state) &&
+		    is_trans_port_sync_master(new_crtc_state))
 			continue;
 
+		if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) {
+			struct intel_encoder *encoder;
+
+			encoder = intel_get_crtc_old_encoder(state,
+							     old_crtc_state);
+			if (intel_dp_mst_master_trans_get(encoder) ==
+			    old_crtc_state->cpu_transcoder)
+				continue;
+		}
+
 		intel_pre_plane_update(old_crtc_state, new_crtc_state);
 		intel_old_crtc_state_disables(state, old_crtc_state,
 					      new_crtc_state, crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 83ea04149b77..23d747cdca64 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1052,6 +1052,8 @@ struct intel_crtc_state {
 	/* Pointer to master transcoder in case of tiled displays */
 	enum transcoder master_transcoder;
 
+	bool mst_master_trans_pending;
+
 	/* Bitmask to indicate slaves attached */
 	u8 sync_mode_slaves_mask;
 };
@@ -1284,6 +1286,7 @@ struct intel_dp {
 	bool can_mst; /* this port supports mst */
 	bool is_mst;
 	int active_mst_links;
+	enum transcoder mst_master_transcoder; /* Only used in TGL+ */
 
 	/*
 	 * DP_TP_* registers may be either on port or transcoder register space.
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3123958e2081..ceff6901451a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7424,6 +7424,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 	intel_dp->reset_link_params = true;
 	intel_dp->pps_pipe = INVALID_PIPE;
 	intel_dp->active_pipe = INVALID_PIPE;
+	intel_dp->mst_master_transcoder = INVALID_TRANSCODER;
 
 	/* Preserve the current hw state. */
 	intel_dp->DP = I915_READ(intel_dp->output_reg);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index f8a350359346..38739d565751 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -157,6 +157,95 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
 	return 0;
 }
 
+static int
+intel_dp_mst_atomic_master_trans_check(struct drm_connector *connector,
+				       struct drm_atomic_state *state)
+{
+	struct drm_i915_private *dev_priv = to_i915(connector->dev);
+	struct intel_connector *intel_conn = to_intel_connector(connector);
+	struct drm_connector_state *new_conn_state, *old_conn_state;
+	struct drm_connector_list_iter conn_list_iter;
+	struct intel_crtc_state *intel_crtc_state;
+	struct drm_crtc_state *crtc_state;
+	struct drm_connector *conn_iter;
+
+	if (INTEL_GEN(dev_priv) < 12)
+		return 0;
+
+	new_conn_state = drm_atomic_get_new_connector_state(state, connector);
+	old_conn_state = drm_atomic_get_old_connector_state(state, connector);
+
+	if (!old_conn_state->crtc && !new_conn_state->crtc)
+		return 0;
+
+	/*
+	 * 3 cases that needs be handled here:
+	 * - connector going from disabled to enabled
+	 * - connector going from enabled to disabled:
+	 * if this transcoder was the master, all slaves needs a modeset
+	 * - connector going from enabled to enabled but it needs a modeset:
+	 * if this transcoder was the master, all slaves also needs a modeset
+	 */
+
+	/* disabled -> enabled */
+	if (!old_conn_state->crtc && new_conn_state->crtc) {
+		crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
+		intel_crtc_state = to_intel_crtc_state(crtc_state);
+		intel_crtc_state->mst_master_trans_pending = true;
+		return 0;
+	}
+
+	/* enabled -> enabled(modeset)? */
+	if (new_conn_state->crtc) {
+		crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
+		if (!drm_atomic_crtc_needs_modeset(crtc_state))
+			return 0;
+	}
+
+	/* handling enabled -> enabled(modeset) and enabled -> disabled */
+	crtc_state = drm_atomic_get_old_crtc_state(state, old_conn_state->crtc);
+	intel_crtc_state = to_intel_crtc_state(crtc_state);
+
+	/* If not master, nothing else needs to be handled */
+	if (intel_conn->mst_port->mst_master_transcoder !=
+	    intel_crtc_state->cpu_transcoder)
+		return 0;
+
+	/* Is master, mark all other CRTCs as needing a modeset */
+	drm_connector_list_iter_begin(state->dev, &conn_list_iter);
+	drm_for_each_connector_iter(conn_iter, &conn_list_iter) {
+		struct intel_connector *intel_conn_iter;
+		struct drm_connector_state *conn_iter_state;
+
+		intel_conn_iter = to_intel_connector(conn_iter);
+		if (intel_conn_iter->mst_port != intel_conn->mst_port)
+			continue;
+
+		conn_iter_state = drm_atomic_get_connector_state(state,
+								 conn_iter);
+		if (IS_ERR(conn_iter_state)) {
+			drm_connector_list_iter_end(&conn_list_iter);
+			return PTR_ERR(conn_iter_state);
+		}
+
+		if (!conn_iter_state->crtc)
+			continue;
+
+		crtc_state = drm_atomic_get_crtc_state(state, conn_iter_state->crtc);
+		if (IS_ERR(crtc_state)) {
+			drm_connector_list_iter_end(&conn_list_iter);
+			return PTR_ERR(conn_iter_state);
+		}
+
+		intel_crtc_state = to_intel_crtc_state(crtc_state);
+		intel_crtc_state->mst_master_trans_pending = true;
+		crtc_state->mode_changed = true;
+	}
+	drm_connector_list_iter_end(&conn_list_iter);
+
+	return 0;
+}
+
 static int
 intel_dp_mst_atomic_check(struct drm_connector *connector,
 			  struct drm_atomic_state *state)
@@ -175,6 +264,10 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
 	if (ret)
 		return ret;
 
+	ret = intel_dp_mst_atomic_master_trans_check(connector, state);
+	if (ret)
+		return ret;
+
 	if (!old_conn_state->crtc)
 		return 0;
 
@@ -259,6 +352,7 @@ static void intel_mst_post_disable_dp(struct intel_encoder *encoder,
 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
 		intel_dig_port->base.post_disable(&intel_dig_port->base,
 						  old_crtc_state, NULL);
+		intel_dp->mst_master_transcoder = INVALID_TRANSCODER;
 	}
 
 	DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
@@ -314,8 +408,11 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
 
 	DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
 
-	if (first_mst_stream)
+	if (first_mst_stream) {
+		WARN_ON(intel_dp->mst_master_transcoder != INVALID_TRANSCODER);
+		intel_dp->mst_master_transcoder = pipe_config->cpu_transcoder;
 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+	}
 
 	drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
 
@@ -717,3 +814,13 @@ intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port)
 	drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr);
 	/* encoders will get killed by normal cleanup */
 }
+
+enum transcoder
+intel_dp_mst_master_trans_get(struct intel_encoder *encoder)
+{
+	struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
+	struct intel_dp *intel_dp = &intel_mst->primary->dp;
+
+	WARN_ON(intel_dp->mst_master_transcoder == INVALID_TRANSCODER);
+	return intel_dp->mst_master_transcoder;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.h b/drivers/gpu/drm/i915/display/intel_dp_mst.h
index f660ad80db04..e6f28a517182 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.h
@@ -7,9 +7,11 @@
 #define __INTEL_DP_MST_H__
 
 struct intel_digital_port;
+struct intel_encoder;
 
 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
 int intel_dp_mst_encoder_active_links(struct intel_digital_port *intel_dig_port);
+enum transcoder intel_dp_mst_master_trans_get(struct intel_encoder *encoder);
 
 #endif /* __INTEL_DP_MST_H__ */
-- 
2.24.0

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^ permalink raw reply related	[flat|nested] 16+ messages in thread

* Re: [PATCH 3/3] drm/i915/tgl: Select master trasconder for MST stream
@ 2019-11-21  1:53     ` Souza, Jose
  0 siblings, 0 replies; 16+ messages in thread
From: Souza, Jose @ 2019-11-21  1:53 UTC (permalink / raw)
  To: intel-gfx; +Cc: De Marchi, Lucas

Please ignore this patch for now, it is missing one step in the
connector config compute phase.

On Wed, 2019-11-20 at 15:48 -0800, José Roberto de Souza wrote:
> On TGL the blending of all the streams have moved from DDI to
> transcoder, so now every transcoder working over the same MST port
> must
> send its stream to a master transcoder and master will send to DDI
> respecting the time slots.
> 
> A previous approach was using the lowest pipe/transcoder as master
> transcoder but as the comment in skl_commit_modeset_enables() states,
> that is not always true.
> 
> So here promoting the first pipe/transcoder of the stream as master.
> That caused several other problems as during the commit phase the
> state computed should not be changed.
> 
> So the master transcoder is store into intel_dp and the modeset in
> slave pipes/transcoders is forced using mst_master_trans_pending.
> 
> BSpec: 50493
> BSpec: 49190
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c      |   9 +-
>  drivers/gpu/drm/i915/display/intel_display.c  |  58 +++++++++-
>  .../drm/i915/display/intel_display_types.h    |   3 +
>  drivers/gpu/drm/i915/display/intel_dp.c       |   1 +
>  drivers/gpu/drm/i915/display/intel_dp_mst.c   | 109
> +++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_dp_mst.h   |   2 +
>  6 files changed, 175 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index a976606d21c7..5d076c84f253 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -35,6 +35,7 @@
>  #include "intel_display_types.h"
>  #include "intel_dp.h"
>  #include "intel_dp_link_training.h"
> +#include "intel_dp_mst.h"
>  #include "intel_dpio_phy.h"
>  #include "intel_dsi.h"
>  #include "intel_fifo_underrun.h"
> @@ -1903,8 +1904,12 @@ intel_ddi_transcoder_func_reg_val_get(const
> struct intel_crtc_state *crtc_state)
>  		temp |= TRANS_DDI_MODE_SELECT_DP_MST;
>  		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
>  
> -		if (INTEL_GEN(dev_priv) >= 12)
> -			temp |=
> TRANS_DDI_MST_TRANSPORT_SELECT(crtc_state->cpu_transcoder);
> +		if (INTEL_GEN(dev_priv) >= 12) {
> +			enum transcoder master;
> +
> +			master =
> intel_dp_mst_master_trans_get(encoder);
> +			temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
> +		}
>  	} else {
>  		temp |= TRANS_DDI_MODE_SELECT_DP_SST;
>  		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 801b975c7d39..35a59108194e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -46,6 +46,7 @@
>  #include "display/intel_crt.h"
>  #include "display/intel_ddi.h"
>  #include "display/intel_dp.h"
> +#include "display/intel_dp_mst.h"
>  #include "display/intel_dsi.h"
>  #include "display/intel_dvo.h"
>  #include "display/intel_gmbus.h"
> @@ -5365,6 +5366,36 @@ intel_get_crtc_new_encoder(const struct
> intel_atomic_state *state,
>  	return encoder;
>  }
>  
> +/*
> + * Finds the encoder associated with the given CRTC. This can only
> be
> + * used when we know that the CRTC isn't feeding multiple encoders!
> + */
> +static struct intel_encoder *
> +intel_get_crtc_old_encoder(const struct intel_atomic_state *state,
> +			   const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	const struct drm_connector_state *connector_state;
> +	const struct drm_connector *connector;
> +	struct intel_encoder *encoder = NULL;
> +	int num_encoders = 0;
> +	int i;
> +
> +	for_each_old_connector_in_state(&state->base, connector,
> +					connector_state, i) {
> +		if (connector_state->crtc != &crtc->base)
> +			continue;
> +
> +		encoder = to_intel_encoder(connector_state-
> >best_encoder);
> +		num_encoders++;
> +	}
> +
> +	WARN(num_encoders != 1, "%d encoders for pipe %c\n",
> +	     num_encoders, pipe_name(crtc->pipe));
> +
> +	return encoder;
> +}
> +
>  /*
>   * Enable PCH resources required for PCH ports:
>   *   - PCH PLLs
> @@ -13365,6 +13396,12 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
>  #undef PIPE_CONF_CHECK_COLOR_LUT
>  #undef PIPE_CONF_QUIRK
>  
> +	if (fastset && pipe_config->mst_master_trans_pending) {
> +		DRM_DEBUG_KMS("[CRTC:%d:%s] fastset mismatch in
> mst_master_trans\n",
> +			      crtc->base.base.id, crtc->base.name);
> +		ret = false;
> +	}
> +
>  	return ret;
>  }
>  
> @@ -14449,22 +14486,35 @@ static void
> intel_commit_modeset_disables(struct intel_atomic_state *state)
>  	struct intel_crtc *crtc;
>  	int i;
>  
> -	/* Only disable port sync slaves */
> +	/* Only disable port sync and MST slaves */
>  	for_each_oldnew_intel_crtc_in_state(state, crtc,
> old_crtc_state,
>  					    new_crtc_state, i) {
>  		if (!needs_modeset(new_crtc_state) || !crtc->active)
>  			continue;
>  
> +		if (!is_trans_port_sync_mode(new_crtc_state) &&
> +		    !intel_crtc_has_type(old_crtc_state,
> INTEL_OUTPUT_DP_MST))
> +			continue;
> +
>  		/* In case of Transcoder port Sync master slave CRTCs
> can be
>  		 * assigned in any order and we need to make sure that
>  		 * slave CRTCs are disabled first and then master CRTC
> since
>  		 * Slave vblanks are masked till Master Vblanks.
>  		 */
> -		if (!is_trans_port_sync_mode(old_crtc_state))
> -			continue;
> -		if (is_trans_port_sync_master(old_crtc_state))
> +		if (is_trans_port_sync_mode(new_crtc_state) &&
> +		    is_trans_port_sync_master(new_crtc_state))
>  			continue;
>  
> +		if (intel_crtc_has_type(old_crtc_state,
> INTEL_OUTPUT_DP_MST)) {
> +			struct intel_encoder *encoder;
> +
> +			encoder = intel_get_crtc_old_encoder(state,
> +							     old_crtc_s
> tate);
> +			if (intel_dp_mst_master_trans_get(encoder) ==
> +			    old_crtc_state->cpu_transcoder)
> +				continue;
> +		}
> +
>  		intel_pre_plane_update(old_crtc_state, new_crtc_state);
>  		intel_old_crtc_state_disables(state, old_crtc_state,
>  					      new_crtc_state, crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 83ea04149b77..23d747cdca64 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1052,6 +1052,8 @@ struct intel_crtc_state {
>  	/* Pointer to master transcoder in case of tiled displays */
>  	enum transcoder master_transcoder;
>  
> +	bool mst_master_trans_pending;
> +
>  	/* Bitmask to indicate slaves attached */
>  	u8 sync_mode_slaves_mask;
>  };
> @@ -1284,6 +1286,7 @@ struct intel_dp {
>  	bool can_mst; /* this port supports mst */
>  	bool is_mst;
>  	int active_mst_links;
> +	enum transcoder mst_master_transcoder; /* Only used in TGL+ */
>  
>  	/*
>  	 * DP_TP_* registers may be either on port or transcoder
> register space.
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 3123958e2081..ceff6901451a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -7424,6 +7424,7 @@ intel_dp_init_connector(struct
> intel_digital_port *intel_dig_port,
>  	intel_dp->reset_link_params = true;
>  	intel_dp->pps_pipe = INVALID_PIPE;
>  	intel_dp->active_pipe = INVALID_PIPE;
> +	intel_dp->mst_master_transcoder = INVALID_TRANSCODER;
>  
>  	/* Preserve the current hw state. */
>  	intel_dp->DP = I915_READ(intel_dp->output_reg);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index f8a350359346..38739d565751 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -157,6 +157,95 @@ static int intel_dp_mst_compute_config(struct
> intel_encoder *encoder,
>  	return 0;
>  }
>  
> +static int
> +intel_dp_mst_atomic_master_trans_check(struct drm_connector
> *connector,
> +				       struct drm_atomic_state *state)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(connector->dev);
> +	struct intel_connector *intel_conn =
> to_intel_connector(connector);
> +	struct drm_connector_state *new_conn_state, *old_conn_state;
> +	struct drm_connector_list_iter conn_list_iter;
> +	struct intel_crtc_state *intel_crtc_state;
> +	struct drm_crtc_state *crtc_state;
> +	struct drm_connector *conn_iter;
> +
> +	if (INTEL_GEN(dev_priv) < 12)
> +		return 0;
> +
> +	new_conn_state = drm_atomic_get_new_connector_state(state,
> connector);
> +	old_conn_state = drm_atomic_get_old_connector_state(state,
> connector);
> +
> +	if (!old_conn_state->crtc && !new_conn_state->crtc)
> +		return 0;
> +
> +	/*
> +	 * 3 cases that needs be handled here:
> +	 * - connector going from disabled to enabled
> +	 * - connector going from enabled to disabled:
> +	 * if this transcoder was the master, all slaves needs a
> modeset
> +	 * - connector going from enabled to enabled but it needs a
> modeset:
> +	 * if this transcoder was the master, all slaves also needs a
> modeset
> +	 */
> +
> +	/* disabled -> enabled */
> +	if (!old_conn_state->crtc && new_conn_state->crtc) {
> +		crtc_state = drm_atomic_get_new_crtc_state(state,
> new_conn_state->crtc);
> +		intel_crtc_state = to_intel_crtc_state(crtc_state);
> +		intel_crtc_state->mst_master_trans_pending = true;
> +		return 0;
> +	}
> +
> +	/* enabled -> enabled(modeset)? */
> +	if (new_conn_state->crtc) {
> +		crtc_state = drm_atomic_get_new_crtc_state(state,
> new_conn_state->crtc);
> +		if (!drm_atomic_crtc_needs_modeset(crtc_state))
> +			return 0;
> +	}
> +
> +	/* handling enabled -> enabled(modeset) and enabled -> disabled
> */
> +	crtc_state = drm_atomic_get_old_crtc_state(state,
> old_conn_state->crtc);
> +	intel_crtc_state = to_intel_crtc_state(crtc_state);
> +
> +	/* If not master, nothing else needs to be handled */
> +	if (intel_conn->mst_port->mst_master_transcoder !=
> +	    intel_crtc_state->cpu_transcoder)
> +		return 0;
> +
> +	/* Is master, mark all other CRTCs as needing a modeset */
> +	drm_connector_list_iter_begin(state->dev, &conn_list_iter);
> +	drm_for_each_connector_iter(conn_iter, &conn_list_iter) {
> +		struct intel_connector *intel_conn_iter;
> +		struct drm_connector_state *conn_iter_state;
> +
> +		intel_conn_iter = to_intel_connector(conn_iter);
> +		if (intel_conn_iter->mst_port != intel_conn->mst_port)
> +			continue;
> +
> +		conn_iter_state = drm_atomic_get_connector_state(state,
> +								 conn_i
> ter);
> +		if (IS_ERR(conn_iter_state)) {
> +			drm_connector_list_iter_end(&conn_list_iter);
> +			return PTR_ERR(conn_iter_state);
> +		}
> +
> +		if (!conn_iter_state->crtc)
> +			continue;
> +
> +		crtc_state = drm_atomic_get_crtc_state(state,
> conn_iter_state->crtc);
> +		if (IS_ERR(crtc_state)) {
> +			drm_connector_list_iter_end(&conn_list_iter);
> +			return PTR_ERR(conn_iter_state);
> +		}
> +
> +		intel_crtc_state = to_intel_crtc_state(crtc_state);
> +		intel_crtc_state->mst_master_trans_pending = true;
> +		crtc_state->mode_changed = true;
> +	}
> +	drm_connector_list_iter_end(&conn_list_iter);
> +
> +	return 0;
> +}
> +
>  static int
>  intel_dp_mst_atomic_check(struct drm_connector *connector,
>  			  struct drm_atomic_state *state)
> @@ -175,6 +264,10 @@ intel_dp_mst_atomic_check(struct drm_connector
> *connector,
>  	if (ret)
>  		return ret;
>  
> +	ret = intel_dp_mst_atomic_master_trans_check(connector, state);
> +	if (ret)
> +		return ret;
> +
>  	if (!old_conn_state->crtc)
>  		return 0;
>  
> @@ -259,6 +352,7 @@ static void intel_mst_post_disable_dp(struct
> intel_encoder *encoder,
>  		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
>  		intel_dig_port->base.post_disable(&intel_dig_port-
> >base,
>  						  old_crtc_state,
> NULL);
> +		intel_dp->mst_master_transcoder = INVALID_TRANSCODER;
>  	}
>  
>  	DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
> @@ -314,8 +408,11 @@ static void intel_mst_pre_enable_dp(struct
> intel_encoder *encoder,
>  
>  	DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
>  
> -	if (first_mst_stream)
> +	if (first_mst_stream) {
> +		WARN_ON(intel_dp->mst_master_transcoder !=
> INVALID_TRANSCODER);
> +		intel_dp->mst_master_transcoder = pipe_config-
> >cpu_transcoder;
>  		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> +	}
>  
>  	drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector-
> >port, true);
>  
> @@ -717,3 +814,13 @@ intel_dp_mst_encoder_cleanup(struct
> intel_digital_port *intel_dig_port)
>  	drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr);
>  	/* encoders will get killed by normal cleanup */
>  }
> +
> +enum transcoder
> +intel_dp_mst_master_trans_get(struct intel_encoder *encoder)
> +{
> +	struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder-
> >base);
> +	struct intel_dp *intel_dp = &intel_mst->primary->dp;
> +
> +	WARN_ON(intel_dp->mst_master_transcoder == INVALID_TRANSCODER);
> +	return intel_dp->mst_master_transcoder;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.h
> b/drivers/gpu/drm/i915/display/intel_dp_mst.h
> index f660ad80db04..e6f28a517182 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.h
> @@ -7,9 +7,11 @@
>  #define __INTEL_DP_MST_H__
>  
>  struct intel_digital_port;
> +struct intel_encoder;
>  
>  int intel_dp_mst_encoder_init(struct intel_digital_port
> *intel_dig_port, int conn_id);
>  void intel_dp_mst_encoder_cleanup(struct intel_digital_port
> *intel_dig_port);
>  int intel_dp_mst_encoder_active_links(struct intel_digital_port
> *intel_dig_port);
> +enum transcoder intel_dp_mst_master_trans_get(struct intel_encoder
> *encoder);
>  
>  #endif /* __INTEL_DP_MST_H__ */
_______________________________________________
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^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [Intel-gfx] [PATCH 3/3] drm/i915/tgl: Select master trasconder for MST stream
@ 2019-11-21  1:53     ` Souza, Jose
  0 siblings, 0 replies; 16+ messages in thread
From: Souza, Jose @ 2019-11-21  1:53 UTC (permalink / raw)
  To: intel-gfx; +Cc: De Marchi, Lucas

Please ignore this patch for now, it is missing one step in the
connector config compute phase.

On Wed, 2019-11-20 at 15:48 -0800, José Roberto de Souza wrote:
> On TGL the blending of all the streams have moved from DDI to
> transcoder, so now every transcoder working over the same MST port
> must
> send its stream to a master transcoder and master will send to DDI
> respecting the time slots.
> 
> A previous approach was using the lowest pipe/transcoder as master
> transcoder but as the comment in skl_commit_modeset_enables() states,
> that is not always true.
> 
> So here promoting the first pipe/transcoder of the stream as master.
> That caused several other problems as during the commit phase the
> state computed should not be changed.
> 
> So the master transcoder is store into intel_dp and the modeset in
> slave pipes/transcoders is forced using mst_master_trans_pending.
> 
> BSpec: 50493
> BSpec: 49190
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c      |   9 +-
>  drivers/gpu/drm/i915/display/intel_display.c  |  58 +++++++++-
>  .../drm/i915/display/intel_display_types.h    |   3 +
>  drivers/gpu/drm/i915/display/intel_dp.c       |   1 +
>  drivers/gpu/drm/i915/display/intel_dp_mst.c   | 109
> +++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_dp_mst.h   |   2 +
>  6 files changed, 175 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index a976606d21c7..5d076c84f253 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -35,6 +35,7 @@
>  #include "intel_display_types.h"
>  #include "intel_dp.h"
>  #include "intel_dp_link_training.h"
> +#include "intel_dp_mst.h"
>  #include "intel_dpio_phy.h"
>  #include "intel_dsi.h"
>  #include "intel_fifo_underrun.h"
> @@ -1903,8 +1904,12 @@ intel_ddi_transcoder_func_reg_val_get(const
> struct intel_crtc_state *crtc_state)
>  		temp |= TRANS_DDI_MODE_SELECT_DP_MST;
>  		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
>  
> -		if (INTEL_GEN(dev_priv) >= 12)
> -			temp |=
> TRANS_DDI_MST_TRANSPORT_SELECT(crtc_state->cpu_transcoder);
> +		if (INTEL_GEN(dev_priv) >= 12) {
> +			enum transcoder master;
> +
> +			master =
> intel_dp_mst_master_trans_get(encoder);
> +			temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
> +		}
>  	} else {
>  		temp |= TRANS_DDI_MODE_SELECT_DP_SST;
>  		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 801b975c7d39..35a59108194e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -46,6 +46,7 @@
>  #include "display/intel_crt.h"
>  #include "display/intel_ddi.h"
>  #include "display/intel_dp.h"
> +#include "display/intel_dp_mst.h"
>  #include "display/intel_dsi.h"
>  #include "display/intel_dvo.h"
>  #include "display/intel_gmbus.h"
> @@ -5365,6 +5366,36 @@ intel_get_crtc_new_encoder(const struct
> intel_atomic_state *state,
>  	return encoder;
>  }
>  
> +/*
> + * Finds the encoder associated with the given CRTC. This can only
> be
> + * used when we know that the CRTC isn't feeding multiple encoders!
> + */
> +static struct intel_encoder *
> +intel_get_crtc_old_encoder(const struct intel_atomic_state *state,
> +			   const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	const struct drm_connector_state *connector_state;
> +	const struct drm_connector *connector;
> +	struct intel_encoder *encoder = NULL;
> +	int num_encoders = 0;
> +	int i;
> +
> +	for_each_old_connector_in_state(&state->base, connector,
> +					connector_state, i) {
> +		if (connector_state->crtc != &crtc->base)
> +			continue;
> +
> +		encoder = to_intel_encoder(connector_state-
> >best_encoder);
> +		num_encoders++;
> +	}
> +
> +	WARN(num_encoders != 1, "%d encoders for pipe %c\n",
> +	     num_encoders, pipe_name(crtc->pipe));
> +
> +	return encoder;
> +}
> +
>  /*
>   * Enable PCH resources required for PCH ports:
>   *   - PCH PLLs
> @@ -13365,6 +13396,12 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
>  #undef PIPE_CONF_CHECK_COLOR_LUT
>  #undef PIPE_CONF_QUIRK
>  
> +	if (fastset && pipe_config->mst_master_trans_pending) {
> +		DRM_DEBUG_KMS("[CRTC:%d:%s] fastset mismatch in
> mst_master_trans\n",
> +			      crtc->base.base.id, crtc->base.name);
> +		ret = false;
> +	}
> +
>  	return ret;
>  }
>  
> @@ -14449,22 +14486,35 @@ static void
> intel_commit_modeset_disables(struct intel_atomic_state *state)
>  	struct intel_crtc *crtc;
>  	int i;
>  
> -	/* Only disable port sync slaves */
> +	/* Only disable port sync and MST slaves */
>  	for_each_oldnew_intel_crtc_in_state(state, crtc,
> old_crtc_state,
>  					    new_crtc_state, i) {
>  		if (!needs_modeset(new_crtc_state) || !crtc->active)
>  			continue;
>  
> +		if (!is_trans_port_sync_mode(new_crtc_state) &&
> +		    !intel_crtc_has_type(old_crtc_state,
> INTEL_OUTPUT_DP_MST))
> +			continue;
> +
>  		/* In case of Transcoder port Sync master slave CRTCs
> can be
>  		 * assigned in any order and we need to make sure that
>  		 * slave CRTCs are disabled first and then master CRTC
> since
>  		 * Slave vblanks are masked till Master Vblanks.
>  		 */
> -		if (!is_trans_port_sync_mode(old_crtc_state))
> -			continue;
> -		if (is_trans_port_sync_master(old_crtc_state))
> +		if (is_trans_port_sync_mode(new_crtc_state) &&
> +		    is_trans_port_sync_master(new_crtc_state))
>  			continue;
>  
> +		if (intel_crtc_has_type(old_crtc_state,
> INTEL_OUTPUT_DP_MST)) {
> +			struct intel_encoder *encoder;
> +
> +			encoder = intel_get_crtc_old_encoder(state,
> +							     old_crtc_s
> tate);
> +			if (intel_dp_mst_master_trans_get(encoder) ==
> +			    old_crtc_state->cpu_transcoder)
> +				continue;
> +		}
> +
>  		intel_pre_plane_update(old_crtc_state, new_crtc_state);
>  		intel_old_crtc_state_disables(state, old_crtc_state,
>  					      new_crtc_state, crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 83ea04149b77..23d747cdca64 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1052,6 +1052,8 @@ struct intel_crtc_state {
>  	/* Pointer to master transcoder in case of tiled displays */
>  	enum transcoder master_transcoder;
>  
> +	bool mst_master_trans_pending;
> +
>  	/* Bitmask to indicate slaves attached */
>  	u8 sync_mode_slaves_mask;
>  };
> @@ -1284,6 +1286,7 @@ struct intel_dp {
>  	bool can_mst; /* this port supports mst */
>  	bool is_mst;
>  	int active_mst_links;
> +	enum transcoder mst_master_transcoder; /* Only used in TGL+ */
>  
>  	/*
>  	 * DP_TP_* registers may be either on port or transcoder
> register space.
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 3123958e2081..ceff6901451a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -7424,6 +7424,7 @@ intel_dp_init_connector(struct
> intel_digital_port *intel_dig_port,
>  	intel_dp->reset_link_params = true;
>  	intel_dp->pps_pipe = INVALID_PIPE;
>  	intel_dp->active_pipe = INVALID_PIPE;
> +	intel_dp->mst_master_transcoder = INVALID_TRANSCODER;
>  
>  	/* Preserve the current hw state. */
>  	intel_dp->DP = I915_READ(intel_dp->output_reg);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index f8a350359346..38739d565751 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -157,6 +157,95 @@ static int intel_dp_mst_compute_config(struct
> intel_encoder *encoder,
>  	return 0;
>  }
>  
> +static int
> +intel_dp_mst_atomic_master_trans_check(struct drm_connector
> *connector,
> +				       struct drm_atomic_state *state)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(connector->dev);
> +	struct intel_connector *intel_conn =
> to_intel_connector(connector);
> +	struct drm_connector_state *new_conn_state, *old_conn_state;
> +	struct drm_connector_list_iter conn_list_iter;
> +	struct intel_crtc_state *intel_crtc_state;
> +	struct drm_crtc_state *crtc_state;
> +	struct drm_connector *conn_iter;
> +
> +	if (INTEL_GEN(dev_priv) < 12)
> +		return 0;
> +
> +	new_conn_state = drm_atomic_get_new_connector_state(state,
> connector);
> +	old_conn_state = drm_atomic_get_old_connector_state(state,
> connector);
> +
> +	if (!old_conn_state->crtc && !new_conn_state->crtc)
> +		return 0;
> +
> +	/*
> +	 * 3 cases that needs be handled here:
> +	 * - connector going from disabled to enabled
> +	 * - connector going from enabled to disabled:
> +	 * if this transcoder was the master, all slaves needs a
> modeset
> +	 * - connector going from enabled to enabled but it needs a
> modeset:
> +	 * if this transcoder was the master, all slaves also needs a
> modeset
> +	 */
> +
> +	/* disabled -> enabled */
> +	if (!old_conn_state->crtc && new_conn_state->crtc) {
> +		crtc_state = drm_atomic_get_new_crtc_state(state,
> new_conn_state->crtc);
> +		intel_crtc_state = to_intel_crtc_state(crtc_state);
> +		intel_crtc_state->mst_master_trans_pending = true;
> +		return 0;
> +	}
> +
> +	/* enabled -> enabled(modeset)? */
> +	if (new_conn_state->crtc) {
> +		crtc_state = drm_atomic_get_new_crtc_state(state,
> new_conn_state->crtc);
> +		if (!drm_atomic_crtc_needs_modeset(crtc_state))
> +			return 0;
> +	}
> +
> +	/* handling enabled -> enabled(modeset) and enabled -> disabled
> */
> +	crtc_state = drm_atomic_get_old_crtc_state(state,
> old_conn_state->crtc);
> +	intel_crtc_state = to_intel_crtc_state(crtc_state);
> +
> +	/* If not master, nothing else needs to be handled */
> +	if (intel_conn->mst_port->mst_master_transcoder !=
> +	    intel_crtc_state->cpu_transcoder)
> +		return 0;
> +
> +	/* Is master, mark all other CRTCs as needing a modeset */
> +	drm_connector_list_iter_begin(state->dev, &conn_list_iter);
> +	drm_for_each_connector_iter(conn_iter, &conn_list_iter) {
> +		struct intel_connector *intel_conn_iter;
> +		struct drm_connector_state *conn_iter_state;
> +
> +		intel_conn_iter = to_intel_connector(conn_iter);
> +		if (intel_conn_iter->mst_port != intel_conn->mst_port)
> +			continue;
> +
> +		conn_iter_state = drm_atomic_get_connector_state(state,
> +								 conn_i
> ter);
> +		if (IS_ERR(conn_iter_state)) {
> +			drm_connector_list_iter_end(&conn_list_iter);
> +			return PTR_ERR(conn_iter_state);
> +		}
> +
> +		if (!conn_iter_state->crtc)
> +			continue;
> +
> +		crtc_state = drm_atomic_get_crtc_state(state,
> conn_iter_state->crtc);
> +		if (IS_ERR(crtc_state)) {
> +			drm_connector_list_iter_end(&conn_list_iter);
> +			return PTR_ERR(conn_iter_state);
> +		}
> +
> +		intel_crtc_state = to_intel_crtc_state(crtc_state);
> +		intel_crtc_state->mst_master_trans_pending = true;
> +		crtc_state->mode_changed = true;
> +	}
> +	drm_connector_list_iter_end(&conn_list_iter);
> +
> +	return 0;
> +}
> +
>  static int
>  intel_dp_mst_atomic_check(struct drm_connector *connector,
>  			  struct drm_atomic_state *state)
> @@ -175,6 +264,10 @@ intel_dp_mst_atomic_check(struct drm_connector
> *connector,
>  	if (ret)
>  		return ret;
>  
> +	ret = intel_dp_mst_atomic_master_trans_check(connector, state);
> +	if (ret)
> +		return ret;
> +
>  	if (!old_conn_state->crtc)
>  		return 0;
>  
> @@ -259,6 +352,7 @@ static void intel_mst_post_disable_dp(struct
> intel_encoder *encoder,
>  		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
>  		intel_dig_port->base.post_disable(&intel_dig_port-
> >base,
>  						  old_crtc_state,
> NULL);
> +		intel_dp->mst_master_transcoder = INVALID_TRANSCODER;
>  	}
>  
>  	DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
> @@ -314,8 +408,11 @@ static void intel_mst_pre_enable_dp(struct
> intel_encoder *encoder,
>  
>  	DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
>  
> -	if (first_mst_stream)
> +	if (first_mst_stream) {
> +		WARN_ON(intel_dp->mst_master_transcoder !=
> INVALID_TRANSCODER);
> +		intel_dp->mst_master_transcoder = pipe_config-
> >cpu_transcoder;
>  		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> +	}
>  
>  	drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector-
> >port, true);
>  
> @@ -717,3 +814,13 @@ intel_dp_mst_encoder_cleanup(struct
> intel_digital_port *intel_dig_port)
>  	drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr);
>  	/* encoders will get killed by normal cleanup */
>  }
> +
> +enum transcoder
> +intel_dp_mst_master_trans_get(struct intel_encoder *encoder)
> +{
> +	struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder-
> >base);
> +	struct intel_dp *intel_dp = &intel_mst->primary->dp;
> +
> +	WARN_ON(intel_dp->mst_master_transcoder == INVALID_TRANSCODER);
> +	return intel_dp->mst_master_transcoder;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.h
> b/drivers/gpu/drm/i915/display/intel_dp_mst.h
> index f660ad80db04..e6f28a517182 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.h
> @@ -7,9 +7,11 @@
>  #define __INTEL_DP_MST_H__
>  
>  struct intel_digital_port;
> +struct intel_encoder;
>  
>  int intel_dp_mst_encoder_init(struct intel_digital_port
> *intel_dig_port, int conn_id);
>  void intel_dp_mst_encoder_cleanup(struct intel_digital_port
> *intel_dig_port);
>  int intel_dp_mst_encoder_active_links(struct intel_digital_port
> *intel_dig_port);
> +enum transcoder intel_dp_mst_master_trans_get(struct intel_encoder
> *encoder);
>  
>  #endif /* __INTEL_DP_MST_H__ */
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 16+ messages in thread

* ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/display: Refactor intel_commit_modeset_disables()
@ 2019-11-21  2:46   ` Patchwork
  0 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2019-11-21  2:46 UTC (permalink / raw)
  To: Souza, Jose; +Cc: intel-gfx

== Series Details ==

Series: series starting with [1/3] drm/i915/display: Refactor intel_commit_modeset_disables()
URL   : https://patchwork.freedesktop.org/series/69787/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7393 -> Patchwork_15362
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_15362:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live_execlists:
    - {fi-tgl-u}:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/fi-tgl-u/igt@i915_selftest@live_execlists.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/fi-tgl-u/igt@i915_selftest@live_execlists.html

  
Known issues
------------

  Here are the changes found in Patchwork_15362 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live_gem_contexts:
    - fi-bsw-n3050:       [PASS][3] -> [INCOMPLETE][4] ([fdo# 111542])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/fi-bsw-n3050/igt@i915_selftest@live_gem_contexts.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/fi-bsw-n3050/igt@i915_selftest@live_gem_contexts.html

  
#### Possible fixes ####

  * igt@i915_module_load@reload-with-fault-injection:
    - {fi-kbl-7560u}:     [INCOMPLETE][5] ([fdo#112298]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/fi-kbl-7560u/igt@i915_module_load@reload-with-fault-injection.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/fi-kbl-7560u/igt@i915_module_load@reload-with-fault-injection.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-u3:          [FAIL][7] ([fdo#103167]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo# 111542]: https://bugs.freedesktop.org/show_bug.cgi?id= 111542
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#112298]: https://bugs.freedesktop.org/show_bug.cgi?id=112298


Participating hosts (50 -> 44)
------------------------------

  Missing    (6): fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-gdg-551 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7393 -> Patchwork_15362

  CI-20190529: 20190529
  CI_DRM_7393: 0e204eb18baca0cd97950bf936fffdbbce1fd337 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5299: 65fed6a79adea14f7bef6d55530da47d7731d370 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15362: 5214c735f98323bd2165e68cec617e49668579b6 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

5214c735f983 drm/i915/tgl: Select master trasconder for MST stream
8914a57cbcf2 drm/i915/display: Check the old state to find port sync slave
1272a1337d74 drm/i915/display: Refactor intel_commit_modeset_disables()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/display: Refactor intel_commit_modeset_disables()
@ 2019-11-21  2:46   ` Patchwork
  0 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2019-11-21  2:46 UTC (permalink / raw)
  To: Souza, Jose; +Cc: intel-gfx

== Series Details ==

Series: series starting with [1/3] drm/i915/display: Refactor intel_commit_modeset_disables()
URL   : https://patchwork.freedesktop.org/series/69787/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7393 -> Patchwork_15362
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_15362:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live_execlists:
    - {fi-tgl-u}:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/fi-tgl-u/igt@i915_selftest@live_execlists.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/fi-tgl-u/igt@i915_selftest@live_execlists.html

  
Known issues
------------

  Here are the changes found in Patchwork_15362 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live_gem_contexts:
    - fi-bsw-n3050:       [PASS][3] -> [INCOMPLETE][4] ([fdo# 111542])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/fi-bsw-n3050/igt@i915_selftest@live_gem_contexts.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/fi-bsw-n3050/igt@i915_selftest@live_gem_contexts.html

  
#### Possible fixes ####

  * igt@i915_module_load@reload-with-fault-injection:
    - {fi-kbl-7560u}:     [INCOMPLETE][5] ([fdo#112298]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/fi-kbl-7560u/igt@i915_module_load@reload-with-fault-injection.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/fi-kbl-7560u/igt@i915_module_load@reload-with-fault-injection.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-u3:          [FAIL][7] ([fdo#103167]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo# 111542]: https://bugs.freedesktop.org/show_bug.cgi?id= 111542
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#112298]: https://bugs.freedesktop.org/show_bug.cgi?id=112298


Participating hosts (50 -> 44)
------------------------------

  Missing    (6): fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-gdg-551 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7393 -> Patchwork_15362

  CI-20190529: 20190529
  CI_DRM_7393: 0e204eb18baca0cd97950bf936fffdbbce1fd337 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5299: 65fed6a79adea14f7bef6d55530da47d7731d370 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15362: 5214c735f98323bd2165e68cec617e49668579b6 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

5214c735f983 drm/i915/tgl: Select master trasconder for MST stream
8914a57cbcf2 drm/i915/display: Check the old state to find port sync slave
1272a1337d74 drm/i915/display: Refactor intel_commit_modeset_disables()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [PATCH v2 3/3] drm/i915/tgl: Select master trasconder for MST stream
@ 2019-11-21 21:20     ` José Roberto de Souza
  0 siblings, 0 replies; 16+ messages in thread
From: José Roberto de Souza @ 2019-11-21 21:20 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

On TGL the blending of all the streams have moved from DDI to
transcoder, so now every transcoder working over the same MST port must
send its stream to a master transcoder and master will send to DDI
respecting the time slots.

A previous approach was using the lowest pipe/transcoder as master
transcoder but as the comment in skl_commit_modeset_enables() states,
that is not always true.

So here promoting the first pipe/transcoder of the stream as master.
That caused several other problems as during the commit phase the
state computed should not be changed.

So the master transcoder is store into intel_dp and the modeset in
slave pipes/transcoders is forced using mst_master_trans_pending.

v2:
- added missing config compute to trigger fullmodeset in slave
transcoders

BSpec: 50493
BSpec: 49190
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      |  10 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  58 ++++++-
 .../drm/i915/display/intel_display_types.h    |   3 +
 drivers/gpu/drm/i915/display/intel_dp.c       |   1 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 149 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp_mst.h   |   2 +
 6 files changed, 216 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a976606d21c7..d2f0d393d3ee 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -35,6 +35,7 @@
 #include "intel_display_types.h"
 #include "intel_dp.h"
 #include "intel_dp_link_training.h"
+#include "intel_dp_mst.h"
 #include "intel_dpio_phy.h"
 #include "intel_dsi.h"
 #include "intel_fifo_underrun.h"
@@ -1903,8 +1904,13 @@ intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
 		temp |= TRANS_DDI_MODE_SELECT_DP_MST;
 		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
 
-		if (INTEL_GEN(dev_priv) >= 12)
-			temp |= TRANS_DDI_MST_TRANSPORT_SELECT(crtc_state->cpu_transcoder);
+		if (INTEL_GEN(dev_priv) >= 12) {
+			enum transcoder master;
+
+			master = intel_dp_mst_master_trans_get(encoder);
+			WARN_ON(master == INVALID_TRANSCODER);
+			temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
+		}
 	} else {
 		temp |= TRANS_DDI_MODE_SELECT_DP_SST;
 		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 801b975c7d39..35a59108194e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -46,6 +46,7 @@
 #include "display/intel_crt.h"
 #include "display/intel_ddi.h"
 #include "display/intel_dp.h"
+#include "display/intel_dp_mst.h"
 #include "display/intel_dsi.h"
 #include "display/intel_dvo.h"
 #include "display/intel_gmbus.h"
@@ -5365,6 +5366,36 @@ intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
 	return encoder;
 }
 
+/*
+ * Finds the encoder associated with the given CRTC. This can only be
+ * used when we know that the CRTC isn't feeding multiple encoders!
+ */
+static struct intel_encoder *
+intel_get_crtc_old_encoder(const struct intel_atomic_state *state,
+			   const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	const struct drm_connector_state *connector_state;
+	const struct drm_connector *connector;
+	struct intel_encoder *encoder = NULL;
+	int num_encoders = 0;
+	int i;
+
+	for_each_old_connector_in_state(&state->base, connector,
+					connector_state, i) {
+		if (connector_state->crtc != &crtc->base)
+			continue;
+
+		encoder = to_intel_encoder(connector_state->best_encoder);
+		num_encoders++;
+	}
+
+	WARN(num_encoders != 1, "%d encoders for pipe %c\n",
+	     num_encoders, pipe_name(crtc->pipe));
+
+	return encoder;
+}
+
 /*
  * Enable PCH resources required for PCH ports:
  *   - PCH PLLs
@@ -13365,6 +13396,12 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 #undef PIPE_CONF_CHECK_COLOR_LUT
 #undef PIPE_CONF_QUIRK
 
+	if (fastset && pipe_config->mst_master_trans_pending) {
+		DRM_DEBUG_KMS("[CRTC:%d:%s] fastset mismatch in mst_master_trans\n",
+			      crtc->base.base.id, crtc->base.name);
+		ret = false;
+	}
+
 	return ret;
 }
 
@@ -14449,22 +14486,35 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
 	struct intel_crtc *crtc;
 	int i;
 
-	/* Only disable port sync slaves */
+	/* Only disable port sync and MST slaves */
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
 					    new_crtc_state, i) {
 		if (!needs_modeset(new_crtc_state) || !crtc->active)
 			continue;
 
+		if (!is_trans_port_sync_mode(new_crtc_state) &&
+		    !intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
+			continue;
+
 		/* In case of Transcoder port Sync master slave CRTCs can be
 		 * assigned in any order and we need to make sure that
 		 * slave CRTCs are disabled first and then master CRTC since
 		 * Slave vblanks are masked till Master Vblanks.
 		 */
-		if (!is_trans_port_sync_mode(old_crtc_state))
-			continue;
-		if (is_trans_port_sync_master(old_crtc_state))
+		if (is_trans_port_sync_mode(new_crtc_state) &&
+		    is_trans_port_sync_master(new_crtc_state))
 			continue;
 
+		if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) {
+			struct intel_encoder *encoder;
+
+			encoder = intel_get_crtc_old_encoder(state,
+							     old_crtc_state);
+			if (intel_dp_mst_master_trans_get(encoder) ==
+			    old_crtc_state->cpu_transcoder)
+				continue;
+		}
+
 		intel_pre_plane_update(old_crtc_state, new_crtc_state);
 		intel_old_crtc_state_disables(state, old_crtc_state,
 					      new_crtc_state, crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 83ea04149b77..23d747cdca64 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1052,6 +1052,8 @@ struct intel_crtc_state {
 	/* Pointer to master transcoder in case of tiled displays */
 	enum transcoder master_transcoder;
 
+	bool mst_master_trans_pending;
+
 	/* Bitmask to indicate slaves attached */
 	u8 sync_mode_slaves_mask;
 };
@@ -1284,6 +1286,7 @@ struct intel_dp {
 	bool can_mst; /* this port supports mst */
 	bool is_mst;
 	int active_mst_links;
+	enum transcoder mst_master_transcoder; /* Only used in TGL+ */
 
 	/*
 	 * DP_TP_* registers may be either on port or transcoder register space.
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3123958e2081..ceff6901451a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7424,6 +7424,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 	intel_dp->reset_link_params = true;
 	intel_dp->pps_pipe = INVALID_PIPE;
 	intel_dp->active_pipe = INVALID_PIPE;
+	intel_dp->mst_master_transcoder = INVALID_TRANSCODER;
 
 	/* Preserve the current hw state. */
 	intel_dp->DP = I915_READ(intel_dp->output_reg);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index f8a350359346..9731c3c1d3f2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -87,6 +87,47 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
 	return 0;
 }
 
+static int
+intel_dp_mst_master_trans_compute(struct intel_encoder *encoder,
+				  struct intel_crtc_state *pipe_config,
+				  struct drm_connector_state *conn_state)
+{
+	struct intel_atomic_state *state = to_intel_atomic_state(pipe_config->uapi.state);
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_crtc_state *new_crtc_state;
+	struct intel_crtc *crtc;
+	enum transcoder master;
+	int i;
+
+	if (INTEL_GEN(dev_priv) < 12)
+		return 0;
+
+	if (!conn_state->crtc)
+		return 0;
+
+	master = intel_dp_mst_master_trans_get(encoder);
+	if (master == INVALID_TRANSCODER)
+		return 0;
+
+	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+		/*
+		 * cpu_transcoder is set when computing CRTC state if it will
+		 * be disabled it will not happen, so checking pipe instead
+		 */
+		if (crtc->pipe != (enum pipe)master)
+			continue;
+
+		if (!drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi) &&
+		    new_crtc_state->uapi.enable)
+			continue;
+
+		pipe_config->mst_master_trans_pending = true;
+		break;
+	}
+
+	return 0;
+}
+
 static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
 				       struct intel_crtc_state *pipe_config,
 				       struct drm_connector_state *conn_state)
@@ -154,6 +195,95 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
 
 	intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
 
+	ret = intel_dp_mst_master_trans_compute(encoder, pipe_config,
+						conn_state);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int
+intel_dp_mst_atomic_master_trans_check(struct drm_connector *connector,
+				       struct drm_atomic_state *state)
+{
+	struct drm_i915_private *dev_priv = to_i915(connector->dev);
+	struct intel_connector *intel_conn = to_intel_connector(connector);
+	struct drm_connector_state *new_conn_state, *old_conn_state;
+	struct drm_connector_list_iter conn_list_iter;
+	struct intel_crtc_state *intel_crtc_state;
+	struct drm_crtc_state *crtc_state;
+	struct drm_connector *conn_iter;
+
+	if (INTEL_GEN(dev_priv) < 12)
+		return 0;
+
+	new_conn_state = drm_atomic_get_new_connector_state(state, connector);
+	old_conn_state = drm_atomic_get_old_connector_state(state, connector);
+
+	if (!old_conn_state->crtc && !new_conn_state->crtc)
+		return 0;
+
+	/*
+	 * 3 cases that needs be handled here:
+	 * - connector going from disabled to enabled
+	 * - connector going from enabled to disabled:
+	 * if this transcoder was the master, all slaves needs a modeset
+	 * - connector going from enabled to enabled but it needs a modeset:
+	 * if this transcoder was the master, all slaves also needs a modeset
+	 */
+
+	/* disabled -> enabled */
+	if (!old_conn_state->crtc && new_conn_state->crtc)
+		return 0;
+
+	/* enabled -> enabled(modeset)? */
+	if (new_conn_state->crtc) {
+		crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
+		if (!drm_atomic_crtc_needs_modeset(crtc_state))
+			return 0;
+	}
+
+	/* handling enabled -> enabled(modeset) and enabled -> disabled */
+	crtc_state = drm_atomic_get_old_crtc_state(state, old_conn_state->crtc);
+	intel_crtc_state = to_intel_crtc_state(crtc_state);
+
+	/* If not master, nothing else needs to be handled */
+	if (intel_conn->mst_port->mst_master_transcoder !=
+	    intel_crtc_state->cpu_transcoder)
+		return 0;
+
+	/* Is master, mark all other CRTCs as needing a modeset */
+	drm_connector_list_iter_begin(state->dev, &conn_list_iter);
+	drm_for_each_connector_iter(conn_iter, &conn_list_iter) {
+		struct intel_connector *intel_conn_iter;
+		struct drm_connector_state *conn_iter_state;
+
+		intel_conn_iter = to_intel_connector(conn_iter);
+		if (intel_conn_iter->mst_port != intel_conn->mst_port)
+			continue;
+
+		conn_iter_state = drm_atomic_get_connector_state(state,
+								 conn_iter);
+		if (IS_ERR(conn_iter_state)) {
+			drm_connector_list_iter_end(&conn_list_iter);
+			return PTR_ERR(conn_iter_state);
+		}
+
+		if (!conn_iter_state->crtc)
+			continue;
+
+		crtc_state = drm_atomic_get_crtc_state(state, conn_iter_state->crtc);
+		if (IS_ERR(crtc_state)) {
+			drm_connector_list_iter_end(&conn_list_iter);
+			return PTR_ERR(conn_iter_state);
+		}
+
+		intel_crtc_state = to_intel_crtc_state(crtc_state);
+		crtc_state->mode_changed = true;
+	}
+	drm_connector_list_iter_end(&conn_list_iter);
+
 	return 0;
 }
 
@@ -175,6 +305,10 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
 	if (ret)
 		return ret;
 
+	ret = intel_dp_mst_atomic_master_trans_check(connector, state);
+	if (ret)
+		return ret;
+
 	if (!old_conn_state->crtc)
 		return 0;
 
@@ -259,6 +393,7 @@ static void intel_mst_post_disable_dp(struct intel_encoder *encoder,
 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
 		intel_dig_port->base.post_disable(&intel_dig_port->base,
 						  old_crtc_state, NULL);
+		intel_dp->mst_master_transcoder = INVALID_TRANSCODER;
 	}
 
 	DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
@@ -314,8 +449,11 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
 
 	DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
 
-	if (first_mst_stream)
+	if (first_mst_stream) {
+		WARN_ON(intel_dp->mst_master_transcoder != INVALID_TRANSCODER);
+		intel_dp->mst_master_transcoder = pipe_config->cpu_transcoder;
 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+	}
 
 	drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
 
@@ -717,3 +855,12 @@ intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port)
 	drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr);
 	/* encoders will get killed by normal cleanup */
 }
+
+enum transcoder
+intel_dp_mst_master_trans_get(struct intel_encoder *encoder)
+{
+	struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
+	struct intel_dp *intel_dp = &intel_mst->primary->dp;
+
+	return intel_dp->mst_master_transcoder;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.h b/drivers/gpu/drm/i915/display/intel_dp_mst.h
index f660ad80db04..e6f28a517182 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.h
@@ -7,9 +7,11 @@
 #define __INTEL_DP_MST_H__
 
 struct intel_digital_port;
+struct intel_encoder;
 
 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
 int intel_dp_mst_encoder_active_links(struct intel_digital_port *intel_dig_port);
+enum transcoder intel_dp_mst_master_trans_get(struct intel_encoder *encoder);
 
 #endif /* __INTEL_DP_MST_H__ */
-- 
2.24.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 16+ messages in thread

* [Intel-gfx] [PATCH v2 3/3] drm/i915/tgl: Select master trasconder for MST stream
@ 2019-11-21 21:20     ` José Roberto de Souza
  0 siblings, 0 replies; 16+ messages in thread
From: José Roberto de Souza @ 2019-11-21 21:20 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

On TGL the blending of all the streams have moved from DDI to
transcoder, so now every transcoder working over the same MST port must
send its stream to a master transcoder and master will send to DDI
respecting the time slots.

A previous approach was using the lowest pipe/transcoder as master
transcoder but as the comment in skl_commit_modeset_enables() states,
that is not always true.

So here promoting the first pipe/transcoder of the stream as master.
That caused several other problems as during the commit phase the
state computed should not be changed.

So the master transcoder is store into intel_dp and the modeset in
slave pipes/transcoders is forced using mst_master_trans_pending.

v2:
- added missing config compute to trigger fullmodeset in slave
transcoders

BSpec: 50493
BSpec: 49190
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      |  10 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  58 ++++++-
 .../drm/i915/display/intel_display_types.h    |   3 +
 drivers/gpu/drm/i915/display/intel_dp.c       |   1 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 149 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp_mst.h   |   2 +
 6 files changed, 216 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a976606d21c7..d2f0d393d3ee 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -35,6 +35,7 @@
 #include "intel_display_types.h"
 #include "intel_dp.h"
 #include "intel_dp_link_training.h"
+#include "intel_dp_mst.h"
 #include "intel_dpio_phy.h"
 #include "intel_dsi.h"
 #include "intel_fifo_underrun.h"
@@ -1903,8 +1904,13 @@ intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
 		temp |= TRANS_DDI_MODE_SELECT_DP_MST;
 		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
 
-		if (INTEL_GEN(dev_priv) >= 12)
-			temp |= TRANS_DDI_MST_TRANSPORT_SELECT(crtc_state->cpu_transcoder);
+		if (INTEL_GEN(dev_priv) >= 12) {
+			enum transcoder master;
+
+			master = intel_dp_mst_master_trans_get(encoder);
+			WARN_ON(master == INVALID_TRANSCODER);
+			temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
+		}
 	} else {
 		temp |= TRANS_DDI_MODE_SELECT_DP_SST;
 		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 801b975c7d39..35a59108194e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -46,6 +46,7 @@
 #include "display/intel_crt.h"
 #include "display/intel_ddi.h"
 #include "display/intel_dp.h"
+#include "display/intel_dp_mst.h"
 #include "display/intel_dsi.h"
 #include "display/intel_dvo.h"
 #include "display/intel_gmbus.h"
@@ -5365,6 +5366,36 @@ intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
 	return encoder;
 }
 
+/*
+ * Finds the encoder associated with the given CRTC. This can only be
+ * used when we know that the CRTC isn't feeding multiple encoders!
+ */
+static struct intel_encoder *
+intel_get_crtc_old_encoder(const struct intel_atomic_state *state,
+			   const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	const struct drm_connector_state *connector_state;
+	const struct drm_connector *connector;
+	struct intel_encoder *encoder = NULL;
+	int num_encoders = 0;
+	int i;
+
+	for_each_old_connector_in_state(&state->base, connector,
+					connector_state, i) {
+		if (connector_state->crtc != &crtc->base)
+			continue;
+
+		encoder = to_intel_encoder(connector_state->best_encoder);
+		num_encoders++;
+	}
+
+	WARN(num_encoders != 1, "%d encoders for pipe %c\n",
+	     num_encoders, pipe_name(crtc->pipe));
+
+	return encoder;
+}
+
 /*
  * Enable PCH resources required for PCH ports:
  *   - PCH PLLs
@@ -13365,6 +13396,12 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 #undef PIPE_CONF_CHECK_COLOR_LUT
 #undef PIPE_CONF_QUIRK
 
+	if (fastset && pipe_config->mst_master_trans_pending) {
+		DRM_DEBUG_KMS("[CRTC:%d:%s] fastset mismatch in mst_master_trans\n",
+			      crtc->base.base.id, crtc->base.name);
+		ret = false;
+	}
+
 	return ret;
 }
 
@@ -14449,22 +14486,35 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
 	struct intel_crtc *crtc;
 	int i;
 
-	/* Only disable port sync slaves */
+	/* Only disable port sync and MST slaves */
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
 					    new_crtc_state, i) {
 		if (!needs_modeset(new_crtc_state) || !crtc->active)
 			continue;
 
+		if (!is_trans_port_sync_mode(new_crtc_state) &&
+		    !intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
+			continue;
+
 		/* In case of Transcoder port Sync master slave CRTCs can be
 		 * assigned in any order and we need to make sure that
 		 * slave CRTCs are disabled first and then master CRTC since
 		 * Slave vblanks are masked till Master Vblanks.
 		 */
-		if (!is_trans_port_sync_mode(old_crtc_state))
-			continue;
-		if (is_trans_port_sync_master(old_crtc_state))
+		if (is_trans_port_sync_mode(new_crtc_state) &&
+		    is_trans_port_sync_master(new_crtc_state))
 			continue;
 
+		if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) {
+			struct intel_encoder *encoder;
+
+			encoder = intel_get_crtc_old_encoder(state,
+							     old_crtc_state);
+			if (intel_dp_mst_master_trans_get(encoder) ==
+			    old_crtc_state->cpu_transcoder)
+				continue;
+		}
+
 		intel_pre_plane_update(old_crtc_state, new_crtc_state);
 		intel_old_crtc_state_disables(state, old_crtc_state,
 					      new_crtc_state, crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 83ea04149b77..23d747cdca64 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1052,6 +1052,8 @@ struct intel_crtc_state {
 	/* Pointer to master transcoder in case of tiled displays */
 	enum transcoder master_transcoder;
 
+	bool mst_master_trans_pending;
+
 	/* Bitmask to indicate slaves attached */
 	u8 sync_mode_slaves_mask;
 };
@@ -1284,6 +1286,7 @@ struct intel_dp {
 	bool can_mst; /* this port supports mst */
 	bool is_mst;
 	int active_mst_links;
+	enum transcoder mst_master_transcoder; /* Only used in TGL+ */
 
 	/*
 	 * DP_TP_* registers may be either on port or transcoder register space.
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3123958e2081..ceff6901451a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7424,6 +7424,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 	intel_dp->reset_link_params = true;
 	intel_dp->pps_pipe = INVALID_PIPE;
 	intel_dp->active_pipe = INVALID_PIPE;
+	intel_dp->mst_master_transcoder = INVALID_TRANSCODER;
 
 	/* Preserve the current hw state. */
 	intel_dp->DP = I915_READ(intel_dp->output_reg);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index f8a350359346..9731c3c1d3f2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -87,6 +87,47 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
 	return 0;
 }
 
+static int
+intel_dp_mst_master_trans_compute(struct intel_encoder *encoder,
+				  struct intel_crtc_state *pipe_config,
+				  struct drm_connector_state *conn_state)
+{
+	struct intel_atomic_state *state = to_intel_atomic_state(pipe_config->uapi.state);
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_crtc_state *new_crtc_state;
+	struct intel_crtc *crtc;
+	enum transcoder master;
+	int i;
+
+	if (INTEL_GEN(dev_priv) < 12)
+		return 0;
+
+	if (!conn_state->crtc)
+		return 0;
+
+	master = intel_dp_mst_master_trans_get(encoder);
+	if (master == INVALID_TRANSCODER)
+		return 0;
+
+	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+		/*
+		 * cpu_transcoder is set when computing CRTC state if it will
+		 * be disabled it will not happen, so checking pipe instead
+		 */
+		if (crtc->pipe != (enum pipe)master)
+			continue;
+
+		if (!drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi) &&
+		    new_crtc_state->uapi.enable)
+			continue;
+
+		pipe_config->mst_master_trans_pending = true;
+		break;
+	}
+
+	return 0;
+}
+
 static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
 				       struct intel_crtc_state *pipe_config,
 				       struct drm_connector_state *conn_state)
@@ -154,6 +195,95 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
 
 	intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
 
+	ret = intel_dp_mst_master_trans_compute(encoder, pipe_config,
+						conn_state);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int
+intel_dp_mst_atomic_master_trans_check(struct drm_connector *connector,
+				       struct drm_atomic_state *state)
+{
+	struct drm_i915_private *dev_priv = to_i915(connector->dev);
+	struct intel_connector *intel_conn = to_intel_connector(connector);
+	struct drm_connector_state *new_conn_state, *old_conn_state;
+	struct drm_connector_list_iter conn_list_iter;
+	struct intel_crtc_state *intel_crtc_state;
+	struct drm_crtc_state *crtc_state;
+	struct drm_connector *conn_iter;
+
+	if (INTEL_GEN(dev_priv) < 12)
+		return 0;
+
+	new_conn_state = drm_atomic_get_new_connector_state(state, connector);
+	old_conn_state = drm_atomic_get_old_connector_state(state, connector);
+
+	if (!old_conn_state->crtc && !new_conn_state->crtc)
+		return 0;
+
+	/*
+	 * 3 cases that needs be handled here:
+	 * - connector going from disabled to enabled
+	 * - connector going from enabled to disabled:
+	 * if this transcoder was the master, all slaves needs a modeset
+	 * - connector going from enabled to enabled but it needs a modeset:
+	 * if this transcoder was the master, all slaves also needs a modeset
+	 */
+
+	/* disabled -> enabled */
+	if (!old_conn_state->crtc && new_conn_state->crtc)
+		return 0;
+
+	/* enabled -> enabled(modeset)? */
+	if (new_conn_state->crtc) {
+		crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
+		if (!drm_atomic_crtc_needs_modeset(crtc_state))
+			return 0;
+	}
+
+	/* handling enabled -> enabled(modeset) and enabled -> disabled */
+	crtc_state = drm_atomic_get_old_crtc_state(state, old_conn_state->crtc);
+	intel_crtc_state = to_intel_crtc_state(crtc_state);
+
+	/* If not master, nothing else needs to be handled */
+	if (intel_conn->mst_port->mst_master_transcoder !=
+	    intel_crtc_state->cpu_transcoder)
+		return 0;
+
+	/* Is master, mark all other CRTCs as needing a modeset */
+	drm_connector_list_iter_begin(state->dev, &conn_list_iter);
+	drm_for_each_connector_iter(conn_iter, &conn_list_iter) {
+		struct intel_connector *intel_conn_iter;
+		struct drm_connector_state *conn_iter_state;
+
+		intel_conn_iter = to_intel_connector(conn_iter);
+		if (intel_conn_iter->mst_port != intel_conn->mst_port)
+			continue;
+
+		conn_iter_state = drm_atomic_get_connector_state(state,
+								 conn_iter);
+		if (IS_ERR(conn_iter_state)) {
+			drm_connector_list_iter_end(&conn_list_iter);
+			return PTR_ERR(conn_iter_state);
+		}
+
+		if (!conn_iter_state->crtc)
+			continue;
+
+		crtc_state = drm_atomic_get_crtc_state(state, conn_iter_state->crtc);
+		if (IS_ERR(crtc_state)) {
+			drm_connector_list_iter_end(&conn_list_iter);
+			return PTR_ERR(conn_iter_state);
+		}
+
+		intel_crtc_state = to_intel_crtc_state(crtc_state);
+		crtc_state->mode_changed = true;
+	}
+	drm_connector_list_iter_end(&conn_list_iter);
+
 	return 0;
 }
 
@@ -175,6 +305,10 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
 	if (ret)
 		return ret;
 
+	ret = intel_dp_mst_atomic_master_trans_check(connector, state);
+	if (ret)
+		return ret;
+
 	if (!old_conn_state->crtc)
 		return 0;
 
@@ -259,6 +393,7 @@ static void intel_mst_post_disable_dp(struct intel_encoder *encoder,
 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
 		intel_dig_port->base.post_disable(&intel_dig_port->base,
 						  old_crtc_state, NULL);
+		intel_dp->mst_master_transcoder = INVALID_TRANSCODER;
 	}
 
 	DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
@@ -314,8 +449,11 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
 
 	DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
 
-	if (first_mst_stream)
+	if (first_mst_stream) {
+		WARN_ON(intel_dp->mst_master_transcoder != INVALID_TRANSCODER);
+		intel_dp->mst_master_transcoder = pipe_config->cpu_transcoder;
 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+	}
 
 	drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
 
@@ -717,3 +855,12 @@ intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port)
 	drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr);
 	/* encoders will get killed by normal cleanup */
 }
+
+enum transcoder
+intel_dp_mst_master_trans_get(struct intel_encoder *encoder)
+{
+	struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
+	struct intel_dp *intel_dp = &intel_mst->primary->dp;
+
+	return intel_dp->mst_master_transcoder;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.h b/drivers/gpu/drm/i915/display/intel_dp_mst.h
index f660ad80db04..e6f28a517182 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.h
@@ -7,9 +7,11 @@
 #define __INTEL_DP_MST_H__
 
 struct intel_digital_port;
+struct intel_encoder;
 
 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
 int intel_dp_mst_encoder_active_links(struct intel_digital_port *intel_dig_port);
+enum transcoder intel_dp_mst_master_trans_get(struct intel_encoder *encoder);
 
 #endif /* __INTEL_DP_MST_H__ */
-- 
2.24.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 16+ messages in thread

* ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/display: Refactor intel_commit_modeset_disables() (rev2)
@ 2019-11-21 21:59   ` Patchwork
  0 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2019-11-21 21:59 UTC (permalink / raw)
  To: José Roberto de Souza; +Cc: intel-gfx

== Series Details ==

Series: series starting with [1/3] drm/i915/display: Refactor intel_commit_modeset_disables() (rev2)
URL   : https://patchwork.freedesktop.org/series/69787/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7401 -> Patchwork_15384
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15384/index.html

Known issues
------------

  Here are the changes found in Patchwork_15384 that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-lmem:        [DMESG-WARN][1] ([fdo#112261]) -> [PASS][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7401/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15384/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live_blt:
    - fi-hsw-peppy:       [DMESG-FAIL][3] ([fdo#112147]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7401/fi-hsw-peppy/igt@i915_selftest@live_blt.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15384/fi-hsw-peppy/igt@i915_selftest@live_blt.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-hsw-peppy:       [DMESG-WARN][5] ([fdo#102614]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7401/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15384/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html

  
  [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
  [fdo#112147]: https://bugs.freedesktop.org/show_bug.cgi?id=112147
  [fdo#112261]: https://bugs.freedesktop.org/show_bug.cgi?id=112261


Participating hosts (51 -> 44)
------------------------------

  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7401 -> Patchwork_15384

  CI-20190529: 20190529
  CI_DRM_7401: 242d04c5d3993e9f0cd025ac9a73a2e81d4206de @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5299: 65fed6a79adea14f7bef6d55530da47d7731d370 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15384: 3d4f60b86327bb177ba8350fcb6c042bf396898a @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

3d4f60b86327 drm/i915/tgl: Select master trasconder for MST stream
702bfe3a109a drm/i915/display: Check the old state to find port sync slave
a34386d15cb9 drm/i915/display: Refactor intel_commit_modeset_disables()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15384/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/display: Refactor intel_commit_modeset_disables() (rev2)
@ 2019-11-21 21:59   ` Patchwork
  0 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2019-11-21 21:59 UTC (permalink / raw)
  To: José Roberto de Souza; +Cc: intel-gfx

== Series Details ==

Series: series starting with [1/3] drm/i915/display: Refactor intel_commit_modeset_disables() (rev2)
URL   : https://patchwork.freedesktop.org/series/69787/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7401 -> Patchwork_15384
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15384/index.html

Known issues
------------

  Here are the changes found in Patchwork_15384 that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-lmem:        [DMESG-WARN][1] ([fdo#112261]) -> [PASS][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7401/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15384/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live_blt:
    - fi-hsw-peppy:       [DMESG-FAIL][3] ([fdo#112147]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7401/fi-hsw-peppy/igt@i915_selftest@live_blt.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15384/fi-hsw-peppy/igt@i915_selftest@live_blt.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-hsw-peppy:       [DMESG-WARN][5] ([fdo#102614]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7401/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15384/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html

  
  [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
  [fdo#112147]: https://bugs.freedesktop.org/show_bug.cgi?id=112147
  [fdo#112261]: https://bugs.freedesktop.org/show_bug.cgi?id=112261


Participating hosts (51 -> 44)
------------------------------

  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7401 -> Patchwork_15384

  CI-20190529: 20190529
  CI_DRM_7401: 242d04c5d3993e9f0cd025ac9a73a2e81d4206de @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5299: 65fed6a79adea14f7bef6d55530da47d7731d370 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15384: 3d4f60b86327bb177ba8350fcb6c042bf396898a @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

3d4f60b86327 drm/i915/tgl: Select master trasconder for MST stream
702bfe3a109a drm/i915/display: Check the old state to find port sync slave
a34386d15cb9 drm/i915/display: Refactor intel_commit_modeset_disables()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15384/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 16+ messages in thread

* ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/display: Refactor intel_commit_modeset_disables()
@ 2019-11-22  2:59   ` Patchwork
  0 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2019-11-22  2:59 UTC (permalink / raw)
  To: José Roberto de Souza; +Cc: intel-gfx

== Series Details ==

Series: series starting with [1/3] drm/i915/display: Refactor intel_commit_modeset_disables()
URL   : https://patchwork.freedesktop.org/series/69787/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7393_full -> Patchwork_15362_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_15362_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@vcs1-dirty-create:
    - shard-iclb:         [PASS][1] -> [SKIP][2] ([fdo#109276] / [fdo#112080]) +3 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb4/igt@gem_ctx_isolation@vcs1-dirty-create.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb8/igt@gem_ctx_isolation@vcs1-dirty-create.html

  * igt@gem_ctx_shared@exec-single-timeline-bsd:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([fdo#110841])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb8/igt@gem_ctx_shared@exec-single-timeline-bsd.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html

  * igt@gem_ctx_switch@vcs1-heavy:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#112080]) +12 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb4/igt@gem_ctx_switch@vcs1-heavy.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb8/igt@gem_ctx_switch@vcs1-heavy.html

  * igt@gem_eio@in-flight-suspend:
    - shard-tglb:         [PASS][7] -> [INCOMPLETE][8] ([fdo#111832] / [fdo#111850] / [fdo#112081])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-tglb1/igt@gem_eio@in-flight-suspend.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-tglb5/igt@gem_eio@in-flight-suspend.html

  * igt@gem_exec_parallel@fds:
    - shard-tglb:         [PASS][9] -> [INCOMPLETE][10] ([fdo#111867])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-tglb1/igt@gem_exec_parallel@fds.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-tglb6/igt@gem_exec_parallel@fds.html

  * igt@gem_exec_schedule@independent-bsd2:
    - shard-iclb:         [PASS][11] -> [SKIP][12] ([fdo#109276]) +17 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb4/igt@gem_exec_schedule@independent-bsd2.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb8/igt@gem_exec_schedule@independent-bsd2.html

  * igt@gem_exec_schedule@preempt-queue-bsd:
    - shard-iclb:         [PASS][13] -> [SKIP][14] ([fdo#112146]) +4 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb8/igt@gem_exec_schedule@preempt-queue-bsd.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb1/igt@gem_exec_schedule@preempt-queue-bsd.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
    - shard-hsw:          [PASS][15] -> [DMESG-WARN][16] ([fdo#111870])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-hsw6/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-hsw1/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-iclb:         [PASS][17] -> [FAIL][18] ([fdo#111830 ])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb6/igt@i915_pm_dc@dc6-dpms.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-apl:          [PASS][19] -> [DMESG-WARN][20] ([fdo#108566]) +2 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-apl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-apl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-skl:          [PASS][21] -> [INCOMPLETE][22] ([fdo#109507])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-skl5/igt@kms_flip@flip-vs-suspend-interruptible.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-skl8/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
    - shard-tglb:         [PASS][23] -> [FAIL][24] ([fdo#103167]) +2 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt:
    - shard-iclb:         [PASS][25] -> [FAIL][26] ([fdo#103167]) +7 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-rte:
    - shard-iclb:         [PASS][27] -> [FAIL][28] ([fdo#103167] / [fdo#110378])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html

  * igt@kms_frontbuffer_tracking@fbcpsr-suspend:
    - shard-tglb:         [PASS][29] -> [INCOMPLETE][30] ([fdo#111832] / [fdo#111850] / [fdo#111884])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-tglb9/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
    - shard-tglb:         [PASS][31] -> [INCOMPLETE][32] ([fdo#111832] / [fdo#111850]) +4 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-tglb4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-tglb3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [PASS][33] -> [SKIP][34] ([fdo#109441]) +1 similar issue
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb4/igt@kms_psr@psr2_cursor_render.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-kbl:          [PASS][35] -> [DMESG-WARN][36] ([fdo#108566]) +3 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  
#### Possible fixes ####

  * igt@gem_busy@close-race:
    - shard-tglb:         [INCOMPLETE][37] ([fdo#111747]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-tglb6/igt@gem_busy@close-race.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-tglb3/igt@gem_busy@close-race.html

  * igt@gem_ctx_persistence@vcs1-mixed-process:
    - shard-iclb:         [SKIP][39] ([fdo#109276] / [fdo#112080]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb6/igt@gem_ctx_persistence@vcs1-mixed-process.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb1/igt@gem_ctx_persistence@vcs1-mixed-process.html

  * igt@gem_ctx_persistence@vecs0-mixed-process:
    - shard-skl:          [FAIL][41] ([fdo#112194]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-skl1/igt@gem_ctx_persistence@vecs0-mixed-process.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-skl6/igt@gem_ctx_persistence@vecs0-mixed-process.html

  * igt@gem_exec_reloc@basic-gtt-cpu-active:
    - shard-skl:          [DMESG-WARN][43] ([fdo#106107]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-skl7/igt@gem_exec_reloc@basic-gtt-cpu-active.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-skl9/igt@gem_exec_reloc@basic-gtt-cpu-active.html

  * igt@gem_exec_schedule@preempt-contexts-bsd2:
    - shard-iclb:         [SKIP][45] ([fdo#109276]) -> [PASS][46] +13 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb8/igt@gem_exec_schedule@preempt-contexts-bsd2.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb1/igt@gem_exec_schedule@preempt-contexts-bsd2.html

  * igt@gem_exec_schedule@preemptive-hang-bsd:
    - shard-iclb:         [SKIP][47] ([fdo#112146]) -> [PASS][48] +5 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb4/igt@gem_exec_schedule@preemptive-hang-bsd.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb8/igt@gem_exec_schedule@preemptive-hang-bsd.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-snb:          [DMESG-WARN][49] ([fdo#111870]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-snb6/igt@gem_userptr_blits@dmabuf-unsync.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-snb7/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@gem_userptr_blits@sync-unmap-cycles:
    - shard-hsw:          [DMESG-WARN][51] ([fdo#111870]) -> [PASS][52] +2 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-hsw4/igt@gem_userptr_blits@sync-unmap-cycles.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-hsw7/igt@gem_userptr_blits@sync-unmap-cycles.html

  * igt@i915_pm_rpm@system-suspend:
    - shard-hsw:          [INCOMPLETE][53] ([fdo#103540] / [fdo#107807]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-hsw2/igt@i915_pm_rpm@system-suspend.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-hsw5/igt@i915_pm_rpm@system-suspend.html

  * igt@kms_big_fb@y-tiled-32bpp-rotate-0:
    - shard-skl:          [INCOMPLETE][55] ([fdo#104108] / [fdo#112347]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-skl9/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-skl2/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-kbl:          [DMESG-WARN][57] ([fdo#108566]) -> [PASS][58] +2 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt:
    - shard-tglb:         [FAIL][59] ([fdo#103167]) -> [PASS][60] +4 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-tglb9/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-1p-rte:
    - shard-iclb:         [FAIL][61] ([fdo#103167] / [fdo#110378]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-rte.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
    - shard-iclb:         [FAIL][63] ([fdo#103167]) -> [PASS][64] +5 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt:
    - shard-skl:          [FAIL][65] ([fdo#103167]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-skl1/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-skl8/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
    - shard-skl:          [FAIL][67] ([fdo#108145]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html

  * igt@kms_psr@no_drrs:
    - shard-iclb:         [FAIL][69] ([fdo#108341]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb1/igt@kms_psr@no_drrs.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb3/igt@kms_psr@no_drrs.html

  * igt@kms_psr@psr2_primary_blt:
    - shard-iclb:         [SKIP][71] ([fdo#109441]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb6/igt@kms_psr@psr2_primary_blt.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb2/igt@kms_psr@psr2_primary_blt.html

  * igt@kms_setmode@basic:
    - shard-apl:          [FAIL][73] ([fdo#99912]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-apl2/igt@kms_setmode@basic.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-apl4/igt@kms_setmode@basic.html
    - shard-glk:          [FAIL][75] ([fdo#99912]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-glk8/igt@kms_setmode@basic.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-glk2/igt@kms_setmode@basic.html
    - shard-kbl:          [FAIL][77] ([fdo#99912]) -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-kbl6/igt@kms_setmode@basic.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-kbl2/igt@kms_setmode@basic.html

  * igt@kms_vblank@pipe-c-ts-continuation-suspend:
    - shard-tglb:         [INCOMPLETE][79] ([fdo#111832] / [fdo#111850]) -> [PASS][80] +2 similar issues
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-tglb5/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-tglb2/igt@kms_vblank@pipe-c-ts-continuation-suspend.html

  * igt@kms_vblank@pipe-d-ts-continuation-suspend:
    - shard-tglb:         [INCOMPLETE][81] ([fdo#111850]) -> [PASS][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-tglb8/igt@kms_vblank@pipe-d-ts-continuation-suspend.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-tglb1/igt@kms_vblank@pipe-d-ts-continuation-suspend.html

  * igt@perf@gen8-unprivileged-single-ctx-counters:
    - shard-skl:          [INCOMPLETE][83] ([fdo#111747]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-skl8/igt@perf@gen8-unprivileged-single-ctx-counters.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-skl4/igt@perf@gen8-unprivileged-single-ctx-counters.html

  * igt@perf_pmu@busy-vcs1:
    - shard-iclb:         [SKIP][85] ([fdo#112080]) -> [PASS][86] +10 similar issues
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb3/igt@perf_pmu@busy-vcs1.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb4/igt@perf_pmu@busy-vcs1.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs2-reset:
    - shard-tglb:         [SKIP][87] ([fdo#111912] / [fdo#112080]) -> [SKIP][88] ([fdo#112080])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-tglb4/igt@gem_ctx_isolation@vcs2-reset.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-tglb9/igt@gem_ctx_isolation@vcs2-reset.html

  * igt@gem_exec_schedule@deep-bsd1:
    - shard-tglb:         [FAIL][89] ([fdo#111646]) -> [INCOMPLETE][90] ([fdo#111671])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-tglb5/igt@gem_exec_schedule@deep-bsd1.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-tglb4/igt@gem_exec_schedule@deep-bsd1.html

  * igt@kms_dp_dsc@basic-dsc-enable-edp:
    - shard-iclb:         [SKIP][91] ([fdo#109349]) -> [DMESG-WARN][92] ([fdo#107724])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb5/igt@kms_dp_dsc@basic-dsc-enable-edp.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
  [fdo#110378]: https://bugs.freedesktop.org/show_bug.cgi?id=110378
  [fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
  [fdo#111646]: https://bugs.freedesktop.org/show_bug.cgi?id=111646
  [fdo#111671]: https://bugs.freedesktop.org/show_bug.cgi?id=111671
  [fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
  [fdo#111830 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111830 
  [fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832
  [fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
  [fdo#111867]: https://bugs.freedesktop.org/show_bug.cgi?id=111867
  [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
  [fdo#111884]: https://bugs.freedesktop.org/show_bug.cgi?id=111884
  [fdo#111912]: https://bugs.freedesktop.org/show_bug.cgi?id=111912
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#112081]: https://bugs.freedesktop.org/show_bug.cgi?id=112081
  [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
  [fdo#112194]: https://bugs.freedesktop.org/show_bug.cgi?id=112194
  [fdo#112347]: https://bugs.freedesktop.org/show_bug.cgi?id=112347
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7393 -> Patchwork_15362

  CI-20190529: 20190529
  CI_DRM_7393: 0e204eb18baca0cd97950bf936fffdbbce1fd337 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5299: 65fed6a79adea14f7bef6d55530da47d7731d370 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15362: 5214c735f98323bd2165e68cec617e49668579b6 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/display: Refactor intel_commit_modeset_disables()
@ 2019-11-22  2:59   ` Patchwork
  0 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2019-11-22  2:59 UTC (permalink / raw)
  To: José Roberto de Souza; +Cc: intel-gfx

== Series Details ==

Series: series starting with [1/3] drm/i915/display: Refactor intel_commit_modeset_disables()
URL   : https://patchwork.freedesktop.org/series/69787/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7393_full -> Patchwork_15362_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_15362_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@vcs1-dirty-create:
    - shard-iclb:         [PASS][1] -> [SKIP][2] ([fdo#109276] / [fdo#112080]) +3 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb4/igt@gem_ctx_isolation@vcs1-dirty-create.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb8/igt@gem_ctx_isolation@vcs1-dirty-create.html

  * igt@gem_ctx_shared@exec-single-timeline-bsd:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([fdo#110841])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb8/igt@gem_ctx_shared@exec-single-timeline-bsd.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html

  * igt@gem_ctx_switch@vcs1-heavy:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#112080]) +12 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb4/igt@gem_ctx_switch@vcs1-heavy.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb8/igt@gem_ctx_switch@vcs1-heavy.html

  * igt@gem_eio@in-flight-suspend:
    - shard-tglb:         [PASS][7] -> [INCOMPLETE][8] ([fdo#111832] / [fdo#111850] / [fdo#112081])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-tglb1/igt@gem_eio@in-flight-suspend.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-tglb5/igt@gem_eio@in-flight-suspend.html

  * igt@gem_exec_parallel@fds:
    - shard-tglb:         [PASS][9] -> [INCOMPLETE][10] ([fdo#111867])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-tglb1/igt@gem_exec_parallel@fds.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-tglb6/igt@gem_exec_parallel@fds.html

  * igt@gem_exec_schedule@independent-bsd2:
    - shard-iclb:         [PASS][11] -> [SKIP][12] ([fdo#109276]) +17 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb4/igt@gem_exec_schedule@independent-bsd2.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb8/igt@gem_exec_schedule@independent-bsd2.html

  * igt@gem_exec_schedule@preempt-queue-bsd:
    - shard-iclb:         [PASS][13] -> [SKIP][14] ([fdo#112146]) +4 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb8/igt@gem_exec_schedule@preempt-queue-bsd.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb1/igt@gem_exec_schedule@preempt-queue-bsd.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
    - shard-hsw:          [PASS][15] -> [DMESG-WARN][16] ([fdo#111870])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-hsw6/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-hsw1/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-iclb:         [PASS][17] -> [FAIL][18] ([fdo#111830 ])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb6/igt@i915_pm_dc@dc6-dpms.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-apl:          [PASS][19] -> [DMESG-WARN][20] ([fdo#108566]) +2 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-apl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-apl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-skl:          [PASS][21] -> [INCOMPLETE][22] ([fdo#109507])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-skl5/igt@kms_flip@flip-vs-suspend-interruptible.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-skl8/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
    - shard-tglb:         [PASS][23] -> [FAIL][24] ([fdo#103167]) +2 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt:
    - shard-iclb:         [PASS][25] -> [FAIL][26] ([fdo#103167]) +7 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-rte:
    - shard-iclb:         [PASS][27] -> [FAIL][28] ([fdo#103167] / [fdo#110378])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html

  * igt@kms_frontbuffer_tracking@fbcpsr-suspend:
    - shard-tglb:         [PASS][29] -> [INCOMPLETE][30] ([fdo#111832] / [fdo#111850] / [fdo#111884])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-tglb9/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
    - shard-tglb:         [PASS][31] -> [INCOMPLETE][32] ([fdo#111832] / [fdo#111850]) +4 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-tglb4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-tglb3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [PASS][33] -> [SKIP][34] ([fdo#109441]) +1 similar issue
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb4/igt@kms_psr@psr2_cursor_render.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-kbl:          [PASS][35] -> [DMESG-WARN][36] ([fdo#108566]) +3 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  
#### Possible fixes ####

  * igt@gem_busy@close-race:
    - shard-tglb:         [INCOMPLETE][37] ([fdo#111747]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-tglb6/igt@gem_busy@close-race.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-tglb3/igt@gem_busy@close-race.html

  * igt@gem_ctx_persistence@vcs1-mixed-process:
    - shard-iclb:         [SKIP][39] ([fdo#109276] / [fdo#112080]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb6/igt@gem_ctx_persistence@vcs1-mixed-process.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb1/igt@gem_ctx_persistence@vcs1-mixed-process.html

  * igt@gem_ctx_persistence@vecs0-mixed-process:
    - shard-skl:          [FAIL][41] ([fdo#112194]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-skl1/igt@gem_ctx_persistence@vecs0-mixed-process.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-skl6/igt@gem_ctx_persistence@vecs0-mixed-process.html

  * igt@gem_exec_reloc@basic-gtt-cpu-active:
    - shard-skl:          [DMESG-WARN][43] ([fdo#106107]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-skl7/igt@gem_exec_reloc@basic-gtt-cpu-active.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-skl9/igt@gem_exec_reloc@basic-gtt-cpu-active.html

  * igt@gem_exec_schedule@preempt-contexts-bsd2:
    - shard-iclb:         [SKIP][45] ([fdo#109276]) -> [PASS][46] +13 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb8/igt@gem_exec_schedule@preempt-contexts-bsd2.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb1/igt@gem_exec_schedule@preempt-contexts-bsd2.html

  * igt@gem_exec_schedule@preemptive-hang-bsd:
    - shard-iclb:         [SKIP][47] ([fdo#112146]) -> [PASS][48] +5 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb4/igt@gem_exec_schedule@preemptive-hang-bsd.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb8/igt@gem_exec_schedule@preemptive-hang-bsd.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-snb:          [DMESG-WARN][49] ([fdo#111870]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-snb6/igt@gem_userptr_blits@dmabuf-unsync.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-snb7/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@gem_userptr_blits@sync-unmap-cycles:
    - shard-hsw:          [DMESG-WARN][51] ([fdo#111870]) -> [PASS][52] +2 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-hsw4/igt@gem_userptr_blits@sync-unmap-cycles.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-hsw7/igt@gem_userptr_blits@sync-unmap-cycles.html

  * igt@i915_pm_rpm@system-suspend:
    - shard-hsw:          [INCOMPLETE][53] ([fdo#103540] / [fdo#107807]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-hsw2/igt@i915_pm_rpm@system-suspend.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-hsw5/igt@i915_pm_rpm@system-suspend.html

  * igt@kms_big_fb@y-tiled-32bpp-rotate-0:
    - shard-skl:          [INCOMPLETE][55] ([fdo#104108] / [fdo#112347]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-skl9/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-skl2/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-kbl:          [DMESG-WARN][57] ([fdo#108566]) -> [PASS][58] +2 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt:
    - shard-tglb:         [FAIL][59] ([fdo#103167]) -> [PASS][60] +4 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-tglb9/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-1p-rte:
    - shard-iclb:         [FAIL][61] ([fdo#103167] / [fdo#110378]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-rte.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
    - shard-iclb:         [FAIL][63] ([fdo#103167]) -> [PASS][64] +5 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt:
    - shard-skl:          [FAIL][65] ([fdo#103167]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-skl1/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-skl8/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
    - shard-skl:          [FAIL][67] ([fdo#108145]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html

  * igt@kms_psr@no_drrs:
    - shard-iclb:         [FAIL][69] ([fdo#108341]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb1/igt@kms_psr@no_drrs.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb3/igt@kms_psr@no_drrs.html

  * igt@kms_psr@psr2_primary_blt:
    - shard-iclb:         [SKIP][71] ([fdo#109441]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb6/igt@kms_psr@psr2_primary_blt.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb2/igt@kms_psr@psr2_primary_blt.html

  * igt@kms_setmode@basic:
    - shard-apl:          [FAIL][73] ([fdo#99912]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-apl2/igt@kms_setmode@basic.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-apl4/igt@kms_setmode@basic.html
    - shard-glk:          [FAIL][75] ([fdo#99912]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-glk8/igt@kms_setmode@basic.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-glk2/igt@kms_setmode@basic.html
    - shard-kbl:          [FAIL][77] ([fdo#99912]) -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-kbl6/igt@kms_setmode@basic.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-kbl2/igt@kms_setmode@basic.html

  * igt@kms_vblank@pipe-c-ts-continuation-suspend:
    - shard-tglb:         [INCOMPLETE][79] ([fdo#111832] / [fdo#111850]) -> [PASS][80] +2 similar issues
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-tglb5/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-tglb2/igt@kms_vblank@pipe-c-ts-continuation-suspend.html

  * igt@kms_vblank@pipe-d-ts-continuation-suspend:
    - shard-tglb:         [INCOMPLETE][81] ([fdo#111850]) -> [PASS][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-tglb8/igt@kms_vblank@pipe-d-ts-continuation-suspend.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-tglb1/igt@kms_vblank@pipe-d-ts-continuation-suspend.html

  * igt@perf@gen8-unprivileged-single-ctx-counters:
    - shard-skl:          [INCOMPLETE][83] ([fdo#111747]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-skl8/igt@perf@gen8-unprivileged-single-ctx-counters.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-skl4/igt@perf@gen8-unprivileged-single-ctx-counters.html

  * igt@perf_pmu@busy-vcs1:
    - shard-iclb:         [SKIP][85] ([fdo#112080]) -> [PASS][86] +10 similar issues
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb3/igt@perf_pmu@busy-vcs1.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb4/igt@perf_pmu@busy-vcs1.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs2-reset:
    - shard-tglb:         [SKIP][87] ([fdo#111912] / [fdo#112080]) -> [SKIP][88] ([fdo#112080])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-tglb4/igt@gem_ctx_isolation@vcs2-reset.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-tglb9/igt@gem_ctx_isolation@vcs2-reset.html

  * igt@gem_exec_schedule@deep-bsd1:
    - shard-tglb:         [FAIL][89] ([fdo#111646]) -> [INCOMPLETE][90] ([fdo#111671])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-tglb5/igt@gem_exec_schedule@deep-bsd1.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-tglb4/igt@gem_exec_schedule@deep-bsd1.html

  * igt@kms_dp_dsc@basic-dsc-enable-edp:
    - shard-iclb:         [SKIP][91] ([fdo#109349]) -> [DMESG-WARN][92] ([fdo#107724])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7393/shard-iclb5/igt@kms_dp_dsc@basic-dsc-enable-edp.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
  [fdo#110378]: https://bugs.freedesktop.org/show_bug.cgi?id=110378
  [fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
  [fdo#111646]: https://bugs.freedesktop.org/show_bug.cgi?id=111646
  [fdo#111671]: https://bugs.freedesktop.org/show_bug.cgi?id=111671
  [fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
  [fdo#111830 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111830 
  [fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832
  [fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
  [fdo#111867]: https://bugs.freedesktop.org/show_bug.cgi?id=111867
  [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
  [fdo#111884]: https://bugs.freedesktop.org/show_bug.cgi?id=111884
  [fdo#111912]: https://bugs.freedesktop.org/show_bug.cgi?id=111912
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#112081]: https://bugs.freedesktop.org/show_bug.cgi?id=112081
  [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
  [fdo#112194]: https://bugs.freedesktop.org/show_bug.cgi?id=112194
  [fdo#112347]: https://bugs.freedesktop.org/show_bug.cgi?id=112347
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7393 -> Patchwork_15362

  CI-20190529: 20190529
  CI_DRM_7393: 0e204eb18baca0cd97950bf936fffdbbce1fd337 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5299: 65fed6a79adea14f7bef6d55530da47d7731d370 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15362: 5214c735f98323bd2165e68cec617e49668579b6 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15362/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 16+ messages in thread

end of thread, other threads:[~2019-11-22  2:59 UTC | newest]

Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-20 23:48 [PATCH 1/3] drm/i915/display: Refactor intel_commit_modeset_disables() José Roberto de Souza
2019-11-20 23:48 ` [Intel-gfx] " José Roberto de Souza
2019-11-20 23:48 ` [PATCH 2/3] drm/i915/display: Check the old state to find port sync slave José Roberto de Souza
2019-11-20 23:48   ` [Intel-gfx] " José Roberto de Souza
2019-11-20 23:48 ` [PATCH 3/3] drm/i915/tgl: Select master trasconder for MST stream José Roberto de Souza
2019-11-20 23:48   ` [Intel-gfx] " José Roberto de Souza
2019-11-21  1:53   ` Souza, Jose
2019-11-21  1:53     ` [Intel-gfx] " Souza, Jose
2019-11-21 21:20   ` [PATCH v2 " José Roberto de Souza
2019-11-21 21:20     ` [Intel-gfx] " José Roberto de Souza
2019-11-21  2:46 ` ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/display: Refactor intel_commit_modeset_disables() Patchwork
2019-11-21  2:46   ` [Intel-gfx] " Patchwork
2019-11-21 21:59 ` ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/display: Refactor intel_commit_modeset_disables() (rev2) Patchwork
2019-11-21 21:59   ` [Intel-gfx] " Patchwork
2019-11-22  2:59 ` ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/display: Refactor intel_commit_modeset_disables() Patchwork
2019-11-22  2:59   ` [Intel-gfx] " Patchwork

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