* [RFC] drm/i915/selftests: add basic selftests for rc6 @ 2019-11-21 12:57 ` Andi Shyti 0 siblings, 0 replies; 8+ messages in thread From: Andi Shyti @ 2019-11-21 12:57 UTC (permalink / raw) To: Chris Wilson; +Cc: Intel GFX Add three basic tests for rc6 power status: 1. live_rc6_basic - simply checks if rc6 works when it's enabled or stops when it's disabled. 2. live_rc6_threshold - rc6 should not work when the evaluation interval is less than the threshold and should work otherwise. 3. live_rc6_busy - keeps the gpu busy and then goes in idle; checks that we don't fall in rc6 when busy and that we do fall in rc6 when idling. The three tests are added as sutest of the bigger live_late_gt_pm selftest. The basic rc6 functionality is tested by checking the reference counter within the evaluation interval. Signed-off-by: Andi Shyti <andi.shyti@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> --- Hi, in this RC6 test the live_rc6_threshold doesn't work, either because I misinterpreted the concept, or the GPU I am using does not support something or the code I am posting is junk. Either way, ideas? Thanks, Andi drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 3 + drivers/gpu/drm/i915/gt/selftest_rc6.c | 180 +++++++++++++++++++++++ drivers/gpu/drm/i915/gt/selftest_rc6.h | 3 + 3 files changed, 186 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c index 5e563b877368..b5a872affa87 100644 --- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c +++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c @@ -68,7 +68,10 @@ int intel_gt_pm_late_selftests(struct drm_i915_private *i915) * They are intended to be run last in CI and the system * rebooted afterwards. */ + SUBTEST(live_rc6_basic), + SUBTEST(live_rc6_threshold), SUBTEST(live_rc6_ctx_wa), + SUBTEST(live_rc6_busy), }; if (intel_gt_is_wedged(&i915->gt)) diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c index 67b7a6bc64f5..c80d17f3da10 100644 --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c @@ -11,6 +11,31 @@ #include "selftest_rc6.h" #include "selftests/i915_random.h" +#include "selftests/igt_spinner.h" + +static bool test_rc6(struct drm_i915_private *dev_priv, bool enabled) +{ + u32 ec1, ec2; + u64 interval; + + interval = I915_READ(GEN6_RC_EVALUATION_INTERVAL); + + /* + * the interval is stored in steps of 1.28us + */ + interval = interval * 128 / 100 / 1000; /* miliseconds */ + + ec1 = I915_READ(GEN6_GT_GFX_RC6); + /* + * it's not important to precisely wait the interval time. + * I'll wait at least twice the time in order to be sure + * that the counting happens in the reference counter. + */ + msleep(2 * interval); + ec2 = I915_READ(GEN6_GT_GFX_RC6); + + return enabled != (ec1 >= ec2); +} static const u32 *__live_rc6_ctx(struct intel_context *ce) { @@ -144,3 +169,158 @@ int live_rc6_ctx_wa(void *arg) kfree(engines); return err; } + +int live_rc6_basic(void *arg) +{ + struct intel_gt *gt = arg; + struct intel_rc6 *rc6 = >->rc6; + int i, err = 0; + + if (!HAS_RC6(gt->i915)) + return -ENODEV; + + /* + * the two loops test rc6 both in case it's enabled + * and in the case it's disabled. It restores the prvious + * status + */ + for (i = 0; i < 2; i++) { + if (!test_rc6(gt->i915, rc6->enabled)) { + if (!i) + return -EINVAL; + + /* restore before leaving */ + err = -EINVAL; + } + + if (rc6->enabled) + intel_rc6_disable(>->rc6); + else + intel_rc6_enable(>->rc6); + } + + return err; +} + +int live_rc6_threshold(void *arg) +{ + struct intel_gt *gt = arg; + struct drm_i915_private *dev_priv = gt->i915; + u32 threshold, interval; + u32 t_orig, i_orig; + int err = 0; + + t_orig = I915_READ(GEN6_RC6_THRESHOLD); + i_orig = I915_READ(GEN6_RC_EVALUATION_INTERVAL); + + /* + * set the threshold to 50ms + * + * 50ms * 1000 = 50000us + * 50000 / (1.28 * 100) / 100 (we don't have floating point) + */ + threshold = 50 * 1000 / 128 * 100; + I915_WRITE(GEN6_RC6_THRESHOLD, threshold); + + /* set interval indicatively to half the threshold */ + interval = threshold / 2; + I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, interval); + + /* interval < threshold */ + if (!test_rc6(gt->i915, false)) { + err = -EINVAL; + pr_err("i915 mismatch: rc6 with interval < threshold\n"); + goto out; + } + + /* set interval indicatively to twice the threshold */ + interval = threshold * 2; + I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, interval); + + /* interval > threshold */ + if (!test_rc6(gt->i915, true)) { + err = -EINVAL; + pr_err("i915 mismatch: not in rc6 with interval > threshold\n"); + } + +out: + I915_WRITE(GEN6_RC6_THRESHOLD, t_orig); + I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, i_orig); + + return err; +} + +static int rc6_busy_thread(void *arg) +{ + struct intel_engine_cs *engine; + struct intel_gt *gt = arg; + struct igt_spinner spin; + enum intel_engine_id id; + struct i915_request *rq; + int err = 0; + + /* any existing engine in the current gt is good */ + for_each_engine(engine, gt, id) + break; + + err = igt_spinner_init(&spin, gt); + if (err) + return err; + + rq = igt_spinner_create_request(&spin, engine->kernel_context, MI_NOOP); + if (IS_ERR(rq)) { + err = PTR_ERR(rq); + goto out; + } + + i915_request_get(rq); + i915_request_add(rq); + igt_wait_for_spinner(&spin, rq); /* it's enough waiting */ + igt_spinner_end(&spin); + + i915_request_wait(rq, 0, HZ / 5); + i915_request_put(rq); + +out: + igt_spinner_fini(&spin); + return err; +} + +int live_rc6_busy(void *arg) +{ + struct intel_gt *gt = arg; + struct task_struct *thread; + int err = 0; + + thread = kmalloc(sizeof(*thread), GFP_KERNEL); + if (!thread) + return -ENOMEM; + + thread = kthread_run(rc6_busy_thread, arg, "rc6_busy_selftest"); + if (IS_ERR(thread)) + return PTR_ERR(thread); + + get_task_struct(thread); + + /* gpu is busy, we shouldn't be in rc6 */ + if (!test_rc6(gt->i915, false)) { + err = -EINVAL; + pr_err("never busy enough for having a nap\n"); + } + + err = kthread_stop(thread); + if (err < 0) + pr_err("fail and exit\n"); + + put_task_struct(thread); + + intel_gt_pm_wait_for_idle(gt); + + /* gpu is busy, we should be in rc6 */ + if (!test_rc6(gt->i915, true)) { + err = -EINVAL; + pr_err("i915 is idle but doesn't go in rc6\n"); + } + + return err; +} diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.h b/drivers/gpu/drm/i915/gt/selftest_rc6.h index f907e7b035ab..23e7945e9eed 100644 --- a/drivers/gpu/drm/i915/gt/selftest_rc6.h +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.h @@ -7,6 +7,9 @@ #ifndef SELFTEST_RC6_H #define SELFTEST_RC6_H +int live_rc6_basic(void *arg); +int live_rc6_threshold(void *arg); +int live_rc6_busy(void *arg); int live_rc6_ctx_wa(void *arg); #endif /* SELFTEST_RC6_H */ -- 2.24.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] [RFC] drm/i915/selftests: add basic selftests for rc6 @ 2019-11-21 12:57 ` Andi Shyti 0 siblings, 0 replies; 8+ messages in thread From: Andi Shyti @ 2019-11-21 12:57 UTC (permalink / raw) To: Chris Wilson; +Cc: Intel GFX Add three basic tests for rc6 power status: 1. live_rc6_basic - simply checks if rc6 works when it's enabled or stops when it's disabled. 2. live_rc6_threshold - rc6 should not work when the evaluation interval is less than the threshold and should work otherwise. 3. live_rc6_busy - keeps the gpu busy and then goes in idle; checks that we don't fall in rc6 when busy and that we do fall in rc6 when idling. The three tests are added as sutest of the bigger live_late_gt_pm selftest. The basic rc6 functionality is tested by checking the reference counter within the evaluation interval. Signed-off-by: Andi Shyti <andi.shyti@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> --- Hi, in this RC6 test the live_rc6_threshold doesn't work, either because I misinterpreted the concept, or the GPU I am using does not support something or the code I am posting is junk. Either way, ideas? Thanks, Andi drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 3 + drivers/gpu/drm/i915/gt/selftest_rc6.c | 180 +++++++++++++++++++++++ drivers/gpu/drm/i915/gt/selftest_rc6.h | 3 + 3 files changed, 186 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c index 5e563b877368..b5a872affa87 100644 --- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c +++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c @@ -68,7 +68,10 @@ int intel_gt_pm_late_selftests(struct drm_i915_private *i915) * They are intended to be run last in CI and the system * rebooted afterwards. */ + SUBTEST(live_rc6_basic), + SUBTEST(live_rc6_threshold), SUBTEST(live_rc6_ctx_wa), + SUBTEST(live_rc6_busy), }; if (intel_gt_is_wedged(&i915->gt)) diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c index 67b7a6bc64f5..c80d17f3da10 100644 --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c @@ -11,6 +11,31 @@ #include "selftest_rc6.h" #include "selftests/i915_random.h" +#include "selftests/igt_spinner.h" + +static bool test_rc6(struct drm_i915_private *dev_priv, bool enabled) +{ + u32 ec1, ec2; + u64 interval; + + interval = I915_READ(GEN6_RC_EVALUATION_INTERVAL); + + /* + * the interval is stored in steps of 1.28us + */ + interval = interval * 128 / 100 / 1000; /* miliseconds */ + + ec1 = I915_READ(GEN6_GT_GFX_RC6); + /* + * it's not important to precisely wait the interval time. + * I'll wait at least twice the time in order to be sure + * that the counting happens in the reference counter. + */ + msleep(2 * interval); + ec2 = I915_READ(GEN6_GT_GFX_RC6); + + return enabled != (ec1 >= ec2); +} static const u32 *__live_rc6_ctx(struct intel_context *ce) { @@ -144,3 +169,158 @@ int live_rc6_ctx_wa(void *arg) kfree(engines); return err; } + +int live_rc6_basic(void *arg) +{ + struct intel_gt *gt = arg; + struct intel_rc6 *rc6 = >->rc6; + int i, err = 0; + + if (!HAS_RC6(gt->i915)) + return -ENODEV; + + /* + * the two loops test rc6 both in case it's enabled + * and in the case it's disabled. It restores the prvious + * status + */ + for (i = 0; i < 2; i++) { + if (!test_rc6(gt->i915, rc6->enabled)) { + if (!i) + return -EINVAL; + + /* restore before leaving */ + err = -EINVAL; + } + + if (rc6->enabled) + intel_rc6_disable(>->rc6); + else + intel_rc6_enable(>->rc6); + } + + return err; +} + +int live_rc6_threshold(void *arg) +{ + struct intel_gt *gt = arg; + struct drm_i915_private *dev_priv = gt->i915; + u32 threshold, interval; + u32 t_orig, i_orig; + int err = 0; + + t_orig = I915_READ(GEN6_RC6_THRESHOLD); + i_orig = I915_READ(GEN6_RC_EVALUATION_INTERVAL); + + /* + * set the threshold to 50ms + * + * 50ms * 1000 = 50000us + * 50000 / (1.28 * 100) / 100 (we don't have floating point) + */ + threshold = 50 * 1000 / 128 * 100; + I915_WRITE(GEN6_RC6_THRESHOLD, threshold); + + /* set interval indicatively to half the threshold */ + interval = threshold / 2; + I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, interval); + + /* interval < threshold */ + if (!test_rc6(gt->i915, false)) { + err = -EINVAL; + pr_err("i915 mismatch: rc6 with interval < threshold\n"); + goto out; + } + + /* set interval indicatively to twice the threshold */ + interval = threshold * 2; + I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, interval); + + /* interval > threshold */ + if (!test_rc6(gt->i915, true)) { + err = -EINVAL; + pr_err("i915 mismatch: not in rc6 with interval > threshold\n"); + } + +out: + I915_WRITE(GEN6_RC6_THRESHOLD, t_orig); + I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, i_orig); + + return err; +} + +static int rc6_busy_thread(void *arg) +{ + struct intel_engine_cs *engine; + struct intel_gt *gt = arg; + struct igt_spinner spin; + enum intel_engine_id id; + struct i915_request *rq; + int err = 0; + + /* any existing engine in the current gt is good */ + for_each_engine(engine, gt, id) + break; + + err = igt_spinner_init(&spin, gt); + if (err) + return err; + + rq = igt_spinner_create_request(&spin, engine->kernel_context, MI_NOOP); + if (IS_ERR(rq)) { + err = PTR_ERR(rq); + goto out; + } + + i915_request_get(rq); + i915_request_add(rq); + igt_wait_for_spinner(&spin, rq); /* it's enough waiting */ + igt_spinner_end(&spin); + + i915_request_wait(rq, 0, HZ / 5); + i915_request_put(rq); + +out: + igt_spinner_fini(&spin); + return err; +} + +int live_rc6_busy(void *arg) +{ + struct intel_gt *gt = arg; + struct task_struct *thread; + int err = 0; + + thread = kmalloc(sizeof(*thread), GFP_KERNEL); + if (!thread) + return -ENOMEM; + + thread = kthread_run(rc6_busy_thread, arg, "rc6_busy_selftest"); + if (IS_ERR(thread)) + return PTR_ERR(thread); + + get_task_struct(thread); + + /* gpu is busy, we shouldn't be in rc6 */ + if (!test_rc6(gt->i915, false)) { + err = -EINVAL; + pr_err("never busy enough for having a nap\n"); + } + + err = kthread_stop(thread); + if (err < 0) + pr_err("fail and exit\n"); + + put_task_struct(thread); + + intel_gt_pm_wait_for_idle(gt); + + /* gpu is busy, we should be in rc6 */ + if (!test_rc6(gt->i915, true)) { + err = -EINVAL; + pr_err("i915 is idle but doesn't go in rc6\n"); + } + + return err; +} diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.h b/drivers/gpu/drm/i915/gt/selftest_rc6.h index f907e7b035ab..23e7945e9eed 100644 --- a/drivers/gpu/drm/i915/gt/selftest_rc6.h +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.h @@ -7,6 +7,9 @@ #ifndef SELFTEST_RC6_H #define SELFTEST_RC6_H +int live_rc6_basic(void *arg); +int live_rc6_threshold(void *arg); +int live_rc6_busy(void *arg); int live_rc6_ctx_wa(void *arg); #endif /* SELFTEST_RC6_H */ -- 2.24.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [RFC] drm/i915/selftests: add basic selftests for rc6 @ 2019-11-21 13:21 ` Chris Wilson 0 siblings, 0 replies; 8+ messages in thread From: Chris Wilson @ 2019-11-21 13:21 UTC (permalink / raw) To: Andi Shyti; +Cc: Intel GFX Quoting Andi Shyti (2019-11-21 12:57:47) > Add three basic tests for rc6 power status: > > 1. live_rc6_basic - simply checks if rc6 works when it's enabled > or stops when it's disabled. > > 2. live_rc6_threshold - rc6 should not work when the evaluation > interval is less than the threshold and should work otherwise. > > 3. live_rc6_busy - keeps the gpu busy and then goes in idle; > checks that we don't fall in rc6 when busy and that we do fall > in rc6 when idling. > > The three tests are added as sutest of the bigger live_late_gt_pm > selftest. > > The basic rc6 functionality is tested by checking the reference > counter within the evaluation interval. > > Signed-off-by: Andi Shyti <andi.shyti@intel.com> > Cc: Chris Wilson <chris@chris-wilson.co.uk> > --- > Hi, > > in this RC6 test the live_rc6_threshold doesn't work, either > because I misinterpreted the concept, or the GPU I am using does > not support something or the code I am posting is junk. Either > way, ideas? > > Thanks, > Andi > > drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 3 + > drivers/gpu/drm/i915/gt/selftest_rc6.c | 180 +++++++++++++++++++++++ > drivers/gpu/drm/i915/gt/selftest_rc6.h | 3 + > 3 files changed, 186 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c > index 5e563b877368..b5a872affa87 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c > +++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c > @@ -68,7 +68,10 @@ int intel_gt_pm_late_selftests(struct drm_i915_private *i915) > * They are intended to be run last in CI and the system > * rebooted afterwards. > */ > + SUBTEST(live_rc6_basic), > + SUBTEST(live_rc6_threshold), > SUBTEST(live_rc6_ctx_wa), > + SUBTEST(live_rc6_busy), The newcomers should be safe, right? No reason not to put them in the normal gt_pm_selftests rather than the dangerous dungeon? > }; > > if (intel_gt_is_wedged(&i915->gt)) > diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c > index 67b7a6bc64f5..c80d17f3da10 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c > +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c > @@ -11,6 +11,31 @@ > #include "selftest_rc6.h" > > #include "selftests/i915_random.h" > +#include "selftests/igt_spinner.h" > + > +static bool test_rc6(struct drm_i915_private *dev_priv, bool enabled) > +{ > + u32 ec1, ec2; > + u64 interval; > + > + interval = I915_READ(GEN6_RC_EVALUATION_INTERVAL); intel_uncore_read()! > + > + /* > + * the interval is stored in steps of 1.28us > + */ > + interval = interval * 128 / 100 / 1000; /* miliseconds */ interval = div_u64(mul_u32_u32(interval, 128), 100 * 1000); or CI will complain about breaking 32b builds. > + > + ec1 = I915_READ(GEN6_GT_GFX_RC6); > + /* > + * it's not important to precisely wait the interval time. > + * I'll wait at least twice the time in order to be sure > + * that the counting happens in the reference counter. > + */ > + msleep(2 * interval); > + ec2 = I915_READ(GEN6_GT_GFX_RC6); Hmm, I still don't trust msleep, but this will do as a first approximation. > + > + return enabled != (ec1 >= ec2); Ok. So sleep for a bit and check the rc6 counter is incrementing. Assumes we are already idle, probably best to add an explicit intel_gt_pm_wait_for_idle() at the start of the rc6 tests (or intel_gt_pm_selftests in general). > +} > > static const u32 *__live_rc6_ctx(struct intel_context *ce) > { > @@ -144,3 +169,158 @@ int live_rc6_ctx_wa(void *arg) > kfree(engines); > return err; > } > + > +int live_rc6_basic(void *arg) > +{ > + struct intel_gt *gt = arg; > + struct intel_rc6 *rc6 = >->rc6; > + int i, err = 0; > + > + if (!HAS_RC6(gt->i915)) > + return -ENODEV; > + > + /* > + * the two loops test rc6 both in case it's enabled > + * and in the case it's disabled. It restores the prvious > + * status > + */ > + for (i = 0; i < 2; i++) { > + if (!test_rc6(gt->i915, rc6->enabled)) { > + if (!i) > + return -EINVAL; > + > + /* restore before leaving */ > + err = -EINVAL; > + } > + > + if (rc6->enabled) > + intel_rc6_disable(>->rc6); > + else > + intel_rc6_enable(>->rc6); > + } > + > + return err; > +} > + > +int live_rc6_threshold(void *arg) > +{ > + struct intel_gt *gt = arg; > + struct drm_i915_private *dev_priv = gt->i915; > + u32 threshold, interval; > + u32 t_orig, i_orig; > + int err = 0; > + > + t_orig = I915_READ(GEN6_RC6_THRESHOLD); > + i_orig = I915_READ(GEN6_RC_EVALUATION_INTERVAL); > + > + /* > + * set the threshold to 50ms > + * > + * 50ms * 1000 = 50000us > + * 50000 / (1.28 * 100) / 100 (we don't have floating point) > + */ > + threshold = 50 * 1000 / 128 * 100; > + I915_WRITE(GEN6_RC6_THRESHOLD, threshold); > + > + /* set interval indicatively to half the threshold */ > + interval = threshold / 2; > + I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, interval); > + > + /* interval < threshold */ > + if (!test_rc6(gt->i915, false)) { > + err = -EINVAL; > + pr_err("i915 mismatch: rc6 with interval < threshold\n"); > + goto out; > + } > + /* set interval indicatively to twice the threshold */ > + interval = threshold * 2; > + I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, interval); > + > + /* interval > threshold */ > + if (!test_rc6(gt->i915, true)) { > + err = -EINVAL; > + pr_err("i915 mismatch: not in rc6 with interval > threshold\n"); > + } > + > +out: > + I915_WRITE(GEN6_RC6_THRESHOLD, t_orig); > + I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, i_orig); > + > + return err; > +} > + > +static int rc6_busy_thread(void *arg) > +{ > + struct intel_engine_cs *engine; > + struct intel_gt *gt = arg; > + struct igt_spinner spin; > + enum intel_engine_id id; > + struct i915_request *rq; > + int err = 0; > + > + /* any existing engine in the current gt is good */ > + for_each_engine(engine, gt, id) > + break; > + > + err = igt_spinner_init(&spin, gt); > + if (err) > + return err; > + > + rq = igt_spinner_create_request(&spin, engine->kernel_context, MI_NOOP); > + if (IS_ERR(rq)) { > + err = PTR_ERR(rq); > + goto out; > + } > + > + i915_request_get(rq); > + i915_request_add(rq); > + igt_wait_for_spinner(&spin, rq); /* it's enough waiting */ > + igt_spinner_end(&spin); > + > + i915_request_wait(rq, 0, HZ / 5); > + i915_request_put(rq); > + > +out: > + igt_spinner_fini(&spin); > + return err; > +} > + > +int live_rc6_busy(void *arg) > +{ > + struct intel_gt *gt = arg; > + struct task_struct *thread; > + int err = 0; > + > + thread = kmalloc(sizeof(*thread), GFP_KERNEL); > + if (!thread) > + return -ENOMEM; > + > + thread = kthread_run(rc6_busy_thread, arg, "rc6_busy_selftest"); > + if (IS_ERR(thread)) > + return PTR_ERR(thread); > + > + get_task_struct(thread); > + > + /* gpu is busy, we shouldn't be in rc6 */ > + if (!test_rc6(gt->i915, false)) { > + err = -EINVAL; > + pr_err("never busy enough for having a nap\n"); > + } I would have used the spinner inline so you have better control over it. As it you you don't sync with the thread before starting and whatnot. > + > + err = kthread_stop(thread); > + if (err < 0) > + pr_err("fail and exit\n"); > + > + put_task_struct(thread); > + > + intel_gt_pm_wait_for_idle(gt); > + > + /* gpu is busy, we should be in rc6 */ > + if (!test_rc6(gt->i915, true)) { > + err = -EINVAL; > + pr_err("i915 is idle but doesn't go in rc6\n"); > + } Aye, this tail is perhaps the most important test of them all! :) Ok, looks like we have the makings of some very useful tests. Lets see why they aren't behaving... -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [RFC] drm/i915/selftests: add basic selftests for rc6 @ 2019-11-21 13:21 ` Chris Wilson 0 siblings, 0 replies; 8+ messages in thread From: Chris Wilson @ 2019-11-21 13:21 UTC (permalink / raw) To: Andi Shyti; +Cc: Intel GFX Quoting Andi Shyti (2019-11-21 12:57:47) > Add three basic tests for rc6 power status: > > 1. live_rc6_basic - simply checks if rc6 works when it's enabled > or stops when it's disabled. > > 2. live_rc6_threshold - rc6 should not work when the evaluation > interval is less than the threshold and should work otherwise. > > 3. live_rc6_busy - keeps the gpu busy and then goes in idle; > checks that we don't fall in rc6 when busy and that we do fall > in rc6 when idling. > > The three tests are added as sutest of the bigger live_late_gt_pm > selftest. > > The basic rc6 functionality is tested by checking the reference > counter within the evaluation interval. > > Signed-off-by: Andi Shyti <andi.shyti@intel.com> > Cc: Chris Wilson <chris@chris-wilson.co.uk> > --- > Hi, > > in this RC6 test the live_rc6_threshold doesn't work, either > because I misinterpreted the concept, or the GPU I am using does > not support something or the code I am posting is junk. Either > way, ideas? > > Thanks, > Andi > > drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 3 + > drivers/gpu/drm/i915/gt/selftest_rc6.c | 180 +++++++++++++++++++++++ > drivers/gpu/drm/i915/gt/selftest_rc6.h | 3 + > 3 files changed, 186 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c > index 5e563b877368..b5a872affa87 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c > +++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c > @@ -68,7 +68,10 @@ int intel_gt_pm_late_selftests(struct drm_i915_private *i915) > * They are intended to be run last in CI and the system > * rebooted afterwards. > */ > + SUBTEST(live_rc6_basic), > + SUBTEST(live_rc6_threshold), > SUBTEST(live_rc6_ctx_wa), > + SUBTEST(live_rc6_busy), The newcomers should be safe, right? No reason not to put them in the normal gt_pm_selftests rather than the dangerous dungeon? > }; > > if (intel_gt_is_wedged(&i915->gt)) > diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c > index 67b7a6bc64f5..c80d17f3da10 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c > +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c > @@ -11,6 +11,31 @@ > #include "selftest_rc6.h" > > #include "selftests/i915_random.h" > +#include "selftests/igt_spinner.h" > + > +static bool test_rc6(struct drm_i915_private *dev_priv, bool enabled) > +{ > + u32 ec1, ec2; > + u64 interval; > + > + interval = I915_READ(GEN6_RC_EVALUATION_INTERVAL); intel_uncore_read()! > + > + /* > + * the interval is stored in steps of 1.28us > + */ > + interval = interval * 128 / 100 / 1000; /* miliseconds */ interval = div_u64(mul_u32_u32(interval, 128), 100 * 1000); or CI will complain about breaking 32b builds. > + > + ec1 = I915_READ(GEN6_GT_GFX_RC6); > + /* > + * it's not important to precisely wait the interval time. > + * I'll wait at least twice the time in order to be sure > + * that the counting happens in the reference counter. > + */ > + msleep(2 * interval); > + ec2 = I915_READ(GEN6_GT_GFX_RC6); Hmm, I still don't trust msleep, but this will do as a first approximation. > + > + return enabled != (ec1 >= ec2); Ok. So sleep for a bit and check the rc6 counter is incrementing. Assumes we are already idle, probably best to add an explicit intel_gt_pm_wait_for_idle() at the start of the rc6 tests (or intel_gt_pm_selftests in general). > +} > > static const u32 *__live_rc6_ctx(struct intel_context *ce) > { > @@ -144,3 +169,158 @@ int live_rc6_ctx_wa(void *arg) > kfree(engines); > return err; > } > + > +int live_rc6_basic(void *arg) > +{ > + struct intel_gt *gt = arg; > + struct intel_rc6 *rc6 = >->rc6; > + int i, err = 0; > + > + if (!HAS_RC6(gt->i915)) > + return -ENODEV; > + > + /* > + * the two loops test rc6 both in case it's enabled > + * and in the case it's disabled. It restores the prvious > + * status > + */ > + for (i = 0; i < 2; i++) { > + if (!test_rc6(gt->i915, rc6->enabled)) { > + if (!i) > + return -EINVAL; > + > + /* restore before leaving */ > + err = -EINVAL; > + } > + > + if (rc6->enabled) > + intel_rc6_disable(>->rc6); > + else > + intel_rc6_enable(>->rc6); > + } > + > + return err; > +} > + > +int live_rc6_threshold(void *arg) > +{ > + struct intel_gt *gt = arg; > + struct drm_i915_private *dev_priv = gt->i915; > + u32 threshold, interval; > + u32 t_orig, i_orig; > + int err = 0; > + > + t_orig = I915_READ(GEN6_RC6_THRESHOLD); > + i_orig = I915_READ(GEN6_RC_EVALUATION_INTERVAL); > + > + /* > + * set the threshold to 50ms > + * > + * 50ms * 1000 = 50000us > + * 50000 / (1.28 * 100) / 100 (we don't have floating point) > + */ > + threshold = 50 * 1000 / 128 * 100; > + I915_WRITE(GEN6_RC6_THRESHOLD, threshold); > + > + /* set interval indicatively to half the threshold */ > + interval = threshold / 2; > + I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, interval); > + > + /* interval < threshold */ > + if (!test_rc6(gt->i915, false)) { > + err = -EINVAL; > + pr_err("i915 mismatch: rc6 with interval < threshold\n"); > + goto out; > + } > + /* set interval indicatively to twice the threshold */ > + interval = threshold * 2; > + I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, interval); > + > + /* interval > threshold */ > + if (!test_rc6(gt->i915, true)) { > + err = -EINVAL; > + pr_err("i915 mismatch: not in rc6 with interval > threshold\n"); > + } > + > +out: > + I915_WRITE(GEN6_RC6_THRESHOLD, t_orig); > + I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, i_orig); > + > + return err; > +} > + > +static int rc6_busy_thread(void *arg) > +{ > + struct intel_engine_cs *engine; > + struct intel_gt *gt = arg; > + struct igt_spinner spin; > + enum intel_engine_id id; > + struct i915_request *rq; > + int err = 0; > + > + /* any existing engine in the current gt is good */ > + for_each_engine(engine, gt, id) > + break; > + > + err = igt_spinner_init(&spin, gt); > + if (err) > + return err; > + > + rq = igt_spinner_create_request(&spin, engine->kernel_context, MI_NOOP); > + if (IS_ERR(rq)) { > + err = PTR_ERR(rq); > + goto out; > + } > + > + i915_request_get(rq); > + i915_request_add(rq); > + igt_wait_for_spinner(&spin, rq); /* it's enough waiting */ > + igt_spinner_end(&spin); > + > + i915_request_wait(rq, 0, HZ / 5); > + i915_request_put(rq); > + > +out: > + igt_spinner_fini(&spin); > + return err; > +} > + > +int live_rc6_busy(void *arg) > +{ > + struct intel_gt *gt = arg; > + struct task_struct *thread; > + int err = 0; > + > + thread = kmalloc(sizeof(*thread), GFP_KERNEL); > + if (!thread) > + return -ENOMEM; > + > + thread = kthread_run(rc6_busy_thread, arg, "rc6_busy_selftest"); > + if (IS_ERR(thread)) > + return PTR_ERR(thread); > + > + get_task_struct(thread); > + > + /* gpu is busy, we shouldn't be in rc6 */ > + if (!test_rc6(gt->i915, false)) { > + err = -EINVAL; > + pr_err("never busy enough for having a nap\n"); > + } I would have used the spinner inline so you have better control over it. As it you you don't sync with the thread before starting and whatnot. > + > + err = kthread_stop(thread); > + if (err < 0) > + pr_err("fail and exit\n"); > + > + put_task_struct(thread); > + > + intel_gt_pm_wait_for_idle(gt); > + > + /* gpu is busy, we should be in rc6 */ > + if (!test_rc6(gt->i915, true)) { > + err = -EINVAL; > + pr_err("i915 is idle but doesn't go in rc6\n"); > + } Aye, this tail is perhaps the most important test of them all! :) Ok, looks like we have the makings of some very useful tests. Lets see why they aren't behaving... -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/selftests: add basic selftests for rc6 @ 2019-11-21 15:48 ` Patchwork 0 siblings, 0 replies; 8+ messages in thread From: Patchwork @ 2019-11-21 15:48 UTC (permalink / raw) To: Andi Shyti; +Cc: intel-gfx == Series Details == Series: drm/i915/selftests: add basic selftests for rc6 URL : https://patchwork.freedesktop.org/series/69825/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7400 -> Patchwork_15376 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_15376 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_15376, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_15376: ### IGT changes ### #### Possible regressions #### * igt@runner@aborted: - fi-kbl-soraka: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-kbl-soraka/igt@runner@aborted.html - fi-kbl-7500u: NOTRUN -> [FAIL][2] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-kbl-7500u/igt@runner@aborted.html - fi-whl-u: NOTRUN -> [FAIL][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-whl-u/igt@runner@aborted.html - fi-bxt-dsi: NOTRUN -> [FAIL][4] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-bxt-dsi/igt@runner@aborted.html - fi-kbl-x1275: NOTRUN -> [FAIL][5] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-kbl-x1275/igt@runner@aborted.html - fi-cfl-8700k: NOTRUN -> [FAIL][6] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-cfl-8700k/igt@runner@aborted.html - fi-kbl-8809g: NOTRUN -> [FAIL][7] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-kbl-8809g/igt@runner@aborted.html - fi-kbl-r: NOTRUN -> [FAIL][8] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-kbl-r/igt@runner@aborted.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt@i915_selftest@live_late_gt_pm}: - fi-bsw-kefka: [PASS][9] -> [DMESG-FAIL][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-bsw-kefka/igt@i915_selftest@live_late_gt_pm.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-bsw-kefka/igt@i915_selftest@live_late_gt_pm.html - fi-pnv-d510: [PASS][11] -> [DMESG-FAIL][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-pnv-d510/igt@i915_selftest@live_late_gt_pm.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-pnv-d510/igt@i915_selftest@live_late_gt_pm.html - fi-skl-6600u: [PASS][13] -> [DMESG-FAIL][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-skl-6600u/igt@i915_selftest@live_late_gt_pm.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-skl-6600u/igt@i915_selftest@live_late_gt_pm.html - fi-apl-guc: [PASS][15] -> [DMESG-FAIL][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-apl-guc/igt@i915_selftest@live_late_gt_pm.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-apl-guc/igt@i915_selftest@live_late_gt_pm.html - fi-bdw-5557u: [PASS][17] -> [DMESG-FAIL][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-bdw-5557u/igt@i915_selftest@live_late_gt_pm.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-bdw-5557u/igt@i915_selftest@live_late_gt_pm.html - fi-glk-dsi: [PASS][19] -> [DMESG-FAIL][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-glk-dsi/igt@i915_selftest@live_late_gt_pm.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-glk-dsi/igt@i915_selftest@live_late_gt_pm.html - fi-kbl-guc: [PASS][21] -> [DMESG-FAIL][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-kbl-guc/igt@i915_selftest@live_late_gt_pm.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-kbl-guc/igt@i915_selftest@live_late_gt_pm.html - fi-hsw-4770: [PASS][23] -> [DMESG-FAIL][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-hsw-4770/igt@i915_selftest@live_late_gt_pm.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-hsw-4770/igt@i915_selftest@live_late_gt_pm.html - fi-kbl-7500u: [PASS][25] -> [DMESG-FAIL][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-kbl-7500u/igt@i915_selftest@live_late_gt_pm.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-kbl-7500u/igt@i915_selftest@live_late_gt_pm.html - fi-cml-u2: [PASS][27] -> [DMESG-FAIL][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-cml-u2/igt@i915_selftest@live_late_gt_pm.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-cml-u2/igt@i915_selftest@live_late_gt_pm.html - fi-bxt-dsi: [PASS][29] -> [DMESG-WARN][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-bxt-dsi/igt@i915_selftest@live_late_gt_pm.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-bxt-dsi/igt@i915_selftest@live_late_gt_pm.html - fi-skl-guc: [PASS][31] -> [DMESG-FAIL][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-skl-guc/igt@i915_selftest@live_late_gt_pm.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-skl-guc/igt@i915_selftest@live_late_gt_pm.html - fi-bsw-n3050: [PASS][33] -> [DMESG-FAIL][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-bsw-n3050/igt@i915_selftest@live_late_gt_pm.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-bsw-n3050/igt@i915_selftest@live_late_gt_pm.html - fi-ilk-650: [PASS][35] -> [DMESG-FAIL][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-ilk-650/igt@i915_selftest@live_late_gt_pm.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-ilk-650/igt@i915_selftest@live_late_gt_pm.html - fi-icl-u2: [PASS][37] -> [DMESG-WARN][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-icl-u2/igt@i915_selftest@live_late_gt_pm.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-icl-u2/igt@i915_selftest@live_late_gt_pm.html - fi-kbl-x1275: [PASS][39] -> [DMESG-FAIL][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-kbl-x1275/igt@i915_selftest@live_late_gt_pm.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-kbl-x1275/igt@i915_selftest@live_late_gt_pm.html - fi-hsw-peppy: [PASS][41] -> [DMESG-FAIL][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-hsw-peppy/igt@i915_selftest@live_late_gt_pm.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-hsw-peppy/igt@i915_selftest@live_late_gt_pm.html - fi-cfl-8700k: [PASS][43] -> [DMESG-FAIL][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-cfl-8700k/igt@i915_selftest@live_late_gt_pm.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-cfl-8700k/igt@i915_selftest@live_late_gt_pm.html - fi-gdg-551: [PASS][45] -> [DMESG-FAIL][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-gdg-551/igt@i915_selftest@live_late_gt_pm.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-gdg-551/igt@i915_selftest@live_late_gt_pm.html - fi-snb-2520m: [PASS][47] -> [DMESG-FAIL][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-snb-2520m/igt@i915_selftest@live_late_gt_pm.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-snb-2520m/igt@i915_selftest@live_late_gt_pm.html - fi-bsw-nick: [PASS][49] -> [DMESG-FAIL][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-bsw-nick/igt@i915_selftest@live_late_gt_pm.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-bsw-nick/igt@i915_selftest@live_late_gt_pm.html - fi-skl-lmem: NOTRUN -> [DMESG-WARN][51] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-skl-lmem/igt@i915_selftest@live_late_gt_pm.html - fi-kbl-soraka: [PASS][52] -> [DMESG-WARN][53] [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-kbl-soraka/igt@i915_selftest@live_late_gt_pm.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-kbl-soraka/igt@i915_selftest@live_late_gt_pm.html - fi-kbl-8809g: [PASS][54] -> [DMESG-FAIL][55] [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-kbl-8809g/igt@i915_selftest@live_late_gt_pm.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-kbl-8809g/igt@i915_selftest@live_late_gt_pm.html - fi-kbl-r: [PASS][56] -> [DMESG-FAIL][57] [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-kbl-r/igt@i915_selftest@live_late_gt_pm.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-kbl-r/igt@i915_selftest@live_late_gt_pm.html - fi-bwr-2160: [PASS][58] -> [DMESG-FAIL][59] [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-bwr-2160/igt@i915_selftest@live_late_gt_pm.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-bwr-2160/igt@i915_selftest@live_late_gt_pm.html - fi-byt-n2820: [PASS][60] -> [DMESG-WARN][61] [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-byt-n2820/igt@i915_selftest@live_late_gt_pm.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-byt-n2820/igt@i915_selftest@live_late_gt_pm.html - fi-skl-6770hq: [PASS][62] -> [DMESG-FAIL][63] [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-skl-6770hq/igt@i915_selftest@live_late_gt_pm.html [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-skl-6770hq/igt@i915_selftest@live_late_gt_pm.html - fi-icl-u3: [PASS][64] -> [DMESG-FAIL][65] [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-icl-u3/igt@i915_selftest@live_late_gt_pm.html [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-icl-u3/igt@i915_selftest@live_late_gt_pm.html - fi-whl-u: [PASS][66] -> [DMESG-FAIL][67] [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-whl-u/igt@i915_selftest@live_late_gt_pm.html [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-whl-u/igt@i915_selftest@live_late_gt_pm.html - {fi-kbl-7560u}: [PASS][68] -> [DMESG-FAIL][69] [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-kbl-7560u/igt@i915_selftest@live_late_gt_pm.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-kbl-7560u/igt@i915_selftest@live_late_gt_pm.html - fi-byt-j1900: [PASS][70] -> [DMESG-WARN][71] [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-byt-j1900/igt@i915_selftest@live_late_gt_pm.html [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-byt-j1900/igt@i915_selftest@live_late_gt_pm.html - fi-snb-2600: [PASS][72] -> [DMESG-FAIL][73] [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-snb-2600/igt@i915_selftest@live_late_gt_pm.html [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-snb-2600/igt@i915_selftest@live_late_gt_pm.html - fi-icl-y: [PASS][74] -> [DMESG-WARN][75] [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-icl-y/igt@i915_selftest@live_late_gt_pm.html [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-icl-y/igt@i915_selftest@live_late_gt_pm.html - fi-skl-6700k2: [PASS][76] -> [DMESG-FAIL][77] [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-skl-6700k2/igt@i915_selftest@live_late_gt_pm.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-skl-6700k2/igt@i915_selftest@live_late_gt_pm.html - fi-blb-e6850: [PASS][78] -> [DMESG-FAIL][79] [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-blb-e6850/igt@i915_selftest@live_late_gt_pm.html [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-blb-e6850/igt@i915_selftest@live_late_gt_pm.html - fi-icl-dsi: [PASS][80] -> [DMESG-FAIL][81] [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-icl-dsi/igt@i915_selftest@live_late_gt_pm.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-icl-dsi/igt@i915_selftest@live_late_gt_pm.html * igt@runner@aborted: - {fi-kbl-7560u}: NOTRUN -> [FAIL][82] [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-kbl-7560u/igt@runner@aborted.html Known issues ------------ Here are the changes found in Patchwork_15376 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_selftest@live_gem_contexts: - fi-cfl-guc: [PASS][83] -> [INCOMPLETE][84] ([fdo#106070] / [fdo#111700]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html * igt@i915_selftest@live_hangcheck: - fi-icl-u2: [PASS][85] -> [DMESG-FAIL][86] ([fdo#111678]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-icl-u2/igt@i915_selftest@live_hangcheck.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-icl-u2/igt@i915_selftest@live_hangcheck.html - fi-hsw-4770r: [PASS][87] -> [DMESG-FAIL][88] ([fdo#111991]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html #### Possible fixes #### * igt@i915_module_load@reload-no-display: - fi-skl-lmem: [DMESG-WARN][89] ([fdo#112261]) -> [PASS][90] [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-skl-lmem/igt@i915_module_load@reload-no-display.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-skl-lmem/igt@i915_module_load@reload-no-display.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [DMESG-WARN][91] ([fdo#106107]) -> [PASS][92] [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html #### Warnings #### * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][93] ([fdo#111045] / [fdo#111096]) -> [FAIL][94] ([fdo#111407]) [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#106070]: https://bugs.freedesktop.org/show_bug.cgi?id=106070 [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107 [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 [fdo#111678]: https://bugs.freedesktop.org/show_bug.cgi?id=111678 [fdo#111700]: https://bugs.freedesktop.org/show_bug.cgi?id=111700 [fdo#111991]: https://bugs.freedesktop.org/show_bug.cgi?id=111991 [fdo#112261]: https://bugs.freedesktop.org/show_bug.cgi?id=112261 [fdo#112269]: https://bugs.freedesktop.org/show_bug.cgi?id=112269 Participating hosts (50 -> 43) ------------------------------ Additional (1): fi-tgl-u Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-ivb-3770 fi-byt-clapper fi-bdw-samus Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_7400 -> Patchwork_15376 CI-20190529: 20190529 CI_DRM_7400: 353c51b7f47ae247ea02b231dc173ba7cfdeb484 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5299: 65fed6a79adea14f7bef6d55530da47d7731d370 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_15376: 2d8b983d2a44783e82ce00005eab76aa6f6dc847 @ git://anongit.freedesktop.org/gfx-ci/linux == Kernel 32bit build == Warning: Kernel 32bit buildtest failed: https://intel-gfx-ci.01.org/Patchwork_15376/build_32bit.log CALL scripts/checksyscalls.sh CALL scripts/atomic/check-atomics.sh CHK include/generated/compile.h Kernel: arch/x86/boot/bzImage is ready (#1) Building modules, stage 2. MODPOST 121 modules ERROR: "__udivdi3" [drivers/gpu/drm/i915/i915.ko] undefined! ERROR: "__divdi3" [drivers/gpu/drm/i915/i915.ko] undefined! scripts/Makefile.modpost:93: recipe for target '__modpost' failed make[1]: *** [__modpost] Error 1 Makefile:1285: recipe for target 'modules' failed make: *** [modules] Error 2 == Linux commits == 2d8b983d2a44 drm/i915/selftests: add basic selftests for rc6 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: add basic selftests for rc6 @ 2019-11-21 15:48 ` Patchwork 0 siblings, 0 replies; 8+ messages in thread From: Patchwork @ 2019-11-21 15:48 UTC (permalink / raw) To: Andi Shyti; +Cc: intel-gfx == Series Details == Series: drm/i915/selftests: add basic selftests for rc6 URL : https://patchwork.freedesktop.org/series/69825/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7400 -> Patchwork_15376 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_15376 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_15376, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_15376: ### IGT changes ### #### Possible regressions #### * igt@runner@aborted: - fi-kbl-soraka: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-kbl-soraka/igt@runner@aborted.html - fi-kbl-7500u: NOTRUN -> [FAIL][2] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-kbl-7500u/igt@runner@aborted.html - fi-whl-u: NOTRUN -> [FAIL][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-whl-u/igt@runner@aborted.html - fi-bxt-dsi: NOTRUN -> [FAIL][4] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-bxt-dsi/igt@runner@aborted.html - fi-kbl-x1275: NOTRUN -> [FAIL][5] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-kbl-x1275/igt@runner@aborted.html - fi-cfl-8700k: NOTRUN -> [FAIL][6] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-cfl-8700k/igt@runner@aborted.html - fi-kbl-8809g: NOTRUN -> [FAIL][7] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-kbl-8809g/igt@runner@aborted.html - fi-kbl-r: NOTRUN -> [FAIL][8] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-kbl-r/igt@runner@aborted.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt@i915_selftest@live_late_gt_pm}: - fi-bsw-kefka: [PASS][9] -> [DMESG-FAIL][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-bsw-kefka/igt@i915_selftest@live_late_gt_pm.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-bsw-kefka/igt@i915_selftest@live_late_gt_pm.html - fi-pnv-d510: [PASS][11] -> [DMESG-FAIL][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-pnv-d510/igt@i915_selftest@live_late_gt_pm.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-pnv-d510/igt@i915_selftest@live_late_gt_pm.html - fi-skl-6600u: [PASS][13] -> [DMESG-FAIL][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-skl-6600u/igt@i915_selftest@live_late_gt_pm.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-skl-6600u/igt@i915_selftest@live_late_gt_pm.html - fi-apl-guc: [PASS][15] -> [DMESG-FAIL][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-apl-guc/igt@i915_selftest@live_late_gt_pm.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-apl-guc/igt@i915_selftest@live_late_gt_pm.html - fi-bdw-5557u: [PASS][17] -> [DMESG-FAIL][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-bdw-5557u/igt@i915_selftest@live_late_gt_pm.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-bdw-5557u/igt@i915_selftest@live_late_gt_pm.html - fi-glk-dsi: [PASS][19] -> [DMESG-FAIL][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-glk-dsi/igt@i915_selftest@live_late_gt_pm.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-glk-dsi/igt@i915_selftest@live_late_gt_pm.html - fi-kbl-guc: [PASS][21] -> [DMESG-FAIL][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-kbl-guc/igt@i915_selftest@live_late_gt_pm.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-kbl-guc/igt@i915_selftest@live_late_gt_pm.html - fi-hsw-4770: [PASS][23] -> [DMESG-FAIL][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-hsw-4770/igt@i915_selftest@live_late_gt_pm.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-hsw-4770/igt@i915_selftest@live_late_gt_pm.html - fi-kbl-7500u: [PASS][25] -> [DMESG-FAIL][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-kbl-7500u/igt@i915_selftest@live_late_gt_pm.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-kbl-7500u/igt@i915_selftest@live_late_gt_pm.html - fi-cml-u2: [PASS][27] -> [DMESG-FAIL][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-cml-u2/igt@i915_selftest@live_late_gt_pm.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-cml-u2/igt@i915_selftest@live_late_gt_pm.html - fi-bxt-dsi: [PASS][29] -> [DMESG-WARN][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-bxt-dsi/igt@i915_selftest@live_late_gt_pm.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-bxt-dsi/igt@i915_selftest@live_late_gt_pm.html - fi-skl-guc: [PASS][31] -> [DMESG-FAIL][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-skl-guc/igt@i915_selftest@live_late_gt_pm.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-skl-guc/igt@i915_selftest@live_late_gt_pm.html - fi-bsw-n3050: [PASS][33] -> [DMESG-FAIL][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-bsw-n3050/igt@i915_selftest@live_late_gt_pm.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-bsw-n3050/igt@i915_selftest@live_late_gt_pm.html - fi-ilk-650: [PASS][35] -> [DMESG-FAIL][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-ilk-650/igt@i915_selftest@live_late_gt_pm.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-ilk-650/igt@i915_selftest@live_late_gt_pm.html - fi-icl-u2: [PASS][37] -> [DMESG-WARN][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-icl-u2/igt@i915_selftest@live_late_gt_pm.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-icl-u2/igt@i915_selftest@live_late_gt_pm.html - fi-kbl-x1275: [PASS][39] -> [DMESG-FAIL][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-kbl-x1275/igt@i915_selftest@live_late_gt_pm.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-kbl-x1275/igt@i915_selftest@live_late_gt_pm.html - fi-hsw-peppy: [PASS][41] -> [DMESG-FAIL][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-hsw-peppy/igt@i915_selftest@live_late_gt_pm.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-hsw-peppy/igt@i915_selftest@live_late_gt_pm.html - fi-cfl-8700k: [PASS][43] -> [DMESG-FAIL][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-cfl-8700k/igt@i915_selftest@live_late_gt_pm.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-cfl-8700k/igt@i915_selftest@live_late_gt_pm.html - fi-gdg-551: [PASS][45] -> [DMESG-FAIL][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-gdg-551/igt@i915_selftest@live_late_gt_pm.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-gdg-551/igt@i915_selftest@live_late_gt_pm.html - fi-snb-2520m: [PASS][47] -> [DMESG-FAIL][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-snb-2520m/igt@i915_selftest@live_late_gt_pm.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-snb-2520m/igt@i915_selftest@live_late_gt_pm.html - fi-bsw-nick: [PASS][49] -> [DMESG-FAIL][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-bsw-nick/igt@i915_selftest@live_late_gt_pm.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-bsw-nick/igt@i915_selftest@live_late_gt_pm.html - fi-skl-lmem: NOTRUN -> [DMESG-WARN][51] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-skl-lmem/igt@i915_selftest@live_late_gt_pm.html - fi-kbl-soraka: [PASS][52] -> [DMESG-WARN][53] [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-kbl-soraka/igt@i915_selftest@live_late_gt_pm.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-kbl-soraka/igt@i915_selftest@live_late_gt_pm.html - fi-kbl-8809g: [PASS][54] -> [DMESG-FAIL][55] [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-kbl-8809g/igt@i915_selftest@live_late_gt_pm.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-kbl-8809g/igt@i915_selftest@live_late_gt_pm.html - fi-kbl-r: [PASS][56] -> [DMESG-FAIL][57] [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-kbl-r/igt@i915_selftest@live_late_gt_pm.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-kbl-r/igt@i915_selftest@live_late_gt_pm.html - fi-bwr-2160: [PASS][58] -> [DMESG-FAIL][59] [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-bwr-2160/igt@i915_selftest@live_late_gt_pm.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-bwr-2160/igt@i915_selftest@live_late_gt_pm.html - fi-byt-n2820: [PASS][60] -> [DMESG-WARN][61] [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-byt-n2820/igt@i915_selftest@live_late_gt_pm.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-byt-n2820/igt@i915_selftest@live_late_gt_pm.html - fi-skl-6770hq: [PASS][62] -> [DMESG-FAIL][63] [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-skl-6770hq/igt@i915_selftest@live_late_gt_pm.html [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-skl-6770hq/igt@i915_selftest@live_late_gt_pm.html - fi-icl-u3: [PASS][64] -> [DMESG-FAIL][65] [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-icl-u3/igt@i915_selftest@live_late_gt_pm.html [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-icl-u3/igt@i915_selftest@live_late_gt_pm.html - fi-whl-u: [PASS][66] -> [DMESG-FAIL][67] [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-whl-u/igt@i915_selftest@live_late_gt_pm.html [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-whl-u/igt@i915_selftest@live_late_gt_pm.html - {fi-kbl-7560u}: [PASS][68] -> [DMESG-FAIL][69] [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-kbl-7560u/igt@i915_selftest@live_late_gt_pm.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-kbl-7560u/igt@i915_selftest@live_late_gt_pm.html - fi-byt-j1900: [PASS][70] -> [DMESG-WARN][71] [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-byt-j1900/igt@i915_selftest@live_late_gt_pm.html [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-byt-j1900/igt@i915_selftest@live_late_gt_pm.html - fi-snb-2600: [PASS][72] -> [DMESG-FAIL][73] [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-snb-2600/igt@i915_selftest@live_late_gt_pm.html [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-snb-2600/igt@i915_selftest@live_late_gt_pm.html - fi-icl-y: [PASS][74] -> [DMESG-WARN][75] [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-icl-y/igt@i915_selftest@live_late_gt_pm.html [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-icl-y/igt@i915_selftest@live_late_gt_pm.html - fi-skl-6700k2: [PASS][76] -> [DMESG-FAIL][77] [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-skl-6700k2/igt@i915_selftest@live_late_gt_pm.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-skl-6700k2/igt@i915_selftest@live_late_gt_pm.html - fi-blb-e6850: [PASS][78] -> [DMESG-FAIL][79] [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-blb-e6850/igt@i915_selftest@live_late_gt_pm.html [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-blb-e6850/igt@i915_selftest@live_late_gt_pm.html - fi-icl-dsi: [PASS][80] -> [DMESG-FAIL][81] [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-icl-dsi/igt@i915_selftest@live_late_gt_pm.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-icl-dsi/igt@i915_selftest@live_late_gt_pm.html * igt@runner@aborted: - {fi-kbl-7560u}: NOTRUN -> [FAIL][82] [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-kbl-7560u/igt@runner@aborted.html Known issues ------------ Here are the changes found in Patchwork_15376 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_selftest@live_gem_contexts: - fi-cfl-guc: [PASS][83] -> [INCOMPLETE][84] ([fdo#106070] / [fdo#111700]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html * igt@i915_selftest@live_hangcheck: - fi-icl-u2: [PASS][85] -> [DMESG-FAIL][86] ([fdo#111678]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-icl-u2/igt@i915_selftest@live_hangcheck.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-icl-u2/igt@i915_selftest@live_hangcheck.html - fi-hsw-4770r: [PASS][87] -> [DMESG-FAIL][88] ([fdo#111991]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html #### Possible fixes #### * igt@i915_module_load@reload-no-display: - fi-skl-lmem: [DMESG-WARN][89] ([fdo#112261]) -> [PASS][90] [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-skl-lmem/igt@i915_module_load@reload-no-display.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-skl-lmem/igt@i915_module_load@reload-no-display.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [DMESG-WARN][91] ([fdo#106107]) -> [PASS][92] [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html #### Warnings #### * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][93] ([fdo#111045] / [fdo#111096]) -> [FAIL][94] ([fdo#111407]) [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7400/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#106070]: https://bugs.freedesktop.org/show_bug.cgi?id=106070 [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107 [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 [fdo#111678]: https://bugs.freedesktop.org/show_bug.cgi?id=111678 [fdo#111700]: https://bugs.freedesktop.org/show_bug.cgi?id=111700 [fdo#111991]: https://bugs.freedesktop.org/show_bug.cgi?id=111991 [fdo#112261]: https://bugs.freedesktop.org/show_bug.cgi?id=112261 [fdo#112269]: https://bugs.freedesktop.org/show_bug.cgi?id=112269 Participating hosts (50 -> 43) ------------------------------ Additional (1): fi-tgl-u Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-ivb-3770 fi-byt-clapper fi-bdw-samus Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_7400 -> Patchwork_15376 CI-20190529: 20190529 CI_DRM_7400: 353c51b7f47ae247ea02b231dc173ba7cfdeb484 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5299: 65fed6a79adea14f7bef6d55530da47d7731d370 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_15376: 2d8b983d2a44783e82ce00005eab76aa6f6dc847 @ git://anongit.freedesktop.org/gfx-ci/linux == Kernel 32bit build == Warning: Kernel 32bit buildtest failed: https://intel-gfx-ci.01.org/Patchwork_15376/build_32bit.log CALL scripts/checksyscalls.sh CALL scripts/atomic/check-atomics.sh CHK include/generated/compile.h Kernel: arch/x86/boot/bzImage is ready (#1) Building modules, stage 2. MODPOST 121 modules ERROR: "__udivdi3" [drivers/gpu/drm/i915/i915.ko] undefined! ERROR: "__divdi3" [drivers/gpu/drm/i915/i915.ko] undefined! scripts/Makefile.modpost:93: recipe for target '__modpost' failed make[1]: *** [__modpost] Error 1 Makefile:1285: recipe for target 'modules' failed make: *** [modules] Error 2 == Linux commits == 2d8b983d2a44 drm/i915/selftests: add basic selftests for rc6 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* ✗ Fi.CI.BUILD: warning for drm/i915/selftests: add basic selftests for rc6 @ 2019-11-21 15:48 ` Patchwork 0 siblings, 0 replies; 8+ messages in thread From: Patchwork @ 2019-11-21 15:48 UTC (permalink / raw) To: Andi Shyti; +Cc: intel-gfx == Series Details == Series: drm/i915/selftests: add basic selftests for rc6 URL : https://patchwork.freedesktop.org/series/69825/ State : warning == Summary == CALL scripts/checksyscalls.sh CALL scripts/atomic/check-atomics.sh CHK include/generated/compile.h Kernel: arch/x86/boot/bzImage is ready (#1) Building modules, stage 2. MODPOST 121 modules ERROR: "__udivdi3" [drivers/gpu/drm/i915/i915.ko] undefined! ERROR: "__divdi3" [drivers/gpu/drm/i915/i915.ko] undefined! scripts/Makefile.modpost:93: recipe for target '__modpost' failed make[1]: *** [__modpost] Error 1 Makefile:1285: recipe for target 'modules' failed make: *** [modules] Error 2 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/build_32bit.log _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: warning for drm/i915/selftests: add basic selftests for rc6 @ 2019-11-21 15:48 ` Patchwork 0 siblings, 0 replies; 8+ messages in thread From: Patchwork @ 2019-11-21 15:48 UTC (permalink / raw) To: Andi Shyti; +Cc: intel-gfx == Series Details == Series: drm/i915/selftests: add basic selftests for rc6 URL : https://patchwork.freedesktop.org/series/69825/ State : warning == Summary == CALL scripts/checksyscalls.sh CALL scripts/atomic/check-atomics.sh CHK include/generated/compile.h Kernel: arch/x86/boot/bzImage is ready (#1) Building modules, stage 2. MODPOST 121 modules ERROR: "__udivdi3" [drivers/gpu/drm/i915/i915.ko] undefined! ERROR: "__divdi3" [drivers/gpu/drm/i915/i915.ko] undefined! scripts/Makefile.modpost:93: recipe for target '__modpost' failed make[1]: *** [__modpost] Error 1 Makefile:1285: recipe for target 'modules' failed make: *** [modules] Error 2 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15376/build_32bit.log _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2019-11-21 15:48 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-11-21 12:57 [RFC] drm/i915/selftests: add basic selftests for rc6 Andi Shyti 2019-11-21 12:57 ` [Intel-gfx] " Andi Shyti 2019-11-21 13:21 ` Chris Wilson 2019-11-21 13:21 ` [Intel-gfx] " Chris Wilson 2019-11-21 15:48 ` ✗ Fi.CI.BAT: failure for " Patchwork 2019-11-21 15:48 ` [Intel-gfx] " Patchwork 2019-11-21 15:48 ` ✗ Fi.CI.BUILD: warning " Patchwork 2019-11-21 15:48 ` [Intel-gfx] " Patchwork
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