From: Mathieu Poirier <mathieu.poirier@linaro.org> To: Mike Leach <mike.leach@linaro.org> Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, suzuki.poulose@arm.com Subject: Re: [PATCH v5 02/14] coresight: cti: Add sysfs coresight mgmt reg access. Date: Fri, 22 Nov 2019 10:19:50 -0700 [thread overview] Message-ID: <20191122171950.GA23396@xps15> (raw) In-Reply-To: <20191119231912.12768-3-mike.leach@linaro.org> On Tue, Nov 19, 2019 at 11:19:00PM +0000, Mike Leach wrote: > Adds sysfs access to the coresight management registers. > > Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> > Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> > Signed-off-by: Mike Leach <mike.leach@linaro.org> Tags added to a patch are like a chain of custody and should be added in order they were published. In this case you wrote the patch so your SoB goes first. Then Suzuki and I have reviewed your patch and as such, our RB come _after_ your SoB. When I add the patch to my tree I'll add my SoB after that and when Greg picks it up in his, he will do the same. Please re-order the tags in this patch and the other ones in this set to reflect the chronology of events. > --- > .../hwtracing/coresight/coresight-cti-sysfs.c | 53 +++++++++++++++++++ > drivers/hwtracing/coresight/coresight-priv.h | 1 + > 2 files changed, 54 insertions(+) > > diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c > index a832b8c6b866..507f8eb487fe 100644 > --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c > @@ -62,11 +62,64 @@ static struct attribute *coresight_cti_attrs[] = { > NULL, > }; > > +/* register based attributes */ > + > +/* macro to access RO registers with power check only (no enable check). */ > +#define coresight_cti_reg(name, offset) \ > +static ssize_t name##_show(struct device *dev, \ > + struct device_attribute *attr, char *buf) \ > +{ \ > + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); \ > + u32 val = 0; \ > + pm_runtime_get_sync(dev->parent); \ > + spin_lock(&drvdata->spinlock); \ > + if (drvdata->config.hw_powered) \ > + val = readl_relaxed(drvdata->base + offset); \ > + spin_unlock(&drvdata->spinlock); \ > + pm_runtime_put_sync(dev->parent); \ > + return scnprintf(buf, PAGE_SIZE, "0x%x\n", val); \ > +} \ > +static DEVICE_ATTR_RO(name) > + > +/* coresight management registers */ > +coresight_cti_reg(devaff0, CTIDEVAFF0); > +coresight_cti_reg(devaff1, CTIDEVAFF1); > +coresight_cti_reg(authstatus, CORESIGHT_AUTHSTATUS); > +coresight_cti_reg(devarch, CORESIGHT_DEVARCH); > +coresight_cti_reg(devid, CORESIGHT_DEVID); > +coresight_cti_reg(devtype, CORESIGHT_DEVTYPE); > +coresight_cti_reg(pidr0, CORESIGHT_PERIPHIDR0); > +coresight_cti_reg(pidr1, CORESIGHT_PERIPHIDR1); > +coresight_cti_reg(pidr2, CORESIGHT_PERIPHIDR2); > +coresight_cti_reg(pidr3, CORESIGHT_PERIPHIDR3); > +coresight_cti_reg(pidr4, CORESIGHT_PERIPHIDR4); > + > +static struct attribute *coresight_cti_mgmt_attrs[] = { > + &dev_attr_devaff0.attr, > + &dev_attr_devaff1.attr, > + &dev_attr_authstatus.attr, > + &dev_attr_devarch.attr, > + &dev_attr_devid.attr, > + &dev_attr_devtype.attr, > + &dev_attr_pidr0.attr, > + &dev_attr_pidr1.attr, > + &dev_attr_pidr2.attr, > + &dev_attr_pidr3.attr, > + &dev_attr_pidr4.attr, > + NULL, > +}; > + > static const struct attribute_group coresight_cti_group = { > .attrs = coresight_cti_attrs, > }; > > +static const struct attribute_group coresight_cti_mgmt_group = { > + .attrs = coresight_cti_mgmt_attrs, > + .name = "mgmt", > +}; > + > const struct attribute_group *coresight_cti_groups[] = { > &coresight_cti_group, > + &coresight_cti_mgmt_group, > NULL, > }; > diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h > index 82e563cdc879..aba6b789c969 100644 > --- a/drivers/hwtracing/coresight/coresight-priv.h > +++ b/drivers/hwtracing/coresight/coresight-priv.h > @@ -22,6 +22,7 @@ > #define CORESIGHT_CLAIMCLR 0xfa4 > #define CORESIGHT_LAR 0xfb0 > #define CORESIGHT_LSR 0xfb4 > +#define CORESIGHT_DEVARCH 0xfbc > #define CORESIGHT_AUTHSTATUS 0xfb8 > #define CORESIGHT_DEVID 0xfc8 > #define CORESIGHT_DEVTYPE 0xfcc > -- > 2.17.1 >
WARNING: multiple messages have this Message-ID (diff)
From: Mathieu Poirier <mathieu.poirier@linaro.org> To: Mike Leach <mike.leach@linaro.org> Cc: devicetree@vger.kernel.org, coresight@lists.linaro.org, suzuki.poulose@arm.com, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org Subject: Re: [PATCH v5 02/14] coresight: cti: Add sysfs coresight mgmt reg access. Date: Fri, 22 Nov 2019 10:19:50 -0700 [thread overview] Message-ID: <20191122171950.GA23396@xps15> (raw) In-Reply-To: <20191119231912.12768-3-mike.leach@linaro.org> On Tue, Nov 19, 2019 at 11:19:00PM +0000, Mike Leach wrote: > Adds sysfs access to the coresight management registers. > > Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> > Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> > Signed-off-by: Mike Leach <mike.leach@linaro.org> Tags added to a patch are like a chain of custody and should be added in order they were published. In this case you wrote the patch so your SoB goes first. Then Suzuki and I have reviewed your patch and as such, our RB come _after_ your SoB. When I add the patch to my tree I'll add my SoB after that and when Greg picks it up in his, he will do the same. Please re-order the tags in this patch and the other ones in this set to reflect the chronology of events. > --- > .../hwtracing/coresight/coresight-cti-sysfs.c | 53 +++++++++++++++++++ > drivers/hwtracing/coresight/coresight-priv.h | 1 + > 2 files changed, 54 insertions(+) > > diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c > index a832b8c6b866..507f8eb487fe 100644 > --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c > @@ -62,11 +62,64 @@ static struct attribute *coresight_cti_attrs[] = { > NULL, > }; > > +/* register based attributes */ > + > +/* macro to access RO registers with power check only (no enable check). */ > +#define coresight_cti_reg(name, offset) \ > +static ssize_t name##_show(struct device *dev, \ > + struct device_attribute *attr, char *buf) \ > +{ \ > + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); \ > + u32 val = 0; \ > + pm_runtime_get_sync(dev->parent); \ > + spin_lock(&drvdata->spinlock); \ > + if (drvdata->config.hw_powered) \ > + val = readl_relaxed(drvdata->base + offset); \ > + spin_unlock(&drvdata->spinlock); \ > + pm_runtime_put_sync(dev->parent); \ > + return scnprintf(buf, PAGE_SIZE, "0x%x\n", val); \ > +} \ > +static DEVICE_ATTR_RO(name) > + > +/* coresight management registers */ > +coresight_cti_reg(devaff0, CTIDEVAFF0); > +coresight_cti_reg(devaff1, CTIDEVAFF1); > +coresight_cti_reg(authstatus, CORESIGHT_AUTHSTATUS); > +coresight_cti_reg(devarch, CORESIGHT_DEVARCH); > +coresight_cti_reg(devid, CORESIGHT_DEVID); > +coresight_cti_reg(devtype, CORESIGHT_DEVTYPE); > +coresight_cti_reg(pidr0, CORESIGHT_PERIPHIDR0); > +coresight_cti_reg(pidr1, CORESIGHT_PERIPHIDR1); > +coresight_cti_reg(pidr2, CORESIGHT_PERIPHIDR2); > +coresight_cti_reg(pidr3, CORESIGHT_PERIPHIDR3); > +coresight_cti_reg(pidr4, CORESIGHT_PERIPHIDR4); > + > +static struct attribute *coresight_cti_mgmt_attrs[] = { > + &dev_attr_devaff0.attr, > + &dev_attr_devaff1.attr, > + &dev_attr_authstatus.attr, > + &dev_attr_devarch.attr, > + &dev_attr_devid.attr, > + &dev_attr_devtype.attr, > + &dev_attr_pidr0.attr, > + &dev_attr_pidr1.attr, > + &dev_attr_pidr2.attr, > + &dev_attr_pidr3.attr, > + &dev_attr_pidr4.attr, > + NULL, > +}; > + > static const struct attribute_group coresight_cti_group = { > .attrs = coresight_cti_attrs, > }; > > +static const struct attribute_group coresight_cti_mgmt_group = { > + .attrs = coresight_cti_mgmt_attrs, > + .name = "mgmt", > +}; > + > const struct attribute_group *coresight_cti_groups[] = { > &coresight_cti_group, > + &coresight_cti_mgmt_group, > NULL, > }; > diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h > index 82e563cdc879..aba6b789c969 100644 > --- a/drivers/hwtracing/coresight/coresight-priv.h > +++ b/drivers/hwtracing/coresight/coresight-priv.h > @@ -22,6 +22,7 @@ > #define CORESIGHT_CLAIMCLR 0xfa4 > #define CORESIGHT_LAR 0xfb0 > #define CORESIGHT_LSR 0xfb4 > +#define CORESIGHT_DEVARCH 0xfbc > #define CORESIGHT_AUTHSTATUS 0xfb8 > #define CORESIGHT_DEVID 0xfc8 > #define CORESIGHT_DEVTYPE 0xfcc > -- > 2.17.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-11-22 17:19 UTC|newest] Thread overview: 124+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-19 23:18 [PATCH v5 00/14] CoreSight CTI Driver Mike Leach 2019-11-19 23:18 ` Mike Leach 2019-11-19 23:18 ` [PATCH v5 01/14] coresight: cti: Initial " Mike Leach 2019-11-19 23:18 ` Mike Leach 2019-11-21 20:21 ` Mathieu Poirier 2019-11-21 20:21 ` Mathieu Poirier 2019-11-29 12:05 ` Mike Leach 2019-11-29 12:05 ` Mike Leach 2019-12-03 16:53 ` Mathieu Poirier 2019-12-03 16:53 ` Mathieu Poirier 2019-11-25 19:03 ` Suzuki Kuruppassery Poulose 2019-11-25 19:03 ` Suzuki Kuruppassery Poulose 2019-11-29 12:06 ` Mike Leach 2019-11-29 12:06 ` Mike Leach 2019-11-19 23:19 ` [PATCH v5 02/14] coresight: cti: Add sysfs coresight mgmt reg access Mike Leach 2019-11-19 23:19 ` Mike Leach 2019-11-22 17:19 ` Mathieu Poirier [this message] 2019-11-22 17:19 ` Mathieu Poirier 2019-11-19 23:19 ` [PATCH v5 03/14] coresight: cti: Add sysfs access to program function regs Mike Leach 2019-11-19 23:19 ` Mike Leach 2019-11-27 18:26 ` Suzuki Kuruppassery Poulose 2019-11-27 18:26 ` Suzuki Kuruppassery Poulose 2019-11-29 12:47 ` Mike Leach 2019-11-29 12:47 ` Mike Leach 2019-11-28 10:54 ` Suzuki Kuruppassery Poulose 2019-11-28 10:54 ` Suzuki Kuruppassery Poulose 2019-11-28 17:20 ` Mathieu Poirier 2019-11-28 17:20 ` Mathieu Poirier 2019-11-28 18:00 ` Suzuki Kuruppassery Poulose 2019-11-28 18:00 ` Suzuki Kuruppassery Poulose 2019-11-29 12:50 ` Mike Leach 2019-11-29 12:50 ` Mike Leach 2019-11-19 23:19 ` [PATCH v5 04/14] coresight: cti: Add sysfs trigger / channel programming API Mike Leach 2019-11-19 23:19 ` Mike Leach 2019-11-22 18:40 ` Mathieu Poirier 2019-11-22 18:40 ` Mathieu Poirier 2019-11-27 18:40 ` Suzuki Kuruppassery Poulose 2019-11-27 18:40 ` Suzuki Kuruppassery Poulose 2019-11-29 13:01 ` Mike Leach 2019-11-29 13:01 ` Mike Leach 2019-11-19 23:19 ` [PATCH v5 05/14] dt-bindings: arm: Adds CoreSight CTI hardware definitions Mike Leach 2019-11-19 23:19 ` Mike Leach 2019-11-20 19:06 ` Mathieu Poirier 2019-11-20 19:06 ` Mathieu Poirier 2019-11-20 22:39 ` Mike Leach 2019-11-20 22:39 ` Mike Leach 2019-11-22 23:33 ` Rob Herring 2019-11-22 23:33 ` Rob Herring 2019-11-29 13:50 ` Mike Leach 2019-11-29 13:50 ` Mike Leach 2019-11-29 14:12 ` Suzuki Kuruppassery Poulose 2019-11-29 14:12 ` Suzuki Kuruppassery Poulose 2019-11-28 18:38 ` Suzuki Kuruppassery Poulose 2019-11-28 18:38 ` Suzuki Kuruppassery Poulose 2019-11-29 13:57 ` Mike Leach 2019-11-29 13:57 ` Mike Leach 2019-11-19 23:19 ` [PATCH v5 06/14] coresight: cti: Add device tree support for v8 arch CTI Mike Leach 2019-11-19 23:19 ` Mike Leach 2019-11-25 19:00 ` Mathieu Poirier 2019-11-25 19:00 ` Mathieu Poirier 2019-11-29 11:33 ` Suzuki Kuruppassery Poulose 2019-11-29 11:33 ` Suzuki Kuruppassery Poulose 2019-12-03 10:59 ` Mike Leach 2019-12-03 10:59 ` Mike Leach 2019-12-03 11:28 ` Suzuki Kuruppassery Poulose 2019-12-03 11:28 ` Suzuki Kuruppassery Poulose 2019-12-03 12:25 ` Mike Leach 2019-12-03 12:25 ` Mike Leach 2019-11-19 23:19 ` [PATCH v5 07/14] coresight: cti: Add device tree support for custom CTI Mike Leach 2019-11-19 23:19 ` Mike Leach 2019-11-25 21:22 ` Mathieu Poirier 2019-11-25 21:22 ` Mathieu Poirier 2019-11-29 14:16 ` Suzuki Kuruppassery Poulose 2019-11-29 14:16 ` Suzuki Kuruppassery Poulose 2019-11-29 21:11 ` Mathieu Poirier 2019-11-29 21:11 ` Mathieu Poirier 2019-11-29 14:18 ` Suzuki Kuruppassery Poulose 2019-11-29 14:18 ` Suzuki Kuruppassery Poulose 2019-12-03 14:05 ` Mike Leach 2019-12-03 14:05 ` Mike Leach 2019-11-19 23:19 ` [PATCH v5 08/14] coresight: cti: Enable CTI associated with devices Mike Leach 2019-11-19 23:19 ` Mike Leach 2019-11-25 22:45 ` Mathieu Poirier 2019-11-25 22:45 ` Mathieu Poirier 2019-12-05 16:33 ` Mike Leach 2019-12-05 16:33 ` Mike Leach 2019-11-29 18:28 ` Suzuki Kuruppassery Poulose 2019-11-29 18:28 ` Suzuki Kuruppassery Poulose 2019-11-29 21:25 ` Mathieu Poirier 2019-11-29 21:25 ` Mathieu Poirier 2019-12-05 16:33 ` Mike Leach 2019-12-05 16:33 ` Mike Leach 2019-11-19 23:19 ` [PATCH v5 09/14] coresight: cti: Add connection information to sysfs Mike Leach 2019-11-19 23:19 ` Mike Leach 2019-11-27 18:09 ` Mathieu Poirier 2019-11-27 18:09 ` Mathieu Poirier 2019-12-06 16:24 ` Mike Leach 2019-12-06 16:24 ` Mike Leach 2019-12-02 9:47 ` Suzuki Kuruppassery Poulose 2019-12-02 9:47 ` Suzuki Kuruppassery Poulose 2019-12-06 16:24 ` Mike Leach 2019-12-06 16:24 ` Mike Leach 2019-11-19 23:19 ` [PATCH v5 10/14] dt-bindings: qcom: Add CTI options for qcom msm8916 Mike Leach 2019-11-19 23:19 ` Mike Leach 2019-11-27 18:18 ` Mathieu Poirier 2019-11-27 18:18 ` Mathieu Poirier 2019-11-19 23:19 ` [PATCH v5 11/14] dt-bindings: arm: Juno platform - add CTI entries to device tree Mike Leach 2019-11-19 23:19 ` Mike Leach 2019-11-27 18:25 ` Mathieu Poirier 2019-11-27 18:25 ` Mathieu Poirier 2019-11-19 23:19 ` [PATCH v5 12/14] dt-bindings: hisilicon: Add CTI bindings for hi-6220 Mike Leach 2019-11-19 23:19 ` Mike Leach 2019-11-19 23:19 ` [PATCH v5 13/14] docs: coresight: Update documentation for CoreSight to cover CTI Mike Leach 2019-11-19 23:19 ` Mike Leach 2019-11-27 19:00 ` Mathieu Poirier 2019-11-27 19:00 ` Mathieu Poirier 2019-12-02 10:43 ` Suzuki Kuruppassery Poulose 2019-12-02 10:43 ` Suzuki Kuruppassery Poulose 2019-12-06 17:39 ` Mike Leach 2019-12-06 17:39 ` Mike Leach 2019-11-19 23:19 ` [PATCH v5 14/14] docs: sysfs: coresight: Add sysfs ABI documentation for CTI Mike Leach 2019-11-19 23:19 ` Mike Leach 2019-11-27 19:08 ` Mathieu Poirier 2019-11-27 19:08 ` Mathieu Poirier
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20191122171950.GA23396@xps15 \ --to=mathieu.poirier@linaro.org \ --cc=coresight@lists.linaro.org \ --cc=devicetree@vger.kernel.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-doc@vger.kernel.org \ --cc=mike.leach@linaro.org \ --cc=suzuki.poulose@arm.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.