From: "José Roberto de Souza" <jose.souza@intel.com> To: intel-gfx@lists.freedesktop.org Cc: Lucas De Marchi <lucas.demarchi@intel.com> Subject: [PATCH v2 1/5] drm/i915/psr: Add bits per pixel limitation Date: Mon, 25 Nov 2019 16:53:56 -0800 [thread overview] Message-ID: <20191126005400.264480-1-jose.souza@intel.com> (raw) PSR2 HW only support a limited number of bits per pixel, if mode has more than supported PSR2 should not be enabled. BSpec: 50422 BSpec: 7713 Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index c1d133362b76..0d84ea28bc6f 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -608,7 +608,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; - int psr_max_h = 0, psr_max_v = 0; + int psr_max_h = 0, psr_max_v = 0, max_bpp = 0; if (!dev_priv->psr.sink_psr2_support) return false; @@ -632,12 +632,15 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, if (INTEL_GEN(dev_priv) >= 12) { psr_max_h = 5120; psr_max_v = 3200; + max_bpp = 30; } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { psr_max_h = 4096; psr_max_v = 2304; + max_bpp = 24; } else if (IS_GEN(dev_priv, 9)) { psr_max_h = 3640; psr_max_v = 2304; + max_bpp = 24; } if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) { @@ -647,6 +650,12 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } + if (crtc_state->pipe_bpp > max_bpp) { + DRM_DEBUG_KMS("PSR2 not enabled, pipe bpp %d > max supported %d\n", + crtc_state->pipe_bpp, max_bpp); + return false; + } + /* * HW sends SU blocks of size four scan lines, which means the starting * X coordinate and Y granularity requirements will always be met. We -- 2.24.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: "José Roberto de Souza" <jose.souza@intel.com> To: intel-gfx@lists.freedesktop.org Cc: Lucas De Marchi <lucas.demarchi@intel.com> Subject: [Intel-gfx] [PATCH v2 1/5] drm/i915/psr: Add bits per pixel limitation Date: Mon, 25 Nov 2019 16:53:56 -0800 [thread overview] Message-ID: <20191126005400.264480-1-jose.souza@intel.com> (raw) Message-ID: <20191126005356.d8khBzhRF5NzPc4Qpsux7Kb9aKKHiVeuydPVpwY91JE@z> (raw) PSR2 HW only support a limited number of bits per pixel, if mode has more than supported PSR2 should not be enabled. BSpec: 50422 BSpec: 7713 Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index c1d133362b76..0d84ea28bc6f 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -608,7 +608,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; - int psr_max_h = 0, psr_max_v = 0; + int psr_max_h = 0, psr_max_v = 0, max_bpp = 0; if (!dev_priv->psr.sink_psr2_support) return false; @@ -632,12 +632,15 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, if (INTEL_GEN(dev_priv) >= 12) { psr_max_h = 5120; psr_max_v = 3200; + max_bpp = 30; } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { psr_max_h = 4096; psr_max_v = 2304; + max_bpp = 24; } else if (IS_GEN(dev_priv, 9)) { psr_max_h = 3640; psr_max_v = 2304; + max_bpp = 24; } if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) { @@ -647,6 +650,12 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } + if (crtc_state->pipe_bpp > max_bpp) { + DRM_DEBUG_KMS("PSR2 not enabled, pipe bpp %d > max supported %d\n", + crtc_state->pipe_bpp, max_bpp); + return false; + } + /* * HW sends SU blocks of size four scan lines, which means the starting * X coordinate and Y granularity requirements will always be met. We -- 2.24.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next reply other threads:[~2019-11-26 0:54 UTC|newest] Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-26 0:53 José Roberto de Souza [this message] 2019-11-26 0:53 ` [Intel-gfx] [PATCH v2 1/5] drm/i915/psr: Add bits per pixel limitation José Roberto de Souza 2019-11-26 0:53 ` [PATCH v2 2/5] drm/i915/psr: Refactor psr short pulse handler José Roberto de Souza 2019-11-26 0:53 ` [Intel-gfx] " José Roberto de Souza 2019-11-28 0:38 ` Matt Roper 2019-11-28 0:38 ` [Intel-gfx] " Matt Roper 2019-11-26 0:53 ` [PATCH v2 3/5] drm/i915/psr: Enable ALPM lock timeout error interruption José Roberto de Souza 2019-11-26 0:53 ` [Intel-gfx] " José Roberto de Souza 2019-11-28 1:01 ` Matt Roper 2019-11-28 1:01 ` [Intel-gfx] " Matt Roper 2019-11-26 0:53 ` [PATCH v2 4/5] drm/i915/psr: Check if sink PSR capability changed José Roberto de Souza 2019-11-26 0:53 ` [Intel-gfx] " José Roberto de Souza 2019-11-28 1:21 ` Matt Roper 2019-11-28 1:21 ` [Intel-gfx] " Matt Roper 2019-11-28 1:30 ` Souza, Jose 2019-11-28 1:30 ` [Intel-gfx] " Souza, Jose 2019-11-26 0:54 ` [PATCH v2 5/5] drm/i915/vbt: Parse power conservation features block José Roberto de Souza 2019-11-26 0:54 ` [Intel-gfx] " José Roberto de Souza 2019-11-27 22:54 ` [PATCH v3 " José Roberto de Souza 2019-11-27 22:54 ` [Intel-gfx] " José Roberto de Souza 2019-11-28 0:38 ` Matt Roper 2019-11-28 0:38 ` [Intel-gfx] " Matt Roper 2019-11-28 14:29 ` Jani Nikula 2019-11-28 14:29 ` [Intel-gfx] " Jani Nikula 2019-12-04 1:38 ` Souza, Jose 2019-12-05 7:59 ` Jani Nikula 2019-11-26 1:37 ` ✓ Fi.CI.BAT: success for series starting with [v2,1/5] drm/i915/psr: Add bits per pixel limitation Patchwork 2019-11-26 1:37 ` [Intel-gfx] " Patchwork 2019-11-26 10:49 ` ✗ Fi.CI.IGT: failure " Patchwork 2019-11-26 10:49 ` [Intel-gfx] " Patchwork 2019-11-26 22:04 ` ✓ Fi.CI.BAT: success for series starting with [v2,1/5] drm/i915/psr: Add bits per pixel limitation (rev2) Patchwork 2019-11-26 22:04 ` [Intel-gfx] " Patchwork 2019-11-27 9:23 ` ✗ Fi.CI.IGT: failure " Patchwork 2019-11-27 9:23 ` [Intel-gfx] " Patchwork 2019-11-27 21:58 ` Souza, Jose 2019-11-27 21:58 ` [Intel-gfx] " Souza, Jose 2019-11-28 0:38 ` [PATCH v2 1/5] drm/i915/psr: Add bits per pixel limitation Matt Roper 2019-11-28 0:38 ` [Intel-gfx] " Matt Roper 2019-11-28 1:58 ` ✓ Fi.CI.BAT: success for series starting with [v2,1/5] drm/i915/psr: Add bits per pixel limitation (rev3) Patchwork 2019-11-28 1:58 ` [Intel-gfx] " Patchwork 2019-11-29 6:21 ` ✓ Fi.CI.IGT: " Patchwork 2019-11-29 6:21 ` [Intel-gfx] " Patchwork
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