[U-Boot] [PATCH 1/3] net: gmac_rockchip: Add support for rk3308

[U-Boot] [PATCH 1/3] net: gmac_rockchip: Add support for rk3308

[David Wu]

Add the glue code to allow the rk3308 variant of the Rockchip gmac
to provide network functionality.

Signed-off-by: David Wu <david.wu@rock-chips.com>
---
 drivers/net/gmac_rockchip.c | 65 +++++++++++++++++++++++++++++++++++++
 1 file changed, 65 insertions(+)

diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index d2c52b4c46..e152faf083 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -17,6 +17,7 @@
 #include <asm/arch-rockchip/grf_px30.h>
 #include <asm/arch-rockchip/grf_rk322x.h>
 #include <asm/arch-rockchip/grf_rk3288.h>
+#include <asm/arch-rk3308/grf_rk3308.h>
 #include <asm/arch-rockchip/grf_rk3328.h>
 #include <asm/arch-rockchip/grf_rk3368.h>
 #include <asm/arch-rockchip/grf_rk3399.h>
@@ -173,6 +174,47 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 	return 0;
 }
 
+static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+{
+	struct rk3308_grf *grf;
+	struct clk clk_speed;
+	int speed, ret;
+	enum {
+		RK3308_GMAC_SPEED_SHIFT = 0x0,
+		RK3308_GMAC_SPEED_MASK  = BIT(0),
+		RK3308_GMAC_SPEED_10M   = 0,
+		RK3308_GMAC_SPEED_100M  = BIT(0),
+	};
+
+	ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed",
+			      &clk_speed);
+	if (ret)
+		return ret;
+
+	switch (priv->phydev->speed) {
+	case 10:
+		speed = RK3308_GMAC_SPEED_10M;
+		ret = clk_set_rate(&clk_speed, 2500000);
+		if (ret)
+			return ret;
+		break;
+	case 100:
+		speed = RK3308_GMAC_SPEED_100M;
+		ret = clk_set_rate(&clk_speed, 25000000);
+		if (ret)
+			return ret;
+		break;
+	default:
+		debug("Unknown phy speed: %d\n", priv->phydev->speed);
+		return -EINVAL;
+	}
+
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed);
+
+	return 0;
+}
+
 static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 {
 	struct rk3328_grf_regs *grf;
@@ -377,6 +419,22 @@ static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 		     pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
 }
 
+static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+{
+	struct rk3308_grf *grf;
+	enum {
+		RK3308_GMAC_PHY_INTF_SEL_SHIFT = 2,
+		RK3308_GMAC_PHY_INTF_SEL_MASK  = GENMASK(4, 2),
+		RK3308_GMAC_PHY_INTF_SEL_RMII  = BIT(4),
+	};
+
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+	rk_clrsetreg(&grf->mac_con0,
+		     RK3308_GMAC_PHY_INTF_SEL_MASK,
+		     RK3308_GMAC_PHY_INTF_SEL_RMII);
+}
+
 static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 {
 	struct rk3328_grf_regs *grf;
@@ -646,6 +704,11 @@ const struct rk_gmac_ops rk3288_gmac_ops = {
 	.set_to_rgmii = rk3288_gmac_set_to_rgmii,
 };
 
+const struct rk_gmac_ops rk3308_gmac_ops = {
+	.fix_mac_speed = rk3308_gmac_fix_mac_speed,
+	.set_to_rmii = rk3308_gmac_set_to_rmii,
+};
+
 const struct rk_gmac_ops rk3328_gmac_ops = {
 	.fix_mac_speed = rk3328_gmac_fix_mac_speed,
 	.set_to_rgmii = rk3328_gmac_set_to_rgmii,
@@ -673,6 +736,8 @@ static const struct udevice_id rockchip_gmac_ids[] = {
 	  .data = (ulong)&rk3228_gmac_ops },
 	{ .compatible = "rockchip,rk3288-gmac",
 	  .data = (ulong)&rk3288_gmac_ops },
+	{ .compatible = "rockchip,rk3308-mac",
+	  .data = (ulong)&rk3308_gmac_ops },
 	{ .compatible = "rockchip,rk3328-gmac",
 	  .data = (ulong)&rk3328_gmac_ops },
 	{ .compatible = "rockchip,rk3368-gmac",
-- 
2.19.1

[U-Boot] [PATCH 2/3] arm: dts: Add mac node for rk3308 at dtsi level

[David Wu]

The rk3308 only support RMII mode, and if it is output clock
mode, better to use ref_clk pin with drive strength 12ma.

Signed-off-by: David Wu <david.wu@rock-chips.com>
---
 arch/arm/dts/rk3308.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/dts/rk3308.dtsi b/arch/arm/dts/rk3308.dtsi
index 0eeec165d4..a5c0b72ae0 100644
--- a/arch/arm/dts/rk3308.dtsi
+++ b/arch/arm/dts/rk3308.dtsi
@@ -627,6 +627,28 @@
 		status = "disabled";
 	};
 
+	mac: ethernet at ff4e0000 {
+		compatible = "rockchip,rk3308-mac";
+		reg = <0x0 0xff4e0000 0x0 0x10000>;
+		rockchip,grf = <&grf>;
+		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "macirq";
+		clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>,
+			 <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>,
+			 <&cru SCLK_MAC>, <&cru ACLK_MAC>,
+			 <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>;
+		clock-names = "stmmaceth", "mac_clk_rx",
+			      "mac_clk_tx", "clk_mac_ref",
+			      "clk_mac_refout", "aclk_mac",
+			      "pclk_mac", "clk_mac_speed";
+		phy-mode = "rmii";
+		pinctrl-names = "default";
+		pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
+		resets = <&cru SRST_MAC_A>;
+		reset-names = "stmmaceth";
+		status = "disabled";
+	};
+
 	cru: clock-controller at ff500000 {
 		compatible = "rockchip,rk3308-cru";
 		reg = <0x0 0xff500000 0x0 0x1000>;
-- 
2.19.1

[U-Boot] [PATCH 3/3] dts: rk3308: Enable ethernet function supported for Firefly ROC_RK3308_CC

[David Wu]

The Firefly ROC_RK3308_CC use ref_clock of input mode,
and rmii pins of m1 group.

Signed-off-by: David Wu <david.wu@rock-chips.com>
---
 arch/arm/dts/rk3308-roc-cc.dts | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/dts/rk3308-roc-cc.dts b/arch/arm/dts/rk3308-roc-cc.dts
index e10aa638a3..b4a54a852c 100644
--- a/arch/arm/dts/rk3308-roc-cc.dts
+++ b/arch/arm/dts/rk3308-roc-cc.dts
@@ -143,6 +143,15 @@
 	};
 };
 
+&mac {
+	assigned-clocks = <&cru SCLK_MAC>;
+	assigned-clock-parents = <&mac_clkin>;
+	clock_in_out = "input";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rmiim1_pins &macm1_refclk>;
+	status = "okay";
+};
+
 &pwm5 {
 	status = "okay";
 	pinctrl-names = "active";
-- 
2.19.1

[U-Boot] [PATCH 2/3] arm: dts: Add mac node for rk3308 at dtsi level

[Kever Yang]

David,


On 2019/11/26 上午9:39, David Wu wrote:
> The rk3308 only support RMII mode, and if it is output clock
> mode, better to use ref_clk pin with drive strength 12ma.
>
> Signed-off-by: David Wu <david.wu@rock-chips.com>

Did you send this to kernel list at the same time?


Thanks,

- Kever

> ---
>   arch/arm/dts/rk3308.dtsi | 22 ++++++++++++++++++++++
>   1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm/dts/rk3308.dtsi b/arch/arm/dts/rk3308.dtsi
> index 0eeec165d4..a5c0b72ae0 100644
> --- a/arch/arm/dts/rk3308.dtsi
> +++ b/arch/arm/dts/rk3308.dtsi
> @@ -627,6 +627,28 @@
>   		status = "disabled";
>   	};
>   
> +	mac: ethernet at ff4e0000 {
> +		compatible = "rockchip,rk3308-mac";
> +		reg = <0x0 0xff4e0000 0x0 0x10000>;
> +		rockchip,grf = <&grf>;
> +		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "macirq";
> +		clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>,
> +			 <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>,
> +			 <&cru SCLK_MAC>, <&cru ACLK_MAC>,
> +			 <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>;
> +		clock-names = "stmmaceth", "mac_clk_rx",
> +			      "mac_clk_tx", "clk_mac_ref",
> +			      "clk_mac_refout", "aclk_mac",
> +			      "pclk_mac", "clk_mac_speed";
> +		phy-mode = "rmii";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
> +		resets = <&cru SRST_MAC_A>;
> +		reset-names = "stmmaceth";
> +		status = "disabled";
> +	};
> +
>   	cru: clock-controller at ff500000 {
>   		compatible = "rockchip,rk3308-cru";
>   		reg = <0x0 0xff500000 0x0 0x1000>;

[U-Boot] [PATCH 1/3] net: gmac_rockchip: Add support for rk3308

[Kever Yang]

On 2019/11/26 上午9:39, David Wu wrote:
> Add the glue code to allow the rk3308 variant of the Rockchip gmac
> to provide network functionality.
>
> Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   drivers/net/gmac_rockchip.c | 65 +++++++++++++++++++++++++++++++++++++
>   1 file changed, 65 insertions(+)
>
> diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
> index d2c52b4c46..e152faf083 100644
> --- a/drivers/net/gmac_rockchip.c
> +++ b/drivers/net/gmac_rockchip.c
> @@ -17,6 +17,7 @@
>   #include <asm/arch-rockchip/grf_px30.h>
>   #include <asm/arch-rockchip/grf_rk322x.h>
>   #include <asm/arch-rockchip/grf_rk3288.h>
> +#include <asm/arch-rk3308/grf_rk3308.h>
>   #include <asm/arch-rockchip/grf_rk3328.h>
>   #include <asm/arch-rockchip/grf_rk3368.h>
>   #include <asm/arch-rockchip/grf_rk3399.h>
> @@ -173,6 +174,47 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
>   	return 0;
>   }
>   
> +static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev *priv)
> +{
> +	struct rk3308_grf *grf;
> +	struct clk clk_speed;
> +	int speed, ret;
> +	enum {
> +		RK3308_GMAC_SPEED_SHIFT = 0x0,
> +		RK3308_GMAC_SPEED_MASK  = BIT(0),
> +		RK3308_GMAC_SPEED_10M   = 0,
> +		RK3308_GMAC_SPEED_100M  = BIT(0),
> +	};
> +
> +	ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed",
> +			      &clk_speed);
> +	if (ret)
> +		return ret;
> +
> +	switch (priv->phydev->speed) {
> +	case 10:
> +		speed = RK3308_GMAC_SPEED_10M;
> +		ret = clk_set_rate(&clk_speed, 2500000);
> +		if (ret)
> +			return ret;
> +		break;
> +	case 100:
> +		speed = RK3308_GMAC_SPEED_100M;
> +		ret = clk_set_rate(&clk_speed, 25000000);
> +		if (ret)
> +			return ret;
> +		break;
> +	default:
> +		debug("Unknown phy speed: %d\n", priv->phydev->speed);
> +		return -EINVAL;
> +	}
> +
> +	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> +	rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed);
> +
> +	return 0;
> +}
> +
>   static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
>   {
>   	struct rk3328_grf_regs *grf;
> @@ -377,6 +419,22 @@ static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
>   		     pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
>   }
>   
> +static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
> +{
> +	struct rk3308_grf *grf;
> +	enum {
> +		RK3308_GMAC_PHY_INTF_SEL_SHIFT = 2,
> +		RK3308_GMAC_PHY_INTF_SEL_MASK  = GENMASK(4, 2),
> +		RK3308_GMAC_PHY_INTF_SEL_RMII  = BIT(4),
> +	};
> +
> +	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> +
> +	rk_clrsetreg(&grf->mac_con0,
> +		     RK3308_GMAC_PHY_INTF_SEL_MASK,
> +		     RK3308_GMAC_PHY_INTF_SEL_RMII);
> +}
> +
>   static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
>   {
>   	struct rk3328_grf_regs *grf;
> @@ -646,6 +704,11 @@ const struct rk_gmac_ops rk3288_gmac_ops = {
>   	.set_to_rgmii = rk3288_gmac_set_to_rgmii,
>   };
>   
> +const struct rk_gmac_ops rk3308_gmac_ops = {
> +	.fix_mac_speed = rk3308_gmac_fix_mac_speed,
> +	.set_to_rmii = rk3308_gmac_set_to_rmii,
> +};
> +
>   const struct rk_gmac_ops rk3328_gmac_ops = {
>   	.fix_mac_speed = rk3328_gmac_fix_mac_speed,
>   	.set_to_rgmii = rk3328_gmac_set_to_rgmii,
> @@ -673,6 +736,8 @@ static const struct udevice_id rockchip_gmac_ids[] = {
>   	  .data = (ulong)&rk3228_gmac_ops },
>   	{ .compatible = "rockchip,rk3288-gmac",
>   	  .data = (ulong)&rk3288_gmac_ops },
> +	{ .compatible = "rockchip,rk3308-mac",
> +	  .data = (ulong)&rk3308_gmac_ops },
>   	{ .compatible = "rockchip,rk3328-gmac",
>   	  .data = (ulong)&rk3328_gmac_ops },
>   	{ .compatible = "rockchip,rk3368-gmac",

[U-Boot] [PATCH 2/3] arm: dts: Add mac node for rk3308 at dtsi level

[David Wu]

Hi Kever,

在 2019/11/27 下午2:23, Kever Yang 写道:
> David,
> 
> 
> On 2019/11/26 上午9:39, David Wu wrote:
>> The rk3308 only support RMII mode, and if it is output clock
>> mode, better to use ref_clk pin with drive strength 12ma.
>>
>> Signed-off-by: David Wu <david.wu@rock-chips.com>
> 
> Did you send this to kernel list at the same time?

I will send it later.

> 
> 
> Thanks,
> 
> - Kever
> 
>> ---
>>   arch/arm/dts/rk3308.dtsi | 22 ++++++++++++++++++++++
>>   1 file changed, 22 insertions(+)
>>
>> diff --git a/arch/arm/dts/rk3308.dtsi b/arch/arm/dts/rk3308.dtsi
>> index 0eeec165d4..a5c0b72ae0 100644
>> --- a/arch/arm/dts/rk3308.dtsi
>> +++ b/arch/arm/dts/rk3308.dtsi
>> @@ -627,6 +627,28 @@
>>           status = "disabled";
>>       };
>> +    mac: ethernet at ff4e0000 {
>> +        compatible = "rockchip,rk3308-mac";
>> +        reg = <0x0 0xff4e0000 0x0 0x10000>;
>> +        rockchip,grf = <&grf>;
>> +        interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
>> +        interrupt-names = "macirq";
>> +        clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>,
>> +             <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>,
>> +             <&cru SCLK_MAC>, <&cru ACLK_MAC>,
>> +             <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>;
>> +        clock-names = "stmmaceth", "mac_clk_rx",
>> +                  "mac_clk_tx", "clk_mac_ref",
>> +                  "clk_mac_refout", "aclk_mac",
>> +                  "pclk_mac", "clk_mac_speed";
>> +        phy-mode = "rmii";
>> +        pinctrl-names = "default";
>> +        pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
>> +        resets = <&cru SRST_MAC_A>;
>> +        reset-names = "stmmaceth";
>> +        status = "disabled";
>> +    };
>> +
>>       cru: clock-controller at ff500000 {
>>           compatible = "rockchip,rk3308-cru";
>>           reg = <0x0 0xff500000 0x0 0x1000>;
> 
> 
> 
> 

[PATCH 3/3] dts: rk3308: Enable ethernet function supported for Firefly ROC_RK3308_CC

[Kever Yang]

On 2019/11/26 上午9:39, David Wu wrote:
> The Firefly ROC_RK3308_CC use ref_clock of input mode,
> and rmii pins of m1 group.
>
> Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   arch/arm/dts/rk3308-roc-cc.dts | 9 +++++++++
>   1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm/dts/rk3308-roc-cc.dts b/arch/arm/dts/rk3308-roc-cc.dts
> index e10aa638a3..b4a54a852c 100644
> --- a/arch/arm/dts/rk3308-roc-cc.dts
> +++ b/arch/arm/dts/rk3308-roc-cc.dts
> @@ -143,6 +143,15 @@
>   	};
>   };
>   
> +&mac {
> +	assigned-clocks = <&cru SCLK_MAC>;
> +	assigned-clock-parents = <&mac_clkin>;
> +	clock_in_out = "input";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&rmiim1_pins &macm1_refclk>;
> +	status = "okay";
> +};
> +
>   &pwm5 {
>   	status = "okay";
>   	pinctrl-names = "active";

[PATCH 2/3] arm: dts: Add mac node for rk3308 at dtsi level

[Kever Yang]

On 2019/11/26 上午9:39, David Wu wrote:
> The rk3308 only support RMII mode, and if it is output clock
> mode, better to use ref_clk pin with drive strength 12ma.
>
> Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   arch/arm/dts/rk3308.dtsi | 22 ++++++++++++++++++++++
>   1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm/dts/rk3308.dtsi b/arch/arm/dts/rk3308.dtsi
> index 0eeec165d4..a5c0b72ae0 100644
> --- a/arch/arm/dts/rk3308.dtsi
> +++ b/arch/arm/dts/rk3308.dtsi
> @@ -627,6 +627,28 @@
>   		status = "disabled";
>   	};
>   
> +	mac: ethernet at ff4e0000 {
> +		compatible = "rockchip,rk3308-mac";
> +		reg = <0x0 0xff4e0000 0x0 0x10000>;
> +		rockchip,grf = <&grf>;
> +		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "macirq";
> +		clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>,
> +			 <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>,
> +			 <&cru SCLK_MAC>, <&cru ACLK_MAC>,
> +			 <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>;
> +		clock-names = "stmmaceth", "mac_clk_rx",
> +			      "mac_clk_tx", "clk_mac_ref",
> +			      "clk_mac_refout", "aclk_mac",
> +			      "pclk_mac", "clk_mac_speed";
> +		phy-mode = "rmii";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
> +		resets = <&cru SRST_MAC_A>;
> +		reset-names = "stmmaceth";
> +		status = "disabled";
> +	};
> +
>   	cru: clock-controller at ff500000 {
>   		compatible = "rockchip,rk3308-cru";
>   		reg = <0x0 0xff500000 0x0 0x1000>;