[U-Boot] [PATCH 1/6] ARM: imx: vining2000: Convert to SPL framework

[U-Boot] [PATCH 1/6] ARM: imx: vining2000: Convert to SPL framework

[Marek Vasut]

In preparation for use of DDR DRAM fine-tuning upon boot,
convert the board to SPL framework instead of using DCD
tables to bring up DRAM and pinmux.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Silvio Fricke <silvio.fricke@softing.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 arch/arm/mach-imx/mx6/Kconfig           |   1 +
 board/softing/vining_2000/vining_2000.c | 182 ++++++++++++++++++++++++
 configs/vining_2000_defconfig           |  12 +-
 include/configs/vining_2000.h           |   4 +
 4 files changed, 198 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 607210520f..ef816a24ff 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -558,6 +558,7 @@ config TARGET_SOFTING_VINING_2000
 	select DM
 	select DM_THERMAL
 	select MX6SX
+	select SUPPORT_SPL
 	imply CMD_DM
 
 config TARGET_WANDBOARD
diff --git a/board/softing/vining_2000/vining_2000.c b/board/softing/vining_2000/vining_2000.c
index 51985b91c2..086de1eaf5 100644
--- a/board/softing/vining_2000/vining_2000.c
+++ b/board/softing/vining_2000/vining_2000.c
@@ -432,3 +432,185 @@ int checkboard(void)
 
 	return 0;
 }
+
+#ifdef CONFIG_SPL_BUILD
+#include <linux/libfdt.h>
+#include <spl.h>
+#include <asm/arch/mx6-ddr.h>
+
+static struct fsl_esdhc_cfg usdhc_cfg = { USDHC4_BASE_ADDR };
+
+static iomux_v3_cfg_t const uart_pads[] = {
+	MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+	MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static void vining2000_spl_setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+	u32 val;
+	u32 port;
+
+	val = readl(&src_regs->sbmr1);
+
+	if ((val & 0xc0) != 0x40) {
+		printf("Not boot from USDHC!\n");
+		return -EINVAL;
+	}
+
+	port = (val >> 11) & 0x3;
+	printf("port %d\n", port);
+	switch (port) {
+	case 3:
+		imx_iomux_v3_setup_multiple_pads(
+			usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+		usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+		usdhc_cfg.esdhc_base = USDHC4_BASE_ADDR;
+		break;
+	}
+
+	gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
+	return fsl_esdhc_initialize(bis, &usdhc_cfg);
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return 1;
+}
+
+const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_dqm0		= 0x00000028,
+	.dram_dqm1		= 0x00000028,
+	.dram_dqm2		= 0x00000028,
+	.dram_dqm3		= 0x00000028,
+	.dram_ras		= 0x00000028,
+	.dram_cas		= 0x00000028,
+	.dram_odt0		= 0x00000028,
+	.dram_odt1		= 0x00000028,
+	.dram_sdba2		= 0x00000000,
+	.dram_sdcke0		= 0x00003000,
+	.dram_sdcke1		= 0x00003000,
+	.dram_sdclk_0		= 0x00000030,
+	.dram_sdqs0		= 0x00000028,
+	.dram_sdqs1		= 0x00000028,
+	.dram_sdqs2		= 0x00000028,
+	.dram_sdqs3		= 0x00000028,
+	.dram_reset		= 0x00000028,
+};
+
+const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
+	.grp_addds		= 0x00000028,
+	.grp_b0ds		= 0x00000028,
+	.grp_b1ds		= 0x00000028,
+	.grp_b2ds		= 0x00000028,
+	.grp_b3ds		= 0x00000028,
+	.grp_ctlds		= 0x00000028,
+	.grp_ddr_type		= 0x000c0000,
+	.grp_ddrmode		= 0x00020000,
+	.grp_ddrmode_ctl	= 0x00020000,
+	.grp_ddrpke		= 0x00000000,
+};
+
+const struct mx6_mmdc_calibration mx6_mmcd_calib = {
+	.p0_mpwldectrl0		= 0x0022001C,
+	.p0_mpwldectrl1		= 0x001F001A,
+	.p0_mpdgctrl0		= 0x01380134,
+	.p0_mpdgctrl1		= 0x0124011C,
+	.p0_mprddlctl		= 0x42404444,
+	.p0_mpwrdlctl		= 0x36383C38,
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+	.mem_speed	= 1600,
+	.density	= 4,
+	.width		= 32,
+	.banks		= 8,
+	.rowaddr	= 15,
+	.coladdr	= 10,
+	.pagesz		= 2,
+	.trcd		= 1391,
+	.trcmin		= 4875,
+	.trasmin	= 3500,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0xF000000F, &ccm->CCGR0);	/* AIPS_TZ{1,2,3} */
+	writel(0x303C0000, &ccm->CCGR1);	/* GPT, OCRAM */
+	writel(0x00FFFCC0, &ccm->CCGR2);	/* IPMUX, I2C1, I2C3 */
+	writel(0x3F300030, &ccm->CCGR3);	/* OCRAM, MMDC, ENET */
+	writel(0x0000C003, &ccm->CCGR4);	/* PCI, PL301 */
+	writel(0x0F0330C3, &ccm->CCGR5);	/* UART, ROM */
+	writel(0x00000F00, &ccm->CCGR6);	/* SDHI4, EIM */
+}
+
+static void vining2000_spl_dram_init(void)
+{
+	struct mx6_ddr_sysinfo sysinfo = {
+		.dsize		= mem_ddr.width / 32,
+		.cs_density	= 24,
+		.ncs		= 1,
+		.cs1_mirror	= 0,
+		.rtt_wr		= 1,	/* RTT_wr = RZQ/4 */
+		.rtt_nom	= 1,	/* RTT_Nom = RZQ/4 */
+		.walat		= 1,	/* Write additional latency */
+		.ralat		= 5,	/* Read additional latency */
+		.mif3_mode	= 3,	/* Command prediction working mode */
+		.bi_on		= 1,	/* Bank interleaving enabled */
+		.sde_to_rst	= 0x10,	/* 14 cycles, 200us (JEDEC default) */
+		.rst_to_cke	= 0x23,	/* 33 cycles, 500us (JEDEC default) */
+		.ddr_type	= DDR_TYPE_DDR3,
+		.refsel		= 1,	/* Refresh cycles at 32KHz */
+		.refr		= 7,	/* 8 refresh commands per refresh cycle */
+	};
+
+	mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+void board_init_f(ulong dummy)
+{
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	ccgr_init();
+
+	/* iomux setup */
+	vining2000_spl_setup_iomux_uart();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	vining2000_spl_dram_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
+#endif
diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig
index 32ef01b639..4f9f538189 100644
--- a/configs/vining_2000_defconfig
+++ b/configs/vining_2000_defconfig
@@ -1,18 +1,29 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_TARGET_SOFTING_VINING_2000=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x80000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
 # CONFIG_CMD_BMODE is not set
+CONFIG_SPL_TEXT_BASE=0x00908000
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/softing/vining_2000/imximage.cfg"
 CONFIG_BOOTDELAY=0
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_FS_EXT4=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_FLASH is not set
@@ -53,7 +64,6 @@ CONFIG_DM_PCI=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_PWM_IMX=y
-CONFIG_SPECIFY_CONSOLE_INDEX=y
 CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_USB=y
diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h
index 54c8c2f62e..377406f842 100644
--- a/include/configs/vining_2000.h
+++ b/include/configs/vining_2000.h
@@ -91,4 +91,8 @@
 #define CONFIG_SYS_MMC_ENV_PART		1 /* boot0 */
 #endif
 
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+#endif
+
 #endif				/* __CONFIG_H */
-- 
2.24.0

[U-Boot] [PATCH 2/6] ARM: imx: vining2000: Enable DDR DRAM calibration

[Marek Vasut]

Enable DRAM calibration in SPL to improve behavior of the board
in edge conditions of the thermal envelope of the board and make
it even more stable.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Silvio Fricke <silvio.fricke@softing.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 board/softing/vining_2000/vining_2000.c | 5 +++++
 configs/vining_2000_defconfig           | 1 +
 2 files changed, 6 insertions(+)

diff --git a/board/softing/vining_2000/vining_2000.c b/board/softing/vining_2000/vining_2000.c
index 086de1eaf5..a745119577 100644
--- a/board/softing/vining_2000/vining_2000.c
+++ b/board/softing/vining_2000/vining_2000.c
@@ -586,6 +586,11 @@ static void vining2000_spl_dram_init(void)
 
 	mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 	mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
+
+	/* Perform DDR DRAM calibration */
+	udelay(100);
+	mmdc_do_write_level_calibration(&sysinfo);
+	mmdc_do_dqs_calibration(&sysinfo);
 }
 
 void board_init_f(ulong dummy)
diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig
index 4f9f538189..512c15baf8 100644
--- a/configs/vining_2000_defconfig
+++ b/configs/vining_2000_defconfig
@@ -5,6 +5,7 @@ CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_MX6_DDRCAL=y
 CONFIG_TARGET_SOFTING_VINING_2000=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
-- 
2.24.0

[U-Boot] [PATCH 3/6] ARM: imx: vining2000: Convert to ethernet DM

[Marek Vasut]

Convert the board to ethernet DM support. Adjust board file accordingly,
as the board_eth_init() contains custom clock configuration required for
this board to work. Furthermore, enable FEC1 clock to make FEC1 work as
well.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Silvio Fricke <silvio.fricke@softing.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 board/softing/vining_2000/vining_2000.c | 38 ++++---------------------
 configs/vining_2000_defconfig           |  3 ++
 include/configs/vining_2000.h           |  2 --
 3 files changed, 8 insertions(+), 35 deletions(-)

diff --git a/board/softing/vining_2000/vining_2000.c b/board/softing/vining_2000/vining_2000.c
index a745119577..83a4d9debe 100644
--- a/board/softing/vining_2000/vining_2000.c
+++ b/board/softing/vining_2000/vining_2000.c
@@ -71,42 +71,23 @@ int dram_init(void)
 	return 0;
 }
 
-static iomux_v3_cfg_t const fec1_pads[] = {
-	MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL) |
-		MUX_MODE_SION,
-	/* LAN8720 PHY Reset */
-	MX6_PAD_RGMII1_TD3__GPIO5_IO_9 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
 static iomux_v3_cfg_t const pwm_led_pads[] = {
 	MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */
 	MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */
 	MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */
 };
 
-#define PHY_RESET IMX_GPIO_NR(5, 9)
-
-int board_eth_init(bd_t *bis)
+static int board_net_init(void)
 {
 	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
-	int ret;
 	unsigned char eth1addr[6];
+	int ret;
 
-	/* just to get secound mac address */
+	/* just to get second mac address */
 	imx_get_mac_from_fuse(1, eth1addr);
 	if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr))
 		eth_env_set_enetaddr("eth1addr", eth1addr);
 
-	imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
-
 	/*
 	 * Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
 	 * ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
@@ -122,15 +103,7 @@ int board_eth_init(bd_t *bis)
 	if (ret)
 		goto eth_fail;
 
-	/* reset phy */
-	gpio_request(PHY_RESET, "PHY-reset");
-	gpio_direction_output(PHY_RESET, 0);
-	mdelay(16);
-	gpio_set_value(PHY_RESET, 1);
-	mdelay(1);
-
-	ret = fecmxc_initialize_multi(bis, 0, CONFIG_FEC_MXC_PHYADDR,
-					IMX_FEC_BASE);
+	ret = enable_fec_anatop_clock(1, ENET_50MHZ);
 	if (ret)
 		goto eth_fail;
 
@@ -138,7 +111,6 @@ int board_eth_init(bd_t *bis)
 
 eth_fail:
 	printf("FEC MXC: %s:failed (%i)\n", __func__, ret);
-	gpio_set_value(PHY_RESET, 0);
 	return ret;
 }
 
@@ -423,7 +395,7 @@ int board_init(void)
 	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 #endif
 
-	return 0;
+	return board_net_init();
 }
 
 int checkboard(void)
diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig
index 512c15baf8..df09cfedb9 100644
--- a/configs/vining_2000_defconfig
+++ b/configs/vining_2000_defconfig
@@ -59,6 +59,9 @@ CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_FSL_USDHC=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_SMSC=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
 CONFIG_MII=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h
index 377406f842..0c0baf2738 100644
--- a/include/configs/vining_2000.h
+++ b/include/configs/vining_2000.h
@@ -58,8 +58,6 @@
 #define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
 
 /* Network */
-#define CONFIG_FEC_MXC
-
 #define IMX_FEC_BASE			ENET_BASE_ADDR
 #define CONFIG_FEC_MXC_PHYADDR          0x0
 
-- 
2.24.0

[U-Boot] [PATCH 4/6] ARM: imx: vining2000: Enable fitImage support

[Marek Vasut]

The fitImage support was enabled in the downstream U-Boot port and the
kernel images on the device are fitImage, yet this functionality is not
enabled in mainline U-Boot. Enable it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Silvio Fricke <silvio.fricke@softing.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 configs/vining_2000_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig
index df09cfedb9..65e16f5a7b 100644
--- a/configs/vining_2000_defconfig
+++ b/configs/vining_2000_defconfig
@@ -16,6 +16,8 @@ CONFIG_SPL=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 # CONFIG_CMD_BMODE is not set
 CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/softing/vining_2000/imximage.cfg"
 CONFIG_BOOTDELAY=0
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-- 
2.24.0

[U-Boot] [PATCH 5/6] ARM: imx: vining2000: Repair PCIe support

[Marek Vasut]

Ever since the conversion to DM PCI, the board was missing the PCIe DT
nodes, hence the PCI did not really work. Fill in the DT nodes and add
missing PCIe device reset.

Moreover, bring the PCIe power domain up before booting Linux. This is
mandatory to keep old broken vendor kernels working, as they do not do
so and depend on the bootloader to bring the power domain up.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Silvio Fricke <silvio.fricke@softing.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 arch/arm/dts/imx6sx-softing-vining-2000.dts | 17 +++++++++++++
 board/softing/vining_2000/vining_2000.c     | 28 +++++++++++++++++++++
 2 files changed, 45 insertions(+)

diff --git a/arch/arm/dts/imx6sx-softing-vining-2000.dts b/arch/arm/dts/imx6sx-softing-vining-2000.dts
index 371890ff60..78dd5755a3 100644
--- a/arch/arm/dts/imx6sx-softing-vining-2000.dts
+++ b/arch/arm/dts/imx6sx-softing-vining-2000.dts
@@ -270,6 +270,17 @@
 	status = "okay";
 };
 
+&reg_pcie {
+	regulator-always-on;
+};
+
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie>;
+	reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
 &iomuxc {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gpios>;
@@ -360,6 +371,12 @@
 		>;
 	};
 
+	pinctrl_pcie: pciegrp {
+		fsl,pins = <
+			MX6SX_PAD_NAND_DATA02__GPIO4_IO_6	0x10b0
+		>;
+	};
+
 	pinctrl_pwm1: pwm1grp-1 {
 		fsl,pins = <
 			/* blue LED */
diff --git a/board/softing/vining_2000/vining_2000.c b/board/softing/vining_2000/vining_2000.c
index 83a4d9debe..5da1e620e6 100644
--- a/board/softing/vining_2000/vining_2000.c
+++ b/board/softing/vining_2000/vining_2000.c
@@ -405,6 +405,19 @@ int checkboard(void)
 	return 0;
 }
 
+#define PCIE_PHY_PUP_REQ		BIT(7)
+
+void board_preboot_os(void)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
+
+	/* Bring the PCI power domain up, so that old vendorkernel works. */
+	setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
+	setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
+	setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
+}
+
 #ifdef CONFIG_SPL_BUILD
 #include <linux/libfdt.h>
 #include <spl.h>
@@ -412,6 +425,10 @@ int checkboard(void)
 
 static struct fsl_esdhc_cfg usdhc_cfg = { USDHC4_BASE_ADDR };
 
+static iomux_v3_cfg_t const pcie_pads[] = {
+	MX6_PAD_NAND_DATA02__GPIO4_IO_6 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
 static iomux_v3_cfg_t const uart_pads[] = {
 	MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 	MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
@@ -430,6 +447,11 @@ static iomux_v3_cfg_t const usdhc4_pads[] = {
 	MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 };
 
+static void vining2000_spl_setup_iomux_pcie(void)
+{
+	imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
+}
+
 static void vining2000_spl_setup_iomux_uart(void)
 {
 	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
@@ -573,11 +595,17 @@ void board_init_f(ulong dummy)
 	ccgr_init();
 
 	/* iomux setup */
+	vining2000_spl_setup_iomux_pcie();
 	vining2000_spl_setup_iomux_uart();
 
 	/* setup GP timer */
 	timer_init();
 
+	/* reset the PCIe device */
+	gpio_set_value(IMX_GPIO_NR(4, 6), 1);
+	udelay(50);
+	gpio_set_value(IMX_GPIO_NR(4, 6), 0);
+
 	/* UART clocks enabled and gd valid - init serial console */
 	preloader_console_init();
 
-- 
2.24.0

[U-Boot] [PATCH 6/6] ARM: imx: vining2000: Align SOC and ARM LDO voltages

[Marek Vasut]

The board has both VDD_SOC_IN and VDD_ARM_IN rails connected to the same
PMIC rail, align the LDO voltages to avoid leaking inside the MX6SX SoC.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Silvio Fricke <silvio.fricke@softing.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 board/softing/vining_2000/vining_2000.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/board/softing/vining_2000/vining_2000.c b/board/softing/vining_2000/vining_2000.c
index 5da1e620e6..2564f8e7e3 100644
--- a/board/softing/vining_2000/vining_2000.c
+++ b/board/softing/vining_2000/vining_2000.c
@@ -225,6 +225,9 @@ int power_init_board(void)
 	if (ret < 0)
 		return ret;
 
+	set_ldo_voltage(LDO_ARM, 1175);	/* Set VDDARM to 1.175V */
+	set_ldo_voltage(LDO_SOC, 1175);	/* Set VDDSOC to 1.175V */
+
 	return 0;
 }
 
-- 
2.24.0