* [PATCH v2 0/2] clk: aspeed: Expose RMII RCLK gate for MACs 1-2 on AST2500 @ 2019-10-10 2:06 ` Andrew Jeffery 0 siblings, 0 replies; 23+ messages in thread From: Andrew Jeffery @ 2019-10-10 2:06 UTC (permalink / raw) To: linux-clk Cc: mturquette, sboyd, joel, robh+dt, mark.rutland, linux-arm-kernel, linux-aspeed, linux-kernel, devicetree Hello, This series is two small changes enable kernel support for controlling the RMII RCLK gate on AST2500-based systems. Previously the kernel has assumed u-boot has ungated RCLK for networking to function. RMII is commonly used for NCSI, which itself is commonly used for BMC-based designs to reduce cabling requirements for the platform. v2: * Rename macros and clock names based on Joel's feedback. v1 can be found here: https://lore.kernel.org/linux-clk/20191008113523.13601-1-andrew@aj.id.au/ Please review! Andrew Andrew Jeffery (2): dt-bindings: clock: Add AST2500 RMII RCLK definitions clk: aspeed: Add RMII RCLK gates for both AST2500 MACs drivers/clk/clk-aspeed.c | 27 +++++++++++++++++++++++- include/dt-bindings/clock/aspeed-clock.h | 2 ++ 2 files changed, 28 insertions(+), 1 deletion(-) -- 2.20.1 ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 0/2] clk: aspeed: Expose RMII RCLK gate for MACs 1-2 on AST2500 @ 2019-10-10 2:06 ` Andrew Jeffery 0 siblings, 0 replies; 23+ messages in thread From: Andrew Jeffery @ 2019-10-10 2:06 UTC (permalink / raw) To: linux-clk Cc: mark.rutland, devicetree, linux-aspeed, sboyd, mturquette, linux-kernel, robh+dt, joel, linux-arm-kernel Hello, This series is two small changes enable kernel support for controlling the RMII RCLK gate on AST2500-based systems. Previously the kernel has assumed u-boot has ungated RCLK for networking to function. RMII is commonly used for NCSI, which itself is commonly used for BMC-based designs to reduce cabling requirements for the platform. v2: * Rename macros and clock names based on Joel's feedback. v1 can be found here: https://lore.kernel.org/linux-clk/20191008113523.13601-1-andrew@aj.id.au/ Please review! Andrew Andrew Jeffery (2): dt-bindings: clock: Add AST2500 RMII RCLK definitions clk: aspeed: Add RMII RCLK gates for both AST2500 MACs drivers/clk/clk-aspeed.c | 27 +++++++++++++++++++++++- include/dt-bindings/clock/aspeed-clock.h | 2 ++ 2 files changed, 28 insertions(+), 1 deletion(-) -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 0/2] clk: aspeed: Expose RMII RCLK gate for MACs 1-2 on AST2500 @ 2019-10-10 2:06 ` Andrew Jeffery 0 siblings, 0 replies; 23+ messages in thread From: Andrew Jeffery @ 2019-10-10 2:06 UTC (permalink / raw) To: linux-clk Cc: mark.rutland, devicetree, linux-aspeed, sboyd, mturquette, linux-kernel, robh+dt, joel, linux-arm-kernel Hello, This series is two small changes enable kernel support for controlling the RMII RCLK gate on AST2500-based systems. Previously the kernel has assumed u-boot has ungated RCLK for networking to function. RMII is commonly used for NCSI, which itself is commonly used for BMC-based designs to reduce cabling requirements for the platform. v2: * Rename macros and clock names based on Joel's feedback. v1 can be found here: https://lore.kernel.org/linux-clk/20191008113523.13601-1-andrew@aj.id.au/ Please review! Andrew Andrew Jeffery (2): dt-bindings: clock: Add AST2500 RMII RCLK definitions clk: aspeed: Add RMII RCLK gates for both AST2500 MACs drivers/clk/clk-aspeed.c | 27 +++++++++++++++++++++++- include/dt-bindings/clock/aspeed-clock.h | 2 ++ 2 files changed, 28 insertions(+), 1 deletion(-) -- 2.20.1 ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 1/2] dt-bindings: clock: Add AST2500 RMII RCLK definitions 2019-10-10 2:06 ` Andrew Jeffery (?) @ 2019-10-10 2:06 ` Andrew Jeffery -1 siblings, 0 replies; 23+ messages in thread From: Andrew Jeffery @ 2019-10-10 2:06 UTC (permalink / raw) To: linux-clk Cc: mturquette, sboyd, joel, robh+dt, mark.rutland, linux-arm-kernel, linux-aspeed, linux-kernel, devicetree The AST2500 has an explicit gate for the RMII RCLK for each of the two MACs. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> --- v2: Drop "_GATE" from symbol names include/dt-bindings/clock/aspeed-clock.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index f43738607d77..9ff4f6e4558c 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -39,6 +39,8 @@ #define ASPEED_CLK_BCLK 33 #define ASPEED_CLK_MPLL 34 #define ASPEED_CLK_24M 35 +#define ASPEED_CLK_MAC1RCLK 36 +#define ASPEED_CLK_MAC2RCLK 37 #define ASPEED_RESET_XDMA 0 #define ASPEED_RESET_MCTP 1 -- 2.20.1 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 1/2] dt-bindings: clock: Add AST2500 RMII RCLK definitions @ 2019-10-10 2:06 ` Andrew Jeffery 0 siblings, 0 replies; 23+ messages in thread From: Andrew Jeffery @ 2019-10-10 2:06 UTC (permalink / raw) To: linux-clk Cc: mark.rutland, devicetree, linux-aspeed, sboyd, mturquette, linux-kernel, robh+dt, joel, linux-arm-kernel The AST2500 has an explicit gate for the RMII RCLK for each of the two MACs. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> --- v2: Drop "_GATE" from symbol names include/dt-bindings/clock/aspeed-clock.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index f43738607d77..9ff4f6e4558c 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -39,6 +39,8 @@ #define ASPEED_CLK_BCLK 33 #define ASPEED_CLK_MPLL 34 #define ASPEED_CLK_24M 35 +#define ASPEED_CLK_MAC1RCLK 36 +#define ASPEED_CLK_MAC2RCLK 37 #define ASPEED_RESET_XDMA 0 #define ASPEED_RESET_MCTP 1 -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 1/2] dt-bindings: clock: Add AST2500 RMII RCLK definitions @ 2019-10-10 2:06 ` Andrew Jeffery 0 siblings, 0 replies; 23+ messages in thread From: Andrew Jeffery @ 2019-10-10 2:06 UTC (permalink / raw) To: linux-clk Cc: mark.rutland, devicetree, linux-aspeed, sboyd, mturquette, linux-kernel, robh+dt, joel, linux-arm-kernel The AST2500 has an explicit gate for the RMII RCLK for each of the two MACs. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> --- v2: Drop "_GATE" from symbol names include/dt-bindings/clock/aspeed-clock.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index f43738607d77..9ff4f6e4558c 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -39,6 +39,8 @@ #define ASPEED_CLK_BCLK 33 #define ASPEED_CLK_MPLL 34 #define ASPEED_CLK_24M 35 +#define ASPEED_CLK_MAC1RCLK 36 +#define ASPEED_CLK_MAC2RCLK 37 #define ASPEED_RESET_XDMA 0 #define ASPEED_RESET_MCTP 1 -- 2.20.1 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH v2 1/2] dt-bindings: clock: Add AST2500 RMII RCLK definitions 2019-10-10 2:06 ` Andrew Jeffery @ 2019-10-10 23:39 ` Joel Stanley -1 siblings, 0 replies; 23+ messages in thread From: Joel Stanley @ 2019-10-10 23:39 UTC (permalink / raw) To: Andrew Jeffery Cc: linux-clk, Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland, Linux ARM, linux-aspeed, Linux Kernel Mailing List, devicetree On Thu, 10 Oct 2019 at 02:05, Andrew Jeffery <andrew@aj.id.au> wrote: > > The AST2500 has an explicit gate for the RMII RCLK for each of the two > MACs. > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 1/2] dt-bindings: clock: Add AST2500 RMII RCLK definitions @ 2019-10-10 23:39 ` Joel Stanley 0 siblings, 0 replies; 23+ messages in thread From: Joel Stanley @ 2019-10-10 23:39 UTC (permalink / raw) To: Andrew Jeffery Cc: Mark Rutland, devicetree, linux-aspeed, Stephen Boyd, Michael Turquette, Linux Kernel Mailing List, Rob Herring, linux-clk, Linux ARM On Thu, 10 Oct 2019 at 02:05, Andrew Jeffery <andrew@aj.id.au> wrote: > > The AST2500 has an explicit gate for the RMII RCLK for each of the two > MACs. > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 1/2] dt-bindings: clock: Add AST2500 RMII RCLK definitions 2019-10-10 2:06 ` Andrew Jeffery @ 2019-10-11 17:01 ` Rob Herring -1 siblings, 0 replies; 23+ messages in thread From: Rob Herring @ 2019-10-11 17:01 UTC (permalink / raw) To: Andrew Jeffery Cc: linux-clk, mturquette, sboyd, joel, robh+dt, mark.rutland, linux-arm-kernel, linux-aspeed, linux-kernel, devicetree On Thu, 10 Oct 2019 12:36:54 +1030, Andrew Jeffery wrote: > The AST2500 has an explicit gate for the RMII RCLK for each of the two > MACs. > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > --- > v2: Drop "_GATE" from symbol names > > include/dt-bindings/clock/aspeed-clock.h | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 1/2] dt-bindings: clock: Add AST2500 RMII RCLK definitions @ 2019-10-11 17:01 ` Rob Herring 0 siblings, 0 replies; 23+ messages in thread From: Rob Herring @ 2019-10-11 17:01 UTC (permalink / raw) To: Andrew Jeffery Cc: mark.rutland, devicetree, linux-aspeed, sboyd, mturquette, linux-kernel, robh+dt, joel, linux-clk, linux-arm-kernel On Thu, 10 Oct 2019 12:36:54 +1030, Andrew Jeffery wrote: > The AST2500 has an explicit gate for the RMII RCLK for each of the two > MACs. > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > --- > v2: Drop "_GATE" from symbol names > > include/dt-bindings/clock/aspeed-clock.h | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring <robh@kernel.org> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 2/2] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs 2019-10-10 2:06 ` Andrew Jeffery (?) @ 2019-10-10 2:06 ` Andrew Jeffery -1 siblings, 0 replies; 23+ messages in thread From: Andrew Jeffery @ 2019-10-10 2:06 UTC (permalink / raw) To: linux-clk Cc: mturquette, sboyd, joel, robh+dt, mark.rutland, linux-arm-kernel, linux-aspeed, linux-kernel, devicetree RCLK is a fixed 50MHz clock derived from HPLL that is described by a single gate for each MAC. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> --- v2: Drop "-gate" from clock names drivers/clk/clk-aspeed.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index abf06fb6453e..411ff5fb2c07 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -14,7 +14,7 @@ #include "clk-aspeed.h" -#define ASPEED_NUM_CLKS 36 +#define ASPEED_NUM_CLKS 38 #define ASPEED_RESET2_OFFSET 32 @@ -28,6 +28,7 @@ #define AST2400_HPLL_BYPASS_EN BIT(17) #define ASPEED_MISC_CTRL 0x2c #define UART_DIV13_EN BIT(12) +#define ASPEED_MAC_CLK_DLY 0x48 #define ASPEED_STRAP 0x70 #define CLKIN_25MHZ_EN BIT(23) #define AST2400_CLK_SOURCE_SEL BIT(18) @@ -462,6 +463,30 @@ static int aspeed_clk_probe(struct platform_device *pdev) return PTR_ERR(hw); aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw; + if (of_device_is_compatible(pdev->dev.of_node, "aspeed,ast2500-scu")) { + /* RMII 50MHz RCLK */ + hw = clk_hw_register_fixed_rate(dev, "mac12rclk", "hpll", 0, + 50000000); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + /* RMII1 50MHz (RCLK) output enable */ + hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0, + scu_base + ASPEED_MAC_CLK_DLY, 29, 0, + &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_MAC1RCLK] = hw; + + /* RMII2 50MHz (RCLK) output enable */ + hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0, + scu_base + ASPEED_MAC_CLK_DLY, 30, 0, + &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_MAC2RCLK] = hw; + } + /* LPC Host (LHCLK) clock divider */ hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0, scu_base + ASPEED_CLK_SELECTION, 20, 3, 0, -- 2.20.1 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 2/2] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs @ 2019-10-10 2:06 ` Andrew Jeffery 0 siblings, 0 replies; 23+ messages in thread From: Andrew Jeffery @ 2019-10-10 2:06 UTC (permalink / raw) To: linux-clk Cc: mark.rutland, devicetree, linux-aspeed, sboyd, mturquette, linux-kernel, robh+dt, joel, linux-arm-kernel RCLK is a fixed 50MHz clock derived from HPLL that is described by a single gate for each MAC. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> --- v2: Drop "-gate" from clock names drivers/clk/clk-aspeed.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index abf06fb6453e..411ff5fb2c07 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -14,7 +14,7 @@ #include "clk-aspeed.h" -#define ASPEED_NUM_CLKS 36 +#define ASPEED_NUM_CLKS 38 #define ASPEED_RESET2_OFFSET 32 @@ -28,6 +28,7 @@ #define AST2400_HPLL_BYPASS_EN BIT(17) #define ASPEED_MISC_CTRL 0x2c #define UART_DIV13_EN BIT(12) +#define ASPEED_MAC_CLK_DLY 0x48 #define ASPEED_STRAP 0x70 #define CLKIN_25MHZ_EN BIT(23) #define AST2400_CLK_SOURCE_SEL BIT(18) @@ -462,6 +463,30 @@ static int aspeed_clk_probe(struct platform_device *pdev) return PTR_ERR(hw); aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw; + if (of_device_is_compatible(pdev->dev.of_node, "aspeed,ast2500-scu")) { + /* RMII 50MHz RCLK */ + hw = clk_hw_register_fixed_rate(dev, "mac12rclk", "hpll", 0, + 50000000); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + /* RMII1 50MHz (RCLK) output enable */ + hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0, + scu_base + ASPEED_MAC_CLK_DLY, 29, 0, + &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_MAC1RCLK] = hw; + + /* RMII2 50MHz (RCLK) output enable */ + hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0, + scu_base + ASPEED_MAC_CLK_DLY, 30, 0, + &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_MAC2RCLK] = hw; + } + /* LPC Host (LHCLK) clock divider */ hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0, scu_base + ASPEED_CLK_SELECTION, 20, 3, 0, -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 2/2] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs @ 2019-10-10 2:06 ` Andrew Jeffery 0 siblings, 0 replies; 23+ messages in thread From: Andrew Jeffery @ 2019-10-10 2:06 UTC (permalink / raw) To: linux-clk Cc: mark.rutland, devicetree, linux-aspeed, sboyd, mturquette, linux-kernel, robh+dt, joel, linux-arm-kernel RCLK is a fixed 50MHz clock derived from HPLL that is described by a single gate for each MAC. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> --- v2: Drop "-gate" from clock names drivers/clk/clk-aspeed.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index abf06fb6453e..411ff5fb2c07 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -14,7 +14,7 @@ #include "clk-aspeed.h" -#define ASPEED_NUM_CLKS 36 +#define ASPEED_NUM_CLKS 38 #define ASPEED_RESET2_OFFSET 32 @@ -28,6 +28,7 @@ #define AST2400_HPLL_BYPASS_EN BIT(17) #define ASPEED_MISC_CTRL 0x2c #define UART_DIV13_EN BIT(12) +#define ASPEED_MAC_CLK_DLY 0x48 #define ASPEED_STRAP 0x70 #define CLKIN_25MHZ_EN BIT(23) #define AST2400_CLK_SOURCE_SEL BIT(18) @@ -462,6 +463,30 @@ static int aspeed_clk_probe(struct platform_device *pdev) return PTR_ERR(hw); aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw; + if (of_device_is_compatible(pdev->dev.of_node, "aspeed,ast2500-scu")) { + /* RMII 50MHz RCLK */ + hw = clk_hw_register_fixed_rate(dev, "mac12rclk", "hpll", 0, + 50000000); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + /* RMII1 50MHz (RCLK) output enable */ + hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0, + scu_base + ASPEED_MAC_CLK_DLY, 29, 0, + &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_MAC1RCLK] = hw; + + /* RMII2 50MHz (RCLK) output enable */ + hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0, + scu_base + ASPEED_MAC_CLK_DLY, 30, 0, + &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_MAC2RCLK] = hw; + } + /* LPC Host (LHCLK) clock divider */ hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0, scu_base + ASPEED_CLK_SELECTION, 20, 3, 0, -- 2.20.1 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/2] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs 2019-10-10 2:06 ` Andrew Jeffery @ 2019-10-10 23:41 ` Joel Stanley -1 siblings, 0 replies; 23+ messages in thread From: Joel Stanley @ 2019-10-10 23:41 UTC (permalink / raw) To: Andrew Jeffery Cc: linux-clk, Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland, Linux ARM, linux-aspeed, Linux Kernel Mailing List, devicetree On Thu, 10 Oct 2019 at 02:06, Andrew Jeffery <andrew@aj.id.au> wrote: > > RCLK is a fixed 50MHz clock derived from HPLL that is described by a > single gate for each MAC. > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/2] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs @ 2019-10-10 23:41 ` Joel Stanley 0 siblings, 0 replies; 23+ messages in thread From: Joel Stanley @ 2019-10-10 23:41 UTC (permalink / raw) To: Andrew Jeffery Cc: Mark Rutland, devicetree, linux-aspeed, Stephen Boyd, Michael Turquette, Linux Kernel Mailing List, Rob Herring, linux-clk, Linux ARM On Thu, 10 Oct 2019 at 02:06, Andrew Jeffery <andrew@aj.id.au> wrote: > > RCLK is a fixed 50MHz clock derived from HPLL that is described by a > single gate for each MAC. > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/2] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs 2019-10-10 23:41 ` Joel Stanley @ 2019-11-26 0:59 ` Joel Stanley -1 siblings, 0 replies; 23+ messages in thread From: Joel Stanley @ 2019-11-26 0:59 UTC (permalink / raw) To: Andrew Jeffery Cc: linux-clk, Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland, Linux ARM, linux-aspeed, Linux Kernel Mailing List, devicetree Hi Stephen, On Thu, 10 Oct 2019 at 23:41, Joel Stanley <joel@jms.id.au> wrote: > > On Thu, 10 Oct 2019 at 02:06, Andrew Jeffery <andrew@aj.id.au> wrote: > > > > RCLK is a fixed 50MHz clock derived from HPLL that is described by a > > single gate for each MAC. > > > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > > Reviewed-by: Joel Stanley <joel@jms.id.au> I noticed this one hasn't been applied to clk-next. Cheers, Joel ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/2] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs @ 2019-11-26 0:59 ` Joel Stanley 0 siblings, 0 replies; 23+ messages in thread From: Joel Stanley @ 2019-11-26 0:59 UTC (permalink / raw) To: Andrew Jeffery Cc: Mark Rutland, devicetree, linux-aspeed, Stephen Boyd, Michael Turquette, Linux Kernel Mailing List, Rob Herring, linux-clk, Linux ARM Hi Stephen, On Thu, 10 Oct 2019 at 23:41, Joel Stanley <joel@jms.id.au> wrote: > > On Thu, 10 Oct 2019 at 02:06, Andrew Jeffery <andrew@aj.id.au> wrote: > > > > RCLK is a fixed 50MHz clock derived from HPLL that is described by a > > single gate for each MAC. > > > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > > Reviewed-by: Joel Stanley <joel@jms.id.au> I noticed this one hasn't been applied to clk-next. Cheers, Joel _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/2] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs 2019-11-26 0:59 ` Joel Stanley @ 2019-11-26 18:01 ` Stephen Boyd -1 siblings, 0 replies; 23+ messages in thread From: Stephen Boyd @ 2019-11-26 18:01 UTC (permalink / raw) To: Andrew Jeffery, Joel Stanley Cc: linux-clk, Michael Turquette, Rob Herring, Mark Rutland, Linux ARM, linux-aspeed, Linux Kernel Mailing List, devicetree Quoting Joel Stanley (2019-11-25 16:59:19) > Hi Stephen, > > On Thu, 10 Oct 2019 at 23:41, Joel Stanley <joel@jms.id.au> wrote: > > > > On Thu, 10 Oct 2019 at 02:06, Andrew Jeffery <andrew@aj.id.au> wrote: > > > > > > RCLK is a fixed 50MHz clock derived from HPLL that is described by a > > > single gate for each MAC. > > > > > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > > > > Reviewed-by: Joel Stanley <joel@jms.id.au> > > I noticed this one hasn't been applied to clk-next. > It's marked awaiting upstream in my UI. I think it was some patch that might have come through your PR? ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/2] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs @ 2019-11-26 18:01 ` Stephen Boyd 0 siblings, 0 replies; 23+ messages in thread From: Stephen Boyd @ 2019-11-26 18:01 UTC (permalink / raw) To: Andrew Jeffery, Joel Stanley Cc: Mark Rutland, devicetree, linux-aspeed, Michael Turquette, Linux Kernel Mailing List, Rob Herring, linux-clk, Linux ARM Quoting Joel Stanley (2019-11-25 16:59:19) > Hi Stephen, > > On Thu, 10 Oct 2019 at 23:41, Joel Stanley <joel@jms.id.au> wrote: > > > > On Thu, 10 Oct 2019 at 02:06, Andrew Jeffery <andrew@aj.id.au> wrote: > > > > > > RCLK is a fixed 50MHz clock derived from HPLL that is described by a > > > single gate for each MAC. > > > > > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > > > > Reviewed-by: Joel Stanley <joel@jms.id.au> > > I noticed this one hasn't been applied to clk-next. > It's marked awaiting upstream in my UI. I think it was some patch that might have come through your PR? _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/2] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs 2019-10-10 2:06 ` Andrew Jeffery @ 2019-11-26 18:03 ` Stephen Boyd -1 siblings, 0 replies; 23+ messages in thread From: Stephen Boyd @ 2019-11-26 18:03 UTC (permalink / raw) To: Andrew Jeffery, linux-clk Cc: mturquette, joel, robh+dt, mark.rutland, linux-arm-kernel, linux-aspeed, linux-kernel, devicetree Quoting Andrew Jeffery (2019-10-09 19:06:55) > RCLK is a fixed 50MHz clock derived from HPLL that is described by a > single gate for each MAC. > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > --- Applied to clk-next ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/2] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs @ 2019-11-26 18:03 ` Stephen Boyd 0 siblings, 0 replies; 23+ messages in thread From: Stephen Boyd @ 2019-11-26 18:03 UTC (permalink / raw) To: Andrew Jeffery, linux-clk Cc: mark.rutland, devicetree, linux-aspeed, mturquette, linux-kernel, robh+dt, joel, linux-arm-kernel Quoting Andrew Jeffery (2019-10-09 19:06:55) > RCLK is a fixed 50MHz clock derived from HPLL that is described by a > single gate for each MAC. > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > --- Applied to clk-next _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/2] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs 2019-11-26 18:03 ` Stephen Boyd @ 2019-11-29 1:22 ` Joel Stanley -1 siblings, 0 replies; 23+ messages in thread From: Joel Stanley @ 2019-11-29 1:22 UTC (permalink / raw) To: Stephen Boyd Cc: Andrew Jeffery, linux-clk, Michael Turquette, Rob Herring, Mark Rutland, Linux ARM, linux-aspeed, Linux Kernel Mailing List, devicetree On Tue, 26 Nov 2019 at 18:03, Stephen Boyd <sboyd@kernel.org> wrote: > > Quoting Andrew Jeffery (2019-10-09 19:06:55) > > RCLK is a fixed 50MHz clock derived from HPLL that is described by a > > single gate for each MAC. > > > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > > --- > > Applied to clk-next > Thanks! ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/2] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs @ 2019-11-29 1:22 ` Joel Stanley 0 siblings, 0 replies; 23+ messages in thread From: Joel Stanley @ 2019-11-29 1:22 UTC (permalink / raw) To: Stephen Boyd Cc: Mark Rutland, devicetree, linux-aspeed, Andrew Jeffery, Michael Turquette, Linux Kernel Mailing List, Rob Herring, linux-clk, Linux ARM On Tue, 26 Nov 2019 at 18:03, Stephen Boyd <sboyd@kernel.org> wrote: > > Quoting Andrew Jeffery (2019-10-09 19:06:55) > > RCLK is a fixed 50MHz clock derived from HPLL that is described by a > > single gate for each MAC. > > > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > > --- > > Applied to clk-next > Thanks! _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2019-11-29 1:23 UTC | newest] Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-10-10 2:06 [PATCH v2 0/2] clk: aspeed: Expose RMII RCLK gate for MACs 1-2 on AST2500 Andrew Jeffery 2019-10-10 2:06 ` Andrew Jeffery 2019-10-10 2:06 ` Andrew Jeffery 2019-10-10 2:06 ` [PATCH v2 1/2] dt-bindings: clock: Add AST2500 RMII RCLK definitions Andrew Jeffery 2019-10-10 2:06 ` Andrew Jeffery 2019-10-10 2:06 ` Andrew Jeffery 2019-10-10 23:39 ` Joel Stanley 2019-10-10 23:39 ` Joel Stanley 2019-10-11 17:01 ` Rob Herring 2019-10-11 17:01 ` Rob Herring 2019-10-10 2:06 ` [PATCH v2 2/2] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs Andrew Jeffery 2019-10-10 2:06 ` Andrew Jeffery 2019-10-10 2:06 ` Andrew Jeffery 2019-10-10 23:41 ` Joel Stanley 2019-10-10 23:41 ` Joel Stanley 2019-11-26 0:59 ` Joel Stanley 2019-11-26 0:59 ` Joel Stanley 2019-11-26 18:01 ` Stephen Boyd 2019-11-26 18:01 ` Stephen Boyd 2019-11-26 18:03 ` Stephen Boyd 2019-11-26 18:03 ` Stephen Boyd 2019-11-29 1:22 ` Joel Stanley 2019-11-29 1:22 ` Joel Stanley
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