From: Bjorn Helgaas <helgaas@kernel.org> To: Vidya Sagar <vidyas@nvidia.com> Cc: lorenzo.pieralisi@arm.com, robh+dt@kernel.org, thierry.reding@gmail.com, jonathanh@nvidia.com, andrew.murray@arm.com, kishon@ti.com, gustavo.pimentel@synopsys.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kthota@nvidia.com, mmaddireddy@nvidia.com, sagar.tv@gmail.com Subject: Re: [PATCH 3/6] PCI: tegra: Add support for PCIe endpoint mode in Tegra194 Date: Tue, 26 Nov 2019 15:37:18 -0600 [thread overview] Message-ID: <20191126213718.GA185422@google.com> (raw) In-Reply-To: <20191122104505.8986-4-vidyas@nvidia.com> On Fri, Nov 22, 2019 at 04:15:02PM +0530, Vidya Sagar wrote: > Add support for the endpoint mode of Synopsys DesignWare core based > dual mode PCIe controllers present in Tegra194 SoC. > +static irqreturn_t tegra_pcie_ep_irq_handler(struct tegra_pcie_dw *pcie) > +{ > + struct dw_pcie_ep *ep = &pcie->pci.ep; > + u32 val, tmp; > + > + val = appl_readl(pcie, APPL_INTR_STATUS_L0); > + if (val & APPL_INTR_STATUS_L0_LINK_STATE_INT) { > + val = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0); > + appl_writel(pcie, val, APPL_INTR_STATUS_L1_0_0); > + if (val & APPL_INTR_STATUS_L1_0_0_HOT_RESET_DONE) { > + /* clear any stale PEX_RST interrupt */ > + if (!kfifo_put(&pcie->event_fifo, EP_HOT_RST_DONE)) { > + dev_err(pcie->dev, "EVENT FIFO is full\n"); > + return IRQ_HANDLED; > + } > + wake_up(&pcie->wq); > + } > + if (val & APPL_INTR_STATUS_L1_0_0_RDLH_LINK_UP_CHGED) { > + tmp = appl_readl(pcie, APPL_LINK_STATUS); > + if (tmp & APPL_LINK_STATUS_RDLH_LINK_UP) { > + dev_info(pcie->dev, "Link is up with Host\n"); > + dw_pcie_ep_linkup(ep); > + } > + } > + } else if (val & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT) { Is it really the case that only one of APPL_INTR_STATUS_L0_LINK_STATE_INT and APPL_INTR_STATUS_L0_PCI_CMD_EN_INT can be set? If it's possible that both could be set, maybe this should be something like this? int spurious = 1; if (val & APPL_INTR_STATUS_L0_LINK_STATE_INT) { ... spurious = 0; } if (val & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT) { ... spurious = 0; } if (spurious) { dev_warn(...) } > + val = appl_readl(pcie, APPL_INTR_STATUS_L1_15); > + appl_writel(pcie, val, APPL_INTR_STATUS_L1_15); > + if (val & APPL_INTR_STATUS_L1_15_CFG_BME_CHGED) { > + if (!kfifo_put(&pcie->event_fifo, EP_BME_CHANGE)) { > + dev_err(pcie->dev, "EVENT FIFO is full\n"); > + return IRQ_HANDLED; > + } > + wake_up(&pcie->wq); > + } > + } else { > + dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n", > + val); > + appl_writel(pcie, val, APPL_INTR_STATUS_L0); > + } > + > + return IRQ_HANDLED; > +} > +static int tegra_pcie_ep_work_thread(void *p) > +{ > + struct tegra_pcie_dw *pcie = (struct tegra_pcie_dw *)p; > + u32 event; > + > + while (true) { > + wait_event_interruptible(pcie->wq, > + !kfifo_is_empty(&pcie->event_fifo)); > + > + if (kthread_should_stop()) > + break; > + > + if (!kfifo_get(&pcie->event_fifo, &event)) { > + dev_warn(pcie->dev, "EVENT FIFO is empty\n"); > + continue; > + } > + > + switch (event) { > + case EP_PEX_RST_DEASSERT: > + dev_info(pcie->dev, "EVENT: EP_PEX_RST_DEASSERT\n"); > + pex_ep_event_pex_rst_deassert(pcie); > + break; > + > + case EP_PEX_RST_ASSERT: > + dev_info(pcie->dev, "EVENT: EP_PEX_RST_ASSERT\n"); > + pex_ep_event_pex_rst_assert(pcie); > + break; > + > + case EP_HOT_RST_DONE: > + dev_info(pcie->dev, "EVENT: EP_HOT_RST_DONE\n"); > + pex_ep_event_hot_rst_done(pcie); > + break; > + > + case EP_BME_CHANGE: > + dev_info(pcie->dev, "EVENT: EP_BME_CHANGE\n"); > + pex_ep_event_bme_change(pcie); > + break; > + > + case EP_EVENT_EXIT: > + dev_info(pcie->dev, "EVENT: EP_EVENT_EXIT\n"); > + return 0; > + > + default: > + dev_warn(pcie->dev, "Invalid PCIe EP event\n"); Maybe include the invalid event value in the message? > + break; > + } > + } > + > + return 0; > +}
WARNING: multiple messages have this Message-ID (diff)
From: Bjorn Helgaas <helgaas@kernel.org> To: Vidya Sagar <vidyas@nvidia.com> Cc: devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com, mmaddireddy@nvidia.com, kthota@nvidia.com, gustavo.pimentel@synopsys.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, kishon@ti.com, thierry.reding@gmail.com, linux-pci@vger.kernel.org, linux-tegra@vger.kernel.org, andrew.murray@arm.com, jonathanh@nvidia.com, linux-arm-kernel@lists.infradead.org, sagar.tv@gmail.com Subject: Re: [PATCH 3/6] PCI: tegra: Add support for PCIe endpoint mode in Tegra194 Date: Tue, 26 Nov 2019 15:37:18 -0600 [thread overview] Message-ID: <20191126213718.GA185422@google.com> (raw) In-Reply-To: <20191122104505.8986-4-vidyas@nvidia.com> On Fri, Nov 22, 2019 at 04:15:02PM +0530, Vidya Sagar wrote: > Add support for the endpoint mode of Synopsys DesignWare core based > dual mode PCIe controllers present in Tegra194 SoC. > +static irqreturn_t tegra_pcie_ep_irq_handler(struct tegra_pcie_dw *pcie) > +{ > + struct dw_pcie_ep *ep = &pcie->pci.ep; > + u32 val, tmp; > + > + val = appl_readl(pcie, APPL_INTR_STATUS_L0); > + if (val & APPL_INTR_STATUS_L0_LINK_STATE_INT) { > + val = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0); > + appl_writel(pcie, val, APPL_INTR_STATUS_L1_0_0); > + if (val & APPL_INTR_STATUS_L1_0_0_HOT_RESET_DONE) { > + /* clear any stale PEX_RST interrupt */ > + if (!kfifo_put(&pcie->event_fifo, EP_HOT_RST_DONE)) { > + dev_err(pcie->dev, "EVENT FIFO is full\n"); > + return IRQ_HANDLED; > + } > + wake_up(&pcie->wq); > + } > + if (val & APPL_INTR_STATUS_L1_0_0_RDLH_LINK_UP_CHGED) { > + tmp = appl_readl(pcie, APPL_LINK_STATUS); > + if (tmp & APPL_LINK_STATUS_RDLH_LINK_UP) { > + dev_info(pcie->dev, "Link is up with Host\n"); > + dw_pcie_ep_linkup(ep); > + } > + } > + } else if (val & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT) { Is it really the case that only one of APPL_INTR_STATUS_L0_LINK_STATE_INT and APPL_INTR_STATUS_L0_PCI_CMD_EN_INT can be set? If it's possible that both could be set, maybe this should be something like this? int spurious = 1; if (val & APPL_INTR_STATUS_L0_LINK_STATE_INT) { ... spurious = 0; } if (val & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT) { ... spurious = 0; } if (spurious) { dev_warn(...) } > + val = appl_readl(pcie, APPL_INTR_STATUS_L1_15); > + appl_writel(pcie, val, APPL_INTR_STATUS_L1_15); > + if (val & APPL_INTR_STATUS_L1_15_CFG_BME_CHGED) { > + if (!kfifo_put(&pcie->event_fifo, EP_BME_CHANGE)) { > + dev_err(pcie->dev, "EVENT FIFO is full\n"); > + return IRQ_HANDLED; > + } > + wake_up(&pcie->wq); > + } > + } else { > + dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n", > + val); > + appl_writel(pcie, val, APPL_INTR_STATUS_L0); > + } > + > + return IRQ_HANDLED; > +} > +static int tegra_pcie_ep_work_thread(void *p) > +{ > + struct tegra_pcie_dw *pcie = (struct tegra_pcie_dw *)p; > + u32 event; > + > + while (true) { > + wait_event_interruptible(pcie->wq, > + !kfifo_is_empty(&pcie->event_fifo)); > + > + if (kthread_should_stop()) > + break; > + > + if (!kfifo_get(&pcie->event_fifo, &event)) { > + dev_warn(pcie->dev, "EVENT FIFO is empty\n"); > + continue; > + } > + > + switch (event) { > + case EP_PEX_RST_DEASSERT: > + dev_info(pcie->dev, "EVENT: EP_PEX_RST_DEASSERT\n"); > + pex_ep_event_pex_rst_deassert(pcie); > + break; > + > + case EP_PEX_RST_ASSERT: > + dev_info(pcie->dev, "EVENT: EP_PEX_RST_ASSERT\n"); > + pex_ep_event_pex_rst_assert(pcie); > + break; > + > + case EP_HOT_RST_DONE: > + dev_info(pcie->dev, "EVENT: EP_HOT_RST_DONE\n"); > + pex_ep_event_hot_rst_done(pcie); > + break; > + > + case EP_BME_CHANGE: > + dev_info(pcie->dev, "EVENT: EP_BME_CHANGE\n"); > + pex_ep_event_bme_change(pcie); > + break; > + > + case EP_EVENT_EXIT: > + dev_info(pcie->dev, "EVENT: EP_EVENT_EXIT\n"); > + return 0; > + > + default: > + dev_warn(pcie->dev, "Invalid PCIe EP event\n"); Maybe include the invalid event value in the message? > + break; > + } > + } > + > + return 0; > +} _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-11-26 21:37 UTC|newest] Thread overview: 61+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-22 10:44 [PATCH 0/6] Add support for PCIe endpoint mode in Tegra194 Vidya Sagar 2019-11-22 10:44 ` Vidya Sagar 2019-11-22 10:44 ` Vidya Sagar 2019-11-22 10:45 ` [PATCH 1/6] soc/tegra: bpmp: Update ABI header Vidya Sagar 2019-11-22 10:45 ` Vidya Sagar 2019-11-22 10:45 ` Vidya Sagar 2019-11-22 10:45 ` [PATCH 2/6] dt-bindings: PCI: tegra: Add DT support for PCIe EP nodes in Tegra194 Vidya Sagar 2019-11-22 10:45 ` Vidya Sagar 2019-11-22 10:45 ` Vidya Sagar 2019-11-22 13:19 ` Thierry Reding 2019-11-22 13:19 ` Thierry Reding 2019-11-25 7:23 ` Vidya Sagar 2019-11-25 7:23 ` Vidya Sagar 2019-11-25 7:23 ` Vidya Sagar 2019-11-25 7:33 ` Thierry Reding 2019-11-25 7:33 ` Thierry Reding 2019-11-25 11:52 ` Gustavo Pimentel 2019-11-25 11:52 ` Gustavo Pimentel 2019-11-25 11:52 ` Gustavo Pimentel 2019-11-29 13:26 ` Vidya Sagar 2019-11-29 13:26 ` Vidya Sagar 2019-11-29 13:26 ` Vidya Sagar 2019-12-05 9:57 ` Vidya Sagar 2019-12-05 9:57 ` Vidya Sagar 2019-12-05 9:57 ` Vidya Sagar 2019-12-04 21:43 ` Rob Herring 2019-12-04 21:43 ` Rob Herring 2019-11-22 10:45 ` [PATCH 3/6] PCI: tegra: Add support for PCIe endpoint mode " Vidya Sagar 2019-11-22 10:45 ` Vidya Sagar 2019-11-22 10:45 ` Vidya Sagar 2019-11-26 21:37 ` Bjorn Helgaas [this message] 2019-11-26 21:37 ` Bjorn Helgaas 2019-11-29 13:22 ` Vidya Sagar 2019-11-29 13:22 ` Vidya Sagar 2019-11-29 13:22 ` Vidya Sagar 2019-11-22 10:45 ` [PATCH 4/6] arm64: tegra: Add PCIe endpoint controllers nodes for Tegra194 Vidya Sagar 2019-11-22 10:45 ` Vidya Sagar 2019-11-22 10:45 ` Vidya Sagar 2019-11-22 10:45 ` [PATCH 5/6] arm64: tegra: Enable GPIO controllers nodes for P2972-0000 platform Vidya Sagar 2019-11-22 10:45 ` Vidya Sagar 2019-11-22 10:45 ` Vidya Sagar 2019-11-22 13:20 ` Thierry Reding 2019-11-22 13:20 ` Thierry Reding 2019-11-25 6:55 ` Vidya Sagar 2019-11-25 6:55 ` Vidya Sagar 2019-11-25 6:55 ` Vidya Sagar 2019-11-22 10:45 ` [PATCH 6/6] arm64: tegra: Add support for PCIe endpoint mode in " Vidya Sagar 2019-11-22 10:45 ` Vidya Sagar 2019-11-22 10:45 ` Vidya Sagar 2019-11-22 13:25 ` Thierry Reding 2019-11-22 13:25 ` Thierry Reding 2019-11-25 7:00 ` Vidya Sagar 2019-11-25 7:00 ` Vidya Sagar 2019-11-25 7:00 ` Vidya Sagar 2019-11-25 7:25 ` Thierry Reding 2019-11-25 7:25 ` Thierry Reding 2019-11-25 7:33 ` Vidya Sagar 2019-11-25 7:33 ` Vidya Sagar 2019-11-25 7:33 ` Vidya Sagar 2019-11-25 7:37 ` Thierry Reding 2019-11-25 7:37 ` Thierry Reding
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