[U-Boot] [PATCH 1/2] rockchip: px30: Fixup PMUGRF registers layout order

[U-Boot] [PATCH 1/2] rockchip: px30: Fixup PMUGRF registers layout order

[Paul Kocialkowski]

According to the PX30 TRM, the iomux registers come first, before the pull
and strength control registers.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
---
 arch/arm/include/asm/arch-rockchip/grf_px30.h | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_px30.h b/arch/arm/include/asm/arch-rockchip/grf_px30.h
index c167bb42fac9..3d2a8770322e 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_px30.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_px30.h
@@ -112,18 +112,18 @@ struct px30_grf {
 check_member(px30_grf, mac_con1, 0x904);
 
 struct px30_pmugrf {
-	unsigned int gpio0a_e;
-	unsigned int gpio0b_e;
-	unsigned int gpio0c_e;
-	unsigned int gpio0d_e;
-	unsigned int gpio0a_p;
-	unsigned int gpio0b_p;
-	unsigned int gpio0c_p;
-	unsigned int gpio0d_p;
 	unsigned int gpio0al_iomux;
 	unsigned int gpio0bl_iomux;
 	unsigned int gpio0cl_iomux;
 	unsigned int gpio0dl_iomux;
+	unsigned int gpio0a_p;
+	unsigned int gpio0b_p;
+	unsigned int gpio0c_p;
+	unsigned int gpio0d_p;
+	unsigned int gpio0a_e;
+	unsigned int gpio0b_e;
+	unsigned int gpio0c_e;
+	unsigned int gpio0d_e;
 	unsigned int gpio0l_sr;
 	unsigned int gpio0h_sr;
 	unsigned int gpio0l_smt;
-- 
2.24.0

[U-Boot] [PATCH 2/2] rockchip: px30: Add support for using UART3 as debug UART

[Paul Kocialkowski]

Some generic PX30 SoMs found in the wild use UART3 as their debug output
instead of UART2 (used for MMC) and UART5.

Make it possible to use UART3 as early debug output, with the associated
clock and pinmux configuration. Two sets of output pins are supported (M0/M1)
so a Kconfig option to select between the two is introduced like it's done
for UART2.

Future users should also note that the pinmux default in the dts is to use
the M1 pins while the Kconfig option takes M0 as a default.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
---
 arch/arm/include/asm/arch-rockchip/cru_px30.h | 19 +++++
 arch/arm/mach-rockchip/px30/Kconfig           |  9 +++
 arch/arm/mach-rockchip/px30/px30.c            | 77 +++++++++++++++++++
 3 files changed, 105 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/cru_px30.h b/arch/arm/include/asm/arch-rockchip/cru_px30.h
index 7d9fd181aca2..798444ae49f5 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_px30.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_px30.h
@@ -357,6 +357,25 @@ enum {
 	UART2_DIVNP5_SHIFT	= 0,
 	UART2_DIVNP5_MASK	= 0x1f << UART2_DIVNP5_SHIFT,
 
+	/* CRU_CLK_SEL40_CON */
+	UART3_PLL_SEL_SHIFT	= 14,
+	UART3_PLL_SEL_MASK	= 3 << UART3_PLL_SEL_SHIFT,
+	UART3_PLL_SEL_GPLL	= 0,
+	UART3_PLL_SEL_24M,
+	UART3_PLL_SEL_480M,
+	UART3_PLL_SEL_NPLL,
+	UART3_DIV_CON_SHIFT	= 0,
+	UART3_DIV_CON_MASK	= 0x1f << UART3_DIV_CON_SHIFT,
+
+	/* CRU_CLK_SEL41_CON */
+	UART3_CLK_SEL_SHIFT	= 14,
+	UART3_CLK_SEL_MASK	= 3 << UART3_PLL_SEL_SHIFT,
+	UART3_CLK_SEL_UART3	= 0,
+	UART3_CLK_SEL_UART3_NP5,
+	UART3_CLK_SEL_UART3_FRAC,
+	UART3_DIVNP5_SHIFT	= 0,
+	UART3_DIVNP5_MASK	= 0x1f << UART3_DIVNP5_SHIFT,
+
 	/* CRU_CLK_SEL46_CON */
 	UART5_PLL_SEL_SHIFT	= 14,
 	UART5_PLL_SEL_MASK	= 3 << UART5_PLL_SEL_SHIFT,
diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig
index 109a37be15ad..167517bbd63f 100644
--- a/arch/arm/mach-rockchip/px30/Kconfig
+++ b/arch/arm/mach-rockchip/px30/Kconfig
@@ -36,6 +36,15 @@ config DEBUG_UART2_CHANNEL
 	  For using the UART for early debugging the route to use needs
 	  to be declared (0 or 1).
 
+config DEBUG_UART3_CHANNEL
+	int "Mux channel to use for debug UART3"
+	depends on DEBUG_UART_BOARD_INIT
+	default 0
+	help
+	  UART3 can use two different set of pins to route the output.
+	  For using the UART for early debugging the route to use needs
+	  to be declared (0 or 1).
+
 source "board/rockchip/evb_px30/Kconfig"
 
 endif
diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c
index bacdcc0b938d..6b12f4f6a502 100644
--- a/arch/arm/mach-rockchip/px30/px30.c
+++ b/arch/arm/mach-rockchip/px30/px30.c
@@ -37,6 +37,7 @@ static struct mm_region px30_mem_map[] = {
 struct mm_region *mem_map = px30_mem_map;
 
 #define PMU_PWRDN_CON			0xff000018
+#define PMUGRF_BASE			0xff010000
 #define GRF_BASE			0xff140000
 #define CRU_BASE			0xff2b0000
 #define VIDEO_PHY_BASE			0xff2e0000
@@ -49,6 +50,23 @@ struct mm_region *mem_map = px30_mem_map;
 
 #define QOS_PRIORITY_LEVEL(h, l)	((((h) & 3) << 8) | ((l) & 3))
 
+/* GRF_GPIO1BH_IOMUX */
+enum {
+	GPIO1B7_SHIFT		= 12,
+	GPIO1B7_MASK		= 0xf << GPIO1B7_SHIFT,
+	GPIO1B7_GPIO		= 0,
+	GPIO1B7_FLASH_RDN,
+	GPIO1B7_UART3_RXM1,
+	GPIO1B7_SPI0_CLK,
+
+	GPIO1B6_SHIFT		= 8,
+	GPIO1B6_MASK		= 0xf << GPIO1B6_SHIFT,
+	GPIO1B6_GPIO		= 0,
+	GPIO1B6_FLASH_CS1,
+	GPIO1B6_UART3_TXM1,
+	GPIO1B6_SPI0_CSN,
+};
+
 /* GRF_GPIO1CL_IOMUX */
 enum {
 	GPIO1C1_SHIFT		= 4,
@@ -128,6 +146,23 @@ enum {
 	GPIO3A1_UART5_RX	= 4,
 };
 
+/* PMUGRF_GPIO0CL_IOMUX */
+enum {
+	GPIO0C1_SHIFT		= 2,
+	GPIO0C1_MASK		= 0x3 << GPIO0C1_SHIFT,
+	GPIO0C1_GPIO		= 0,
+	GPIO0C1_PWM_3,
+	GPIO0C1_UART3_RXM0,
+	GPIO0C1_PMU_DEBUG4,
+
+	GPIO0C0_SHIFT		= 0,
+	GPIO0C0_MASK		= 0x3 << GPIO0C0_SHIFT,
+	GPIO0C0_GPIO		= 0,
+	GPIO0C0_PWM_1,
+	GPIO0C0_UART3_TXM0,
+	GPIO0C0_PMU_DEBUG3,
+};
+
 int arch_cpu_init(void)
 {
 	static struct px30_grf * const grf = (void *)GRF_BASE;
@@ -175,6 +210,11 @@ int arch_cpu_init(void)
 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
 void board_debug_uart_init(void)
 {
+#if defined(CONFIG_DEBUG_UART_BASE) && \
+	(CONFIG_DEBUG_UART_BASE == 0xff168000) && \
+	(CONFIG_DEBUG_UART3_CHANNEL != 1)
+	static struct px30_pmugrf * const pmugrf = (void *)PMUGRF_BASE;
+#endif
 	static struct px30_grf * const grf = (void *)GRF_BASE;
 	static struct px30_cru * const cru = (void *)CRU_BASE;
 
@@ -191,6 +231,43 @@ void board_debug_uart_init(void)
 		     GPIO1C1_MASK | GPIO1C0_MASK,
 		     GPIO1C1_UART1_TX << GPIO1C1_SHIFT |
 		     GPIO1C0_UART1_RX << GPIO1C0_SHIFT);
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff168000)
+	/* GRF_IOFUNC_CON0 */
+	enum {
+		CON_IOMUX_UART3SEL_SHIFT	= 9,
+		CON_IOMUX_UART3SEL_MASK = 1 << CON_IOMUX_UART3SEL_SHIFT,
+		CON_IOMUX_UART3SEL_M0	= 0,
+		CON_IOMUX_UART3SEL_M1,
+	};
+
+	/* uart_sel_clk default select 24MHz */
+	rk_clrsetreg(&cru->clksel_con[40],
+		     UART3_PLL_SEL_MASK | UART3_DIV_CON_MASK,
+		     UART3_PLL_SEL_24M << UART3_PLL_SEL_SHIFT | 0);
+	rk_clrsetreg(&cru->clksel_con[41],
+		     UART3_CLK_SEL_MASK,
+		     UART3_CLK_SEL_UART3 << UART3_CLK_SEL_SHIFT);
+
+#if (CONFIG_DEBUG_UART3_CHANNEL == 1)
+	rk_clrsetreg(&grf->iofunc_con0,
+		     CON_IOMUX_UART3SEL_MASK,
+		     CON_IOMUX_UART3SEL_M1 << CON_IOMUX_UART3SEL_SHIFT);
+
+	rk_clrsetreg(&grf->gpio1bh_iomux,
+		     GPIO1B7_MASK | GPIO1B6_MASK,
+		     GPIO1B7_UART3_RXM1 << GPIO1B7_SHIFT |
+		     GPIO1B6_UART3_TXM1 << GPIO1B6_SHIFT);
+#else
+	rk_clrsetreg(&grf->iofunc_con0,
+		     CON_IOMUX_UART3SEL_MASK,
+		     CON_IOMUX_UART3SEL_M0 << CON_IOMUX_UART3SEL_SHIFT);
+
+	rk_clrsetreg(&pmugrf->gpio0cl_iomux,
+		     GPIO0C1_MASK | GPIO0C0_MASK,
+		     GPIO0C1_UART3_RXM0 << GPIO0C1_SHIFT |
+		     GPIO0C0_UART3_TXM0 << GPIO0C0_SHIFT);
+#endif /* CONFIG_DEBUG_UART3_CHANNEL == 1 */
+
 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff178000)
 	/* uart_sel_clk default select 24MHz */
 	rk_clrsetreg(&cru->clksel_con[46],
-- 
2.24.0

[U-Boot] [PATCH 1/2] rockchip: px30: Fixup PMUGRF registers layout order

[Kever Yang]

On 2019/11/27 下午6:12, Paul Kocialkowski wrote:
> According to the PX30 TRM, the iomux registers come first, before the pull
> and strength control registers.
>
> Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   arch/arm/include/asm/arch-rockchip/grf_px30.h | 16 ++++++++--------
>   1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-rockchip/grf_px30.h b/arch/arm/include/asm/arch-rockchip/grf_px30.h
> index c167bb42fac9..3d2a8770322e 100644
> --- a/arch/arm/include/asm/arch-rockchip/grf_px30.h
> +++ b/arch/arm/include/asm/arch-rockchip/grf_px30.h
> @@ -112,18 +112,18 @@ struct px30_grf {
>   check_member(px30_grf, mac_con1, 0x904);
>   
>   struct px30_pmugrf {
> -	unsigned int gpio0a_e;
> -	unsigned int gpio0b_e;
> -	unsigned int gpio0c_e;
> -	unsigned int gpio0d_e;
> -	unsigned int gpio0a_p;
> -	unsigned int gpio0b_p;
> -	unsigned int gpio0c_p;
> -	unsigned int gpio0d_p;
>   	unsigned int gpio0al_iomux;
>   	unsigned int gpio0bl_iomux;
>   	unsigned int gpio0cl_iomux;
>   	unsigned int gpio0dl_iomux;
> +	unsigned int gpio0a_p;
> +	unsigned int gpio0b_p;
> +	unsigned int gpio0c_p;
> +	unsigned int gpio0d_p;
> +	unsigned int gpio0a_e;
> +	unsigned int gpio0b_e;
> +	unsigned int gpio0c_e;
> +	unsigned int gpio0d_e;
>   	unsigned int gpio0l_sr;
>   	unsigned int gpio0h_sr;
>   	unsigned int gpio0l_smt;

[U-Boot] [PATCH 2/2] rockchip: px30: Add support for using UART3 as debug UART

[Kever Yang]

On 2019/11/27 下午6:12, Paul Kocialkowski wrote:
> Some generic PX30 SoMs found in the wild use UART3 as their debug output
> instead of UART2 (used for MMC) and UART5.
>
> Make it possible to use UART3 as early debug output, with the associated
> clock and pinmux configuration. Two sets of output pins are supported (M0/M1)
> so a Kconfig option to select between the two is introduced like it's done
> for UART2.
>
> Future users should also note that the pinmux default in the dts is to use
> the M1 pins while the Kconfig option takes M0 as a default.
>
> Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>


Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever

> ---
>   arch/arm/include/asm/arch-rockchip/cru_px30.h | 19 +++++
>   arch/arm/mach-rockchip/px30/Kconfig           |  9 +++
>   arch/arm/mach-rockchip/px30/px30.c            | 77 +++++++++++++++++++
>   3 files changed, 105 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-rockchip/cru_px30.h b/arch/arm/include/asm/arch-rockchip/cru_px30.h
> index 7d9fd181aca2..798444ae49f5 100644
> --- a/arch/arm/include/asm/arch-rockchip/cru_px30.h
> +++ b/arch/arm/include/asm/arch-rockchip/cru_px30.h
> @@ -357,6 +357,25 @@ enum {
>   	UART2_DIVNP5_SHIFT	= 0,
>   	UART2_DIVNP5_MASK	= 0x1f << UART2_DIVNP5_SHIFT,
>   
> +	/* CRU_CLK_SEL40_CON */
> +	UART3_PLL_SEL_SHIFT	= 14,
> +	UART3_PLL_SEL_MASK	= 3 << UART3_PLL_SEL_SHIFT,
> +	UART3_PLL_SEL_GPLL	= 0,
> +	UART3_PLL_SEL_24M,
> +	UART3_PLL_SEL_480M,
> +	UART3_PLL_SEL_NPLL,
> +	UART3_DIV_CON_SHIFT	= 0,
> +	UART3_DIV_CON_MASK	= 0x1f << UART3_DIV_CON_SHIFT,
> +
> +	/* CRU_CLK_SEL41_CON */
> +	UART3_CLK_SEL_SHIFT	= 14,
> +	UART3_CLK_SEL_MASK	= 3 << UART3_PLL_SEL_SHIFT,
> +	UART3_CLK_SEL_UART3	= 0,
> +	UART3_CLK_SEL_UART3_NP5,
> +	UART3_CLK_SEL_UART3_FRAC,
> +	UART3_DIVNP5_SHIFT	= 0,
> +	UART3_DIVNP5_MASK	= 0x1f << UART3_DIVNP5_SHIFT,
> +
>   	/* CRU_CLK_SEL46_CON */
>   	UART5_PLL_SEL_SHIFT	= 14,
>   	UART5_PLL_SEL_MASK	= 3 << UART5_PLL_SEL_SHIFT,
> diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig
> index 109a37be15ad..167517bbd63f 100644
> --- a/arch/arm/mach-rockchip/px30/Kconfig
> +++ b/arch/arm/mach-rockchip/px30/Kconfig
> @@ -36,6 +36,15 @@ config DEBUG_UART2_CHANNEL
>   	  For using the UART for early debugging the route to use needs
>   	  to be declared (0 or 1).
>   
> +config DEBUG_UART3_CHANNEL
> +	int "Mux channel to use for debug UART3"
> +	depends on DEBUG_UART_BOARD_INIT
> +	default 0
> +	help
> +	  UART3 can use two different set of pins to route the output.
> +	  For using the UART for early debugging the route to use needs
> +	  to be declared (0 or 1).
> +
>   source "board/rockchip/evb_px30/Kconfig"
>   
>   endif
> diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c
> index bacdcc0b938d..6b12f4f6a502 100644
> --- a/arch/arm/mach-rockchip/px30/px30.c
> +++ b/arch/arm/mach-rockchip/px30/px30.c
> @@ -37,6 +37,7 @@ static struct mm_region px30_mem_map[] = {
>   struct mm_region *mem_map = px30_mem_map;
>   
>   #define PMU_PWRDN_CON			0xff000018
> +#define PMUGRF_BASE			0xff010000
>   #define GRF_BASE			0xff140000
>   #define CRU_BASE			0xff2b0000
>   #define VIDEO_PHY_BASE			0xff2e0000
> @@ -49,6 +50,23 @@ struct mm_region *mem_map = px30_mem_map;
>   
>   #define QOS_PRIORITY_LEVEL(h, l)	((((h) & 3) << 8) | ((l) & 3))
>   
> +/* GRF_GPIO1BH_IOMUX */
> +enum {
> +	GPIO1B7_SHIFT		= 12,
> +	GPIO1B7_MASK		= 0xf << GPIO1B7_SHIFT,
> +	GPIO1B7_GPIO		= 0,
> +	GPIO1B7_FLASH_RDN,
> +	GPIO1B7_UART3_RXM1,
> +	GPIO1B7_SPI0_CLK,
> +
> +	GPIO1B6_SHIFT		= 8,
> +	GPIO1B6_MASK		= 0xf << GPIO1B6_SHIFT,
> +	GPIO1B6_GPIO		= 0,
> +	GPIO1B6_FLASH_CS1,
> +	GPIO1B6_UART3_TXM1,
> +	GPIO1B6_SPI0_CSN,
> +};
> +
>   /* GRF_GPIO1CL_IOMUX */
>   enum {
>   	GPIO1C1_SHIFT		= 4,
> @@ -128,6 +146,23 @@ enum {
>   	GPIO3A1_UART5_RX	= 4,
>   };
>   
> +/* PMUGRF_GPIO0CL_IOMUX */
> +enum {
> +	GPIO0C1_SHIFT		= 2,
> +	GPIO0C1_MASK		= 0x3 << GPIO0C1_SHIFT,
> +	GPIO0C1_GPIO		= 0,
> +	GPIO0C1_PWM_3,
> +	GPIO0C1_UART3_RXM0,
> +	GPIO0C1_PMU_DEBUG4,
> +
> +	GPIO0C0_SHIFT		= 0,
> +	GPIO0C0_MASK		= 0x3 << GPIO0C0_SHIFT,
> +	GPIO0C0_GPIO		= 0,
> +	GPIO0C0_PWM_1,
> +	GPIO0C0_UART3_TXM0,
> +	GPIO0C0_PMU_DEBUG3,
> +};
> +
>   int arch_cpu_init(void)
>   {
>   	static struct px30_grf * const grf = (void *)GRF_BASE;
> @@ -175,6 +210,11 @@ int arch_cpu_init(void)
>   #ifdef CONFIG_DEBUG_UART_BOARD_INIT
>   void board_debug_uart_init(void)
>   {
> +#if defined(CONFIG_DEBUG_UART_BASE) && \
> +	(CONFIG_DEBUG_UART_BASE == 0xff168000) && \
> +	(CONFIG_DEBUG_UART3_CHANNEL != 1)
> +	static struct px30_pmugrf * const pmugrf = (void *)PMUGRF_BASE;
> +#endif
>   	static struct px30_grf * const grf = (void *)GRF_BASE;
>   	static struct px30_cru * const cru = (void *)CRU_BASE;
>   
> @@ -191,6 +231,43 @@ void board_debug_uart_init(void)
>   		     GPIO1C1_MASK | GPIO1C0_MASK,
>   		     GPIO1C1_UART1_TX << GPIO1C1_SHIFT |
>   		     GPIO1C0_UART1_RX << GPIO1C0_SHIFT);
> +#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff168000)
> +	/* GRF_IOFUNC_CON0 */
> +	enum {
> +		CON_IOMUX_UART3SEL_SHIFT	= 9,
> +		CON_IOMUX_UART3SEL_MASK = 1 << CON_IOMUX_UART3SEL_SHIFT,
> +		CON_IOMUX_UART3SEL_M0	= 0,
> +		CON_IOMUX_UART3SEL_M1,
> +	};
> +
> +	/* uart_sel_clk default select 24MHz */
> +	rk_clrsetreg(&cru->clksel_con[40],
> +		     UART3_PLL_SEL_MASK | UART3_DIV_CON_MASK,
> +		     UART3_PLL_SEL_24M << UART3_PLL_SEL_SHIFT | 0);
> +	rk_clrsetreg(&cru->clksel_con[41],
> +		     UART3_CLK_SEL_MASK,
> +		     UART3_CLK_SEL_UART3 << UART3_CLK_SEL_SHIFT);
> +
> +#if (CONFIG_DEBUG_UART3_CHANNEL == 1)
> +	rk_clrsetreg(&grf->iofunc_con0,
> +		     CON_IOMUX_UART3SEL_MASK,
> +		     CON_IOMUX_UART3SEL_M1 << CON_IOMUX_UART3SEL_SHIFT);
> +
> +	rk_clrsetreg(&grf->gpio1bh_iomux,
> +		     GPIO1B7_MASK | GPIO1B6_MASK,
> +		     GPIO1B7_UART3_RXM1 << GPIO1B7_SHIFT |
> +		     GPIO1B6_UART3_TXM1 << GPIO1B6_SHIFT);
> +#else
> +	rk_clrsetreg(&grf->iofunc_con0,
> +		     CON_IOMUX_UART3SEL_MASK,
> +		     CON_IOMUX_UART3SEL_M0 << CON_IOMUX_UART3SEL_SHIFT);
> +
> +	rk_clrsetreg(&pmugrf->gpio0cl_iomux,
> +		     GPIO0C1_MASK | GPIO0C0_MASK,
> +		     GPIO0C1_UART3_RXM0 << GPIO0C1_SHIFT |
> +		     GPIO0C0_UART3_TXM0 << GPIO0C0_SHIFT);
> +#endif /* CONFIG_DEBUG_UART3_CHANNEL == 1 */
> +
>   #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff178000)
>   	/* uart_sel_clk default select 24MHz */
>   	rk_clrsetreg(&cru->clksel_con[46],

[U-Boot] [PATCH 1/2] rockchip: px30: Fixup PMUGRF registers layout order

[Heiko Stuebner]

On 27.11.19 11:12, Paul Kocialkowski wrote:
> According to the PX30 TRM, the iomux registers come first, before the pull
> and strength control registers.
>
> Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>

Reviewed-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>

Thanks for that catch
Heiko

[U-Boot] [PATCH 2/2] rockchip: px30: Add support for using UART3 as debug UART

[Heiko Stuebner]

On 27.11.19 11:12, Paul Kocialkowski wrote:
> Some generic PX30 SoMs found in the wild use UART3 as their debug output
> instead of UART2 (used for MMC) and UART5.
>
> Make it possible to use UART3 as early debug output, with the associated
> clock and pinmux configuration. Two sets of output pins are supported (M0/M1)
> so a Kconfig option to select between the two is introduced like it's done
> for UART2.
>
> Future users should also note that the pinmux default in the dts is to use
> the M1 pins while the Kconfig option takes M0 as a default.
>
> Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>

Reviewed-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>

with one small question below

> diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig
> index 109a37be15ad..167517bbd63f 100644
> --- a/arch/arm/mach-rockchip/px30/Kconfig
> +++ b/arch/arm/mach-rockchip/px30/Kconfig
> @@ -36,6 +36,15 @@ config DEBUG_UART2_CHANNEL
>   	  For using the UART for early debugging the route to use needs
>   	  to be declared (0 or 1).
>   
> +config DEBUG_UART3_CHANNEL
> +	int "Mux channel to use for debug UART3"
> +	depends on DEBUG_UART_BOARD_INIT
> +	default 0
> +	help
> +	  UART3 can use two different set of pins to route the output.
> +	  For using the UART for early debugging the route to use needs
> +	  to be declared (0 or 1).
> +
>   source "board/rockchip/evb_px30/Kconfig"

Would it make sense to rename DEBUG_UART3_CHANNEL to just
DEBUG_UART_CHANNEL and reuse it, so that we don't collect similar
options for each uart?

Heiko

[U-Boot] [PATCH 2/2] rockchip: px30: Add support for using UART3 as debug UART

[Philipp Tomsich]

Heiko,

> On 28.11.2019, at 10:44, Heiko Stuebner <heiko.stuebner@theobroma-systems.com> wrote:
> 
> On 27.11.19 11:12, Paul Kocialkowski wrote:
>> Some generic PX30 SoMs found in the wild use UART3 as their debug output
>> instead of UART2 (used for MMC) and UART5.
>> 
>> Make it possible to use UART3 as early debug output, with the associated
>> clock and pinmux configuration. Two sets of output pins are supported (M0/M1)
>> so a Kconfig option to select between the two is introduced like it's done
>> for UART2.
>> 
>> Future users should also note that the pinmux default in the dts is to use
>> the M1 pins while the Kconfig option takes M0 as a default.
>> 
>> Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
> 
> Reviewed-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> 
> with one small question below
> 
>> diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig
>> index 109a37be15ad..167517bbd63f 100644
>> --- a/arch/arm/mach-rockchip/px30/Kconfig
>> +++ b/arch/arm/mach-rockchip/px30/Kconfig
>> @@ -36,6 +36,15 @@ config DEBUG_UART2_CHANNEL
>>  	  For using the UART for early debugging the route to use needs
>>  	  to be declared (0 or 1).
>>  +config DEBUG_UART3_CHANNEL
>> +	int "Mux channel to use for debug UART3"
>> +	depends on DEBUG_UART_BOARD_INIT
>> +	default 0
>> +	help
>> +	  UART3 can use two different set of pins to route the output.
>> +	  For using the UART for early debugging the route to use needs
>> +	  to be declared (0 or 1).
>> +
>>  source "board/rockchip/evb_px30/Kconfig"
> 
> Would it make sense to rename DEBUG_UART3_CHANNEL to just
> DEBUG_UART_CHANNEL and reuse it, so that we don't collect similar
> options for each uart?

Let me also check what we use on the Jaguar platform, as that will be
our baseline platform for PX30 support for TSD boards...

Thanks,
Philipp.

[U-Boot] [PATCH 2/2] rockchip: px30: Add support for using UART3 as debug UART

[Paul Kocialkowski]

Hi Heiko,

On Thu 28 Nov 19, 10:44, Heiko Stuebner wrote:
> On 27.11.19 11:12, Paul Kocialkowski wrote:
> > Some generic PX30 SoMs found in the wild use UART3 as their debug output
> > instead of UART2 (used for MMC) and UART5.
> > 
> > Make it possible to use UART3 as early debug output, with the associated
> > clock and pinmux configuration. Two sets of output pins are supported (M0/M1)
> > so a Kconfig option to select between the two is introduced like it's done
> > for UART2.
> > 
> > Future users should also note that the pinmux default in the dts is to use
> > the M1 pins while the Kconfig option takes M0 as a default.
> > 
> > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
> 
> Reviewed-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> 
> with one small question below
> 
> > diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig
> > index 109a37be15ad..167517bbd63f 100644
> > --- a/arch/arm/mach-rockchip/px30/Kconfig
> > +++ b/arch/arm/mach-rockchip/px30/Kconfig
> > @@ -36,6 +36,15 @@ config DEBUG_UART2_CHANNEL
> >   	  For using the UART for early debugging the route to use needs
> >   	  to be declared (0 or 1).
> > +config DEBUG_UART3_CHANNEL
> > +	int "Mux channel to use for debug UART3"
> > +	depends on DEBUG_UART_BOARD_INIT
> > +	default 0
> > +	help
> > +	  UART3 can use two different set of pins to route the output.
> > +	  For using the UART for early debugging the route to use needs
> > +	  to be declared (0 or 1).
> > +
> >   source "board/rockchip/evb_px30/Kconfig"
> 
> Would it make sense to rename DEBUG_UART3_CHANNEL to just
> DEBUG_UART_CHANNEL and reuse it, so that we don't collect similar
> options for each uart?

Yes I like that better too. Will craft a v2 with that.

And thanks for the review!

Cheers,

Paul

-- 
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com
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