* [PATCH 0/2] ppc/pnv: HOMER fixes and improvements
@ 2019-12-11 8:29 Cédric Le Goater
2019-12-11 8:29 ` [PATCH 1/2] ppc/pnv: Introduce PBA registers Cédric Le Goater
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Cédric Le Goater @ 2019-12-11 8:29 UTC (permalink / raw)
To: David Gibson
Cc: qemu-devel, Cédric Le Goater, qemu-ppc, Greg Kurz, bala24
Hello,
The first patch introduces a new XSCOM region for the PBA bridge unit
(Power Bus Access) which connects the OCC (On Chip Controller) to the
Power bus and System Memory. The PBA is used to gather sensor data,
for power management, for sleep states, for initial boot, among other
things. This first patch also fixes :
- BAR sizes and BAR masks
- The mapping of the OCC common area, which is common to all chips
and should be mapped once.
- OCC common area is in BAR 3 on P8
and more globally, it fixes multichip support which is currently
broken because of wrong mappings.
The OCC common area is mapped at a unique address on the system and
each OCC is assigned a segment to expose its sensor data. This is
fixed in the second patch.
Thanks,
C.
Cédric Le Goater (2):
ppc/pnv: Introduce PBA registers
ppc/pnv: Fix OCC common area region mapping
include/hw/ppc/pnv.h | 20 +++----
include/hw/ppc/pnv_homer.h | 3 +
include/hw/ppc/pnv_occ.h | 8 ++-
include/hw/ppc/pnv_xscom.h | 6 ++
hw/ppc/pnv.c | 12 +++-
hw/ppc/pnv_homer.c | 109 +++++++++++++++++++++++++++++++++++++
hw/ppc/pnv_occ.c | 11 ++--
hw/ppc/pnv_xscom.c | 32 -----------
8 files changed, 148 insertions(+), 53 deletions(-)
--
2.21.0
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/2] ppc/pnv: Introduce PBA registers
2019-12-11 8:29 [PATCH 0/2] ppc/pnv: HOMER fixes and improvements Cédric Le Goater
@ 2019-12-11 8:29 ` Cédric Le Goater
2019-12-11 8:29 ` [PATCH 2/2] ppc/pnv: Fix OCC common area region mapping Cédric Le Goater
2019-12-12 5:11 ` [PATCH 0/2] ppc/pnv: HOMER fixes and improvements David Gibson
2 siblings, 0 replies; 4+ messages in thread
From: Cédric Le Goater @ 2019-12-11 8:29 UTC (permalink / raw)
To: David Gibson
Cc: qemu-devel, Cédric Le Goater, qemu-ppc, Greg Kurz, bala24
The PBA bridge unit (Power Bus Access) connects the OCC (On Chip
Controller) to the Power bus and System Memory. The PBA is used to
gather sensor data, for power management, for sleep states, for
initial boot, among other things.
The PBA logic provides a set of four registers PowerBus Access Base
Address Registers (PBABAR0..3) which map the OCC address space to the
PowerBus space. These registers are setup by the initial FW and define
the PowerBus Range of system memory that can be accessed by PBA.
The current modeling of the PBABAR registers is done under the common
XSCOM handlers. We introduce a specific XSCOM regions for these
registers and fix :
- BAR sizes and BAR masks
- The mapping of the OCC common area. It is common to all chips and
should be mapped once. We will address per-OCC area in the next
change.
- OCC common area is in BAR 3 on P8
Inspired by previous work of Balamuruhan S <bala24@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/pnv.h | 16 ++----
include/hw/ppc/pnv_homer.h | 3 +
include/hw/ppc/pnv_xscom.h | 6 ++
hw/ppc/pnv.c | 12 +++-
hw/ppc/pnv_homer.c | 109 +++++++++++++++++++++++++++++++++++++
hw/ppc/pnv_xscom.c | 32 -----------
6 files changed, 134 insertions(+), 44 deletions(-)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 56d1161515dd..301c7e62fa73 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -244,12 +244,10 @@ IPMIBmc *pnv_bmc_create(void);
#define PNV_XSCOM_BASE(chip) \
(0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE)
-#define PNV_OCC_COMMON_AREA_SIZE 0x0000000000700000ull
-#define PNV_OCC_COMMON_AREA(chip) \
- (0x7fff800000ull + ((uint64_t)PNV_CHIP_INDEX(chip) * \
- PNV_OCC_COMMON_AREA_SIZE))
+#define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
+#define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull
-#define PNV_HOMER_SIZE 0x0000000000300000ull
+#define PNV_HOMER_SIZE 0x0000000000400000ull
#define PNV_HOMER_BASE(chip) \
(0x7ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV_HOMER_SIZE)
@@ -312,12 +310,10 @@ IPMIBmc *pnv_bmc_create(void);
#define PNV9_XSCOM_SIZE 0x0000000400000000ull
#define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull)
-#define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000700000ull
-#define PNV9_OCC_COMMON_AREA(chip) \
- (0x203fff800000ull + ((uint64_t)PNV_CHIP_INDEX(chip) * \
- PNV9_OCC_COMMON_AREA_SIZE))
+#define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
+#define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull
-#define PNV9_HOMER_SIZE 0x0000000000300000ull
+#define PNV9_HOMER_SIZE 0x0000000000400000ull
#define PNV9_HOMER_BASE(chip) \
(0x203ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV9_HOMER_SIZE)
diff --git a/include/hw/ppc/pnv_homer.h b/include/hw/ppc/pnv_homer.h
index abaec43c2d62..1e91c950f691 100644
--- a/include/hw/ppc/pnv_homer.h
+++ b/include/hw/ppc/pnv_homer.h
@@ -33,6 +33,7 @@ typedef struct PnvHomer {
DeviceState parent;
struct PnvChip *chip;
+ MemoryRegion pba_regs;
MemoryRegion regs;
} PnvHomer;
@@ -44,6 +45,8 @@ typedef struct PnvHomer {
typedef struct PnvHomerClass {
DeviceClass parent_class;
+ int pba_size;
+ const MemoryRegionOps *pba_ops;
int homer_size;
const MemoryRegionOps *homer_ops;
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index a40d2a2a2a98..97b091afbe71 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -70,6 +70,9 @@ typedef struct PnvXScomInterfaceClass {
#define PNV_XSCOM_OCC_BASE 0x0066000
#define PNV_XSCOM_OCC_SIZE 0x6000
+#define PNV_XSCOM_PBA_BASE 0x2013f00
+#define PNV_XSCOM_PBA_SIZE 0x40
+
/*
* Layout of the XSCOM PCB addresses (POWER 9)
*/
@@ -84,6 +87,9 @@ typedef struct PnvXScomInterfaceClass {
#define PNV9_XSCOM_OCC_BASE PNV_XSCOM_OCC_BASE
#define PNV9_XSCOM_OCC_SIZE 0x8000
+#define PNV9_XSCOM_PBA_BASE 0x5012b00
+#define PNV9_XSCOM_PBA_SIZE 0x40
+
#define PNV9_XSCOM_PSIHB_BASE 0x5012900
#define PNV9_XSCOM_PSIHB_SIZE 0x100
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 67d0ad55b870..af7317a86d2f 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1065,7 +1065,7 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
/* OCC SRAM model */
- memory_region_add_subregion(get_system_memory(), PNV_OCC_COMMON_AREA(chip),
+ memory_region_add_subregion(get_system_memory(), PNV_OCC_COMMON_AREA_BASE,
&chip8->occ.sram_regs);
/* HOMER */
@@ -1077,6 +1077,10 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
error_propagate(errp, local_err);
return;
}
+ /* Homer Xscom region */
+ pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs);
+
+ /* Homer mmio region */
memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
&chip8->homer.regs);
}
@@ -1274,7 +1278,7 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
/* OCC SRAM model */
- memory_region_add_subregion(get_system_memory(), PNV9_OCC_COMMON_AREA(chip),
+ memory_region_add_subregion(get_system_memory(), PNV9_OCC_COMMON_AREA_BASE,
&chip9->occ.sram_regs);
/* HOMER */
@@ -1286,6 +1290,10 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
error_propagate(errp, local_err);
return;
}
+ /* Homer Xscom region */
+ pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs);
+
+ /* Homer mmio region */
memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip),
&chip9->homer.regs);
}
diff --git a/hw/ppc/pnv_homer.c b/hw/ppc/pnv_homer.c
index 994a378108da..a08b7914f746 100644
--- a/hw/ppc/pnv_homer.c
+++ b/hw/ppc/pnv_homer.c
@@ -17,6 +17,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/log.h"
#include "qapi/error.h"
#include "exec/hwaddr.h"
#include "exec/memory.h"
@@ -25,6 +26,7 @@
#include "hw/qdev-properties.h"
#include "hw/ppc/pnv.h"
#include "hw/ppc/pnv_homer.h"
+#include "hw/ppc/pnv_xscom.h"
static bool core_max_array(PnvHomer *homer, hwaddr addr)
@@ -114,10 +116,67 @@ static const MemoryRegionOps pnv_power8_homer_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
+/* P8 PBA BARs */
+#define PBA_BAR0 0x00
+#define PBA_BAR1 0x01
+#define PBA_BAR2 0x02
+#define PBA_BAR3 0x03
+#define PBA_BARMASK0 0x04
+#define PBA_BARMASK1 0x05
+#define PBA_BARMASK2 0x06
+#define PBA_BARMASK3 0x07
+
+static uint64_t pnv_homer_power8_pba_read(void *opaque, hwaddr addr,
+ unsigned size)
+{
+ PnvHomer *homer = PNV_HOMER(opaque);
+ PnvChip *chip = homer->chip;
+ uint32_t reg = addr >> 3;
+ uint64_t val = 0;
+
+ switch (reg) {
+ case PBA_BAR0:
+ val = PNV_HOMER_BASE(chip);
+ break;
+ case PBA_BARMASK0: /* P8 homer region mask */
+ val = (PNV_HOMER_SIZE - 1) & 0x300000;
+ break;
+ case PBA_BAR3: /* P8 occ common area */
+ val = PNV_OCC_COMMON_AREA_BASE;
+ break;
+ case PBA_BARMASK3: /* P8 occ common area mask */
+ val = (PNV_OCC_COMMON_AREA_SIZE - 1) & 0x700000;
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "PBA: read to unimplemented register: Ox%"
+ HWADDR_PRIx "\n", addr >> 3);
+ }
+ return val;
+}
+
+static void pnv_homer_power8_pba_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+ qemu_log_mask(LOG_UNIMP, "PBA: write to unimplemented register: Ox%"
+ HWADDR_PRIx "\n", addr >> 3);
+}
+
+static const MemoryRegionOps pnv_homer_power8_pba_ops = {
+ .read = pnv_homer_power8_pba_read,
+ .write = pnv_homer_power8_pba_write,
+ .valid.min_access_size = 8,
+ .valid.max_access_size = 8,
+ .impl.min_access_size = 8,
+ .impl.max_access_size = 8,
+ .endianness = DEVICE_BIG_ENDIAN,
+};
+
static void pnv_homer_power8_class_init(ObjectClass *klass, void *data)
{
PnvHomerClass *homer = PNV_HOMER_CLASS(klass);
+ homer->pba_size = PNV_XSCOM_PBA_SIZE;
+ homer->pba_ops = &pnv_homer_power8_pba_ops;
homer->homer_size = PNV_HOMER_SIZE;
homer->homer_ops = &pnv_power8_homer_ops;
homer->core_max_base = PNV8_CORE_MAX_BASE;
@@ -210,10 +269,57 @@ static const MemoryRegionOps pnv_power9_homer_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
+static uint64_t pnv_homer_power9_pba_read(void *opaque, hwaddr addr,
+ unsigned size)
+{
+ PnvHomer *homer = PNV_HOMER(opaque);
+ PnvChip *chip = homer->chip;
+ uint32_t reg = addr >> 3;
+ uint64_t val = 0;
+
+ switch (reg) {
+ case PBA_BAR0:
+ val = PNV9_HOMER_BASE(chip);
+ break;
+ case PBA_BARMASK0: /* P9 homer region mask */
+ val = (PNV9_HOMER_SIZE - 1) & 0x300000;
+ break;
+ case PBA_BAR2: /* P9 occ common area */
+ val = PNV9_OCC_COMMON_AREA_BASE;
+ break;
+ case PBA_BARMASK2: /* P9 occ common area size */
+ val = (PNV9_OCC_COMMON_AREA_SIZE - 1) & 0x700000;
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "PBA: read to unimplemented register: Ox%"
+ HWADDR_PRIx "\n", addr >> 3);
+ }
+ return val;
+}
+
+static void pnv_homer_power9_pba_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+ qemu_log_mask(LOG_UNIMP, "PBA: write to unimplemented register: Ox%"
+ HWADDR_PRIx "\n", addr >> 3);
+}
+
+static const MemoryRegionOps pnv_homer_power9_pba_ops = {
+ .read = pnv_homer_power9_pba_read,
+ .write = pnv_homer_power9_pba_write,
+ .valid.min_access_size = 8,
+ .valid.max_access_size = 8,
+ .impl.min_access_size = 8,
+ .impl.max_access_size = 8,
+ .endianness = DEVICE_BIG_ENDIAN,
+};
+
static void pnv_homer_power9_class_init(ObjectClass *klass, void *data)
{
PnvHomerClass *homer = PNV_HOMER_CLASS(klass);
+ homer->pba_size = PNV9_XSCOM_PBA_SIZE;
+ homer->pba_ops = &pnv_homer_power9_pba_ops;
homer->homer_size = PNV9_HOMER_SIZE;
homer->homer_ops = &pnv_power9_homer_ops;
homer->core_max_base = PNV9_CORE_MAX_BASE;
@@ -233,6 +339,9 @@ static void pnv_homer_realize(DeviceState *dev, Error **errp)
assert(homer->chip);
+ pnv_xscom_region_init(&homer->pba_regs, OBJECT(dev), hmrc->pba_ops,
+ homer, "xscom-pba", hmrc->pba_size);
+
/* homer region */
memory_region_init_io(&homer->regs, OBJECT(dev),
hmrc->homer_ops, homer, "homer-main-memory",
diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c
index 277f65adeb87..6d3745a49e50 100644
--- a/hw/ppc/pnv_xscom.c
+++ b/hw/ppc/pnv_xscom.c
@@ -36,16 +36,6 @@
#define PRD_P9_IPOLL_REG_MASK 0x000F0033
#define PRD_P9_IPOLL_REG_STATUS 0x000F0034
-/* PBA BARs */
-#define P8_PBA_BAR0 0x2013f00
-#define P8_PBA_BAR2 0x2013f02
-#define P8_PBA_BARMASK0 0x2013f04
-#define P8_PBA_BARMASK2 0x2013f06
-#define P9_PBA_BAR0 0x5012b00
-#define P9_PBA_BAR2 0x5012b02
-#define P9_PBA_BARMASK0 0x5012b04
-#define P9_PBA_BARMASK2 0x5012b06
-
static void xscom_complete(CPUState *cs, uint64_t hmer_bits)
{
/*
@@ -90,26 +80,6 @@ static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba)
case 0x18002: /* ECID2 */
return 0;
- case P9_PBA_BAR0:
- return PNV9_HOMER_BASE(chip);
- case P8_PBA_BAR0:
- return PNV_HOMER_BASE(chip);
-
- case P9_PBA_BARMASK0: /* P9 homer region size */
- return PNV9_HOMER_SIZE;
- case P8_PBA_BARMASK0: /* P8 homer region size */
- return PNV_HOMER_SIZE;
-
- case P9_PBA_BAR2: /* P9 occ common area */
- return PNV9_OCC_COMMON_AREA(chip);
- case P8_PBA_BAR2: /* P8 occ common area */
- return PNV_OCC_COMMON_AREA(chip);
-
- case P9_PBA_BARMASK2: /* P9 occ common area size */
- return PNV9_OCC_COMMON_AREA_SIZE;
- case P8_PBA_BARMASK2: /* P8 occ common area size */
- return PNV_OCC_COMMON_AREA_SIZE;
-
case 0x1010c00: /* PIBAM FIR */
case 0x1010c03: /* PIBAM FIR MASK */
@@ -130,9 +100,7 @@ static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba)
case 0x202000f: /* ADU stuff, receive status register*/
return 0;
case 0x2013f01: /* PBA stuff */
- case 0x2013f03: /* PBA stuff */
case 0x2013f05: /* PBA stuff */
- case 0x2013f07: /* PBA stuff */
return 0;
case 0x2013028: /* CAPP stuff */
case 0x201302a: /* CAPP stuff */
--
2.21.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] ppc/pnv: Fix OCC common area region mapping
2019-12-11 8:29 [PATCH 0/2] ppc/pnv: HOMER fixes and improvements Cédric Le Goater
2019-12-11 8:29 ` [PATCH 1/2] ppc/pnv: Introduce PBA registers Cédric Le Goater
@ 2019-12-11 8:29 ` Cédric Le Goater
2019-12-12 5:11 ` [PATCH 0/2] ppc/pnv: HOMER fixes and improvements David Gibson
2 siblings, 0 replies; 4+ messages in thread
From: Cédric Le Goater @ 2019-12-11 8:29 UTC (permalink / raw)
To: David Gibson
Cc: qemu-devel, Cédric Le Goater, qemu-ppc, Greg Kurz, bala24
The OCC common area is mapped at a unique address on the system and
each OCC is assigned a segment to expose its sensor data :
-------------------------------------------------------------------------
| Start (Offset from | End | Size |Description |
| BAR2 base address) | | | |
-------------------------------------------------------------------------
| 0x00580000 | 0x005A57FF |150kB |OCC 0 Sensor Data Block|
| 0x005A5800 | 0x005CAFFF |150kB |OCC 1 Sensor Data Block|
| : | : | : | : |
| 0x00686800 | 0x006ABFFF |150kB |OCC 7 Sensor Data Block|
| 0x006AC000 | 0x006FFFFF |336kB |Reserved |
-------------------------------------------------------------------------
Maximum size is 1.5MB.
We could define a "OCC common area" memory region at the machine level
and sub regions for each OCC. But it adds some extra complexity to the
models. Fix the current layout with a simpler model.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/pnv.h | 4 ++++
include/hw/ppc/pnv_occ.h | 8 ++++++--
hw/ppc/pnv.c | 4 ++--
hw/ppc/pnv_occ.c | 11 ++++-------
4 files changed, 16 insertions(+), 11 deletions(-)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 301c7e62fa73..92f80b1ccead 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -246,6 +246,8 @@ IPMIBmc *pnv_bmc_create(void);
#define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
#define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull
+#define PNV_OCC_SENSOR_BASE(chip) (PNV_OCC_COMMON_AREA_BASE + \
+ PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip)))
#define PNV_HOMER_SIZE 0x0000000000400000ull
#define PNV_HOMER_BASE(chip) \
@@ -312,6 +314,8 @@ IPMIBmc *pnv_bmc_create(void);
#define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
#define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull
+#define PNV9_OCC_SENSOR_BASE(chip) (PNV9_OCC_COMMON_AREA_BASE + \
+ PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip)))
#define PNV9_HOMER_SIZE 0x0000000000400000ull
#define PNV9_HOMER_BASE(chip) \
diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h
index 66b0989be69d..f8d3061419dc 100644
--- a/include/hw/ppc/pnv_occ.h
+++ b/include/hw/ppc/pnv_occ.h
@@ -29,6 +29,9 @@
#define TYPE_PNV9_OCC TYPE_PNV_OCC "-POWER9"
#define PNV9_OCC(obj) OBJECT_CHECK(PnvOCC, (obj), TYPE_PNV9_OCC)
+#define PNV_OCC_SENSOR_DATA_BLOCK_OFFSET 0x00580000
+#define PNV_OCC_SENSOR_DATA_BLOCK_SIZE 0x00025800
+
typedef struct PnvOCC {
DeviceState xd;
@@ -50,10 +53,11 @@ typedef struct PnvOCCClass {
DeviceClass parent_class;
int xscom_size;
- int sram_size;
const MemoryRegionOps *xscom_ops;
- const MemoryRegionOps *sram_ops;
int psi_irq;
} PnvOCCClass;
+#define PNV_OCC_SENSOR_DATA_BLOCK_BASE(i) \
+ (PNV_OCC_SENSOR_DATA_BLOCK_OFFSET + (i) * PNV_OCC_SENSOR_DATA_BLOCK_SIZE)
+
#endif /* PPC_PNV_OCC_H */
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index af7317a86d2f..0be0b6b411c3 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1065,7 +1065,7 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
/* OCC SRAM model */
- memory_region_add_subregion(get_system_memory(), PNV_OCC_COMMON_AREA_BASE,
+ memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
&chip8->occ.sram_regs);
/* HOMER */
@@ -1278,7 +1278,7 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
/* OCC SRAM model */
- memory_region_add_subregion(get_system_memory(), PNV9_OCC_COMMON_AREA_BASE,
+ memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
&chip9->occ.sram_regs);
/* HOMER */
diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c
index 765c0a6ce595..924fdabc9e63 100644
--- a/hw/ppc/pnv_occ.c
+++ b/hw/ppc/pnv_occ.c
@@ -167,9 +167,7 @@ static void pnv_occ_power8_class_init(ObjectClass *klass, void *data)
PnvOCCClass *poc = PNV_OCC_CLASS(klass);
poc->xscom_size = PNV_XSCOM_OCC_SIZE;
- poc->sram_size = PNV_OCC_COMMON_AREA_SIZE;
poc->xscom_ops = &pnv_occ_power8_xscom_ops;
- poc->sram_ops = &pnv_occ_sram_ops;
poc->psi_irq = PSIHB_IRQ_OCC;
}
@@ -240,9 +238,7 @@ static void pnv_occ_power9_class_init(ObjectClass *klass, void *data)
PnvOCCClass *poc = PNV_OCC_CLASS(klass);
poc->xscom_size = PNV9_XSCOM_OCC_SIZE;
- poc->sram_size = PNV9_OCC_COMMON_AREA_SIZE;
poc->xscom_ops = &pnv_occ_power9_xscom_ops;
- poc->sram_ops = &pnv_occ_sram_ops;
poc->psi_irq = PSIHB9_IRQ_OCC;
}
@@ -266,9 +262,10 @@ static void pnv_occ_realize(DeviceState *dev, Error **errp)
pnv_xscom_region_init(&occ->xscom_regs, OBJECT(dev), poc->xscom_ops,
occ, "xscom-occ", poc->xscom_size);
- /* XScom region for OCC SRAM registers */
- pnv_xscom_region_init(&occ->sram_regs, OBJECT(dev), poc->sram_ops,
- occ, "occ-common-area", poc->sram_size);
+ /* OCC common area mmio region for OCC SRAM registers */
+ memory_region_init_io(&occ->sram_regs, OBJECT(dev), &pnv_occ_sram_ops,
+ occ, "occ-common-area",
+ PNV_OCC_SENSOR_DATA_BLOCK_SIZE);
}
static Property pnv_occ_properties[] = {
--
2.21.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 0/2] ppc/pnv: HOMER fixes and improvements
2019-12-11 8:29 [PATCH 0/2] ppc/pnv: HOMER fixes and improvements Cédric Le Goater
2019-12-11 8:29 ` [PATCH 1/2] ppc/pnv: Introduce PBA registers Cédric Le Goater
2019-12-11 8:29 ` [PATCH 2/2] ppc/pnv: Fix OCC common area region mapping Cédric Le Goater
@ 2019-12-12 5:11 ` David Gibson
2 siblings, 0 replies; 4+ messages in thread
From: David Gibson @ 2019-12-12 5:11 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-devel, qemu-ppc, Greg Kurz, bala24
[-- Attachment #1: Type: text/plain, Size: 1681 bytes --]
On Wed, Dec 11, 2019 at 09:29:10AM +0100, Cédric Le Goater wrote:
> Hello,
>
> The first patch introduces a new XSCOM region for the PBA bridge unit
> (Power Bus Access) which connects the OCC (On Chip Controller) to the
> Power bus and System Memory. The PBA is used to gather sensor data,
> for power management, for sleep states, for initial boot, among other
> things. This first patch also fixes :
>
> - BAR sizes and BAR masks
> - The mapping of the OCC common area, which is common to all chips
> and should be mapped once.
> - OCC common area is in BAR 3 on P8
>
> and more globally, it fixes multichip support which is currently
> broken because of wrong mappings.
>
> The OCC common area is mapped at a unique address on the system and
> each OCC is assigned a segment to expose its sensor data. This is
> fixed in the second patch.
>
> Thanks,
Applied to ppc-for-5.0.
>
> C.
>
> Cédric Le Goater (2):
> ppc/pnv: Introduce PBA registers
> ppc/pnv: Fix OCC common area region mapping
>
> include/hw/ppc/pnv.h | 20 +++----
> include/hw/ppc/pnv_homer.h | 3 +
> include/hw/ppc/pnv_occ.h | 8 ++-
> include/hw/ppc/pnv_xscom.h | 6 ++
> hw/ppc/pnv.c | 12 +++-
> hw/ppc/pnv_homer.c | 109 +++++++++++++++++++++++++++++++++++++
> hw/ppc/pnv_occ.c | 11 ++--
> hw/ppc/pnv_xscom.c | 32 -----------
> 8 files changed, 148 insertions(+), 53 deletions(-)
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2019-12-12 5:14 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-12-11 8:29 [PATCH 0/2] ppc/pnv: HOMER fixes and improvements Cédric Le Goater
2019-12-11 8:29 ` [PATCH 1/2] ppc/pnv: Introduce PBA registers Cédric Le Goater
2019-12-11 8:29 ` [PATCH 2/2] ppc/pnv: Fix OCC common area region mapping Cédric Le Goater
2019-12-12 5:11 ` [PATCH 0/2] ppc/pnv: HOMER fixes and improvements David Gibson
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