* [Intel-gfx] [PATCH v2 0/6] drm/i915: Some cleanup near the SKL wm/ddb area
@ 2019-12-10 14:41 Ville Syrjala
2019-12-10 14:41 ` [Intel-gfx] [PATCH v2 1/4] drm/i915: Streamline skl_commit_modeset_enables() Ville Syrjala
` (7 more replies)
0 siblings, 8 replies; 10+ messages in thread
From: Ville Syrjala @ 2019-12-10 14:41 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Rebased leftovers from my earlier series to nuke the dirty_pipes junk.
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Ville Syrjälä (6):
drm/i915: Streamline skl_commit_modeset_enables()
drm/i915: Polish WM_LINETIME register stuff
drm/i915: Move linetime wms into the crtc state
drm/i915: Nuke skl wm.dirty_pipes bitmask
drm/i915: Kill struct skl_ddb_allocation
drm/i915: Implement pps w/a #1124 for bxt+
drivers/gpu/drm/i915/display/intel_display.c | 170 +++++++++++----
.../drm/i915/display/intel_display_power.c | 28 +--
.../drm/i915/display/intel_display_power.h | 2 +-
.../drm/i915/display/intel_display_types.h | 11 +-
drivers/gpu/drm/i915/display/intel_dp.c | 11 +
drivers/gpu/drm/i915/gvt/handlers.c | 6 +-
drivers/gpu/drm/i915/i915_drv.h | 14 +-
drivers/gpu/drm/i915/i915_reg.h | 14 +-
drivers/gpu/drm/i915/intel_pm.c | 202 +++---------------
drivers/gpu/drm/i915/intel_pm.h | 4 +-
10 files changed, 187 insertions(+), 275 deletions(-)
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH v2 1/4] drm/i915: Streamline skl_commit_modeset_enables()
2019-12-10 14:41 [Intel-gfx] [PATCH v2 0/6] drm/i915: Some cleanup near the SKL wm/ddb area Ville Syrjala
@ 2019-12-10 14:41 ` Ville Syrjala
2019-12-10 14:41 ` [Intel-gfx] [PATCH v2 2/4] drm/i915: Polish WM_LINETIME register stuff Ville Syrjala
` (6 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Ville Syrjala @ 2019-12-10 14:41 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
skl_commit_modeset_enables() is a bit of mess. Let's streamline
it by simply tracking which pipes still need to be updated.
As a bonus we get rid of the state->wm_results.dirty_pipes usage.
v2: Rebase due to port sync
Cc: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> #v1
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 48 +++++++++-----------
1 file changed, 21 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1d2fad1610ef..c1940954e304 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14553,17 +14553,19 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc *crtc;
struct intel_crtc_state *old_crtc_state, *new_crtc_state;
- unsigned int updated = 0;
- bool progress;
- int i;
u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
u8 required_slices = state->wm_results.ddb.enabled_slices;
struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
+ u8 dirty_pipes = 0;
+ int i;
- for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
/* ignore allocations for crtc's that have been turned off. */
if (!needs_modeset(new_crtc_state) && new_crtc_state->hw.active)
entries[i] = old_crtc_state->wm.skl.ddb;
+ if (new_crtc_state->hw.active)
+ dirty_pipes |= BIT(crtc->pipe);
+ }
/* If 2nd DBuf slice required, enable it here */
if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
@@ -14575,15 +14577,13 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
* never overlap with eachother inbetween CRTC updates. Otherwise we'll
* cause pipe underruns and other bad stuff.
*/
- do {
- progress = false;
-
- for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
+ while (dirty_pipes) {
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
enum pipe pipe = crtc->pipe;
- bool vbl_wait = false;
bool modeset = needs_modeset(new_crtc_state);
- if (updated & BIT(crtc->pipe) || !new_crtc_state->hw.active)
+ if ((dirty_pipes & BIT(pipe)) == 0)
continue;
if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
@@ -14591,20 +14591,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
INTEL_NUM_PIPES(dev_priv), i))
continue;
- updated |= BIT(pipe);
entries[i] = new_crtc_state->wm.skl.ddb;
-
- /*
- * If this is an already active pipe, it's DDB changed,
- * and this isn't the last pipe that needs updating
- * then we need to wait for a vblank to pass for the
- * new ddb allocation to take effect.
- */
- if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
- &old_crtc_state->wm.skl.ddb) &&
- !modeset &&
- state->wm_results.dirty_pipes != updated)
- vbl_wait = true;
+ dirty_pipes &= ~BIT(pipe);
if (modeset && is_trans_port_sync_mode(new_crtc_state)) {
if (is_trans_port_sync_master(new_crtc_state))
@@ -14619,12 +14607,18 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
new_crtc_state);
}
- if (vbl_wait)
+ /*
+ * If this is an already active pipe, it's DDB changed,
+ * and this isn't the last pipe that needs updating
+ * then we need to wait for a vblank to pass for the
+ * new ddb allocation to take effect.
+ */
+ if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
+ &old_crtc_state->wm.skl.ddb) &&
+ !modeset && dirty_pipes)
intel_wait_for_vblank(dev_priv, pipe);
-
- progress = true;
}
- } while (progress);
+ }
/* If 2nd DBuf slice is no more required disable it */
if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH v2 2/4] drm/i915: Polish WM_LINETIME register stuff
2019-12-10 14:41 [Intel-gfx] [PATCH v2 0/6] drm/i915: Some cleanup near the SKL wm/ddb area Ville Syrjala
2019-12-10 14:41 ` [Intel-gfx] [PATCH v2 1/4] drm/i915: Streamline skl_commit_modeset_enables() Ville Syrjala
@ 2019-12-10 14:41 ` Ville Syrjala
2019-12-10 14:41 ` [Intel-gfx] [PATCH v2 3/4] drm/i915: Move linetime wms into the crtc state Ville Syrjala
` (5 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Ville Syrjala @ 2019-12-10 14:41 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Let's store the normal and IPS linetime watermarks individually,
and while at it we'll pimp the register definitions as well.
v2: Deal with gvt
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../drm/i915/display/intel_display_types.h | 3 +-
drivers/gpu/drm/i915/gvt/handlers.c | 6 +-
drivers/gpu/drm/i915/i915_reg.h | 14 ++--
drivers/gpu/drm/i915/intel_pm.c | 72 ++++++++++---------
4 files changed, 52 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 83ea04149b77..f77f47efb8b6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -659,7 +659,8 @@ struct intel_crtc_scaler_state {
struct intel_pipe_wm {
struct intel_wm_level wm[5];
- u32 linetime;
+ u16 linetime;
+ u16 ips_linetime;
bool fbc_wm_enabled;
bool pipe_enabled;
bool sprites_enabled;
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index bb9fe6bf5275..717c9afd9f6f 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2401,9 +2401,9 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
- MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL);
- MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL);
- MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL);
+ MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
+ MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
+ MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
MMIO_D(SPLL_CTL, D_ALL);
MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1a6376a97d48..d20d42980d5c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10538,13 +10538,13 @@ enum skl_power_gate {
#define D_COMP_COMP_DISABLE (1 << 0)
/* Pipe WM_LINETIME - watermark line time */
-#define _PIPE_WM_LINETIME_A 0x45270
-#define _PIPE_WM_LINETIME_B 0x45274
-#define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B)
-#define PIPE_WM_LINETIME_MASK (0x1ff)
-#define PIPE_WM_LINETIME_TIME(x) ((x))
-#define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff << 16)
-#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x) << 16)
+#define _WM_LINETIME_A 0x45270
+#define _WM_LINETIME_B 0x45274
+#define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B)
+#define HSW_LINETIME_MASK REG_GENMASK(8, 0)
+#define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x))
+#define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16)
+#define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x))
/* SFUSE_STRAP */
#define SFUSE_STRAP _MMIO(0xc2014)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ccbbdf4a6aab..b9eb0a89be93 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2788,31 +2788,31 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
}
static u32
-hsw_compute_linetime_wm(const struct intel_crtc_state *crtc_state)
+hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
{
- const struct intel_atomic_state *intel_state =
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+
+ if (!crtc_state->hw.active)
+ return 0;
+
+ return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
+ adjusted_mode->crtc_clock);
+}
+
+static u32
+hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state)
+{
+ const struct intel_atomic_state *state =
to_intel_atomic_state(crtc_state->uapi.state);
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
- u32 linetime, ips_linetime;
if (!crtc_state->hw.active)
return 0;
- if (WARN_ON(adjusted_mode->crtc_clock == 0))
- return 0;
- if (WARN_ON(intel_state->cdclk.logical.cdclk == 0))
- return 0;
- /* The WM are computed with base on how long it takes to fill a single
- * row at the given clock rate, multiplied by 8.
- * */
- linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
- adjusted_mode->crtc_clock);
- ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
- intel_state->cdclk.logical.cdclk);
-
- return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
- PIPE_WM_LINETIME_TIME(linetime);
+ return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
+ state->cdclk.logical.cdclk);
}
static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
@@ -3150,8 +3150,10 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
ilk_compute_wm_level(dev_priv, intel_crtc, 0, crtc_state,
pristate, sprstate, curstate, &pipe_wm->wm[0]);
- if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
- pipe_wm->linetime = hsw_compute_linetime_wm(crtc_state);
+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
+ pipe_wm->linetime = hsw_linetime_wm(crtc_state);
+ pipe_wm->ips_linetime = hsw_ips_linetime_wm(crtc_state);
+ }
if (!ilk_validate_pipe_wm(dev_priv, pipe_wm))
return -EINVAL;
@@ -3351,7 +3353,7 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
enum intel_ddb_partitioning partitioning,
struct ilk_wm_values *results)
{
- struct intel_crtc *intel_crtc;
+ struct intel_crtc *crtc;
int level, wm_lp;
results->enable_fbc_wm = merged->fbc_wm_enabled;
@@ -3396,15 +3398,17 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
}
/* LP0 register values */
- for_each_intel_crtc(&dev_priv->drm, intel_crtc) {
- enum pipe pipe = intel_crtc->pipe;
- const struct intel_wm_level *r =
- &intel_crtc->wm.active.ilk.wm[0];
+ for_each_intel_crtc(&dev_priv->drm, crtc) {
+ enum pipe pipe = crtc->pipe;
+ const struct intel_pipe_wm *pipe_wm = &crtc->wm.active.ilk;
+ const struct intel_wm_level *r = &pipe_wm->wm[0];
if (WARN_ON(!r->enable))
continue;
- results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
+ results->wm_linetime[pipe] =
+ HSW_LINETIME(pipe_wm->linetime) |
+ HSW_IPS_LINETIME(pipe_wm->ips_linetime);
results->wm_pipe[pipe] =
(r->pri_val << WM0_PIPE_PLANE_SHIFT) |
@@ -3557,11 +3561,11 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
if (dirty & WM_DIRTY_LINETIME(PIPE_A))
- I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
+ I915_WRITE(WM_LINETIME(PIPE_A), results->wm_linetime[0]);
if (dirty & WM_DIRTY_LINETIME(PIPE_B))
- I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
+ I915_WRITE(WM_LINETIME(PIPE_B), results->wm_linetime[1]);
if (dirty & WM_DIRTY_LINETIME(PIPE_C))
- I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
+ I915_WRITE(WM_LINETIME(PIPE_C), results->wm_linetime[2]);
if (dirty & WM_DIRTY_DDB) {
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
@@ -5532,7 +5536,7 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
if ((state->wm_results.dirty_pipes & BIT(crtc->pipe)) == 0)
return;
- I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
+ I915_WRITE(WM_LINETIME(pipe), HSW_LINETIME(pipe_wm->linetime));
}
static void skl_initial_wm(struct intel_atomic_state *state,
@@ -5677,7 +5681,8 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
if (!crtc->active)
return;
- out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
+ val = I915_READ(WM_LINETIME(pipe));
+ out->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, val);
}
void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
@@ -5719,7 +5724,7 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
- hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
+ hw->wm_linetime[pipe] = I915_READ(WM_LINETIME(pipe));
memset(active, 0, sizeof(*active));
@@ -5738,7 +5743,10 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
- active->linetime = hw->wm_linetime[pipe];
+ active->linetime = REG_FIELD_GET(HSW_LINETIME_MASK,
+ hw->wm_linetime[pipe]);
+ active->ips_linetime = REG_FIELD_GET(HSW_IPS_LINETIME_MASK,
+ hw->wm_linetime[pipe]);
} else {
int level, max_level = ilk_wm_max_level(dev_priv);
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH v2 3/4] drm/i915: Move linetime wms into the crtc state
2019-12-10 14:41 [Intel-gfx] [PATCH v2 0/6] drm/i915: Some cleanup near the SKL wm/ddb area Ville Syrjala
2019-12-10 14:41 ` [Intel-gfx] [PATCH v2 1/4] drm/i915: Streamline skl_commit_modeset_enables() Ville Syrjala
2019-12-10 14:41 ` [Intel-gfx] [PATCH v2 2/4] drm/i915: Polish WM_LINETIME register stuff Ville Syrjala
@ 2019-12-10 14:41 ` Ville Syrjala
2019-12-11 14:25 ` [Intel-gfx] [PATCH v3 " Ville Syrjala
2019-12-10 14:41 ` [Intel-gfx] [PATCH v2 4/4] drm/i915: Nuke skl wm.dirty_pipes bitmask Ville Syrjala
` (4 subsequent siblings)
7 siblings, 1 reply; 10+ messages in thread
From: Ville Syrjala @ 2019-12-10 14:41 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The linetime watermarks really have very little in common with the
plane watermarks. It looks to be cleaner to simply track them in
the crtc_state and program them from the normal modeset/fastset
paths.
The only dark cloud comes from the fact that the register is
still supposedly single buffered. So in theory it might still
need some form of two stage programming. Note that even though
HSW/BDWhave two stage programming we never computed any special
intermediate values for the linetime watermarks, and on SKL+
we don't even have the two stage stuff plugged in since everything
else is double buffered. So let's assume it's all fine and
continue doing what we've been doing.
Actually on HSW/BDW the value should not even change without
a full modeset since it doesn't account for pfit downscaling.
Thus only fastboot might be affected. But on SKL+ the pfit
scaling factor is take into consideration so the value may
change during any fastset.
As a bonus we'll plug this thing into the state
checker/dump now.
v2: Rebase due to bigjoiner prep
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 94 +++++++++++++-
.../drm/i915/display/intel_display_types.h | 7 +-
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/intel_pm.c | 118 +-----------------
4 files changed, 97 insertions(+), 123 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c1940954e304..9205b5bc1cc2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6549,6 +6549,16 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
}
+static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+ I915_WRITE(WM_LINETIME(crtc->pipe),
+ HSW_LINETIME(crtc_state->linetime) |
+ HSW_IPS_LINETIME(crtc_state->ips_linetime));
+}
+
static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -6633,6 +6643,8 @@ static void haswell_crtc_enable(struct intel_atomic_state *state,
if (INTEL_GEN(dev_priv) < 9)
intel_disable_primary_plane(new_crtc_state);
+ hsw_set_linetime_wm(new_crtc_state);
+
if (INTEL_GEN(dev_priv) >= 11)
icl_set_pipe_chicken(crtc);
@@ -10630,6 +10642,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
enum intel_display_power_domain power_domain;
u64 power_domain_mask;
bool active;
+ u32 tmp;
intel_crtc_init_scalers(crtc, pipe_config);
@@ -10695,7 +10708,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
if (INTEL_GEN(dev_priv) >= 9) {
- u32 tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe));
+ tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe));
if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
pipe_config->gamma_enable = true;
@@ -10708,6 +10721,12 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
intel_color_get_config(pipe_config);
+ tmp = I915_READ(WM_LINETIME(crtc->pipe));
+ pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
+ if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
+ pipe_config->ips_linetime =
+ REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
+
power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
WARN_ON(power_domain_mask & BIT_ULL(power_domain));
@@ -12133,6 +12152,53 @@ static int icl_add_sync_mode_crtcs(struct intel_crtc_state *crtc_state)
return 0;
}
+static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
+{
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+
+ if (!crtc_state->hw.enable)
+ return 0;
+
+ return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
+ adjusted_mode->crtc_clock);
+}
+
+static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state)
+{
+ const struct intel_atomic_state *state =
+ to_intel_atomic_state(crtc_state->uapi.state);
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+
+ if (!crtc_state->hw.enable)
+ return 0;
+
+ return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
+ state->cdclk.logical.cdclk);
+}
+
+static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+ u16 linetime_wm;
+
+ if (!crtc_state->hw.enable)
+ return 0;
+
+ linetime_wm = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000 * 8,
+ crtc_state->pixel_rate);
+
+ /* Display WA #1135: BXT:ALL GLK:ALL */
+ if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled)
+ linetime_wm /= 2;
+
+ return linetime_wm;
+}
+
static int intel_crtc_atomic_check(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
@@ -12204,6 +12270,13 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
if (HAS_IPS(dev_priv))
crtc_state->ips_enabled = hsw_compute_ips_config(crtc_state);
+ if (INTEL_GEN(dev_priv) >= 9) {
+ crtc_state->linetime = skl_linetime_wm(crtc_state);
+ } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
+ crtc_state->linetime = hsw_linetime_wm(crtc_state);
+ crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state);
+ }
+
return ret;
}
@@ -12493,6 +12566,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
pipe_config->pipe_src_w, pipe_config->pipe_src_h,
pipe_config->pixel_rate);
+ DRM_DEBUG_KMS("linetime: %d, ips linetime: %d\n",
+ pipe_config->linetime, pipe_config->ips_linetime);
+
if (INTEL_GEN(dev_priv) >= 9)
DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
crtc->num_scalers,
@@ -13239,10 +13315,12 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_BOOL(gamma_enable);
PIPE_CONF_CHECK_BOOL(csc_enable);
+ PIPE_CONF_CHECK_I(linetime);
+ PIPE_CONF_CHECK_I(ips_linetime);
+
bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
if (bp_gamma)
PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
-
}
PIPE_CONF_CHECK_BOOL(double_wide);
@@ -14250,6 +14328,18 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
ironlake_pfit_disable(old_crtc_state);
}
+ /*
+ * The register is supposedly single buffered so perhaps
+ * not 100% correct to do this here. But SKL+ calculate
+ * this based on the adjust pixel rate so pfit changes do
+ * affect it and so it must be updated for fastsets.
+ * HSW/BDW only really need this here for fastboot, after
+ * that the value should not change without a full modeset.
+ */
+ if (INTEL_GEN(dev_priv) >= 9 ||
+ IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
+ hsw_set_linetime_wm(new_crtc_state);
+
if (INTEL_GEN(dev_priv) >= 11)
icl_set_pipe_chicken(crtc);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index f77f47efb8b6..1b5bd558e65d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -659,8 +659,6 @@ struct intel_crtc_scaler_state {
struct intel_pipe_wm {
struct intel_wm_level wm[5];
- u16 linetime;
- u16 ips_linetime;
bool fbc_wm_enabled;
bool pipe_enabled;
bool sprites_enabled;
@@ -676,7 +674,6 @@ struct skl_plane_wm {
struct skl_pipe_wm {
struct skl_plane_wm planes[I915_MAX_PLANES];
- u32 linetime;
};
enum vlv_wm_level {
@@ -1047,6 +1044,10 @@ struct intel_crtc_state {
struct drm_dsc_config config;
} dsc;
+ /* HSW+ linetime watermarks */
+ u16 linetime;
+ u16 ips_linetime;
+
/* Forward Error correction State */
bool fec_enable;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ce130e1f1e47..db15a8f4847f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -743,7 +743,6 @@ struct ilk_wm_values {
u32 wm_pipe[3];
u32 wm_lp[3];
u32 wm_lp_spr[3];
- u32 wm_linetime[3];
bool enable_fbc_wm;
enum intel_ddb_partitioning partitioning;
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b9eb0a89be93..07e95440b40d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2787,34 +2787,6 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
result->enable = true;
}
-static u32
-hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
-{
- const struct drm_display_mode *adjusted_mode =
- &crtc_state->hw.adjusted_mode;
-
- if (!crtc_state->hw.active)
- return 0;
-
- return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
- adjusted_mode->crtc_clock);
-}
-
-static u32
-hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state)
-{
- const struct intel_atomic_state *state =
- to_intel_atomic_state(crtc_state->uapi.state);
- const struct drm_display_mode *adjusted_mode =
- &crtc_state->hw.adjusted_mode;
-
- if (!crtc_state->hw.active)
- return 0;
-
- return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
- state->cdclk.logical.cdclk);
-}
-
static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
u16 wm[8])
{
@@ -3150,11 +3122,6 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
ilk_compute_wm_level(dev_priv, intel_crtc, 0, crtc_state,
pristate, sprstate, curstate, &pipe_wm->wm[0]);
- if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
- pipe_wm->linetime = hsw_linetime_wm(crtc_state);
- pipe_wm->ips_linetime = hsw_ips_linetime_wm(crtc_state);
- }
-
if (!ilk_validate_pipe_wm(dev_priv, pipe_wm))
return -EINVAL;
@@ -3406,10 +3373,6 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
if (WARN_ON(!r->enable))
continue;
- results->wm_linetime[pipe] =
- HSW_LINETIME(pipe_wm->linetime) |
- HSW_IPS_LINETIME(pipe_wm->ips_linetime);
-
results->wm_pipe[pipe] =
(r->pri_val << WM0_PIPE_PLANE_SHIFT) |
(r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
@@ -3448,7 +3411,6 @@ ilk_find_best_result(struct drm_i915_private *dev_priv,
/* dirty bits used to track which watermarks need changes */
#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
-#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
#define WM_DIRTY_FBC (1 << 24)
@@ -3463,12 +3425,6 @@ static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
int wm_lp;
for_each_pipe(dev_priv, pipe) {
- if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
- dirty |= WM_DIRTY_LINETIME(pipe);
- /* Must disable LP1+ watermarks too */
- dirty |= WM_DIRTY_LP_ALL;
- }
-
if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
dirty |= WM_DIRTY_PIPE(pipe);
/* Must disable LP1+ watermarks too */
@@ -3560,13 +3516,6 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
if (dirty & WM_DIRTY_PIPE(PIPE_C))
I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
- if (dirty & WM_DIRTY_LINETIME(PIPE_A))
- I915_WRITE(WM_LINETIME(PIPE_A), results->wm_linetime[0]);
- if (dirty & WM_DIRTY_LINETIME(PIPE_B))
- I915_WRITE(WM_LINETIME(PIPE_B), results->wm_linetime[1]);
- if (dirty & WM_DIRTY_LINETIME(PIPE_C))
- I915_WRITE(WM_LINETIME(PIPE_C), results->wm_linetime[2]);
-
if (dirty & WM_DIRTY_DDB) {
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
val = I915_READ(WM_MISC);
@@ -4817,24 +4766,6 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
}
}
-static u32
-skl_compute_linetime_wm(const struct intel_crtc_state *crtc_state)
-{
- struct drm_atomic_state *state = crtc_state->uapi.state;
- struct drm_i915_private *dev_priv = to_i915(state->dev);
- uint_fixed_16_16_t linetime_us;
- u32 linetime_wm;
-
- linetime_us = intel_get_linetime_us(crtc_state);
- linetime_wm = fixed16_to_u32_round_up(mul_u32_fixed16(8, linetime_us));
-
- /* Display WA #1135: BXT:ALL GLK:ALL */
- if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled)
- linetime_wm /= 2;
-
- return linetime_wm;
-}
-
static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
const struct skl_wm_params *wp,
struct skl_plane_wm *wm)
@@ -5022,8 +4953,6 @@ static int skl_build_pipe_wm(struct intel_crtc_state *crtc_state)
return ret;
}
- pipe_wm->linetime = skl_compute_linetime_wm(crtc_state);
-
return 0;
}
@@ -5148,7 +5077,7 @@ static bool skl_pipe_wm_equals(struct intel_crtc *crtc,
return false;
}
- return wm1->linetime == wm2->linetime;
+ return true;
}
static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
@@ -5524,40 +5453,6 @@ skl_compute_wm(struct intel_atomic_state *state)
return 0;
}
-static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- const struct intel_crtc_state *crtc_state =
- intel_atomic_get_new_crtc_state(state, crtc);
- const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
- enum pipe pipe = crtc->pipe;
-
- if ((state->wm_results.dirty_pipes & BIT(crtc->pipe)) == 0)
- return;
-
- I915_WRITE(WM_LINETIME(pipe), HSW_LINETIME(pipe_wm->linetime));
-}
-
-static void skl_initial_wm(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- const struct intel_crtc_state *crtc_state =
- intel_atomic_get_new_crtc_state(state, crtc);
- struct skl_ddb_values *results = &state->wm_results;
-
- if ((results->dirty_pipes & BIT(crtc->pipe)) == 0)
- return;
-
- mutex_lock(&dev_priv->wm.wm_mutex);
-
- if (crtc_state->uapi.active_changed)
- skl_atomic_update_crtc_wm(state, crtc);
-
- mutex_unlock(&dev_priv->wm.wm_mutex);
-}
-
static void ilk_compute_wm_config(struct drm_i915_private *dev_priv,
struct intel_wm_config *config)
{
@@ -5680,9 +5575,6 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
if (!crtc->active)
return;
-
- val = I915_READ(WM_LINETIME(pipe));
- out->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, val);
}
void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
@@ -5723,8 +5615,6 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
};
hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
- if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
- hw->wm_linetime[pipe] = I915_READ(WM_LINETIME(pipe));
memset(active, 0, sizeof(*active));
@@ -5743,10 +5633,6 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
- active->linetime = REG_FIELD_GET(HSW_LINETIME_MASK,
- hw->wm_linetime[pipe]);
- active->ips_linetime = REG_FIELD_GET(HSW_IPS_LINETIME_MASK,
- hw->wm_linetime[pipe]);
} else {
int level, max_level = ilk_wm_max_level(dev_priv);
@@ -7197,8 +7083,6 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
/* For FIFO watermark updates */
if (INTEL_GEN(dev_priv) >= 9) {
skl_setup_wm_latency(dev_priv);
- dev_priv->display.initial_watermarks = skl_initial_wm;
- dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
dev_priv->display.compute_global_watermarks = skl_compute_wm;
} else if (HAS_PCH_SPLIT(dev_priv)) {
ilk_setup_wm_latency(dev_priv);
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH v2 4/4] drm/i915: Nuke skl wm.dirty_pipes bitmask
2019-12-10 14:41 [Intel-gfx] [PATCH v2 0/6] drm/i915: Some cleanup near the SKL wm/ddb area Ville Syrjala
` (2 preceding siblings ...)
2019-12-10 14:41 ` [Intel-gfx] [PATCH v2 3/4] drm/i915: Move linetime wms into the crtc state Ville Syrjala
@ 2019-12-10 14:41 ` Ville Syrjala
2019-12-10 14:46 ` [Intel-gfx] [PATCH v2 0/6] drm/i915: Some cleanup near the SKL wm/ddb area Ville Syrjälä
` (3 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Ville Syrjala @ 2019-12-10 14:41 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The dirty_pipes bitmask is now unused. Get rid of it.
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/intel_pm.c | 35 +--------------------------------
2 files changed, 1 insertion(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index db15a8f4847f..54a432104c85 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -802,7 +802,6 @@ struct skl_ddb_allocation {
};
struct skl_ddb_values {
- unsigned dirty_pipes;
struct skl_ddb_allocation ddb;
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 07e95440b40d..f42c78a2cd23 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5063,23 +5063,6 @@ static bool skl_plane_wm_equals(struct drm_i915_private *dev_priv,
return skl_wm_level_equals(&wm1->trans_wm, &wm2->trans_wm);
}
-static bool skl_pipe_wm_equals(struct intel_crtc *crtc,
- const struct skl_pipe_wm *wm1,
- const struct skl_pipe_wm *wm2)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum plane_id plane_id;
-
- for_each_plane_id_on_crtc(crtc, plane_id) {
- if (!skl_plane_wm_equals(dev_priv,
- &wm1->planes[plane_id],
- &wm2->planes[plane_id]))
- return false;
- }
-
- return true;
-}
-
static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
const struct skl_ddb_entry *b)
{
@@ -5336,8 +5319,6 @@ skl_ddb_add_affected_pipes(struct intel_atomic_state *state)
* to grab the lock on *all* CRTC's.
*/
if (state->active_pipe_changes || state->modeset) {
- state->wm_results.dirty_pipes = INTEL_INFO(dev_priv)->pipe_mask;
-
ret = intel_add_all_pipes(state);
if (ret)
return ret;
@@ -5412,12 +5393,8 @@ skl_compute_wm(struct intel_atomic_state *state)
struct intel_crtc *crtc;
struct intel_crtc_state *new_crtc_state;
struct intel_crtc_state *old_crtc_state;
- struct skl_ddb_values *results = &state->wm_results;
int ret, i;
- /* Clear all dirty flags */
- results->dirty_pipes = 0;
-
ret = skl_ddb_add_affected_pipes(state);
if (ret)
return ret;
@@ -5425,8 +5402,7 @@ skl_compute_wm(struct intel_atomic_state *state)
/*
* Calculate WM's for all pipes that are part of this transaction.
* Note that skl_ddb_add_affected_pipes may have added more CRTC's that
- * weren't otherwise being modified (and set bits in dirty_pipes) if
- * pipe allocations had to change.
+ * weren't otherwise being modified if pipe allocations had to change.
*/
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
@@ -5437,11 +5413,6 @@ skl_compute_wm(struct intel_atomic_state *state)
ret = skl_wm_add_affected_planes(state, crtc);
if (ret)
return ret;
-
- if (!skl_pipe_wm_equals(crtc,
- &old_crtc_state->wm.skl.optimal,
- &new_crtc_state->wm.skl.optimal))
- results->dirty_pipes |= BIT(crtc->pipe);
}
ret = skl_compute_ddb(state);
@@ -5579,7 +5550,6 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
{
- struct skl_ddb_values *hw = &dev_priv->wm.skl_hw;
struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
struct intel_crtc *crtc;
struct intel_crtc_state *crtc_state;
@@ -5589,9 +5559,6 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
crtc_state = to_intel_crtc_state(crtc->base.state);
skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);
-
- if (crtc->active)
- hw->dirty_pipes |= BIT(crtc->pipe);
}
if (dev_priv->active_pipes) {
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH v2 0/6] drm/i915: Some cleanup near the SKL wm/ddb area
2019-12-10 14:41 [Intel-gfx] [PATCH v2 0/6] drm/i915: Some cleanup near the SKL wm/ddb area Ville Syrjala
` (3 preceding siblings ...)
2019-12-10 14:41 ` [Intel-gfx] [PATCH v2 4/4] drm/i915: Nuke skl wm.dirty_pipes bitmask Ville Syrjala
@ 2019-12-10 14:46 ` Ville Syrjälä
2019-12-11 0:59 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Some cleanup near the SKL wm/ddb area (rev3) Patchwork
` (2 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Ville Syrjälä @ 2019-12-10 14:46 UTC (permalink / raw)
To: intel-gfx
On Tue, Dec 10, 2019 at 04:41:01PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Rebased leftovers from my earlier series to nuke the dirty_pipes junk.
>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> Ville Syrjälä (6):
> drm/i915: Streamline skl_commit_modeset_enables()
> drm/i915: Polish WM_LINETIME register stuff
> drm/i915: Move linetime wms into the crtc state
> drm/i915: Nuke skl wm.dirty_pipes bitmask
> drm/i915: Kill struct skl_ddb_allocation
> drm/i915: Implement pps w/a #1124 for bxt+
Drat. Last two aren't part of the series. Time to see how badly patchwork
reacts to this one...
>
> drivers/gpu/drm/i915/display/intel_display.c | 170 +++++++++++----
> .../drm/i915/display/intel_display_power.c | 28 +--
> .../drm/i915/display/intel_display_power.h | 2 +-
> .../drm/i915/display/intel_display_types.h | 11 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 11 +
> drivers/gpu/drm/i915/gvt/handlers.c | 6 +-
> drivers/gpu/drm/i915/i915_drv.h | 14 +-
> drivers/gpu/drm/i915/i915_reg.h | 14 +-
> drivers/gpu/drm/i915/intel_pm.c | 202 +++---------------
> drivers/gpu/drm/i915/intel_pm.h | 4 +-
> 10 files changed, 187 insertions(+), 275 deletions(-)
>
> --
> 2.23.0
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Some cleanup near the SKL wm/ddb area (rev3)
2019-12-10 14:41 [Intel-gfx] [PATCH v2 0/6] drm/i915: Some cleanup near the SKL wm/ddb area Ville Syrjala
` (4 preceding siblings ...)
2019-12-10 14:46 ` [Intel-gfx] [PATCH v2 0/6] drm/i915: Some cleanup near the SKL wm/ddb area Ville Syrjälä
@ 2019-12-11 0:59 ` Patchwork
2019-12-11 20:19 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Some cleanup near the SKL wm/ddb area (rev4) Patchwork
2019-12-12 6:29 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
7 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2019-12-11 0:59 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Some cleanup near the SKL wm/ddb area (rev3)
URL : https://patchwork.freedesktop.org/series/67930/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7533 -> Patchwork_15672
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15672 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15672, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15672/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15672:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live_blt:
- fi-ivb-3770: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7533/fi-ivb-3770/igt@i915_selftest@live_blt.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15672/fi-ivb-3770/igt@i915_selftest@live_blt.html
* igt@kms_busy@basic-flip-pipe-b:
- fi-hsw-4770: [PASS][3] -> [DMESG-WARN][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7533/fi-hsw-4770/igt@kms_busy@basic-flip-pipe-b.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15672/fi-hsw-4770/igt@kms_busy@basic-flip-pipe-b.html
- fi-hsw-peppy: [PASS][5] -> [DMESG-WARN][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7533/fi-hsw-peppy/igt@kms_busy@basic-flip-pipe-b.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15672/fi-hsw-peppy/igt@kms_busy@basic-flip-pipe-b.html
- fi-hsw-4770r: [PASS][7] -> [DMESG-WARN][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7533/fi-hsw-4770r/igt@kms_busy@basic-flip-pipe-b.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15672/fi-hsw-4770r/igt@kms_busy@basic-flip-pipe-b.html
* igt@runner@aborted:
- fi-hsw-peppy: NOTRUN -> [FAIL][9]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15672/fi-hsw-peppy/igt@runner@aborted.html
- fi-hsw-4770: NOTRUN -> [FAIL][10]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15672/fi-hsw-4770/igt@runner@aborted.html
- fi-hsw-4770r: NOTRUN -> [FAIL][11]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15672/fi-hsw-4770r/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_15672 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@module-reload:
- fi-skl-lmem: [PASS][12] -> [DMESG-WARN][13] ([i915#592])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7533/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15672/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live_gem_contexts:
- fi-byt-n2820: [PASS][14] -> [INCOMPLETE][15] ([i915#45])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7533/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15672/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][16] -> [FAIL][17] ([fdo#111096] / [i915#323])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7533/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15672/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
#### Possible fixes ####
* igt@gem_mmap_gtt@basic-small-bo:
- fi-icl-dsi: [DMESG-WARN][18] ([i915#109]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7533/fi-icl-dsi/igt@gem_mmap_gtt@basic-small-bo.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15672/fi-icl-dsi/igt@gem_mmap_gtt@basic-small-bo.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [FAIL][20] ([i915#178]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7533/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15672/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
- fi-kbl-guc: [FAIL][22] ([i915#579]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7533/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15672/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live_gt_heartbeat:
- fi-bsw-kefka: [DMESG-FAIL][24] -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7533/fi-bsw-kefka/igt@i915_selftest@live_gt_heartbeat.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15672/fi-bsw-kefka/igt@i915_selftest@live_gt_heartbeat.html
#### Warnings ####
* igt@gem_exec_suspend@basic-s4-devices:
- fi-kbl-x1275: [DMESG-WARN][26] ([fdo#107139] / [i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][27] ([fdo#107139] / [i915#62] / [i915#92])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7533/fi-kbl-x1275/igt@gem_exec_suspend@basic-s4-devices.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15672/fi-kbl-x1275/igt@gem_exec_suspend@basic-s4-devices.html
* igt@kms_flip@basic-flip-vs-modeset:
- fi-kbl-x1275: [DMESG-WARN][28] ([i915#62] / [i915#92]) -> [DMESG-WARN][29] ([i915#62] / [i915#92] / [i915#95]) +5 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7533/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15672/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a:
- fi-kbl-x1275: [DMESG-WARN][30] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][31] ([i915#62] / [i915#92]) +2 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7533/fi-kbl-x1275/igt@kms_pipe_crc_basic@read-crc-pipe-a.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15672/fi-kbl-x1275/igt@kms_pipe_crc_basic@read-crc-pipe-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
[i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
[i915#178]: https://gitlab.freedesktop.org/drm/intel/issues/178
[i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
[i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45
[i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
[i915#592]: https://gitlab.freedesktop.org/drm/intel/issues/592
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (53 -> 46)
------------------------------
Additional (2): fi-tgl-u fi-tgl-y
Missing (9): fi-icl-1065g7 fi-ilk-m540 fi-hsw-4200u fi-bsw-n3050 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7533 -> Patchwork_15672
CI-20190529: 20190529
CI_DRM_7533: 5f07735eaf4b5debe7c2d70908388af179a11d1f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5341: 5fe683cdebde2d77d16ffc42c9fdf29a9f95bb82 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15672: 8805fc21abaafbe7f8e6b1cdbfc0d479d8136ce6 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8805fc21abaa drm/i915: Nuke skl wm.dirty_pipes bitmask
52b6bbbcf75d drm/i915: Move linetime wms into the crtc state
df9b02b98f43 drm/i915: Polish WM_LINETIME register stuff
89746f18d943 drm/i915: Streamline skl_commit_modeset_enables()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15672/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH v3 3/4] drm/i915: Move linetime wms into the crtc state
2019-12-10 14:41 ` [Intel-gfx] [PATCH v2 3/4] drm/i915: Move linetime wms into the crtc state Ville Syrjala
@ 2019-12-11 14:25 ` Ville Syrjala
0 siblings, 0 replies; 10+ messages in thread
From: Ville Syrjala @ 2019-12-11 14:25 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The linetime watermarks really have very little in common with the
plane watermarks. It looks to be cleaner to simply track them in
the crtc_state and program them from the normal modeset/fastset
paths.
The only dark cloud comes from the fact that the register is
still supposedly single buffered. So in theory it might still
need some form of two stage programming. Note that even though
HSW/BDWhave two stage programming we never computed any special
intermediate values for the linetime watermarks, and on SKL+
we don't even have the two stage stuff plugged in since everything
else is double buffered. So let's assume it's all fine and
continue doing what we've been doing.
Actually on HSW/BDW the value should not even change without
a full modeset since it doesn't account for pfit downscaling.
Thus only fastboot might be affected. But on SKL+ the pfit
scaling factor is take into consideration so the value may
change during any fastset.
As a bonus we'll plug this thing into the state
checker/dump now.
v2: Rebase due to bigjoiner prep
v2: Only compute ips linetime for IPS capable pipes.
Bspec says the register values is ignored for other
pipes, but in fact it can't even be written so the
state checker becomes unhappy if we don't compute
it as zero.
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 95 +++++++++++++-
.../drm/i915/display/intel_display_types.h | 7 +-
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/intel_pm.c | 118 +-----------------
4 files changed, 98 insertions(+), 123 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c1940954e304..70fbeb2916e2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6549,6 +6549,16 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
}
+static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+ I915_WRITE(WM_LINETIME(crtc->pipe),
+ HSW_LINETIME(crtc_state->linetime) |
+ HSW_IPS_LINETIME(crtc_state->ips_linetime));
+}
+
static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -6633,6 +6643,8 @@ static void haswell_crtc_enable(struct intel_atomic_state *state,
if (INTEL_GEN(dev_priv) < 9)
intel_disable_primary_plane(new_crtc_state);
+ hsw_set_linetime_wm(new_crtc_state);
+
if (INTEL_GEN(dev_priv) >= 11)
icl_set_pipe_chicken(crtc);
@@ -10630,6 +10642,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
enum intel_display_power_domain power_domain;
u64 power_domain_mask;
bool active;
+ u32 tmp;
intel_crtc_init_scalers(crtc, pipe_config);
@@ -10695,7 +10708,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
if (INTEL_GEN(dev_priv) >= 9) {
- u32 tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe));
+ tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe));
if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
pipe_config->gamma_enable = true;
@@ -10708,6 +10721,12 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
intel_color_get_config(pipe_config);
+ tmp = I915_READ(WM_LINETIME(crtc->pipe));
+ pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
+ if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
+ pipe_config->ips_linetime =
+ REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
+
power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
WARN_ON(power_domain_mask & BIT_ULL(power_domain));
@@ -12133,6 +12152,53 @@ static int icl_add_sync_mode_crtcs(struct intel_crtc_state *crtc_state)
return 0;
}
+static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
+{
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+
+ if (!crtc_state->hw.enable)
+ return 0;
+
+ return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
+ adjusted_mode->crtc_clock);
+}
+
+static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state)
+{
+ const struct intel_atomic_state *state =
+ to_intel_atomic_state(crtc_state->uapi.state);
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+
+ if (!crtc_state->hw.enable)
+ return 0;
+
+ return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
+ state->cdclk.logical.cdclk);
+}
+
+static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+ u16 linetime_wm;
+
+ if (!crtc_state->hw.enable)
+ return 0;
+
+ linetime_wm = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000 * 8,
+ crtc_state->pixel_rate);
+
+ /* Display WA #1135: BXT:ALL GLK:ALL */
+ if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled)
+ linetime_wm /= 2;
+
+ return linetime_wm;
+}
+
static int intel_crtc_atomic_check(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
@@ -12204,6 +12270,14 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
if (HAS_IPS(dev_priv))
crtc_state->ips_enabled = hsw_compute_ips_config(crtc_state);
+ if (INTEL_GEN(dev_priv) >= 9) {
+ crtc_state->linetime = skl_linetime_wm(crtc_state);
+ } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
+ crtc_state->linetime = hsw_linetime_wm(crtc_state);
+ if (hsw_crtc_supports_ips(crtc))
+ crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state);
+ }
+
return ret;
}
@@ -12493,6 +12567,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
pipe_config->pipe_src_w, pipe_config->pipe_src_h,
pipe_config->pixel_rate);
+ DRM_DEBUG_KMS("linetime: %d, ips linetime: %d\n",
+ pipe_config->linetime, pipe_config->ips_linetime);
+
if (INTEL_GEN(dev_priv) >= 9)
DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
crtc->num_scalers,
@@ -13239,10 +13316,12 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_BOOL(gamma_enable);
PIPE_CONF_CHECK_BOOL(csc_enable);
+ PIPE_CONF_CHECK_I(linetime);
+ PIPE_CONF_CHECK_I(ips_linetime);
+
bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
if (bp_gamma)
PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
-
}
PIPE_CONF_CHECK_BOOL(double_wide);
@@ -14250,6 +14329,18 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
ironlake_pfit_disable(old_crtc_state);
}
+ /*
+ * The register is supposedly single buffered so perhaps
+ * not 100% correct to do this here. But SKL+ calculate
+ * this based on the adjust pixel rate so pfit changes do
+ * affect it and so it must be updated for fastsets.
+ * HSW/BDW only really need this here for fastboot, after
+ * that the value should not change without a full modeset.
+ */
+ if (INTEL_GEN(dev_priv) >= 9 ||
+ IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
+ hsw_set_linetime_wm(new_crtc_state);
+
if (INTEL_GEN(dev_priv) >= 11)
icl_set_pipe_chicken(crtc);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index f77f47efb8b6..1b5bd558e65d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -659,8 +659,6 @@ struct intel_crtc_scaler_state {
struct intel_pipe_wm {
struct intel_wm_level wm[5];
- u16 linetime;
- u16 ips_linetime;
bool fbc_wm_enabled;
bool pipe_enabled;
bool sprites_enabled;
@@ -676,7 +674,6 @@ struct skl_plane_wm {
struct skl_pipe_wm {
struct skl_plane_wm planes[I915_MAX_PLANES];
- u32 linetime;
};
enum vlv_wm_level {
@@ -1047,6 +1044,10 @@ struct intel_crtc_state {
struct drm_dsc_config config;
} dsc;
+ /* HSW+ linetime watermarks */
+ u16 linetime;
+ u16 ips_linetime;
+
/* Forward Error correction State */
bool fec_enable;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ce130e1f1e47..db15a8f4847f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -743,7 +743,6 @@ struct ilk_wm_values {
u32 wm_pipe[3];
u32 wm_lp[3];
u32 wm_lp_spr[3];
- u32 wm_linetime[3];
bool enable_fbc_wm;
enum intel_ddb_partitioning partitioning;
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b9eb0a89be93..07e95440b40d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2787,34 +2787,6 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
result->enable = true;
}
-static u32
-hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
-{
- const struct drm_display_mode *adjusted_mode =
- &crtc_state->hw.adjusted_mode;
-
- if (!crtc_state->hw.active)
- return 0;
-
- return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
- adjusted_mode->crtc_clock);
-}
-
-static u32
-hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state)
-{
- const struct intel_atomic_state *state =
- to_intel_atomic_state(crtc_state->uapi.state);
- const struct drm_display_mode *adjusted_mode =
- &crtc_state->hw.adjusted_mode;
-
- if (!crtc_state->hw.active)
- return 0;
-
- return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
- state->cdclk.logical.cdclk);
-}
-
static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
u16 wm[8])
{
@@ -3150,11 +3122,6 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
ilk_compute_wm_level(dev_priv, intel_crtc, 0, crtc_state,
pristate, sprstate, curstate, &pipe_wm->wm[0]);
- if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
- pipe_wm->linetime = hsw_linetime_wm(crtc_state);
- pipe_wm->ips_linetime = hsw_ips_linetime_wm(crtc_state);
- }
-
if (!ilk_validate_pipe_wm(dev_priv, pipe_wm))
return -EINVAL;
@@ -3406,10 +3373,6 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
if (WARN_ON(!r->enable))
continue;
- results->wm_linetime[pipe] =
- HSW_LINETIME(pipe_wm->linetime) |
- HSW_IPS_LINETIME(pipe_wm->ips_linetime);
-
results->wm_pipe[pipe] =
(r->pri_val << WM0_PIPE_PLANE_SHIFT) |
(r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
@@ -3448,7 +3411,6 @@ ilk_find_best_result(struct drm_i915_private *dev_priv,
/* dirty bits used to track which watermarks need changes */
#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
-#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
#define WM_DIRTY_FBC (1 << 24)
@@ -3463,12 +3425,6 @@ static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
int wm_lp;
for_each_pipe(dev_priv, pipe) {
- if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
- dirty |= WM_DIRTY_LINETIME(pipe);
- /* Must disable LP1+ watermarks too */
- dirty |= WM_DIRTY_LP_ALL;
- }
-
if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
dirty |= WM_DIRTY_PIPE(pipe);
/* Must disable LP1+ watermarks too */
@@ -3560,13 +3516,6 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
if (dirty & WM_DIRTY_PIPE(PIPE_C))
I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
- if (dirty & WM_DIRTY_LINETIME(PIPE_A))
- I915_WRITE(WM_LINETIME(PIPE_A), results->wm_linetime[0]);
- if (dirty & WM_DIRTY_LINETIME(PIPE_B))
- I915_WRITE(WM_LINETIME(PIPE_B), results->wm_linetime[1]);
- if (dirty & WM_DIRTY_LINETIME(PIPE_C))
- I915_WRITE(WM_LINETIME(PIPE_C), results->wm_linetime[2]);
-
if (dirty & WM_DIRTY_DDB) {
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
val = I915_READ(WM_MISC);
@@ -4817,24 +4766,6 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
}
}
-static u32
-skl_compute_linetime_wm(const struct intel_crtc_state *crtc_state)
-{
- struct drm_atomic_state *state = crtc_state->uapi.state;
- struct drm_i915_private *dev_priv = to_i915(state->dev);
- uint_fixed_16_16_t linetime_us;
- u32 linetime_wm;
-
- linetime_us = intel_get_linetime_us(crtc_state);
- linetime_wm = fixed16_to_u32_round_up(mul_u32_fixed16(8, linetime_us));
-
- /* Display WA #1135: BXT:ALL GLK:ALL */
- if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled)
- linetime_wm /= 2;
-
- return linetime_wm;
-}
-
static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
const struct skl_wm_params *wp,
struct skl_plane_wm *wm)
@@ -5022,8 +4953,6 @@ static int skl_build_pipe_wm(struct intel_crtc_state *crtc_state)
return ret;
}
- pipe_wm->linetime = skl_compute_linetime_wm(crtc_state);
-
return 0;
}
@@ -5148,7 +5077,7 @@ static bool skl_pipe_wm_equals(struct intel_crtc *crtc,
return false;
}
- return wm1->linetime == wm2->linetime;
+ return true;
}
static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
@@ -5524,40 +5453,6 @@ skl_compute_wm(struct intel_atomic_state *state)
return 0;
}
-static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- const struct intel_crtc_state *crtc_state =
- intel_atomic_get_new_crtc_state(state, crtc);
- const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
- enum pipe pipe = crtc->pipe;
-
- if ((state->wm_results.dirty_pipes & BIT(crtc->pipe)) == 0)
- return;
-
- I915_WRITE(WM_LINETIME(pipe), HSW_LINETIME(pipe_wm->linetime));
-}
-
-static void skl_initial_wm(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- const struct intel_crtc_state *crtc_state =
- intel_atomic_get_new_crtc_state(state, crtc);
- struct skl_ddb_values *results = &state->wm_results;
-
- if ((results->dirty_pipes & BIT(crtc->pipe)) == 0)
- return;
-
- mutex_lock(&dev_priv->wm.wm_mutex);
-
- if (crtc_state->uapi.active_changed)
- skl_atomic_update_crtc_wm(state, crtc);
-
- mutex_unlock(&dev_priv->wm.wm_mutex);
-}
-
static void ilk_compute_wm_config(struct drm_i915_private *dev_priv,
struct intel_wm_config *config)
{
@@ -5680,9 +5575,6 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
if (!crtc->active)
return;
-
- val = I915_READ(WM_LINETIME(pipe));
- out->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, val);
}
void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
@@ -5723,8 +5615,6 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
};
hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
- if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
- hw->wm_linetime[pipe] = I915_READ(WM_LINETIME(pipe));
memset(active, 0, sizeof(*active));
@@ -5743,10 +5633,6 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
- active->linetime = REG_FIELD_GET(HSW_LINETIME_MASK,
- hw->wm_linetime[pipe]);
- active->ips_linetime = REG_FIELD_GET(HSW_IPS_LINETIME_MASK,
- hw->wm_linetime[pipe]);
} else {
int level, max_level = ilk_wm_max_level(dev_priv);
@@ -7197,8 +7083,6 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
/* For FIFO watermark updates */
if (INTEL_GEN(dev_priv) >= 9) {
skl_setup_wm_latency(dev_priv);
- dev_priv->display.initial_watermarks = skl_initial_wm;
- dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
dev_priv->display.compute_global_watermarks = skl_compute_wm;
} else if (HAS_PCH_SPLIT(dev_priv)) {
ilk_setup_wm_latency(dev_priv);
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Some cleanup near the SKL wm/ddb area (rev4)
2019-12-10 14:41 [Intel-gfx] [PATCH v2 0/6] drm/i915: Some cleanup near the SKL wm/ddb area Ville Syrjala
` (5 preceding siblings ...)
2019-12-11 0:59 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Some cleanup near the SKL wm/ddb area (rev3) Patchwork
@ 2019-12-11 20:19 ` Patchwork
2019-12-12 6:29 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
7 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2019-12-11 20:19 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Some cleanup near the SKL wm/ddb area (rev4)
URL : https://patchwork.freedesktop.org/series/67930/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7543 -> Patchwork_15693
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/index.html
Known issues
------------
Here are the changes found in Patchwork_15693 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [FAIL][1] ([i915#178]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live_requests:
- fi-hsw-4770: [INCOMPLETE][3] ([i915#773]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/fi-hsw-4770/igt@i915_selftest@live_requests.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/fi-hsw-4770/igt@i915_selftest@live_requests.html
* igt@kms_busy@basic-flip-pipe-a:
- fi-kbl-soraka: [DMESG-WARN][5] ([i915#95]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/fi-kbl-soraka/igt@kms_busy@basic-flip-pipe-a.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/fi-kbl-soraka/igt@kms_busy@basic-flip-pipe-a.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][7] ([fdo#111096] / [i915#323]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
#### Warnings ####
* igt@i915_selftest@live_gem_contexts:
- fi-byt-n2820: [DMESG-FAIL][9] ([i915#722]) -> [INCOMPLETE][10] ([i915#45])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html
* igt@kms_busy@basic-flip-pipe-a:
- fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#62] / [i915#92]) +6 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/fi-kbl-x1275/igt@kms_busy@basic-flip-pipe-a.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/fi-kbl-x1275/igt@kms_busy@basic-flip-pipe-a.html
* igt@kms_busy@basic-flip-pipe-b:
- fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) +6 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/fi-kbl-x1275/igt@kms_busy@basic-flip-pipe-b.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/fi-kbl-x1275/igt@kms_busy@basic-flip-pipe-b.html
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[i915#178]: https://gitlab.freedesktop.org/drm/intel/issues/178
[i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
[i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#722]: https://gitlab.freedesktop.org/drm/intel/issues/722
[i915#773]: https://gitlab.freedesktop.org/drm/intel/issues/773
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (51 -> 45)
------------------------------
Additional (1): fi-tgl-y
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7543 -> Patchwork_15693
CI-20190529: 20190529
CI_DRM_7543: 91752f80df9b582561be6bbac12ef780b12f606c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5345: 9e0c82b6d70065db894ececf2be8de372e983cf0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15693: cdf87f3344feb85d6caeae76996aeebf3f985b3d @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
cdf87f3344fe drm/i915: Nuke skl wm.dirty_pipes bitmask
9cc8ae13c86b drm/i915: Move linetime wms into the crtc state
6f0f126e1146 drm/i915: Polish WM_LINETIME register stuff
7e8583214760 drm/i915: Streamline skl_commit_modeset_enables()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Some cleanup near the SKL wm/ddb area (rev4)
2019-12-10 14:41 [Intel-gfx] [PATCH v2 0/6] drm/i915: Some cleanup near the SKL wm/ddb area Ville Syrjala
` (6 preceding siblings ...)
2019-12-11 20:19 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Some cleanup near the SKL wm/ddb area (rev4) Patchwork
@ 2019-12-12 6:29 ` Patchwork
7 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2019-12-12 6:29 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Some cleanup near the SKL wm/ddb area (rev4)
URL : https://patchwork.freedesktop.org/series/67930/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7543_full -> Patchwork_15693_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15693_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15693_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15693_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_balancer@bonded-slice:
- shard-tglb: NOTRUN -> [FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-tglb2/igt@gem_exec_balancer@bonded-slice.html
* igt@kms_cursor_crc@pipe-c-cursor-128x128-onscreen:
- shard-tglb: NOTRUN -> [DMESG-WARN][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-tglb3/igt@kms_cursor_crc@pipe-c-cursor-128x128-onscreen.html
* igt@perf@oa-exponents:
- shard-tglb: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-tglb3/igt@perf@oa-exponents.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-tglb6/igt@perf@oa-exponents.html
Known issues
------------
Here are the changes found in Patchwork_15693_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@bcs0-s3:
- shard-tglb: [PASS][5] -> [INCOMPLETE][6] ([i915#456])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-tglb2/igt@gem_ctx_isolation@bcs0-s3.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-tglb3/igt@gem_ctx_isolation@bcs0-s3.html
* igt@gem_ctx_isolation@rcs0-s3:
- shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#180])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-kbl2/igt@gem_ctx_isolation@rcs0-s3.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-kbl6/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_ctx_persistence@vcs0-mixed-process:
- shard-skl: [PASS][9] -> [FAIL][10] ([i915#679])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-skl6/igt@gem_ctx_persistence@vcs0-mixed-process.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-skl9/igt@gem_ctx_persistence@vcs0-mixed-process.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#110841])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-iclb3/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-iclb4/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_ctx_shared@q-smoketest-all:
- shard-tglb: [PASS][13] -> [INCOMPLETE][14] ([fdo#111735])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-tglb7/igt@gem_ctx_shared@q-smoketest-all.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-tglb9/igt@gem_ctx_shared@q-smoketest-all.html
* igt@gem_exec_schedule@out-order-bsd2:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109276]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-iclb2/igt@gem_exec_schedule@out-order-bsd2.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-iclb5/igt@gem_exec_schedule@out-order-bsd2.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#112146]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-iclb5/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-iclb4/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd1:
- shard-tglb: [PASS][19] -> [INCOMPLETE][20] ([fdo#111677])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-tglb9/igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd1.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-tglb6/igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd1.html
* igt@gem_persistent_relocs@forked-faulting-reloc-thrashing:
- shard-iclb: [PASS][21] -> [INCOMPLETE][22] ([i915#140] / [i915#530])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-iclb3/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-iclb7/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-skl: [PASS][23] -> [FAIL][24] ([i915#644])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-skl9/igt@gem_ppgtt@flink-and-close-vma-leak.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-skl1/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_sync@basic-store-each:
- shard-tglb: [PASS][25] -> [INCOMPLETE][26] ([i915#435] / [i915#472])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-tglb8/igt@gem_sync@basic-store-each.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-tglb4/igt@gem_sync@basic-store-each.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
- shard-snb: [PASS][27] -> [DMESG-WARN][28] ([fdo#111870])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-snb7/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
* igt@gem_workarounds@suspend-resume-context:
- shard-skl: [PASS][29] -> [INCOMPLETE][30] ([i915#69]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-skl2/igt@gem_workarounds@suspend-resume-context.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-skl4/igt@gem_workarounds@suspend-resume-context.html
* igt@i915_pm_rpm@system-suspend-modeset:
- shard-tglb: [PASS][31] -> [INCOMPLETE][32] ([i915#456] / [i915#460]) +2 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-tglb8/igt@i915_pm_rpm@system-suspend-modeset.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-tglb2/igt@i915_pm_rpm@system-suspend-modeset.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-180:
- shard-skl: [PASS][33] -> [DMESG-WARN][34] ([i915#109])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-skl3/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-skl7/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html
* igt@kms_cursor_legacy@cursor-vs-flip-legacy:
- shard-hsw: [PASS][35] -> [FAIL][36] ([i915#57])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-hsw4/igt@kms_cursor_legacy@cursor-vs-flip-legacy.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-hsw8/igt@kms_cursor_legacy@cursor-vs-flip-legacy.html
* igt@kms_flip@flip-vs-suspend:
- shard-tglb: [PASS][37] -> [INCOMPLETE][38] ([i915#460] / [i915#516])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-tglb6/igt@kms_flip@flip-vs-suspend.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-tglb2/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-apl: [PASS][39] -> [DMESG-WARN][40] ([i915#180]) +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip_tiling@flip-changes-tiling:
- shard-skl: [PASS][41] -> [FAIL][42] ([i915#699])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-skl5/igt@kms_flip_tiling@flip-changes-tiling.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-skl5/igt@kms_flip_tiling@flip-changes-tiling.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-blt:
- shard-tglb: [PASS][43] -> [FAIL][44] ([i915#49])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-blt.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-blt.html
* igt@kms_plane@pixel-format-pipe-a-planes:
- shard-kbl: [PASS][45] -> [INCOMPLETE][46] ([fdo#103665] / [i915#648] / [i915#667])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-kbl6/igt@kms_plane@pixel-format-pipe-a-planes.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-kbl4/igt@kms_plane@pixel-format-pipe-a-planes.html
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-kbl: [PASS][47] -> [INCOMPLETE][48] ([fdo#103665] / [i915#435] / [i915#648] / [i915#667])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-kbl4/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-kbl1/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][49] -> [FAIL][50] ([fdo#108145])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][51] -> [FAIL][52] ([fdo#108145] / [i915#265])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_cursor_mmap_gtt:
- shard-iclb: [PASS][53] -> [SKIP][54] ([fdo#109441])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_gtt.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-iclb5/igt@kms_psr@psr2_cursor_mmap_gtt.html
#### Possible fixes ####
* igt@gem_ctx_persistence@processes:
- shard-skl: [FAIL][55] ([i915#570]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-skl8/igt@gem_ctx_persistence@processes.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-skl2/igt@gem_ctx_persistence@processes.html
* igt@gem_exec_parallel@vcs1-fds:
- shard-iclb: [SKIP][57] ([fdo#112080]) -> [PASS][58] +5 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-iclb5/igt@gem_exec_parallel@vcs1-fds.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-iclb4/igt@gem_exec_parallel@vcs1-fds.html
* igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive:
- shard-snb: [TIMEOUT][59] ([i915#530]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-snb1/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-snb1/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-glk: [FAIL][61] ([i915#644]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-glk7/igt@gem_ppgtt@flink-and-close-vma-leak.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-glk3/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-snb: [DMESG-WARN][63] ([fdo#111870]) -> [PASS][64] +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* igt@gem_wait@await-vecs0:
- shard-skl: [DMESG-WARN][65] ([i915#109]) -> [PASS][66] +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-skl4/igt@gem_wait@await-vecs0.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-skl4/igt@gem_wait@await-vecs0.html
* igt@i915_pm_dc@dc5-dpms:
- shard-iclb: [FAIL][67] ([i915#447]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-iclb3/igt@i915_pm_dc@dc5-dpms.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-iclb5/igt@i915_pm_dc@dc5-dpms.html
* igt@i915_selftest@live_gt_timelines:
- shard-tglb: [INCOMPLETE][69] ([i915#455]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-tglb3/igt@i915_selftest@live_gt_timelines.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-tglb4/igt@i915_selftest@live_gt_timelines.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [DMESG-WARN][71] ([i915#180]) -> [PASS][72] +3 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-apl6/igt@i915_suspend@sysfs-reader.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-apl7/igt@i915_suspend@sysfs-reader.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][73] ([i915#180]) -> [PASS][74] +8 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-c-cursor-256x85-sliding:
- shard-skl: [FAIL][75] ([i915#54]) -> [PASS][76] +2 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-skl2/igt@kms_cursor_crc@pipe-c-cursor-256x85-sliding.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-skl4/igt@kms_cursor_crc@pipe-c-cursor-256x85-sliding.html
* igt@kms_cursor_crc@pipe-d-cursor-suspend:
- shard-tglb: [INCOMPLETE][77] ([i915#460]) -> [PASS][78] +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-tglb1/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-tglb8/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
* igt@kms_draw_crc@draw-method-rgb565-blt-xtiled:
- shard-tglb: [INCOMPLETE][79] ([i915#667]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-tglb9/igt@kms_draw_crc@draw-method-rgb565-blt-xtiled.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-tglb3/igt@kms_draw_crc@draw-method-rgb565-blt-xtiled.html
* igt@kms_draw_crc@draw-method-xrgb8888-render-ytiled:
- shard-tglb: [INCOMPLETE][81] ([fdo#112393] / [i915#667]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-tglb8/igt@kms_draw_crc@draw-method-xrgb8888-render-ytiled.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-tglb1/igt@kms_draw_crc@draw-method-xrgb8888-render-ytiled.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk: [FAIL][83] ([i915#79]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [FAIL][85] ([i915#79]) -> [PASS][86] +1 similar issue
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-skl3/igt@kms_flip@flip-vs-expired-vblank.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-skl6/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-onoff:
- shard-tglb: [INCOMPLETE][87] ([i915#474] / [i915#667]) -> [PASS][88] +1 similar issue
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-tglb9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-onoff.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-tglb: [FAIL][89] ([i915#49]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][91] ([fdo#108145] / [i915#265]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_setmode@basic:
- shard-kbl: [FAIL][93] ([i915#31]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-kbl3/igt@kms_setmode@basic.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-kbl6/igt@kms_setmode@basic.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [SKIP][95] ([fdo#109276]) -> [PASS][96] +7 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-iclb7/igt@prime_vgem@fence-wait-bsd2.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-iclb1/igt@prime_vgem@fence-wait-bsd2.html
#### Warnings ####
* igt@gem_eio@kms:
- shard-snb: [INCOMPLETE][97] ([i915#82]) -> [DMESG-WARN][98] ([i915#444])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-snb4/igt@gem_eio@kms.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-snb4/igt@gem_eio@kms.html
* igt@kms_plane@pixel-format-pipe-a-planes:
- shard-skl: [INCOMPLETE][99] ([fdo#112391] / [i915#648] / [i915#667]) -> [INCOMPLETE][100] ([fdo#112347] / [i915#648] / [i915#667])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7543/shard-skl7/igt@kms_plane@pixel-format-pipe-a-planes.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/shard-skl3/igt@kms_plane@pixel-format-pipe-a-planes.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#111677]: https://bugs.freedesktop.org/show_bug.cgi?id=111677
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
[fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[fdo#112347]: https://bugs.freedesktop.org/show_bug.cgi?id=112347
[fdo#112391]: https://bugs.freedesktop.org/show_bug.cgi?id=112391
[fdo#112393]: https://bugs.freedesktop.org/show_bug.cgi?id=112393
[i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
[i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#435]: https://gitlab.freedesktop.org/drm/intel/issues/435
[i915#444]: https://gitlab.freedesktop.org/drm/intel/issues/444
[i915#447]: https://gitlab.freedesktop.org/drm/intel/issues/447
[i915#455]: https://gitlab.freedesktop.org/drm/intel/issues/455
[i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
[i915#460]: https://gitlab.freedesktop.org/drm/intel/issues/460
[i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472
[i915#474]: https://gitlab.freedesktop.org/drm/intel/issues/474
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#516]: https://gitlab.freedesktop.org/drm/intel/issues/516
[i915#530]: https://gitlab.freedesktop.org/drm/intel/issues/530
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#57]: https://gitlab.freedesktop.org/drm/intel/issues/57
[i915#570]: https://gitlab.freedesktop.org/drm/intel/issues/570
[i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
[i915#648]: https://gitlab.freedesktop.org/drm/intel/issues/648
[i915#667]: https://gitlab.freedesktop.org/drm/intel/issues/667
[i915#679]: https://gitlab.freedesktop.org/drm/intel/issues/679
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#699]: https://gitlab.freedesktop.org/drm/intel/issues/699
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7543 -> Patchwork_15693
CI-20190529: 20190529
CI_DRM_7543: 91752f80df9b582561be6bbac12ef780b12f606c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5345: 9e0c82b6d70065db894ececf2be8de372e983cf0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15693: cdf87f3344feb85d6caeae76996aeebf3f985b3d @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15693/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2019-12-12 6:29 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-12-10 14:41 [Intel-gfx] [PATCH v2 0/6] drm/i915: Some cleanup near the SKL wm/ddb area Ville Syrjala
2019-12-10 14:41 ` [Intel-gfx] [PATCH v2 1/4] drm/i915: Streamline skl_commit_modeset_enables() Ville Syrjala
2019-12-10 14:41 ` [Intel-gfx] [PATCH v2 2/4] drm/i915: Polish WM_LINETIME register stuff Ville Syrjala
2019-12-10 14:41 ` [Intel-gfx] [PATCH v2 3/4] drm/i915: Move linetime wms into the crtc state Ville Syrjala
2019-12-11 14:25 ` [Intel-gfx] [PATCH v3 " Ville Syrjala
2019-12-10 14:41 ` [Intel-gfx] [PATCH v2 4/4] drm/i915: Nuke skl wm.dirty_pipes bitmask Ville Syrjala
2019-12-10 14:46 ` [Intel-gfx] [PATCH v2 0/6] drm/i915: Some cleanup near the SKL wm/ddb area Ville Syrjälä
2019-12-11 0:59 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Some cleanup near the SKL wm/ddb area (rev3) Patchwork
2019-12-11 20:19 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Some cleanup near the SKL wm/ddb area (rev4) Patchwork
2019-12-12 6:29 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.