From: Marek Behun <marek.behun@nic.cz>
To: Andrew Lunn <andrew@lunn.ch>
Cc: Baruch Siach <baruch@tkos.co.il>,
Vivien Didelot <vivien.didelot@gmail.com>,
netdev@vger.kernel.org,
Denis Odintsov <d.odintsov@traviangames.com>,
Hubert Feurstein <h.feurstein@gmail.com>
Subject: Re: [BUG] mv88e6xxx: tx regression in v5.3
Date: Thu, 12 Dec 2019 20:41:41 +0100 [thread overview]
Message-ID: <20191212204141.16a406cd@nic.cz> (raw)
In-Reply-To: <20191212193129.GF30053@lunn.ch>
On Thu, 12 Dec 2019 20:31:29 +0100
Andrew Lunn <andrew@lunn.ch> wrote:
> > diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
> > index bd881497b872..8f61cae9d3b0 100644
> > --- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
> > +++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
> > @@ -408,6 +408,11 @@ port@5 {
> > reg = <5>;
> > label = "cpu";
> > ethernet = <&cp1_eth2>;
> > +
> > + fixed-link {
> > + speed = <2500>;
> > + full-duplex;
> > + };
> > };
> > };
>
> The DSA driver is expected to configure the CPU port at its maximum
> speed. You should only add a fixed link if you need to slow it down.
> I expect 2500 is the maximum speed of this port.
>
> Andrew
Baruch, if the cpu port is in 2500 base-x, remove the fixed-link and do
this:
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&cp1_eth2>;
phy-mode = "2500base-x";
managed = "in-band-status";
};
Andrew, if the dsa driver is expected to do that, the code certainly
does not do so. For example in mv88e6xxx_port_set_cmode you have:
/* Default to a slow mode, so freeing up SERDES interfaces for
* other ports which might use them for SFPs.
*/
if (mode == PHY_INTERFACE_MODE_NA)
mode = PHY_INTERFACE_MODE_1000BASEX;
Marek
next prev parent reply other threads:[~2019-12-12 19:41 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-11 9:48 [BUG] mv88e6xxx: tx regression in v5.3 Baruch Siach
2019-12-11 13:11 ` Andrew Lunn
2019-12-11 17:07 ` Baruch Siach
2019-12-11 17:49 ` Andrew Lunn
2019-12-12 8:50 ` Baruch Siach
2019-12-12 13:14 ` Andrew Lunn
2019-12-12 14:19 ` Andreas Tobler
2019-12-12 15:08 ` Baruch Siach
2019-12-12 15:13 ` Andrew Lunn
2019-12-12 15:23 ` Baruch Siach
2019-12-12 18:17 ` Baruch Siach
2019-12-12 18:32 ` Marek Behun
2019-12-12 18:48 ` Baruch Siach
2019-12-12 18:36 ` Marek Behun
2019-12-12 19:06 ` Baruch Siach
2019-12-12 19:31 ` Andrew Lunn
2019-12-12 19:41 ` Marek Behun [this message]
2019-12-12 20:49 ` Andrew Lunn
2019-12-15 10:13 ` Baruch Siach
2019-12-15 11:10 ` Baruch Siach
2019-12-15 14:53 ` Andrew Lunn
2019-12-15 15:08 ` Baruch Siach
2019-12-15 16:14 ` Andrew Lunn
2019-12-17 18:26 ` Baruch Siach
2019-12-18 14:30 ` Marek Behún
2019-12-18 16:04 ` Baruch Siach
2019-12-19 9:04 ` Baruch Siach
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