[Intel-gfx] [PATCH v2 1/7] drm/i915/guc: Merge communication_stop and communication_disable

[Intel-gfx] [PATCH v2 1/7] drm/i915/guc: Merge communication_stop and communication_disable

[Daniele Ceraolo Spurio]

The only difference from the GuC POV between guc_communication_stop and
guc_communication_disable is that the former can be called after GuC
has been reset. Instead of having two separate paths, we can just skip
the call into GuC in the disabling path and re-use that.

Note that by using the disable() path instead of the stop() one there
are two additional changes in SW side for the stop path:

- interrupts are now disabled before disabling the CT, which is ok
  because we do not want interrupts with CT disabled;
- guc_get_mmio_msg() is called in the stop case as well, which is ok
  because if there are errors before the reset we do want to record
  them.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 14 ++++++++------
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h |  5 -----
 drivers/gpu/drm/i915/gt/uc/intel_uc.c     | 18 ++----------------
 3 files changed, 10 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 5fb7f957edf9..f74ba4750a94 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -241,12 +241,14 @@ static void ctch_disable(struct intel_guc *guc,
 
 	ctch->enabled = false;
 
-	guc_action_deregister_ct_buffer(guc,
-					ctch->owner,
-					INTEL_GUC_CT_BUFFER_TYPE_SEND);
-	guc_action_deregister_ct_buffer(guc,
-					ctch->owner,
-					INTEL_GUC_CT_BUFFER_TYPE_RECV);
+	if (intel_guc_is_running(guc)) {
+		guc_action_deregister_ct_buffer(guc,
+						ctch->owner,
+						INTEL_GUC_CT_BUFFER_TYPE_SEND);
+		guc_action_deregister_ct_buffer(guc,
+						ctch->owner,
+						INTEL_GUC_CT_BUFFER_TYPE_RECV);
+	}
 }
 
 static u32 ctch_get_next_fence(struct intel_guc_ct_channel *ctch)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
index 7c24d83f5c24..77c80d6cc25d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
@@ -81,11 +81,6 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct);
 int intel_guc_ct_enable(struct intel_guc_ct *ct);
 void intel_guc_ct_disable(struct intel_guc_ct *ct);
 
-static inline void intel_guc_ct_stop(struct intel_guc_ct *ct)
-{
-	ct->host_channel.enabled = false;
-}
-
 int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len,
 		      u32 *response_buf, u32 response_buf_size);
 void intel_guc_to_host_event_handler_ct(struct intel_guc *guc);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index f42952403c0b..6e17e449e0a8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -224,7 +224,7 @@ static int guc_enable_communication(struct intel_guc *guc)
 	return 0;
 }
 
-static void __guc_stop_communication(struct intel_guc *guc)
+static void guc_disable_communication(struct intel_guc *guc)
 {
 	/*
 	 * Events generated during or after CT disable are logged by guc in
@@ -237,20 +237,6 @@ static void __guc_stop_communication(struct intel_guc *guc)
 
 	guc->send = intel_guc_send_nop;
 	guc->handler = intel_guc_to_host_event_handler_nop;
-}
-
-static void guc_stop_communication(struct intel_guc *guc)
-{
-	intel_guc_ct_stop(&guc->ct);
-
-	__guc_stop_communication(guc);
-
-	DRM_INFO("GuC communication stopped\n");
-}
-
-static void guc_disable_communication(struct intel_guc *guc)
-{
-	__guc_stop_communication(guc);
 
 	intel_guc_ct_disable(&guc->ct);
 
@@ -556,7 +542,7 @@ void intel_uc_reset_prepare(struct intel_uc *uc)
 	if (!intel_guc_is_running(guc))
 		return;
 
-	guc_stop_communication(guc);
+	guc_disable_communication(guc);
 	__uc_sanitize(uc);
 }
 
-- 
2.23.0

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[Intel-gfx] [PATCH v2 2/7] drm/i915/guc/ct: Drop guards in enable/disable calls

[Daniele Ceraolo Spurio]

We track the status of the GuC much more closely now and we expect the
enable/disable functions to be correctly called only once. If this isn't
true we do want to flag it as a flow failure (via the BUG_ON in the ctch
functions) and not silently ignore the call.

Suggested-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index f74ba4750a94..b23b46619742 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -862,9 +862,6 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
 	struct intel_guc *guc = ct_to_guc(ct);
 	struct intel_guc_ct_channel *ctch = &ct->host_channel;
 
-	if (ctch->enabled)
-		return 0;
-
 	return ctch_enable(guc, ctch);
 }
 
@@ -877,8 +874,5 @@ void intel_guc_ct_disable(struct intel_guc_ct *ct)
 	struct intel_guc *guc = ct_to_guc(ct);
 	struct intel_guc_ct_channel *ctch = &ct->host_channel;
 
-	if (!ctch->enabled)
-		return;
-
 	ctch_disable(guc, ctch);
 }
-- 
2.23.0

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[Intel-gfx] [PATCH v2 3/7] drm/i915/guc/ct: Stop expecting multiple CT channels

[Daniele Ceraolo Spurio]

The GuC supports having multiple CT buffer pairs and we designed our
implementation with that in mind. However, the different channels are not
processed in parallel within the GuC, so there is very little advantage
in having multiple channels (independent locks?), compared to the
drawbacks (one channel can starve the other if messages keep being
submitted to it). Given this, it is unlikely we'll ever add a second
channel and therefore we can simplify our code by removing the
flexibility.

v2: split substructure grouping to separate patch, improve docs (Michal)

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 219 ++++++++--------------
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h |  43 ++---
 2 files changed, 90 insertions(+), 172 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index b23b46619742..4e20f6c48a4f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -37,9 +37,6 @@ static void ct_incoming_request_worker_func(struct work_struct *w);
  */
 void intel_guc_ct_init_early(struct intel_guc_ct *ct)
 {
-	/* we're using static channel owners */
-	ct->host_channel.owner = CTB_OWNER_HOST;
-
 	spin_lock_init(&ct->lock);
 	INIT_LIST_HEAD(&ct->pending_requests);
 	INIT_LIST_HEAD(&ct->incoming_requests);
@@ -64,14 +61,13 @@ static inline const char *guc_ct_buffer_type_to_str(u32 type)
 }
 
 static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc,
-				    u32 cmds_addr, u32 size, u32 owner)
+				    u32 cmds_addr, u32 size)
 {
-	CT_DEBUG_DRIVER("CT: desc %p init addr=%#x size=%u owner=%u\n",
-			desc, cmds_addr, size, owner);
+	CT_DEBUG_DRIVER("CT: init addr=%#x size=%u\n", cmds_addr, size);
 	memset(desc, 0, sizeof(*desc));
 	desc->addr = cmds_addr;
 	desc->size = size;
-	desc->owner = owner;
+	desc->owner = CTB_OWNER_HOST;
 }
 
 static void guc_ct_buffer_desc_reset(struct guc_ct_buffer_desc *desc)
@@ -104,12 +100,11 @@ static int guc_action_register_ct_buffer(struct intel_guc *guc,
 }
 
 static int guc_action_deregister_ct_buffer(struct intel_guc *guc,
-					   u32 owner,
 					   u32 type)
 {
 	u32 action[] = {
 		INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER,
-		owner,
+		CTB_OWNER_HOST,
 		type
 	};
 	int err;
@@ -117,19 +112,27 @@ static int guc_action_deregister_ct_buffer(struct intel_guc *guc,
 	/* Can't use generic send(), CT deregistration must go over MMIO */
 	err = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
 	if (err)
-		DRM_ERROR("CT: deregister %s buffer failed; owner=%d err=%d\n",
-			  guc_ct_buffer_type_to_str(type), owner, err);
+		DRM_ERROR("CT: deregister %s buffer failed; err=%d\n",
+			  guc_ct_buffer_type_to_str(type), err);
 	return err;
 }
 
-static int ctch_init(struct intel_guc *guc,
-		     struct intel_guc_ct_channel *ctch)
+/**
+ * intel_guc_ct_init - Init buffer-based communication
+ * @ct: pointer to CT struct
+ *
+ * Allocate memory required for buffer-based communication.
+ *
+ * Return: 0 on success, a negative errno code on failure.
+ */
+int intel_guc_ct_init(struct intel_guc_ct *ct)
 {
+	struct intel_guc *guc = ct_to_guc(ct);
 	void *blob;
 	int err;
 	int i;
 
-	GEM_BUG_ON(ctch->vma);
+	GEM_BUG_ON(ct->vma);
 
 	/* We allocate 1 page to hold both descriptors and both buffers.
 	 *       ___________.....................
@@ -153,57 +156,65 @@ static int ctch_init(struct intel_guc *guc,
 	 * other code will need updating as well.
 	 */
 
-	err = intel_guc_allocate_and_map_vma(guc, PAGE_SIZE, &ctch->vma, &blob);
+	err = intel_guc_allocate_and_map_vma(guc, PAGE_SIZE, &ct->vma, &blob);
 	if (err) {
-		CT_DEBUG_DRIVER("CT: channel %d initialization failed; err=%d\n",
-				ctch->owner, err);
+		DRM_ERROR("CT: channel allocation failed; err=%d\n", err);
 		return err;
 	}
 
 	CT_DEBUG_DRIVER("CT: vma base=%#x\n",
-			intel_guc_ggtt_offset(guc, ctch->vma));
+			intel_guc_ggtt_offset(guc, ct->vma));
 
 	/* store pointers to desc and cmds */
-	for (i = 0; i < ARRAY_SIZE(ctch->ctbs); i++) {
-		GEM_BUG_ON((i != CTB_SEND) && (i != CTB_RECV));
-		ctch->ctbs[i].desc = blob + PAGE_SIZE/4 * i;
-		ctch->ctbs[i].cmds = blob + PAGE_SIZE/4 * i + PAGE_SIZE/2;
+	for (i = 0; i < ARRAY_SIZE(ct->ctbs); i++) {
+		GEM_BUG_ON((i !=  CTB_SEND) && (i != CTB_RECV));
+		ct->ctbs[i].desc = blob + PAGE_SIZE/4 * i;
+		ct->ctbs[i].cmds = blob + PAGE_SIZE/4 * i + PAGE_SIZE/2;
 	}
 
 	return 0;
 }
 
-static void ctch_fini(struct intel_guc *guc,
-		      struct intel_guc_ct_channel *ctch)
+/**
+ * intel_guc_ct_fini - Fini buffer-based communication
+ * @ct: pointer to CT struct
+ *
+ * Deallocate memory required for buffer-based communication.
+ */
+void intel_guc_ct_fini(struct intel_guc_ct *ct)
 {
-	GEM_BUG_ON(ctch->enabled);
+	GEM_BUG_ON(ct->enabled);
 
-	i915_vma_unpin_and_release(&ctch->vma, I915_VMA_RELEASE_MAP);
+	i915_vma_unpin_and_release(&ct->vma, I915_VMA_RELEASE_MAP);
 }
 
-static int ctch_enable(struct intel_guc *guc,
-		       struct intel_guc_ct_channel *ctch)
+/**
+ * intel_guc_ct_enable - Enable buffer based command transport.
+ * @ct: pointer to CT struct
+ *
+ * Return: 0 on success, a negative errno code on failure.
+ */
+int intel_guc_ct_enable(struct intel_guc_ct *ct)
 {
+	struct intel_guc *guc = ct_to_guc(ct);
 	u32 base;
 	int err;
 	int i;
 
-	GEM_BUG_ON(!ctch->vma);
-
-	GEM_BUG_ON(ctch->enabled);
+	GEM_BUG_ON(ct->enabled);
 
 	/* vma should be already allocated and map'ed */
-	base = intel_guc_ggtt_offset(guc, ctch->vma);
+	GEM_BUG_ON(!ct->vma);
+	base = intel_guc_ggtt_offset(guc, ct->vma);
 
 	/* (re)initialize descriptors
 	 * cmds buffers are in the second half of the blob page
 	 */
-	for (i = 0; i < ARRAY_SIZE(ctch->ctbs); i++) {
+	for (i = 0; i < ARRAY_SIZE(ct->ctbs); i++) {
 		GEM_BUG_ON((i != CTB_SEND) && (i != CTB_RECV));
-		guc_ct_buffer_desc_init(ctch->ctbs[i].desc,
+		guc_ct_buffer_desc_init(ct->ctbs[i].desc,
 					base + PAGE_SIZE/4 * i + PAGE_SIZE/2,
-					PAGE_SIZE/4,
-					ctch->owner);
+					PAGE_SIZE/4);
 	}
 
 	/* register buffers, starting wirh RECV buffer
@@ -221,40 +232,42 @@ static int ctch_enable(struct intel_guc *guc,
 	if (unlikely(err))
 		goto err_deregister;
 
-	ctch->enabled = true;
+	ct->enabled = true;
 
 	return 0;
 
 err_deregister:
 	guc_action_deregister_ct_buffer(guc,
-					ctch->owner,
 					INTEL_GUC_CT_BUFFER_TYPE_RECV);
 err_out:
-	DRM_ERROR("CT: can't open channel %d; err=%d\n", ctch->owner, err);
+	DRM_ERROR("CT: can't open channel; err=%d\n", err);
 	return err;
 }
 
-static void ctch_disable(struct intel_guc *guc,
-			 struct intel_guc_ct_channel *ctch)
+/**
+ * intel_guc_ct_disable - Disable buffer based command transport.
+ * @ct: pointer to CT struct
+ */
+void intel_guc_ct_disable(struct intel_guc_ct *ct)
 {
-	GEM_BUG_ON(!ctch->enabled);
+	struct intel_guc *guc = ct_to_guc(ct);
 
-	ctch->enabled = false;
+	GEM_BUG_ON(!ct->enabled);
+
+	ct->enabled = false;
 
 	if (intel_guc_is_running(guc)) {
 		guc_action_deregister_ct_buffer(guc,
-						ctch->owner,
 						INTEL_GUC_CT_BUFFER_TYPE_SEND);
 		guc_action_deregister_ct_buffer(guc,
-						ctch->owner,
 						INTEL_GUC_CT_BUFFER_TYPE_RECV);
 	}
 }
 
-static u32 ctch_get_next_fence(struct intel_guc_ct_channel *ctch)
+static u32 ct_get_next_fence(struct intel_guc_ct *ct)
 {
 	/* For now it's trivial */
-	return ++ctch->next_fence;
+	return ++ct->next_fence;
 }
 
 /**
@@ -427,27 +440,26 @@ static int wait_for_ct_request_update(struct ct_request *req, u32 *status)
 	return err;
 }
 
-static int ctch_send(struct intel_guc_ct *ct,
-		     struct intel_guc_ct_channel *ctch,
-		     const u32 *action,
-		     u32 len,
-		     u32 *response_buf,
-		     u32 response_buf_size,
-		     u32 *status)
+static int ct_send(struct intel_guc_ct *ct,
+		   const u32 *action,
+		   u32 len,
+		   u32 *response_buf,
+		   u32 response_buf_size,
+		   u32 *status)
 {
-	struct intel_guc_ct_buffer *ctb = &ctch->ctbs[CTB_SEND];
+	struct intel_guc_ct_buffer *ctb = &ct->ctbs[CTB_SEND];
 	struct guc_ct_buffer_desc *desc = ctb->desc;
 	struct ct_request request;
 	unsigned long flags;
 	u32 fence;
 	int err;
 
-	GEM_BUG_ON(!ctch->enabled);
+	GEM_BUG_ON(!ct->enabled);
 	GEM_BUG_ON(!len);
 	GEM_BUG_ON(len & ~GUC_CT_MSG_LEN_MASK);
 	GEM_BUG_ON(!response_buf && response_buf_size);
 
-	fence = ctch_get_next_fence(ctch);
+	fence = ct_get_next_fence(ct);
 	request.fence = fence;
 	request.status = 0;
 	request.response_len = response_buf_size;
@@ -502,14 +514,12 @@ int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len,
 		      u32 *response_buf, u32 response_buf_size)
 {
 	struct intel_guc_ct *ct = &guc->ct;
-	struct intel_guc_ct_channel *ctch = &ct->host_channel;
 	u32 status = ~0; /* undefined */
 	int ret;
 
 	mutex_lock(&guc->send_mutex);
 
-	ret = ctch_send(ct, ctch, action, len, response_buf, response_buf_size,
-			&status);
+	ret = ct_send(ct, action, len, response_buf, response_buf_size, &status);
 	if (unlikely(ret < 0)) {
 		DRM_ERROR("CT: send action %#X failed; err=%d status=%#X\n",
 			  action[0], ret, status);
@@ -772,14 +782,18 @@ static int ct_handle_request(struct intel_guc_ct *ct, const u32 *msg)
 	return 0;
 }
 
-static void ct_process_host_channel(struct intel_guc_ct *ct)
+/*
+ * When we're communicating with the GuC over CT, GuC uses events
+ * to notify us about new messages being posted on the RECV buffer.
+ */
+void intel_guc_to_host_event_handler_ct(struct intel_guc *guc)
 {
-	struct intel_guc_ct_channel *ctch = &ct->host_channel;
-	struct intel_guc_ct_buffer *ctb = &ctch->ctbs[CTB_RECV];
+	struct intel_guc_ct *ct = &guc->ct;
+	struct intel_guc_ct_buffer *ctb = &ct->ctbs[CTB_RECV];
 	u32 msg[GUC_CT_MSG_LEN_MASK + 1]; /* one extra dw for the header */
 	int err = 0;
 
-	if (!ctch->enabled)
+	if (!ct->enabled)
 		return;
 
 	do {
@@ -799,80 +813,3 @@ static void ct_process_host_channel(struct intel_guc_ct *ct)
 	}
 }
 
-/*
- * When we're communicating with the GuC over CT, GuC uses events
- * to notify us about new messages being posted on the RECV buffer.
- */
-void intel_guc_to_host_event_handler_ct(struct intel_guc *guc)
-{
-	struct intel_guc_ct *ct = &guc->ct;
-
-	ct_process_host_channel(ct);
-}
-
-/**
- * intel_guc_ct_init - Init CT communication
- * @ct: pointer to CT struct
- *
- * Allocate memory required for communication via
- * the CT channel.
- *
- * Return: 0 on success, a negative errno code on failure.
- */
-int intel_guc_ct_init(struct intel_guc_ct *ct)
-{
-	struct intel_guc *guc = ct_to_guc(ct);
-	struct intel_guc_ct_channel *ctch = &ct->host_channel;
-	int err;
-
-	err = ctch_init(guc, ctch);
-	if (unlikely(err)) {
-		DRM_ERROR("CT: can't open channel %d; err=%d\n",
-			  ctch->owner, err);
-		return err;
-	}
-
-	GEM_BUG_ON(!ctch->vma);
-	return 0;
-}
-
-/**
- * intel_guc_ct_fini - Fini CT communication
- * @ct: pointer to CT struct
- *
- * Deallocate memory required for communication via
- * the CT channel.
- */
-void intel_guc_ct_fini(struct intel_guc_ct *ct)
-{
-	struct intel_guc *guc = ct_to_guc(ct);
-	struct intel_guc_ct_channel *ctch = &ct->host_channel;
-
-	ctch_fini(guc, ctch);
-}
-
-/**
- * intel_guc_ct_enable - Enable buffer based command transport.
- * @ct: pointer to CT struct
- *
- * Return: 0 on success, a negative errno code on failure.
- */
-int intel_guc_ct_enable(struct intel_guc_ct *ct)
-{
-	struct intel_guc *guc = ct_to_guc(ct);
-	struct intel_guc_ct_channel *ctch = &ct->host_channel;
-
-	return ctch_enable(guc, ctch);
-}
-
-/**
- * intel_guc_ct_disable - Disable buffer based command transport.
- * @ct: pointer to CT struct
- */
-void intel_guc_ct_disable(struct intel_guc_ct *ct)
-{
-	struct intel_guc *guc = ct_to_guc(ct);
-	struct intel_guc_ct_channel *ctch = &ct->host_channel;
-
-	ctch_disable(guc, ctch);
-}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
index 77c80d6cc25d..6e3d789b9f01 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
@@ -35,44 +35,25 @@ struct intel_guc_ct_buffer {
 	u32 *cmds;
 };
 
-/** Represents pair of command transport buffers.
- *
- * Buffers go in pairs to allow bi-directional communication.
- * To simplify the code we place both of them in the same vma.
- * Buffers from the same pair must share unique owner id.
- *
- * @vma: pointer to the vma with pair of CT buffers
- * @ctbs: buffers for sending(0) and receiving(1) commands
- * @owner: unique identifier
- * @next_fence: fence to be used with next send command
- */
-struct intel_guc_ct_channel {
-	struct i915_vma *vma;
-	struct intel_guc_ct_buffer ctbs[2];
-	u32 owner;
-	u32 next_fence;
-	bool enabled;
-};
 
-/** Holds all command transport channels.
+/** Top-level structure for Command Transport related data
  *
- * @host_channel: main channel used by the host
+ * Includes a pair of CT buffers for bi-directional communication and tracking
+ * for the H2G and G2H requests sent and received through the buffers.
  */
 struct intel_guc_ct {
-	struct intel_guc_ct_channel host_channel;
-	/* other channels are tbd */
-
-	/** @lock: protects pending requests list */
-	spinlock_t lock;
+	struct i915_vma *vma;
+	bool enabled;
 
-	/** @pending_requests: list of requests waiting for response */
-	struct list_head pending_requests;
+	/* buffers for sending(0) and receiving(1) commands */
+	struct intel_guc_ct_buffer ctbs[2];
 
-	/** @incoming_requests: list of incoming requests */
-	struct list_head incoming_requests;
+	u32 next_fence; /* fence to be used with next send command */
 
-	/** @worker: worker for handling incoming requests */
-	struct work_struct worker;
+	spinlock_t lock; /* protects pending requests list */
+	struct list_head pending_requests; /* requests waiting for response */
+	struct list_head incoming_requests; /* incoming requests */
+	struct work_struct worker; /* handler for incoming requests */
 };
 
 void intel_guc_ct_init_early(struct intel_guc_ct *ct);
-- 
2.23.0

_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v2 4/7] drm/i915/guc/ct: Group request-related variables in a sub-structure

[Daniele Ceraolo Spurio]

For better isolation of the request tracking from the rest of the
CT-related data.

v2: split to separate patch, move next_fence to substructure (Michal)

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 47 ++++++++++++-----------
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 13 ++++---
 2 files changed, 32 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 4e20f6c48a4f..f22cd9b2311b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -37,10 +37,10 @@ static void ct_incoming_request_worker_func(struct work_struct *w);
  */
 void intel_guc_ct_init_early(struct intel_guc_ct *ct)
 {
-	spin_lock_init(&ct->lock);
-	INIT_LIST_HEAD(&ct->pending_requests);
-	INIT_LIST_HEAD(&ct->incoming_requests);
-	INIT_WORK(&ct->worker, ct_incoming_request_worker_func);
+	spin_lock_init(&ct->requests.lock);
+	INIT_LIST_HEAD(&ct->requests.pending);
+	INIT_LIST_HEAD(&ct->requests.incoming);
+	INIT_WORK(&ct->requests.worker, ct_incoming_request_worker_func);
 }
 
 static inline struct intel_guc *ct_to_guc(struct intel_guc_ct *ct)
@@ -267,7 +267,7 @@ void intel_guc_ct_disable(struct intel_guc_ct *ct)
 static u32 ct_get_next_fence(struct intel_guc_ct *ct)
 {
 	/* For now it's trivial */
-	return ++ct->next_fence;
+	return ++ct->requests.next_fence;
 }
 
 /**
@@ -465,9 +465,9 @@ static int ct_send(struct intel_guc_ct *ct,
 	request.response_len = response_buf_size;
 	request.response_buf = response_buf;
 
-	spin_lock_irqsave(&ct->lock, flags);
-	list_add_tail(&request.link, &ct->pending_requests);
-	spin_unlock_irqrestore(&ct->lock, flags);
+	spin_lock_irqsave(&ct->requests.lock, flags);
+	list_add_tail(&request.link, &ct->requests.pending);
+	spin_unlock_irqrestore(&ct->requests.lock, flags);
 
 	err = ctb_write(ctb, action, len, fence, !!response_buf);
 	if (unlikely(err))
@@ -500,9 +500,9 @@ static int ct_send(struct intel_guc_ct *ct,
 	}
 
 unlink:
-	spin_lock_irqsave(&ct->lock, flags);
+	spin_lock_irqsave(&ct->requests.lock, flags);
 	list_del(&request.link);
-	spin_unlock_irqrestore(&ct->lock, flags);
+	spin_unlock_irqrestore(&ct->requests.lock, flags);
 
 	return err;
 }
@@ -650,8 +650,8 @@ static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg)
 
 	CT_DEBUG_DRIVER("CT: response fence %u status %#x\n", fence, status);
 
-	spin_lock(&ct->lock);
-	list_for_each_entry(req, &ct->pending_requests, link) {
+	spin_lock(&ct->requests.lock);
+	list_for_each_entry(req, &ct->requests.pending, link) {
 		if (unlikely(fence != req->fence)) {
 			CT_DEBUG_DRIVER("CT: request %u awaits response\n",
 					req->fence);
@@ -669,7 +669,7 @@ static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg)
 		found = true;
 		break;
 	}
-	spin_unlock(&ct->lock);
+	spin_unlock(&ct->requests.lock);
 
 	if (!found)
 		DRM_ERROR("CT: unsolicited response %*ph\n", 4 * msglen, msg);
@@ -707,13 +707,13 @@ static bool ct_process_incoming_requests(struct intel_guc_ct *ct)
 	u32 *payload;
 	bool done;
 
-	spin_lock_irqsave(&ct->lock, flags);
-	request = list_first_entry_or_null(&ct->incoming_requests,
+	spin_lock_irqsave(&ct->requests.lock, flags);
+	request = list_first_entry_or_null(&ct->requests.incoming,
 					   struct ct_incoming_request, link);
 	if (request)
 		list_del(&request->link);
-	done = !!list_empty(&ct->incoming_requests);
-	spin_unlock_irqrestore(&ct->lock, flags);
+	done = !!list_empty(&ct->requests.incoming);
+	spin_unlock_irqrestore(&ct->requests.lock, flags);
 
 	if (!request)
 		return true;
@@ -731,12 +731,13 @@ static bool ct_process_incoming_requests(struct intel_guc_ct *ct)
 
 static void ct_incoming_request_worker_func(struct work_struct *w)
 {
-	struct intel_guc_ct *ct = container_of(w, struct intel_guc_ct, worker);
+	struct intel_guc_ct *ct =
+		container_of(w, struct intel_guc_ct, requests.worker);
 	bool done;
 
 	done = ct_process_incoming_requests(ct);
 	if (!done)
-		queue_work(system_unbound_wq, &ct->worker);
+		queue_work(system_unbound_wq, &ct->requests.worker);
 }
 
 /**
@@ -774,11 +775,11 @@ static int ct_handle_request(struct intel_guc_ct *ct, const u32 *msg)
 	}
 	memcpy(request->msg, msg, 4 * msglen);
 
-	spin_lock_irqsave(&ct->lock, flags);
-	list_add_tail(&request->link, &ct->incoming_requests);
-	spin_unlock_irqrestore(&ct->lock, flags);
+	spin_lock_irqsave(&ct->requests.lock, flags);
+	list_add_tail(&request->link, &ct->requests.incoming);
+	spin_unlock_irqrestore(&ct->requests.lock, flags);
 
-	queue_work(system_unbound_wq, &ct->worker);
+	queue_work(system_unbound_wq, &ct->requests.worker);
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
index 6e3d789b9f01..29a026dc3a13 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
@@ -48,12 +48,15 @@ struct intel_guc_ct {
 	/* buffers for sending(0) and receiving(1) commands */
 	struct intel_guc_ct_buffer ctbs[2];
 
-	u32 next_fence; /* fence to be used with next send command */
+	struct {
+		u32 next_fence; /* fence to be used with next request to send */
 
-	spinlock_t lock; /* protects pending requests list */
-	struct list_head pending_requests; /* requests waiting for response */
-	struct list_head incoming_requests; /* incoming requests */
-	struct work_struct worker; /* handler for incoming requests */
+		spinlock_t lock; /* protects pending requests list */
+		struct list_head pending; /* requests waiting for response */
+
+		struct list_head incoming; /* incoming requests */
+		struct work_struct worker; /* handler for incoming requests */
+	} requests;
 };
 
 void intel_guc_ct_init_early(struct intel_guc_ct *ct);
-- 
2.23.0

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[Intel-gfx] [PATCH v2 5/7] drm/i915/guc: Remove function pointers for send/receive calls

[Daniele Ceraolo Spurio]

Since we started using CT buffers on all gens, the function pointers can
only be set to either the _nop() or the _ct() functions. Since the
_nop() case applies to when the CT are disabled, we can just handle that
case in the _ct() functions and call them directly.

v2: keep intel_guc_send() and make the CT send/receive functions work on
    intel_guc_ct. (Michal)

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc.c        | 14 -------------
 drivers/gpu/drm/i915/gt/uc/intel_guc.h        | 18 ++++-------------
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c     | 16 ++++++++++-----
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h     |  9 +++++++--
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  1 -
 drivers/gpu/drm/i915/gt/uc/intel_uc.c         | 20 +++++++------------
 6 files changed, 29 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 922a19635d20..daebfec0034c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -177,8 +177,6 @@ void intel_guc_init_early(struct intel_guc *guc)
 
 	mutex_init(&guc->send_mutex);
 	spin_lock_init(&guc->irq_lock);
-	guc->send = intel_guc_send_nop;
-	guc->handler = intel_guc_to_host_event_handler_nop;
 	if (INTEL_GEN(i915) >= 11) {
 		guc->notify = gen11_guc_raise_irq;
 		guc->interrupts.reset = gen11_reset_guc_interrupts;
@@ -403,18 +401,6 @@ void intel_guc_fini(struct intel_guc *guc)
 	intel_uc_fw_cleanup_fetch(&guc->fw);
 }
 
-int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len,
-		       u32 *response_buf, u32 response_buf_size)
-{
-	WARN(1, "Unexpected send: action=%#x\n", *action);
-	return -ENODEV;
-}
-
-void intel_guc_to_host_event_handler_nop(struct intel_guc *guc)
-{
-	WARN(1, "Unexpected event: no suitable handler\n");
-}
-
 /*
  * This function implements the MMIO based host to GuC interface.
  */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index cd09c912e361..253b1ac7716e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -70,13 +70,6 @@ struct intel_guc {
 	/* To serialize the intel_guc_send actions */
 	struct mutex send_mutex;
 
-	/* GuC's FW specific send function */
-	int (*send)(struct intel_guc *guc, const u32 *data, u32 len,
-		    u32 *response_buf, u32 response_buf_size);
-
-	/* GuC's FW specific event handler function */
-	void (*handler)(struct intel_guc *guc);
-
 	/* GuC's FW specific notify function */
 	void (*notify)(struct intel_guc *guc);
 };
@@ -84,14 +77,15 @@ struct intel_guc {
 static
 inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
 {
-	return guc->send(guc, action, len, NULL, 0);
+	return intel_guc_ct_send(&guc->ct, action, len, NULL, 0);
 }
 
 static inline int
 intel_guc_send_and_receive(struct intel_guc *guc, const u32 *action, u32 len,
 			   u32 *response_buf, u32 response_buf_size)
 {
-	return guc->send(guc, action, len, response_buf, response_buf_size);
+	return intel_guc_ct_send(&guc->ct, action, len,
+				 response_buf, response_buf_size);
 }
 
 static inline void intel_guc_notify(struct intel_guc *guc)
@@ -101,7 +95,7 @@ static inline void intel_guc_notify(struct intel_guc *guc)
 
 static inline void intel_guc_to_host_event_handler(struct intel_guc *guc)
 {
-	guc->handler(guc);
+	intel_guc_ct_event_handler(&guc->ct);
 }
 
 /* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */
@@ -136,12 +130,8 @@ void intel_guc_init_send_regs(struct intel_guc *guc);
 void intel_guc_write_params(struct intel_guc *guc);
 int intel_guc_init(struct intel_guc *guc);
 void intel_guc_fini(struct intel_guc *guc);
-int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len,
-		       u32 *response_buf, u32 response_buf_size);
 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
 			u32 *response_buf, u32 response_buf_size);
-void intel_guc_to_host_event_handler(struct intel_guc *guc);
-void intel_guc_to_host_event_handler_nop(struct intel_guc *guc);
 int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
 				       const u32 *payload, u32 len);
 int intel_guc_sample_forcewake(struct intel_guc *guc);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index f22cd9b2311b..c6f971a049f9 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -510,13 +510,18 @@ static int ct_send(struct intel_guc_ct *ct,
 /*
  * Command Transport (CT) buffer based GuC send function.
  */
-int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len,
+int intel_guc_ct_send(struct intel_guc_ct *ct, const u32 *action, u32 len,
 		      u32 *response_buf, u32 response_buf_size)
 {
-	struct intel_guc_ct *ct = &guc->ct;
+	struct intel_guc *guc = ct_to_guc(ct);
 	u32 status = ~0; /* undefined */
 	int ret;
 
+	if (unlikely(!ct->enabled)) {
+		WARN(1, "Unexpected send: action=%#x\n", *action);
+		return -ENODEV;
+	}
+
 	mutex_lock(&guc->send_mutex);
 
 	ret = ct_send(ct, action, len, response_buf, response_buf_size, &status);
@@ -787,15 +792,16 @@ static int ct_handle_request(struct intel_guc_ct *ct, const u32 *msg)
  * When we're communicating with the GuC over CT, GuC uses events
  * to notify us about new messages being posted on the RECV buffer.
  */
-void intel_guc_to_host_event_handler_ct(struct intel_guc *guc)
+void intel_guc_ct_event_handler(struct intel_guc_ct *ct)
 {
-	struct intel_guc_ct *ct = &guc->ct;
 	struct intel_guc_ct_buffer *ctb = &ct->ctbs[CTB_RECV];
 	u32 msg[GUC_CT_MSG_LEN_MASK + 1]; /* one extra dw for the header */
 	int err = 0;
 
-	if (!ct->enabled)
+	if (unlikely(!ct->enabled)) {
+		WARN(1, "Unexpected GuC event received while CT disabled!\n");
 		return;
+	}
 
 	do {
 		err = ctb_read(ctb, msg);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
index 29a026dc3a13..3e7fe237cfa5 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
@@ -65,8 +65,13 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct);
 int intel_guc_ct_enable(struct intel_guc_ct *ct);
 void intel_guc_ct_disable(struct intel_guc_ct *ct);
 
-int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len,
+static inline bool intel_guc_ct_enabled(struct intel_guc_ct *ct)
+{
+	return ct->enabled;
+}
+
+int intel_guc_ct_send(struct intel_guc_ct *ct, const u32 *action, u32 len,
 		      u32 *response_buf, u32 response_buf_size);
-void intel_guc_to_host_event_handler_ct(struct intel_guc *guc);
+void intel_guc_ct_event_handler(struct intel_guc_ct *ct);
 
 #endif /* _INTEL_GUC_CT_H_ */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index af04ed6e48d9..44a7d2e736a7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -43,7 +43,6 @@
  * Firmware writes a success/fail code back to the action register after
  * processes the request. The kernel driver polls waiting for this update and
  * then proceeds.
- * See intel_guc_send()
  *
  * Work Items:
  * There are several types of work items that the host may place into a
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 6e17e449e0a8..782b8f95183f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -123,6 +123,11 @@ static void __uc_free_load_err_log(struct intel_uc *uc)
 		i915_gem_object_put(log);
 }
 
+static inline bool guc_communication_enabled(struct intel_guc *guc)
+{
+	return intel_guc_ct_enabled(&guc->ct);
+}
+
 /*
  * Events triggered while CT buffers are disabled are logged in the SCRATCH_15
  * register using the same bits used in the CT message payload. Since our
@@ -158,7 +163,7 @@ static void guc_handle_mmio_msg(struct intel_guc *guc)
 	struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
 
 	/* we need communication to be enabled to reply to GuC */
-	GEM_BUG_ON(guc->handler == intel_guc_to_host_event_handler_nop);
+	GEM_BUG_ON(!guc_communication_enabled(guc));
 
 	if (!guc->mmio_msg)
 		return;
@@ -185,11 +190,6 @@ static void guc_disable_interrupts(struct intel_guc *guc)
 	guc->interrupts.disable(guc);
 }
 
-static inline bool guc_communication_enabled(struct intel_guc *guc)
-{
-	return guc->send != intel_guc_send_nop;
-}
-
 static int guc_enable_communication(struct intel_guc *guc)
 {
 	struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
@@ -205,9 +205,6 @@ static int guc_enable_communication(struct intel_guc *guc)
 	if (ret)
 		return ret;
 
-	guc->send = intel_guc_send_ct;
-	guc->handler = intel_guc_to_host_event_handler_ct;
-
 	/* check for mmio messages received before/during the CT enable */
 	guc_get_mmio_msg(guc);
 	guc_handle_mmio_msg(guc);
@@ -216,7 +213,7 @@ static int guc_enable_communication(struct intel_guc *guc)
 
 	/* check for CT messages received before we enabled interrupts */
 	spin_lock_irq(&i915->irq_lock);
-	intel_guc_to_host_event_handler_ct(guc);
+	intel_guc_ct_event_handler(&guc->ct);
 	spin_unlock_irq(&i915->irq_lock);
 
 	DRM_INFO("GuC communication enabled\n");
@@ -235,9 +232,6 @@ static void guc_disable_communication(struct intel_guc *guc)
 
 	guc_disable_interrupts(guc);
 
-	guc->send = intel_guc_send_nop;
-	guc->handler = intel_guc_to_host_event_handler_nop;
-
 	intel_guc_ct_disable(&guc->ct);
 
 	/*
-- 
2.23.0

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[Intel-gfx] [PATCH v2 6/7] drm/i915/guc: Unify notify() functions

[Daniele Ceraolo Spurio]

The Gen11+ and the legacy function differ in the register and value
written to interrupt the GuC. However, while on older gen the value
matches a bit on the register, on Gen11+ the value is a SW defined
payload that is sent to the FW. Since the FW behaves the same no matter
what value we pass to it, we can just write the same thing on all gens
and get rid of the function pointer by saving the register offset.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc.c | 21 ++++++++++-----------
 drivers/gpu/drm/i915/gt/uc/intel_guc.h | 12 ++++--------
 2 files changed, 14 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index daebfec0034c..9d6301292e13 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -32,18 +32,17 @@
  * just the HuC, but more are expected to land in the future).
  */
 
-static void gen8_guc_raise_irq(struct intel_guc *guc)
+void intel_guc_notify(struct intel_guc *guc)
 {
 	struct intel_gt *gt = guc_to_gt(guc);
 
-	intel_uncore_write(gt->uncore, GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
-}
-
-static void gen11_guc_raise_irq(struct intel_guc *guc)
-{
-	struct intel_gt *gt = guc_to_gt(guc);
-
-	intel_uncore_write(gt->uncore, GEN11_GUC_HOST_INTERRUPT, 0);
+	/*
+	 * On Gen11+, the value written to the register is passes as a payload
+	 * to the FW. However, the FW currently treats all values the same way
+	 * (H2G interrupt), so we can just write the value that the HW expects
+	 * on older gens.
+	 */
+	intel_uncore_write(gt->uncore, guc->notify_reg, GUC_SEND_TRIGGER);
 }
 
 static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
@@ -178,12 +177,12 @@ void intel_guc_init_early(struct intel_guc *guc)
 	mutex_init(&guc->send_mutex);
 	spin_lock_init(&guc->irq_lock);
 	if (INTEL_GEN(i915) >= 11) {
-		guc->notify = gen11_guc_raise_irq;
+		guc->notify_reg = GEN11_GUC_HOST_INTERRUPT;
 		guc->interrupts.reset = gen11_reset_guc_interrupts;
 		guc->interrupts.enable = gen11_enable_guc_interrupts;
 		guc->interrupts.disable = gen11_disable_guc_interrupts;
 	} else {
-		guc->notify = gen8_guc_raise_irq;
+		guc->notify_reg = GUC_SEND_INTERRUPT;
 		guc->interrupts.reset = gen9_reset_guc_interrupts;
 		guc->interrupts.enable = gen9_enable_guc_interrupts;
 		guc->interrupts.disable = gen9_disable_guc_interrupts;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 253b1ac7716e..910d49590068 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -64,14 +64,14 @@ struct intel_guc {
 		enum forcewake_domains fw_domains;
 	} send_regs;
 
+	/* register used to send interrupts to the GuC FW */
+	i915_reg_t notify_reg;
+
 	/* Store msg (e.g. log flush) that we see while CTBs are disabled */
 	u32 mmio_msg;
 
 	/* To serialize the intel_guc_send actions */
 	struct mutex send_mutex;
-
-	/* GuC's FW specific notify function */
-	void (*notify)(struct intel_guc *guc);
 };
 
 static
@@ -88,11 +88,6 @@ intel_guc_send_and_receive(struct intel_guc *guc, const u32 *action, u32 len,
 				 response_buf, response_buf_size);
 }
 
-static inline void intel_guc_notify(struct intel_guc *guc)
-{
-	guc->notify(guc);
-}
-
 static inline void intel_guc_to_host_event_handler(struct intel_guc *guc)
 {
 	intel_guc_ct_event_handler(&guc->ct);
@@ -130,6 +125,7 @@ void intel_guc_init_send_regs(struct intel_guc *guc);
 void intel_guc_write_params(struct intel_guc *guc);
 int intel_guc_init(struct intel_guc *guc);
 void intel_guc_fini(struct intel_guc *guc);
+void intel_guc_notify(struct intel_guc *guc);
 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
 			u32 *response_buf, u32 response_buf_size);
 int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
-- 
2.23.0

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[Intel-gfx] [PATCH v2 7/7] HAX: force enable_guc=2 and WA i915#571

[Daniele Ceraolo Spurio]

To get a full run with GuC loading and HuC auth enabled.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
 drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 9 +++++++++
 drivers/gpu/drm/i915/i915_params.h       | 2 +-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
index 09ff8e4f88af..86b176c887b4 100644
--- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
@@ -12,8 +12,11 @@ static int live_gt_resume(void *arg)
 {
 	struct intel_gt *gt = arg;
 	IGT_TIMEOUT(end_time);
+	intel_wakeref_t wakeref;
 	int err;
 
+	wakeref = intel_runtime_pm_get(gt->uncore->rpm);
+
 	/* Do several suspend/resume cycles to check we don't explode! */
 	do {
 		intel_gt_suspend_prepare(gt);
@@ -26,6 +29,10 @@ static int live_gt_resume(void *arg)
 			break;
 		}
 
+		err = intel_gt_init_hw(gt);
+		if (err)
+			break;
+
 		err = intel_gt_resume(gt);
 		if (err)
 			break;
@@ -45,6 +52,8 @@ static int live_gt_resume(void *arg)
 		}
 	} while (!__igt_timeout(end_time, NULL));
 
+	intel_runtime_pm_put(gt->uncore->rpm, wakeref);
+
 	return err;
 }
 
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 31b88f297fbc..acda9f2a1207 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -54,7 +54,7 @@ struct drm_printer;
 	param(int, disable_power_well, -1) \
 	param(int, enable_ips, 1) \
 	param(int, invert_brightness, 0) \
-	param(int, enable_guc, 0) \
+	param(int, enable_guc, 2) \
 	param(int, guc_log_level, -1) \
 	param(char *, guc_firmware_path, NULL) \
 	param(char *, huc_firmware_path, NULL) \
-- 
2.23.0

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/7] drm/i915/guc: Merge communication_stop and communication_disable

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/7] drm/i915/guc: Merge communication_stop and communication_disable
URL   : https://patchwork.freedesktop.org/series/71020/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
b1167fe23f5a drm/i915/guc: Merge communication_stop and communication_disable
d8b5ef3911bc drm/i915/guc/ct: Drop guards in enable/disable calls
0f240dde5bd9 drm/i915/guc/ct: Stop expecting multiple CT channels
-:125: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#125: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c:171:
+		ct->ctbs[i].desc = blob + PAGE_SIZE/4 * i;
 		                                   ^

-:126: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#126: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c:172:
+		ct->ctbs[i].cmds = blob + PAGE_SIZE/4 * i + PAGE_SIZE/2;
 		                                   ^

-:126: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#126: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c:172:
+		ct->ctbs[i].cmds = blob + PAGE_SIZE/4 * i + PAGE_SIZE/2;
 		                                                     ^

-:185: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#185: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c:217:
+					PAGE_SIZE/4);
 					         ^

total: 0 errors, 0 warnings, 4 checks, 343 lines checked
fc2ab66c04c1 drm/i915/guc/ct: Group request-related variables in a sub-structure
fb103861ef07 drm/i915/guc: Remove function pointers for send/receive calls
bd8a56cf311b drm/i915/guc: Unify notify() functions
ea5f8a3163af HAX: force enable_guc=2 and WA i915#571

_______________________________________________
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/7] drm/i915/guc: Merge communication_stop and communication_disable

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/7] drm/i915/guc: Merge communication_stop and communication_disable
URL   : https://patchwork.freedesktop.org/series/71020/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7578 -> Patchwork_15805
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/index.html

Known issues
------------

  Here are the changes found in Patchwork_15805 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_close_race@basic-threads:
    - fi-byt-j1900:       [PASS][1] -> [TIMEOUT][2] ([i915#816])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-byt-j1900/igt@gem_close_race@basic-threads.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/fi-byt-j1900/igt@gem_close_race@basic-threads.html

  * igt@gem_exec_suspend@basic-s0:
    - fi-icl-u3:          [PASS][3] -> [INCOMPLETE][4] ([i915#140])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-icl-u3/igt@gem_exec_suspend@basic-s0.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/fi-icl-u3/igt@gem_exec_suspend@basic-s0.html

  * igt@i915_selftest@live_blt:
    - fi-hsw-4770r:       [PASS][5] -> [DMESG-FAIL][6] ([i915#563])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-hsw-4770r/igt@i915_selftest@live_blt.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/fi-hsw-4770r/igt@i915_selftest@live_blt.html
    - fi-hsw-peppy:       [PASS][7] -> [DMESG-FAIL][8] ([i915#553] / [i915#725])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-hsw-peppy/igt@i915_selftest@live_blt.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/fi-hsw-peppy/igt@i915_selftest@live_blt.html

  * igt@i915_selftest@live_gem_contexts:
    - fi-hsw-4770:        [PASS][9] -> [DMESG-FAIL][10] ([i915#623])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-hsw-4770/igt@i915_selftest@live_gem_contexts.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/fi-hsw-4770/igt@i915_selftest@live_gem_contexts.html

  
#### Possible fixes ####

  * igt@gem_exec_parallel@basic:
    - {fi-tgl-u}:         [INCOMPLETE][11] ([i915#476]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-tgl-u/igt@gem_exec_parallel@basic.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/fi-tgl-u/igt@gem_exec_parallel@basic.html

  * igt@gem_exec_suspend@basic-s3:
    - fi-icl-u2:          [FAIL][13] ([fdo#103375]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-icl-u2/igt@gem_exec_suspend@basic-s3.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/fi-icl-u2/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_exec_suspend@basic-s4-devices:
    - fi-icl-u2:          [FAIL][15] ([fdo#111550]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-icl-u2/igt@gem_exec_suspend@basic-s4-devices.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/fi-icl-u2/igt@gem_exec_suspend@basic-s4-devices.html

  * igt@i915_selftest@live_gem_contexts:
    - fi-cfl-guc:         [DMESG-FAIL][17] ([i915#730]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html

  * igt@i915_selftest@live_gt_pm:
    - fi-icl-guc:         [DMESG-FAIL][19] ([i915#571]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-icl-guc/igt@i915_selftest@live_gt_pm.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/fi-icl-guc/igt@i915_selftest@live_gt_pm.html

  * igt@kms_busy@basic-flip-pipe-a:
    - fi-icl-u2:          [INCOMPLETE][21] ([i915#140]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-icl-u2/igt@kms_busy@basic-flip-pipe-a.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/fi-icl-u2/igt@kms_busy@basic-flip-pipe-a.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-kbl-7500u:       [FAIL][23] ([fdo#109635] / [i915#217]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][25] ([fdo#111096] / [i915#323]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
#### Warnings ####

  * igt@gem_exec_suspend@basic-s0:
    - fi-kbl-x1275:       [DMESG-WARN][27] ([i915#62] / [i915#92]) -> [DMESG-WARN][28] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html

  * igt@i915_selftest@live_blt:
    - fi-ivb-3770:        [DMESG-FAIL][29] ([i915#725]) -> [DMESG-FAIL][30] ([i915#770])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-ivb-3770/igt@i915_selftest@live_blt.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/fi-ivb-3770/igt@i915_selftest@live_blt.html
    - fi-hsw-4770:        [DMESG-FAIL][31] ([i915#553] / [i915#725]) -> [DMESG-FAIL][32] ([i915#563])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-hsw-4770/igt@i915_selftest@live_blt.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/fi-hsw-4770/igt@i915_selftest@live_blt.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - fi-kbl-x1275:       [DMESG-WARN][33] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][34] ([i915#62] / [i915#92]) +7 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109635]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111550]: https://bugs.freedesktop.org/show_bug.cgi?id=111550
  [i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140
  [i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217
  [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
  [i915#470]: https://gitlab.freedesktop.org/drm/intel/issues/470
  [i915#476]: https://gitlab.freedesktop.org/drm/intel/issues/476
  [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
  [i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563
  [i915#571]: https://gitlab.freedesktop.org/drm/intel/issues/571
  [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
  [i915#623]: https://gitlab.freedesktop.org/drm/intel/issues/623
  [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
  [i915#730]: https://gitlab.freedesktop.org/drm/intel/issues/730
  [i915#770]: https://gitlab.freedesktop.org/drm/intel/issues/770
  [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816
  [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (51 -> 42)
------------------------------

  Additional (1): fi-kbl-soraka 
  Missing    (10): fi-ilk-m540 fi-bdw-5557u fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-gdg-551 fi-byt-n2820 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7578 -> Patchwork_15805

  CI-20190529: 20190529
  CI_DRM_7578: cc329d389f5609d2969d0797bc96f754adb26d62 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5349: 048f58513d8b8ec6bb307a939f0ac959bc0f0e10 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15805: ea5f8a3163af3b8faacefeaca30363aeebd40ef7 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

ea5f8a3163af HAX: force enable_guc=2 and WA i915#571
bd8a56cf311b drm/i915/guc: Unify notify() functions
fb103861ef07 drm/i915/guc: Remove function pointers for send/receive calls
fc2ab66c04c1 drm/i915/guc/ct: Group request-related variables in a sub-structure
0f240dde5bd9 drm/i915/guc/ct: Stop expecting multiple CT channels
d8b5ef3911bc drm/i915/guc/ct: Drop guards in enable/disable calls
b1167fe23f5a drm/i915/guc: Merge communication_stop and communication_disable

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/index.html
_______________________________________________
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/7] drm/i915/guc: Merge communication_stop and communication_disable

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/7] drm/i915/guc: Merge communication_stop and communication_disable
URL   : https://patchwork.freedesktop.org/series/71020/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7578_full -> Patchwork_15805_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_15805_full:

### Piglit changes ###

#### Possible regressions ####

  * spec@ext_framebuffer_multisample@bitmap 6 (NEW):
    - {pig-hsw-4770r}:    NOTRUN -> [FAIL][1] +4 similar issues
   [1]: None

  
New tests
---------

  New tests have been introduced between CI_DRM_7578_full and Patchwork_15805_full:

### New Piglit tests (5) ###

  * spec@arb_gpu_shader5@texturegatheroffset@vs-rg-0-unorm-2darray-const:
    - Statuses : 1 fail(s)
    - Exec time: [7.36] s

  * spec@arb_stencil_texturing@draw:
    - Statuses : 1 fail(s)
    - Exec time: [0.11] s

  * spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-float_mat3_array3-position-double_dvec3_array2:
    - Statuses : 1 fail(s)
    - Exec time: [0.17] s

  * spec@ext_framebuffer_multisample@bitmap 6:
    - Statuses : 1 fail(s)
    - Exec time: [0.23] s

  * spec@glsl-4.10@execution@vs_in@vs-input-uint_uvec4_array3-double_double_array2-position:
    - Statuses : 1 fail(s)
    - Exec time: [0.23] s

  

Known issues
------------

  Here are the changes found in Patchwork_15805_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@vcs1-none:
    - shard-iclb:         [PASS][2] -> [SKIP][3] ([fdo#109276] / [fdo#112080]) +1 similar issue
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb1/igt@gem_ctx_isolation@vcs1-none.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-iclb3/igt@gem_ctx_isolation@vcs1-none.html

  * igt@gem_eio@in-flight-suspend:
    - shard-tglb:         [PASS][4] -> [INCOMPLETE][5] ([i915#456] / [i915#460] / [i915#534])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb3/igt@gem_eio@in-flight-suspend.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb3/igt@gem_eio@in-flight-suspend.html

  * igt@gem_eio@kms:
    - shard-tglb:         [PASS][6] -> [INCOMPLETE][7] ([i915#476])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb7/igt@gem_eio@kms.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb8/igt@gem_eio@kms.html

  * igt@gem_exec_parallel@fds:
    - shard-tglb:         [PASS][8] -> [INCOMPLETE][9] ([i915#470])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb3/igt@gem_exec_parallel@fds.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb9/igt@gem_exec_parallel@fds.html

  * igt@gem_exec_parallel@vecs0:
    - shard-tglb:         [PASS][10] -> [INCOMPLETE][11] ([fdo#111736])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb3/igt@gem_exec_parallel@vecs0.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb2/igt@gem_exec_parallel@vecs0.html

  * igt@gem_exec_schedule@fifo-bsd1:
    - shard-iclb:         [PASS][12] -> [SKIP][13] ([fdo#109276]) +5 similar issues
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb4/igt@gem_exec_schedule@fifo-bsd1.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-iclb6/igt@gem_exec_schedule@fifo-bsd1.html

  * igt@gem_exec_schedule@independent-bsd:
    - shard-iclb:         [PASS][14] -> [SKIP][15] ([fdo#112146])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb3/igt@gem_exec_schedule@independent-bsd.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-iclb1/igt@gem_exec_schedule@independent-bsd.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-glk:          [PASS][16] -> [FAIL][17] ([i915#644])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-glk7/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-glk2/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * igt@gem_sync@basic-store-all:
    - shard-tglb:         [PASS][18] -> [INCOMPLETE][19] ([i915#472])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb9/igt@gem_sync@basic-store-all.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb6/igt@gem_sync@basic-store-all.html

  * igt@i915_hangman@error-state-capture-vcs1:
    - shard-iclb:         [PASS][20] -> [SKIP][21] ([fdo#112080]) +6 similar issues
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb1/igt@i915_hangman@error-state-capture-vcs1.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-iclb3/igt@i915_hangman@error-state-capture-vcs1.html

  * igt@i915_pm_rpm@modeset-stress-extra-wait:
    - shard-glk:          [PASS][22] -> [DMESG-WARN][23] ([i915#118] / [i915#95])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-glk4/igt@i915_pm_rpm@modeset-stress-extra-wait.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-glk8/igt@i915_pm_rpm@modeset-stress-extra-wait.html

  * igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen:
    - shard-hsw:          [PASS][24] -> [DMESG-WARN][25] ([IGT#6])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-hsw4/igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-hsw6/igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen.html

  * igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding:
    - shard-skl:          [PASS][26] -> [FAIL][27] ([i915#54]) +3 similar issues
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-skl6/igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-skl4/igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-skl:          [PASS][28] -> [FAIL][29] ([i915#79])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-hsw:          [PASS][30] -> [INCOMPLETE][31] ([i915#61])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-hsw6/igt@kms_flip@flip-vs-suspend.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-hsw4/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-apl:          [PASS][32] -> [DMESG-WARN][33] ([i915#180])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-tglb:         [PASS][34] -> [INCOMPLETE][35] ([i915#456] / [i915#460] / [i915#474])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb4/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move:
    - shard-tglb:         [PASS][36] -> [INCOMPLETE][37] ([i915#474] / [i915#667])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@psr-suspend:
    - shard-tglb:         [PASS][38] -> [INCOMPLETE][39] ([i915#456] / [i915#460]) +1 similar issue
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb8/igt@kms_frontbuffer_tracking@psr-suspend.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb3/igt@kms_frontbuffer_tracking@psr-suspend.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [PASS][40] -> [FAIL][41] ([fdo#108145] / [i915#265])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_psr@psr2_cursor_plane_onoff:
    - shard-iclb:         [PASS][42] -> [SKIP][43] ([fdo#109441]) +1 similar issue
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-iclb4/igt@kms_psr@psr2_cursor_plane_onoff.html

  * igt@kms_setmode@basic:
    - shard-apl:          [PASS][44] -> [FAIL][45] ([i915#31])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-apl8/igt@kms_setmode@basic.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-apl7/igt@kms_setmode@basic.html

  * igt@perf@oa-exponents:
    - shard-tglb:         [PASS][46] -> [FAIL][47] ([i915#84])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb4/igt@perf@oa-exponents.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb6/igt@perf@oa-exponents.html

  
#### Possible fixes ####

  * igt@gem_busy@close-race:
    - shard-tglb:         [INCOMPLETE][48] ([i915#435]) -> [PASS][49]
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb6/igt@gem_busy@close-race.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb2/igt@gem_busy@close-race.html

  * igt@gem_ctx_isolation@bcs0-s3:
    - shard-tglb:         [INCOMPLETE][50] ([i915#456]) -> [PASS][51] +1 similar issue
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb5/igt@gem_ctx_isolation@bcs0-s3.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb1/igt@gem_ctx_isolation@bcs0-s3.html

  * igt@gem_ctx_persistence@vcs0-mixed-process:
    - shard-apl:          [FAIL][52] ([i915#679]) -> [PASS][53]
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-apl3/igt@gem_ctx_persistence@vcs0-mixed-process.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-apl1/igt@gem_ctx_persistence@vcs0-mixed-process.html

  * igt@gem_ctx_persistence@vcs1-persistence:
    - shard-iclb:         [SKIP][54] ([fdo#109276] / [fdo#112080]) -> [PASS][55]
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb3/igt@gem_ctx_persistence@vcs1-persistence.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-iclb1/igt@gem_ctx_persistence@vcs1-persistence.html

  * igt@gem_eio@banned:
    - shard-tglb:         [INCOMPLETE][56] ([i915#476]) -> [PASS][57]
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb6/igt@gem_eio@banned.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb9/igt@gem_eio@banned.html

  * igt@gem_exec_reloc@basic-wc-active:
    - shard-skl:          [DMESG-WARN][58] ([i915#109]) -> [PASS][59]
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-skl8/igt@gem_exec_reloc@basic-wc-active.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-skl7/igt@gem_exec_reloc@basic-wc-active.html

  * igt@gem_exec_schedule@preempt-queue-contexts-vebox:
    - shard-tglb:         [INCOMPLETE][60] ([fdo#111677]) -> [PASS][61]
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb6/igt@gem_exec_schedule@preempt-queue-contexts-vebox.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb9/igt@gem_exec_schedule@preempt-queue-contexts-vebox.html

  * igt@gem_exec_schedule@preemptive-hang-bsd:
    - shard-iclb:         [SKIP][62] ([fdo#112146]) -> [PASS][63] +3 similar issues
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb1/igt@gem_exec_schedule@preemptive-hang-bsd.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-iclb3/igt@gem_exec_schedule@preemptive-hang-bsd.html

  * igt@gem_sync@basic-each:
    - shard-tglb:         [INCOMPLETE][64] ([i915#472] / [i915#707]) -> [PASS][65]
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb9/igt@gem_sync@basic-each.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb9/igt@gem_sync@basic-each.html

  * igt@gem_tiled_blits@interruptible:
    - shard-hsw:          [FAIL][66] ([i915#818]) -> [PASS][67]
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-hsw7/igt@gem_tiled_blits@interruptible.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-hsw4/igt@gem_tiled_blits@interruptible.html

  * {igt@gen9_exec_parse@allowed-single}:
    - shard-apl:          [DMESG-WARN][68] ([i915#716]) -> [PASS][69]
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-apl7/igt@gen9_exec_parse@allowed-single.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-apl6/igt@gen9_exec_parse@allowed-single.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-apl:          [DMESG-WARN][70] ([i915#180]) -> [PASS][71] +3 similar issues
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding:
    - shard-hsw:          [DMESG-WARN][72] ([IGT#6]) -> [PASS][73]
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-hsw6/igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-hsw4/igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding.html

  * igt@kms_cursor_crc@pipe-d-cursor-suspend:
    - shard-tglb:         [INCOMPLETE][74] ([i915#460]) -> [PASS][75]
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb2/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb6/igt@kms_cursor_crc@pipe-d-cursor-suspend.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
    - shard-glk:          [FAIL][76] ([i915#79]) -> [PASS][77]
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-apl:          [FAIL][78] ([i915#79]) -> [PASS][79]
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-apl8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-apl8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-skl:          [INCOMPLETE][80] ([i915#221]) -> [PASS][81]
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-skl4/igt@kms_flip@flip-vs-suspend.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-skl1/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt:
    - shard-tglb:         [FAIL][82] ([i915#49]) -> [PASS][83] +2 similar issues
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-suspend:
    - shard-tglb:         [INCOMPLETE][84] ([i915#456] / [i915#460] / [i915#474]) -> [PASS][85]
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html

  * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
    - shard-iclb:         [INCOMPLETE][86] ([i915#140] / [i915#246]) -> [PASS][87]
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb4/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-iclb2/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
    - shard-kbl:          [DMESG-WARN][88] ([i915#180]) -> [PASS][89] +2 similar issues
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          [FAIL][90] ([fdo#108145]) -> [PASS][91] +1 similar issue
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [FAIL][92] ([fdo#108145] / [i915#265]) -> [PASS][93]
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr@psr2_sprite_mmap_gtt:
    - shard-iclb:         [SKIP][94] ([fdo#109441]) -> [PASS][95]
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb5/igt@kms_psr@psr2_sprite_mmap_gtt.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html

  * igt@perf_pmu@busy-no-semaphores-vcs1:
    - shard-iclb:         [SKIP][96] ([fdo#112080]) -> [PASS][97] +3 similar issues
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb8/igt@perf_pmu@busy-no-semaphores-vcs1.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-iclb4/igt@perf_pmu@busy-no-semaphores-vcs1.html

  * igt@prime_vgem@fence-wait-bsd2:
    - shard-iclb:         [SKIP][98] ([fdo#109276]) -> [PASS][99] +10 similar issues
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb3/igt@prime_vgem@fence-wait-bsd2.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-iclb1/igt@prime_vgem@fence-wait-bsd2.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs2-dirty-create:
    - shard-tglb:         [SKIP][100] ([fdo#111912] / [fdo#112080]) -> [SKIP][101] ([fdo#112080]) +1 similar issue
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb6/igt@gem_ctx_isolation@vcs2-dirty-create.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb9/igt@gem_ctx_isolation@vcs2-dirty-create.html

  * igt@gem_tiled_blits@normal:
    - shard-hsw:          [FAIL][102] ([i915#818]) -> [FAIL][103] ([i915#832])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-hsw7/igt@gem_tiled_blits@normal.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-hsw4/igt@gem_tiled_blits@normal.html

  * igt@kms_atomic_transition@6x-modeset-transitions:
    - shard-tglb:         [SKIP][104] ([fdo#112021]) -> [SKIP][105] ([fdo#112016] / [fdo#112021])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb9/igt@kms_atomic_transition@6x-modeset-transitions.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb6/igt@kms_atomic_transition@6x-modeset-transitions.html

  * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
    - shard-skl:          [INCOMPLETE][106] ([i915#648]) -> [INCOMPLETE][107] ([i915#648] / [i915#667])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-skl5/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-skl4/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html

  * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
    - shard-skl:          [INCOMPLETE][108] ([fdo#112347] / [i915#648] / [i915#667]) -> [INCOMPLETE][109] ([fdo#112347] / [fdo#112391] / [i915#648] / [i915#667])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-skl7/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-skl3/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#6]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/6
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#111677]: https://bugs.freedesktop.org/show_bug.cgi?id=111677
  [fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736
  [fdo#111912]: https://bugs.freedesktop.org/show_bug.cgi?id=111912
  [fdo#112016]: https://bugs.freedesktop.org/show_bug.cgi?id=112016
  [fdo#112021]: https://bugs.freedesktop.org/show_bug.cgi?id=112021
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
  [fdo#112347]: https://bugs.freedesktop.org/show_bug.cgi?id=112347
  [fdo#112391]: https://bugs.freedesktop.org/show_bug.cgi?id=112391
  [i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
  [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
  [i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#221]: https://gitlab.freedesktop.org/drm/intel/issues/221
  [i915#246]: https://gitlab.freedesktop.org/drm/intel/issues/246
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
  [i915#435]: https://gitlab.freedesktop.org/drm/intel/issues/435
  [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
  [i915#460]: https://gitlab.freedesktop.org/drm/intel/issues/460
  [i915#470]: https://gitlab.freedesktop.org/drm/intel/issues/470
  [i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472
  [i915#474]: https://gitlab.freedesktop.org/drm/intel/issues/474
  [i915#476]: https://gitlab.freedesktop.org/drm/intel/issues/476
  [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
  [i915#534]: https://gitlab.freedesktop.org/drm/intel/issues/534
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
  [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
  [i915#648]: https://gitlab.freedesktop.org/drm/intel/issues/648
  [i915#667]: https://gitlab.freedesktop.org/drm/intel/issues/667
  [i915#679]: https://gitlab.freedesktop.org/drm/intel/issues/679
  [i915#707]: https://gitlab.freedesktop.org/drm/intel/issues/707
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#818]: https://gitlab.freedesktop.org/drm/intel/issues/818
  [i915#832]: https://gitlab.freedesktop.org/drm/intel/issues/832
  [i915#84]: https://gitlab.freedesktop.org/drm/intel/issues/84
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (10 -> 11)
------------------------------

  Additional (1): pig-hsw-4770r 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7578 -> Patchwork_15805

  CI-20190529: 20190529
  CI_DRM_7578: cc329d389f5609d2969d0797bc96f754adb26d62 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5349: 048f58513d8b8ec6bb307a939f0ac959bc0f0e10 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15805: ea5f8a3163af3b8faacefeaca30363aeebd40ef7 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/index.html
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Re: [Intel-gfx] [PATCH v2 2/7] drm/i915/guc/ct: Drop guards in enable/disable calls

[Michal Wajdeczko]

On Tue, 17 Dec 2019 02:23:11 +0100, Daniele Ceraolo Spurio  
<daniele.ceraolospurio@intel.com> wrote:

> We track the status of the GuC much more closely now and we expect the
> enable/disable functions to be correctly called only once. If this isn't
> true we do want to flag it as a flow failure (via the BUG_ON in the ctch
> functions) and not silently ignore the call.
>
> Suggested-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
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Re: [Intel-gfx] [PATCH v2 3/7] drm/i915/guc/ct: Stop expecting multiple CT channels

[Michal Wajdeczko]

On Tue, 17 Dec 2019 02:23:12 +0100, Daniele Ceraolo Spurio  
<daniele.ceraolospurio@intel.com> wrote:

> The GuC supports having multiple CT buffer pairs and we designed our
> implementation with that in mind. However, the different channels are not
> processed in parallel within the GuC, so there is very little advantage
> in having multiple channels (independent locks?), compared to the
> drawbacks (one channel can starve the other if messages keep being
> submitted to it). Given this, it is unlikely we'll ever add a second
> channel and therefore we can simplify our code by removing the
> flexibility.
>
> v2: split substructure grouping to separate patch, improve docs (Michal)
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: John Harrison <John.C.Harrison@Intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> ---
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
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Re: [Intel-gfx] [PATCH v2 4/7] drm/i915/guc/ct: Group request-related variables in a sub-structure

[Michal Wajdeczko]

On Tue, 17 Dec 2019 02:23:13 +0100, Daniele Ceraolo Spurio  
<daniele.ceraolospurio@intel.com> wrote:

> For better isolation of the request tracking from the rest of the
> CT-related data.
>
> v2: split to separate patch, move next_fence to substructure (Michal)
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: John Harrison <John.C.Harrison@Intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> ---

Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>

with some nits below (we may fix them later)

/snip/

> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h  
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> index 6e3d789b9f01..29a026dc3a13 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> @@ -48,12 +48,15 @@ struct intel_guc_ct {
>  	/* buffers for sending(0) and receiving(1) commands */
>  	struct intel_guc_ct_buffer ctbs[2];
> -	u32 next_fence; /* fence to be used with next send command */
> +	struct {
> +		u32 next_fence; /* fence to be used with next request to send */

nit: strictly speaking this is "last" fence
      we just use it to generate next one

> -	spinlock_t lock; /* protects pending requests list */
> -	struct list_head pending_requests; /* requests waiting for response */
> -	struct list_head incoming_requests; /* incoming requests */
> -	struct work_struct worker; /* handler for incoming requests */
> +		spinlock_t lock; /* protects pending requests list */

nit: do we want to use this lock to protect "next/last" fence ?
      if yes, then maybe lock shall be first ?

> +		struct list_head pending; /* requests waiting for response */
> +
> +		struct list_head incoming; /* incoming requests */
> +		struct work_struct worker; /* handler for incoming requests */
> +	} requests;
>  };
> void intel_guc_ct_init_early(struct intel_guc_ct *ct);
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Re: [Intel-gfx] [PATCH v2 5/7] drm/i915/guc: Remove function pointers for send/receive calls

[Michal Wajdeczko]

On Tue, 17 Dec 2019 02:23:14 +0100, Daniele Ceraolo Spurio  
<daniele.ceraolospurio@intel.com> wrote:

> Since we started using CT buffers on all gens, the function pointers can
> only be set to either the _nop() or the _ct() functions. Since the
> _nop() case applies to when the CT are disabled, we can just handle that
> case in the _ct() functions and call them directly.
>
> v2: keep intel_guc_send() and make the CT send/receive functions work on
>     intel_guc_ct. (Michal)
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: John Harrison <John.C.Harrison@Intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/uc/intel_guc.c        | 14 -------------
>  drivers/gpu/drm/i915/gt/uc/intel_guc.h        | 18 ++++-------------
>  drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c     | 16 ++++++++++-----
>  drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h     |  9 +++++++--
>  .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  1 -
>  drivers/gpu/drm/i915/gt/uc/intel_uc.c         | 20 +++++++------------
>  6 files changed, 29 insertions(+), 49 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c  
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 922a19635d20..daebfec0034c 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -177,8 +177,6 @@ void intel_guc_init_early(struct intel_guc *guc)
> 	mutex_init(&guc->send_mutex);
>  	spin_lock_init(&guc->irq_lock);
> -	guc->send = intel_guc_send_nop;
> -	guc->handler = intel_guc_to_host_event_handler_nop;
>  	if (INTEL_GEN(i915) >= 11) {
>  		guc->notify = gen11_guc_raise_irq;
>  		guc->interrupts.reset = gen11_reset_guc_interrupts;
> @@ -403,18 +401,6 @@ void intel_guc_fini(struct intel_guc *guc)
>  	intel_uc_fw_cleanup_fetch(&guc->fw);
>  }
> -int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32  
> len,
> -		       u32 *response_buf, u32 response_buf_size)
> -{
> -	WARN(1, "Unexpected send: action=%#x\n", *action);
> -	return -ENODEV;
> -}
> -
> -void intel_guc_to_host_event_handler_nop(struct intel_guc *guc)
> -{
> -	WARN(1, "Unexpected event: no suitable handler\n");
> -}
> -
>  /*
>   * This function implements the MMIO based host to GuC interface.
>   */
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h  
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> index cd09c912e361..253b1ac7716e 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> @@ -70,13 +70,6 @@ struct intel_guc {
>  	/* To serialize the intel_guc_send actions */
>  	struct mutex send_mutex;
> -	/* GuC's FW specific send function */
> -	int (*send)(struct intel_guc *guc, const u32 *data, u32 len,
> -		    u32 *response_buf, u32 response_buf_size);
> -
> -	/* GuC's FW specific event handler function */
> -	void (*handler)(struct intel_guc *guc);
> -
>  	/* GuC's FW specific notify function */
>  	void (*notify)(struct intel_guc *guc);
>  };
> @@ -84,14 +77,15 @@ struct intel_guc {
>  static
>  inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32  
> len)
>  {
> -	return guc->send(guc, action, len, NULL, 0);
> +	return intel_guc_ct_send(&guc->ct, action, len, NULL, 0);
>  }
> static inline int
>  intel_guc_send_and_receive(struct intel_guc *guc, const u32 *action,  
> u32 len,
>  			   u32 *response_buf, u32 response_buf_size)
>  {
> -	return guc->send(guc, action, len, response_buf, response_buf_size);
> +	return intel_guc_ct_send(&guc->ct, action, len,
> +				 response_buf, response_buf_size);
>  }
> static inline void intel_guc_notify(struct intel_guc *guc)
> @@ -101,7 +95,7 @@ static inline void intel_guc_notify(struct intel_guc  
> *guc)
> static inline void intel_guc_to_host_event_handler(struct intel_guc *guc)
>  {
> -	guc->handler(guc);
> +	intel_guc_ct_event_handler(&guc->ct);
>  }
> /* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */
> @@ -136,12 +130,8 @@ void intel_guc_init_send_regs(struct intel_guc  
> *guc);
>  void intel_guc_write_params(struct intel_guc *guc);
>  int intel_guc_init(struct intel_guc *guc);
>  void intel_guc_fini(struct intel_guc *guc);
> -int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32  
> len,
> -		       u32 *response_buf, u32 response_buf_size);
>  int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32  
> len,
>  			u32 *response_buf, u32 response_buf_size);
> -void intel_guc_to_host_event_handler(struct intel_guc *guc);
> -void intel_guc_to_host_event_handler_nop(struct intel_guc *guc);
>  int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
>  				       const u32 *payload, u32 len);
>  int intel_guc_sample_forcewake(struct intel_guc *guc);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c  
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> index f22cd9b2311b..c6f971a049f9 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> @@ -510,13 +510,18 @@ static int ct_send(struct intel_guc_ct *ct,
>  /*
>   * Command Transport (CT) buffer based GuC send function.
>   */
> -int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len,
> +int intel_guc_ct_send(struct intel_guc_ct *ct, const u32 *action, u32  
> len,
>  		      u32 *response_buf, u32 response_buf_size)
>  {
> -	struct intel_guc_ct *ct = &guc->ct;
> +	struct intel_guc *guc = ct_to_guc(ct);
>  	u32 status = ~0; /* undefined */
>  	int ret;
> +	if (unlikely(!ct->enabled)) {
> +		WARN(1, "Unexpected send: action=%#x\n", *action);
> +		return -ENODEV;
> +	}
> +
>  	mutex_lock(&guc->send_mutex);
> 	ret = ct_send(ct, action, len, response_buf, response_buf_size,  
> &status);
> @@ -787,15 +792,16 @@ static int ct_handle_request(struct intel_guc_ct  
> *ct, const u32 *msg)
>   * When we're communicating with the GuC over CT, GuC uses events
>   * to notify us about new messages being posted on the RECV buffer.
>   */
> -void intel_guc_to_host_event_handler_ct(struct intel_guc *guc)
> +void intel_guc_ct_event_handler(struct intel_guc_ct *ct)
>  {
> -	struct intel_guc_ct *ct = &guc->ct;
>  	struct intel_guc_ct_buffer *ctb = &ct->ctbs[CTB_RECV];
>  	u32 msg[GUC_CT_MSG_LEN_MASK + 1]; /* one extra dw for the header */
>  	int err = 0;
> -	if (!ct->enabled)
> +	if (unlikely(!ct->enabled)) {
> +		WARN(1, "Unexpected GuC event received while CT disabled!\n");

hmm, maybe we should just return false to indicate that we didn't
process that G2H event and decide in irq_handler what to do with that?
but not a blocker, so

Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>

Michal

>  		return;
> +	}
> 	do {
>  		err = ctb_read(ctb, msg);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h  
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> index 29a026dc3a13..3e7fe237cfa5 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> @@ -65,8 +65,13 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct);
>  int intel_guc_ct_enable(struct intel_guc_ct *ct);
>  void intel_guc_ct_disable(struct intel_guc_ct *ct);
> -int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len,
> +static inline bool intel_guc_ct_enabled(struct intel_guc_ct *ct)
> +{
> +	return ct->enabled;
> +}
> +
> +int intel_guc_ct_send(struct intel_guc_ct *ct, const u32 *action, u32  
> len,
>  		      u32 *response_buf, u32 response_buf_size);
> -void intel_guc_to_host_event_handler_ct(struct intel_guc *guc);
> +void intel_guc_ct_event_handler(struct intel_guc_ct *ct);
> #endif /* _INTEL_GUC_CT_H_ */
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c  
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index af04ed6e48d9..44a7d2e736a7 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -43,7 +43,6 @@
>   * Firmware writes a success/fail code back to the action register after
>   * processes the request. The kernel driver polls waiting for this  
> update and
>   * then proceeds.
> - * See intel_guc_send()
>   *
>   * Work Items:
>   * There are several types of work items that the host may place into a
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c  
> b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> index 6e17e449e0a8..782b8f95183f 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> @@ -123,6 +123,11 @@ static void __uc_free_load_err_log(struct intel_uc  
> *uc)
>  		i915_gem_object_put(log);
>  }
> +static inline bool guc_communication_enabled(struct intel_guc *guc)
> +{
> +	return intel_guc_ct_enabled(&guc->ct);
> +}
> +
>  /*
>   * Events triggered while CT buffers are disabled are logged in the  
> SCRATCH_15
>   * register using the same bits used in the CT message payload. Since  
> our
> @@ -158,7 +163,7 @@ static void guc_handle_mmio_msg(struct intel_guc  
> *guc)
>  	struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> 	/* we need communication to be enabled to reply to GuC */
> -	GEM_BUG_ON(guc->handler == intel_guc_to_host_event_handler_nop);
> +	GEM_BUG_ON(!guc_communication_enabled(guc));
> 	if (!guc->mmio_msg)
>  		return;
> @@ -185,11 +190,6 @@ static void guc_disable_interrupts(struct intel_guc  
> *guc)
>  	guc->interrupts.disable(guc);
>  }
> -static inline bool guc_communication_enabled(struct intel_guc *guc)
> -{
> -	return guc->send != intel_guc_send_nop;
> -}
> -
>  static int guc_enable_communication(struct intel_guc *guc)
>  {
>  	struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> @@ -205,9 +205,6 @@ static int guc_enable_communication(struct intel_guc  
> *guc)
>  	if (ret)
>  		return ret;
> -	guc->send = intel_guc_send_ct;
> -	guc->handler = intel_guc_to_host_event_handler_ct;
> -
>  	/* check for mmio messages received before/during the CT enable */
>  	guc_get_mmio_msg(guc);
>  	guc_handle_mmio_msg(guc);
> @@ -216,7 +213,7 @@ static int guc_enable_communication(struct intel_guc  
> *guc)
> 	/* check for CT messages received before we enabled interrupts */
>  	spin_lock_irq(&i915->irq_lock);
> -	intel_guc_to_host_event_handler_ct(guc);
> +	intel_guc_ct_event_handler(&guc->ct);
>  	spin_unlock_irq(&i915->irq_lock);
> 	DRM_INFO("GuC communication enabled\n");
> @@ -235,9 +232,6 @@ static void guc_disable_communication(struct  
> intel_guc *guc)
> 	guc_disable_interrupts(guc);
> -	guc->send = intel_guc_send_nop;
> -	guc->handler = intel_guc_to_host_event_handler_nop;
> -
>  	intel_guc_ct_disable(&guc->ct);
> 	/*
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Re: [Intel-gfx] [PATCH v2 4/7] drm/i915/guc/ct: Group request-related variables in a sub-structure

[Daniele Ceraolo Spurio]

On 12/17/19 1:42 PM, Michal Wajdeczko wrote:
> On Tue, 17 Dec 2019 02:23:13 +0100, Daniele Ceraolo Spurio 
> <daniele.ceraolospurio@intel.com> wrote:
> 
>> For better isolation of the request tracking from the rest of the
>> CT-related data.
>>
>> v2: split to separate patch, move next_fence to substructure (Michal)
>>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
>> Cc: John Harrison <John.C.Harrison@Intel.com>
>> Cc: Matthew Brost <matthew.brost@intel.com>
>> ---
> 
> Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> 
> with some nits below (we may fix them later)
> 
> /snip/
> 
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h 
>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
>> index 6e3d789b9f01..29a026dc3a13 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
>> @@ -48,12 +48,15 @@ struct intel_guc_ct {
>>      /* buffers for sending(0) and receiving(1) commands */
>>      struct intel_guc_ct_buffer ctbs[2];
>> -    u32 next_fence; /* fence to be used with next send command */
>> +    struct {
>> +        u32 next_fence; /* fence to be used with next request to send */
> 
> nit: strictly speaking this is "last" fence
>       we just use it to generate next one
> 
>> -    spinlock_t lock; /* protects pending requests list */
>> -    struct list_head pending_requests; /* requests waiting for 
>> response */
>> -    struct list_head incoming_requests; /* incoming requests */
>> -    struct work_struct worker; /* handler for incoming requests */
>> +        spinlock_t lock; /* protects pending requests list */
> 
> nit: do we want to use this lock to protect "next/last" fence ?
>       if yes, then maybe lock shall be first ?

We currently only touch this while holding send_mutex, so we don't need 
the spinlock as well. We can move it later if we ever re-organize the 
locking structure.

Daniele

> 
>> +        struct list_head pending; /* requests waiting for response */
>> +
>> +        struct list_head incoming; /* incoming requests */
>> +        struct work_struct worker; /* handler for incoming requests */
>> +    } requests;
>>  };
>> void intel_guc_ct_init_early(struct intel_guc_ct *ct);
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Re: [Intel-gfx] [PATCH v2 5/7] drm/i915/guc: Remove function pointers for send/receive calls

[Daniele Ceraolo Spurio]

On 12/17/19 1:49 PM, Michal Wajdeczko wrote:
> On Tue, 17 Dec 2019 02:23:14 +0100, Daniele Ceraolo Spurio 
> <daniele.ceraolospurio@intel.com> wrote:
> 
>> Since we started using CT buffers on all gens, the function pointers can
>> only be set to either the _nop() or the _ct() functions. Since the
>> _nop() case applies to when the CT are disabled, we can just handle that
>> case in the _ct() functions and call them directly.
>>
>> v2: keep intel_guc_send() and make the CT send/receive functions work on
>>     intel_guc_ct. (Michal)
>>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
>> Cc: John Harrison <John.C.Harrison@Intel.com>
>> Cc: Matthew Brost <matthew.brost@intel.com>
>> ---
>>  drivers/gpu/drm/i915/gt/uc/intel_guc.c        | 14 -------------
>>  drivers/gpu/drm/i915/gt/uc/intel_guc.h        | 18 ++++-------------
>>  drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c     | 16 ++++++++++-----
>>  drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h     |  9 +++++++--
>>  .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  1 -
>>  drivers/gpu/drm/i915/gt/uc/intel_uc.c         | 20 +++++++------------
>>  6 files changed, 29 insertions(+), 49 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
>> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> index 922a19635d20..daebfec0034c 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> @@ -177,8 +177,6 @@ void intel_guc_init_early(struct intel_guc *guc)
>>     mutex_init(&guc->send_mutex);
>>      spin_lock_init(&guc->irq_lock);
>> -    guc->send = intel_guc_send_nop;
>> -    guc->handler = intel_guc_to_host_event_handler_nop;
>>      if (INTEL_GEN(i915) >= 11) {
>>          guc->notify = gen11_guc_raise_irq;
>>          guc->interrupts.reset = gen11_reset_guc_interrupts;
>> @@ -403,18 +401,6 @@ void intel_guc_fini(struct intel_guc *guc)
>>      intel_uc_fw_cleanup_fetch(&guc->fw);
>>  }
>> -int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 
>> len,
>> -               u32 *response_buf, u32 response_buf_size)
>> -{
>> -    WARN(1, "Unexpected send: action=%#x\n", *action);
>> -    return -ENODEV;
>> -}
>> -
>> -void intel_guc_to_host_event_handler_nop(struct intel_guc *guc)
>> -{
>> -    WARN(1, "Unexpected event: no suitable handler\n");
>> -}
>> -
>>  /*
>>   * This function implements the MMIO based host to GuC interface.
>>   */
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
>> b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
>> index cd09c912e361..253b1ac7716e 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
>> @@ -70,13 +70,6 @@ struct intel_guc {
>>      /* To serialize the intel_guc_send actions */
>>      struct mutex send_mutex;
>> -    /* GuC's FW specific send function */
>> -    int (*send)(struct intel_guc *guc, const u32 *data, u32 len,
>> -            u32 *response_buf, u32 response_buf_size);
>> -
>> -    /* GuC's FW specific event handler function */
>> -    void (*handler)(struct intel_guc *guc);
>> -
>>      /* GuC's FW specific notify function */
>>      void (*notify)(struct intel_guc *guc);
>>  };
>> @@ -84,14 +77,15 @@ struct intel_guc {
>>  static
>>  inline int intel_guc_send(struct intel_guc *guc, const u32 *action, 
>> u32 len)
>>  {
>> -    return guc->send(guc, action, len, NULL, 0);
>> +    return intel_guc_ct_send(&guc->ct, action, len, NULL, 0);
>>  }
>> static inline int
>>  intel_guc_send_and_receive(struct intel_guc *guc, const u32 *action, 
>> u32 len,
>>                 u32 *response_buf, u32 response_buf_size)
>>  {
>> -    return guc->send(guc, action, len, response_buf, response_buf_size);
>> +    return intel_guc_ct_send(&guc->ct, action, len,
>> +                 response_buf, response_buf_size);
>>  }
>> static inline void intel_guc_notify(struct intel_guc *guc)
>> @@ -101,7 +95,7 @@ static inline void intel_guc_notify(struct 
>> intel_guc *guc)
>> static inline void intel_guc_to_host_event_handler(struct intel_guc *guc)
>>  {
>> -    guc->handler(guc);
>> +    intel_guc_ct_event_handler(&guc->ct);
>>  }
>> /* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */
>> @@ -136,12 +130,8 @@ void intel_guc_init_send_regs(struct intel_guc 
>> *guc);
>>  void intel_guc_write_params(struct intel_guc *guc);
>>  int intel_guc_init(struct intel_guc *guc);
>>  void intel_guc_fini(struct intel_guc *guc);
>> -int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 
>> len,
>> -               u32 *response_buf, u32 response_buf_size);
>>  int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 
>> len,
>>              u32 *response_buf, u32 response_buf_size);
>> -void intel_guc_to_host_event_handler(struct intel_guc *guc);
>> -void intel_guc_to_host_event_handler_nop(struct intel_guc *guc);
>>  int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
>>                         const u32 *payload, u32 len);
>>  int intel_guc_sample_forcewake(struct intel_guc *guc);
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 
>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>> index f22cd9b2311b..c6f971a049f9 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>> @@ -510,13 +510,18 @@ static int ct_send(struct intel_guc_ct *ct,
>>  /*
>>   * Command Transport (CT) buffer based GuC send function.
>>   */
>> -int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len,
>> +int intel_guc_ct_send(struct intel_guc_ct *ct, const u32 *action, u32 
>> len,
>>                u32 *response_buf, u32 response_buf_size)
>>  {
>> -    struct intel_guc_ct *ct = &guc->ct;
>> +    struct intel_guc *guc = ct_to_guc(ct);
>>      u32 status = ~0; /* undefined */
>>      int ret;
>> +    if (unlikely(!ct->enabled)) {
>> +        WARN(1, "Unexpected send: action=%#x\n", *action);
>> +        return -ENODEV;
>> +    }
>> +
>>      mutex_lock(&guc->send_mutex);
>>     ret = ct_send(ct, action, len, response_buf, response_buf_size, 
>> &status);
>> @@ -787,15 +792,16 @@ static int ct_handle_request(struct intel_guc_ct 
>> *ct, const u32 *msg)
>>   * When we're communicating with the GuC over CT, GuC uses events
>>   * to notify us about new messages being posted on the RECV buffer.
>>   */
>> -void intel_guc_to_host_event_handler_ct(struct intel_guc *guc)
>> +void intel_guc_ct_event_handler(struct intel_guc_ct *ct)
>>  {
>> -    struct intel_guc_ct *ct = &guc->ct;
>>      struct intel_guc_ct_buffer *ctb = &ct->ctbs[CTB_RECV];
>>      u32 msg[GUC_CT_MSG_LEN_MASK + 1]; /* one extra dw for the header */
>>      int err = 0;
>> -    if (!ct->enabled)
>> +    if (unlikely(!ct->enabled)) {
>> +        WARN(1, "Unexpected GuC event received while CT disabled!\n");
> 
> hmm, maybe we should just return false to indicate that we didn't
> process that G2H event and decide in irq_handler what to do with that?

IMO it only makes sense to modify the return chain if we indeed end up 
doing something with the returned code, but I don't see what we could do 
with it in addition to printing an error, which we already do in this 
function.

Anyway, I believe such a change should be separate from this series as 
here the focus is on simplifying the structures.

> but not a blocker, so
> 
> Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>

Thanks for quickly reviewing all the patches!

Daniele

> 
> Michal
> 
>>          return;
>> +    }
>>     do {
>>          err = ctb_read(ctb, msg);
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h 
>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
>> index 29a026dc3a13..3e7fe237cfa5 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
>> @@ -65,8 +65,13 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct);
>>  int intel_guc_ct_enable(struct intel_guc_ct *ct);
>>  void intel_guc_ct_disable(struct intel_guc_ct *ct);
>> -int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len,
>> +static inline bool intel_guc_ct_enabled(struct intel_guc_ct *ct)
>> +{
>> +    return ct->enabled;
>> +}
>> +
>> +int intel_guc_ct_send(struct intel_guc_ct *ct, const u32 *action, u32 
>> len,
>>                u32 *response_buf, u32 response_buf_size);
>> -void intel_guc_to_host_event_handler_ct(struct intel_guc *guc);
>> +void intel_guc_ct_event_handler(struct intel_guc_ct *ct);
>> #endif /* _INTEL_GUC_CT_H_ */
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> index af04ed6e48d9..44a7d2e736a7 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> @@ -43,7 +43,6 @@
>>   * Firmware writes a success/fail code back to the action register after
>>   * processes the request. The kernel driver polls waiting for this 
>> update and
>>   * then proceeds.
>> - * See intel_guc_send()
>>   *
>>   * Work Items:
>>   * There are several types of work items that the host may place into a
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c 
>> b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
>> index 6e17e449e0a8..782b8f95183f 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
>> @@ -123,6 +123,11 @@ static void __uc_free_load_err_log(struct 
>> intel_uc *uc)
>>          i915_gem_object_put(log);
>>  }
>> +static inline bool guc_communication_enabled(struct intel_guc *guc)
>> +{
>> +    return intel_guc_ct_enabled(&guc->ct);
>> +}
>> +
>>  /*
>>   * Events triggered while CT buffers are disabled are logged in the 
>> SCRATCH_15
>>   * register using the same bits used in the CT message payload. Since 
>> our
>> @@ -158,7 +163,7 @@ static void guc_handle_mmio_msg(struct intel_guc 
>> *guc)
>>      struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>>     /* we need communication to be enabled to reply to GuC */
>> -    GEM_BUG_ON(guc->handler == intel_guc_to_host_event_handler_nop);
>> +    GEM_BUG_ON(!guc_communication_enabled(guc));
>>     if (!guc->mmio_msg)
>>          return;
>> @@ -185,11 +190,6 @@ static void guc_disable_interrupts(struct 
>> intel_guc *guc)
>>      guc->interrupts.disable(guc);
>>  }
>> -static inline bool guc_communication_enabled(struct intel_guc *guc)
>> -{
>> -    return guc->send != intel_guc_send_nop;
>> -}
>> -
>>  static int guc_enable_communication(struct intel_guc *guc)
>>  {
>>      struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>> @@ -205,9 +205,6 @@ static int guc_enable_communication(struct 
>> intel_guc *guc)
>>      if (ret)
>>          return ret;
>> -    guc->send = intel_guc_send_ct;
>> -    guc->handler = intel_guc_to_host_event_handler_ct;
>> -
>>      /* check for mmio messages received before/during the CT enable */
>>      guc_get_mmio_msg(guc);
>>      guc_handle_mmio_msg(guc);
>> @@ -216,7 +213,7 @@ static int guc_enable_communication(struct 
>> intel_guc *guc)
>>     /* check for CT messages received before we enabled interrupts */
>>      spin_lock_irq(&i915->irq_lock);
>> -    intel_guc_to_host_event_handler_ct(guc);
>> +    intel_guc_ct_event_handler(&guc->ct);
>>      spin_unlock_irq(&i915->irq_lock);
>>     DRM_INFO("GuC communication enabled\n");
>> @@ -235,9 +232,6 @@ static void guc_disable_communication(struct 
>> intel_guc *guc)
>>     guc_disable_interrupts(guc);
>> -    guc->send = intel_guc_send_nop;
>> -    guc->handler = intel_guc_to_host_event_handler_nop;
>> -
>>      intel_guc_ct_disable(&guc->ct);
>>     /*
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Re: [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/7] drm/i915/guc: Merge communication_stop and communication_disable

[Daniele Ceraolo Spurio]

On 12/17/19 5:31 AM, Patchwork wrote:
> == Series Details ==
> 
> Series: series starting with [v2,1/7] drm/i915/guc: Merge communication_stop and communication_disable
> URL   : https://patchwork.freedesktop.org/series/71020/
> State : success
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_7578_full -> Patchwork_15805_full
> ====================================================
> 
> Summary
> -------
> 
>    **SUCCESS**
> 
>    No regressions found.
> 
>    
> 
> Possible new issues
> -------------------
> 
>    Here are the unknown changes that may have been introduced in Patchwork_15805_full:
> 
> ### Piglit changes ###
> 
> #### Possible regressions ####
> 
>    * spec@ext_framebuffer_multisample@bitmap 6 (NEW):
>      - {pig-hsw-4770r}:    NOTRUN -> [FAIL][1] +4 similar issues
>     [1]: None

No logs here, but other series are hitting similar issues on this 
machine so I'm pretty sure it isn't this series' fault.

Patches pushed.

Thanks,
Daniele

> 
>    
> New tests
> ---------
> 
>    New tests have been introduced between CI_DRM_7578_full and Patchwork_15805_full:
> 
> ### New Piglit tests (5) ###
> 
>    * spec@arb_gpu_shader5@texturegatheroffset@vs-rg-0-unorm-2darray-const:
>      - Statuses : 1 fail(s)
>      - Exec time: [7.36] s
> 
>    * spec@arb_stencil_texturing@draw:
>      - Statuses : 1 fail(s)
>      - Exec time: [0.11] s
> 
>    * spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-float_mat3_array3-position-double_dvec3_array2:
>      - Statuses : 1 fail(s)
>      - Exec time: [0.17] s
> 
>    * spec@ext_framebuffer_multisample@bitmap 6:
>      - Statuses : 1 fail(s)
>      - Exec time: [0.23] s
> 
>    * spec@glsl-4.10@execution@vs_in@vs-input-uint_uvec4_array3-double_double_array2-position:
>      - Statuses : 1 fail(s)
>      - Exec time: [0.23] s
> 
>    
> 
> Known issues
> ------------
> 
>    Here are the changes found in Patchwork_15805_full that come from known issues:
> 
> ### IGT changes ###
> 
> #### Issues hit ####
> 
>    * igt@gem_ctx_isolation@vcs1-none:
>      - shard-iclb:         [PASS][2] -> [SKIP][3] ([fdo#109276] / [fdo#112080]) +1 similar issue
>     [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb1/igt@gem_ctx_isolation@vcs1-none.html
>     [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-iclb3/igt@gem_ctx_isolation@vcs1-none.html
> 
>    * igt@gem_eio@in-flight-suspend:
>      - shard-tglb:         [PASS][4] -> [INCOMPLETE][5] ([i915#456] / [i915#460] / [i915#534])
>     [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb3/igt@gem_eio@in-flight-suspend.html
>     [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb3/igt@gem_eio@in-flight-suspend.html
> 
>    * igt@gem_eio@kms:
>      - shard-tglb:         [PASS][6] -> [INCOMPLETE][7] ([i915#476])
>     [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb7/igt@gem_eio@kms.html
>     [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb8/igt@gem_eio@kms.html
> 
>    * igt@gem_exec_parallel@fds:
>      - shard-tglb:         [PASS][8] -> [INCOMPLETE][9] ([i915#470])
>     [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb3/igt@gem_exec_parallel@fds.html
>     [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb9/igt@gem_exec_parallel@fds.html
> 
>    * igt@gem_exec_parallel@vecs0:
>      - shard-tglb:         [PASS][10] -> [INCOMPLETE][11] ([fdo#111736])
>     [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb3/igt@gem_exec_parallel@vecs0.html
>     [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb2/igt@gem_exec_parallel@vecs0.html
> 
>    * igt@gem_exec_schedule@fifo-bsd1:
>      - shard-iclb:         [PASS][12] -> [SKIP][13] ([fdo#109276]) +5 similar issues
>     [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb4/igt@gem_exec_schedule@fifo-bsd1.html
>     [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-iclb6/igt@gem_exec_schedule@fifo-bsd1.html
> 
>    * igt@gem_exec_schedule@independent-bsd:
>      - shard-iclb:         [PASS][14] -> [SKIP][15] ([fdo#112146])
>     [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb3/igt@gem_exec_schedule@independent-bsd.html
>     [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-iclb1/igt@gem_exec_schedule@independent-bsd.html
> 
>    * igt@gem_ppgtt@flink-and-close-vma-leak:
>      - shard-glk:          [PASS][16] -> [FAIL][17] ([i915#644])
>     [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-glk7/igt@gem_ppgtt@flink-and-close-vma-leak.html
>     [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-glk2/igt@gem_ppgtt@flink-and-close-vma-leak.html
> 
>    * igt@gem_sync@basic-store-all:
>      - shard-tglb:         [PASS][18] -> [INCOMPLETE][19] ([i915#472])
>     [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb9/igt@gem_sync@basic-store-all.html
>     [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb6/igt@gem_sync@basic-store-all.html
> 
>    * igt@i915_hangman@error-state-capture-vcs1:
>      - shard-iclb:         [PASS][20] -> [SKIP][21] ([fdo#112080]) +6 similar issues
>     [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb1/igt@i915_hangman@error-state-capture-vcs1.html
>     [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-iclb3/igt@i915_hangman@error-state-capture-vcs1.html
> 
>    * igt@i915_pm_rpm@modeset-stress-extra-wait:
>      - shard-glk:          [PASS][22] -> [DMESG-WARN][23] ([i915#118] / [i915#95])
>     [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-glk4/igt@i915_pm_rpm@modeset-stress-extra-wait.html
>     [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-glk8/igt@i915_pm_rpm@modeset-stress-extra-wait.html
> 
>    * igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen:
>      - shard-hsw:          [PASS][24] -> [DMESG-WARN][25] ([IGT#6])
>     [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-hsw4/igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen.html
>     [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-hsw6/igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen.html
> 
>    * igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding:
>      - shard-skl:          [PASS][26] -> [FAIL][27] ([i915#54]) +3 similar issues
>     [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-skl6/igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding.html
>     [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-skl4/igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding.html
> 
>    * igt@kms_flip@flip-vs-expired-vblank-interruptible:
>      - shard-skl:          [PASS][28] -> [FAIL][29] ([i915#79])
>     [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
>     [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
> 
>    * igt@kms_flip@flip-vs-suspend:
>      - shard-hsw:          [PASS][30] -> [INCOMPLETE][31] ([i915#61])
>     [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-hsw6/igt@kms_flip@flip-vs-suspend.html
>     [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-hsw4/igt@kms_flip@flip-vs-suspend.html
> 
>    * igt@kms_flip@flip-vs-suspend-interruptible:
>      - shard-apl:          [PASS][32] -> [DMESG-WARN][33] ([i915#180])
>     [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible.html
>     [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible.html
> 
>    * igt@kms_frontbuffer_tracking@fbc-suspend:
>      - shard-tglb:         [PASS][34] -> [INCOMPLETE][35] ([i915#456] / [i915#460] / [i915#474])
>     [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb4/igt@kms_frontbuffer_tracking@fbc-suspend.html
>     [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-suspend.html
> 
>    * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move:
>      - shard-tglb:         [PASS][36] -> [INCOMPLETE][37] ([i915#474] / [i915#667])
>     [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html
>     [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html
> 
>    * igt@kms_frontbuffer_tracking@psr-suspend:
>      - shard-tglb:         [PASS][38] -> [INCOMPLETE][39] ([i915#456] / [i915#460]) +1 similar issue
>     [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb8/igt@kms_frontbuffer_tracking@psr-suspend.html
>     [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb3/igt@kms_frontbuffer_tracking@psr-suspend.html
> 
>    * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
>      - shard-skl:          [PASS][40] -> [FAIL][41] ([fdo#108145] / [i915#265])
>     [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
>     [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
> 
>    * igt@kms_psr@psr2_cursor_plane_onoff:
>      - shard-iclb:         [PASS][42] -> [SKIP][43] ([fdo#109441]) +1 similar issue
>     [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html
>     [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-iclb4/igt@kms_psr@psr2_cursor_plane_onoff.html
> 
>    * igt@kms_setmode@basic:
>      - shard-apl:          [PASS][44] -> [FAIL][45] ([i915#31])
>     [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-apl8/igt@kms_setmode@basic.html
>     [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-apl7/igt@kms_setmode@basic.html
> 
>    * igt@perf@oa-exponents:
>      - shard-tglb:         [PASS][46] -> [FAIL][47] ([i915#84])
>     [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb4/igt@perf@oa-exponents.html
>     [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb6/igt@perf@oa-exponents.html
> 
>    
> #### Possible fixes ####
> 
>    * igt@gem_busy@close-race:
>      - shard-tglb:         [INCOMPLETE][48] ([i915#435]) -> [PASS][49]
>     [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb6/igt@gem_busy@close-race.html
>     [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb2/igt@gem_busy@close-race.html
> 
>    * igt@gem_ctx_isolation@bcs0-s3:
>      - shard-tglb:         [INCOMPLETE][50] ([i915#456]) -> [PASS][51] +1 similar issue
>     [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb5/igt@gem_ctx_isolation@bcs0-s3.html
>     [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb1/igt@gem_ctx_isolation@bcs0-s3.html
> 
>    * igt@gem_ctx_persistence@vcs0-mixed-process:
>      - shard-apl:          [FAIL][52] ([i915#679]) -> [PASS][53]
>     [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-apl3/igt@gem_ctx_persistence@vcs0-mixed-process.html
>     [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-apl1/igt@gem_ctx_persistence@vcs0-mixed-process.html
> 
>    * igt@gem_ctx_persistence@vcs1-persistence:
>      - shard-iclb:         [SKIP][54] ([fdo#109276] / [fdo#112080]) -> [PASS][55]
>     [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb3/igt@gem_ctx_persistence@vcs1-persistence.html
>     [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-iclb1/igt@gem_ctx_persistence@vcs1-persistence.html
> 
>    * igt@gem_eio@banned:
>      - shard-tglb:         [INCOMPLETE][56] ([i915#476]) -> [PASS][57]
>     [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb6/igt@gem_eio@banned.html
>     [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb9/igt@gem_eio@banned.html
> 
>    * igt@gem_exec_reloc@basic-wc-active:
>      - shard-skl:          [DMESG-WARN][58] ([i915#109]) -> [PASS][59]
>     [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-skl8/igt@gem_exec_reloc@basic-wc-active.html
>     [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-skl7/igt@gem_exec_reloc@basic-wc-active.html
> 
>    * igt@gem_exec_schedule@preempt-queue-contexts-vebox:
>      - shard-tglb:         [INCOMPLETE][60] ([fdo#111677]) -> [PASS][61]
>     [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb6/igt@gem_exec_schedule@preempt-queue-contexts-vebox.html
>     [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb9/igt@gem_exec_schedule@preempt-queue-contexts-vebox.html
> 
>    * igt@gem_exec_schedule@preemptive-hang-bsd:
>      - shard-iclb:         [SKIP][62] ([fdo#112146]) -> [PASS][63] +3 similar issues
>     [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb1/igt@gem_exec_schedule@preemptive-hang-bsd.html
>     [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-iclb3/igt@gem_exec_schedule@preemptive-hang-bsd.html
> 
>    * igt@gem_sync@basic-each:
>      - shard-tglb:         [INCOMPLETE][64] ([i915#472] / [i915#707]) -> [PASS][65]
>     [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb9/igt@gem_sync@basic-each.html
>     [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb9/igt@gem_sync@basic-each.html
> 
>    * igt@gem_tiled_blits@interruptible:
>      - shard-hsw:          [FAIL][66] ([i915#818]) -> [PASS][67]
>     [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-hsw7/igt@gem_tiled_blits@interruptible.html
>     [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-hsw4/igt@gem_tiled_blits@interruptible.html
> 
>    * {igt@gen9_exec_parse@allowed-single}:
>      - shard-apl:          [DMESG-WARN][68] ([i915#716]) -> [PASS][69]
>     [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-apl7/igt@gen9_exec_parse@allowed-single.html
>     [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-apl6/igt@gen9_exec_parse@allowed-single.html
> 
>    * igt@i915_suspend@fence-restore-tiled2untiled:
>      - shard-apl:          [DMESG-WARN][70] ([i915#180]) -> [PASS][71] +3 similar issues
>     [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html
>     [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html
> 
>    * igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding:
>      - shard-hsw:          [DMESG-WARN][72] ([IGT#6]) -> [PASS][73]
>     [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-hsw6/igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding.html
>     [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-hsw4/igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding.html
> 
>    * igt@kms_cursor_crc@pipe-d-cursor-suspend:
>      - shard-tglb:         [INCOMPLETE][74] ([i915#460]) -> [PASS][75]
>     [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb2/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
>     [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb6/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
> 
>    * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
>      - shard-glk:          [FAIL][76] ([i915#79]) -> [PASS][77]
>     [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
>     [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
> 
>    * igt@kms_flip@flip-vs-expired-vblank-interruptible:
>      - shard-apl:          [FAIL][78] ([i915#79]) -> [PASS][79]
>     [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-apl8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
>     [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-apl8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
> 
>    * igt@kms_flip@flip-vs-suspend:
>      - shard-skl:          [INCOMPLETE][80] ([i915#221]) -> [PASS][81]
>     [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-skl4/igt@kms_flip@flip-vs-suspend.html
>     [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-skl1/igt@kms_flip@flip-vs-suspend.html
> 
>    * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt:
>      - shard-tglb:         [FAIL][82] ([i915#49]) -> [PASS][83] +2 similar issues
>     [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
>     [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
> 
>    * igt@kms_frontbuffer_tracking@fbcpsr-suspend:
>      - shard-tglb:         [INCOMPLETE][84] ([i915#456] / [i915#460] / [i915#474]) -> [PASS][85]
>     [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
>     [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
> 
>    * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
>      - shard-iclb:         [INCOMPLETE][86] ([i915#140] / [i915#246]) -> [PASS][87]
>     [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb4/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
>     [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-iclb2/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
> 
>    * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
>      - shard-kbl:          [DMESG-WARN][88] ([i915#180]) -> [PASS][89] +2 similar issues
>     [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
>     [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
> 
>    * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
>      - shard-skl:          [FAIL][90] ([fdo#108145]) -> [PASS][91] +1 similar issue
>     [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
>     [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
> 
>    * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
>      - shard-skl:          [FAIL][92] ([fdo#108145] / [i915#265]) -> [PASS][93]
>     [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
>     [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
> 
>    * igt@kms_psr@psr2_sprite_mmap_gtt:
>      - shard-iclb:         [SKIP][94] ([fdo#109441]) -> [PASS][95]
>     [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb5/igt@kms_psr@psr2_sprite_mmap_gtt.html
>     [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
> 
>    * igt@perf_pmu@busy-no-semaphores-vcs1:
>      - shard-iclb:         [SKIP][96] ([fdo#112080]) -> [PASS][97] +3 similar issues
>     [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb8/igt@perf_pmu@busy-no-semaphores-vcs1.html
>     [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-iclb4/igt@perf_pmu@busy-no-semaphores-vcs1.html
> 
>    * igt@prime_vgem@fence-wait-bsd2:
>      - shard-iclb:         [SKIP][98] ([fdo#109276]) -> [PASS][99] +10 similar issues
>     [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-iclb3/igt@prime_vgem@fence-wait-bsd2.html
>     [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-iclb1/igt@prime_vgem@fence-wait-bsd2.html
> 
>    
> #### Warnings ####
> 
>    * igt@gem_ctx_isolation@vcs2-dirty-create:
>      - shard-tglb:         [SKIP][100] ([fdo#111912] / [fdo#112080]) -> [SKIP][101] ([fdo#112080]) +1 similar issue
>     [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb6/igt@gem_ctx_isolation@vcs2-dirty-create.html
>     [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb9/igt@gem_ctx_isolation@vcs2-dirty-create.html
> 
>    * igt@gem_tiled_blits@normal:
>      - shard-hsw:          [FAIL][102] ([i915#818]) -> [FAIL][103] ([i915#832])
>     [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-hsw7/igt@gem_tiled_blits@normal.html
>     [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-hsw4/igt@gem_tiled_blits@normal.html
> 
>    * igt@kms_atomic_transition@6x-modeset-transitions:
>      - shard-tglb:         [SKIP][104] ([fdo#112021]) -> [SKIP][105] ([fdo#112016] / [fdo#112021])
>     [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb9/igt@kms_atomic_transition@6x-modeset-transitions.html
>     [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-tglb6/igt@kms_atomic_transition@6x-modeset-transitions.html
> 
>    * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
>      - shard-skl:          [INCOMPLETE][106] ([i915#648]) -> [INCOMPLETE][107] ([i915#648] / [i915#667])
>     [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-skl5/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html
>     [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-skl4/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html
> 
>    * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
>      - shard-skl:          [INCOMPLETE][108] ([fdo#112347] / [i915#648] / [i915#667]) -> [INCOMPLETE][109] ([fdo#112347] / [fdo#112391] / [i915#648] / [i915#667])
>     [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-skl7/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
>     [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/shard-skl3/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
> 
>    
>    {name}: This element is suppressed. This means it is ignored when computing
>            the status of the difference (SUCCESS, WARNING, or FAILURE).
> 
>    [IGT#6]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/6
>    [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
>    [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
>    [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
>    [fdo#111677]: https://bugs.freedesktop.org/show_bug.cgi?id=111677
>    [fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736
>    [fdo#111912]: https://bugs.freedesktop.org/show_bug.cgi?id=111912
>    [fdo#112016]: https://bugs.freedesktop.org/show_bug.cgi?id=112016
>    [fdo#112021]: https://bugs.freedesktop.org/show_bug.cgi?id=112021
>    [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
>    [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
>    [fdo#112347]: https://bugs.freedesktop.org/show_bug.cgi?id=112347
>    [fdo#112391]: https://bugs.freedesktop.org/show_bug.cgi?id=112391
>    [i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
>    [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
>    [i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140
>    [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
>    [i915#221]: https://gitlab.freedesktop.org/drm/intel/issues/221
>    [i915#246]: https://gitlab.freedesktop.org/drm/intel/issues/246
>    [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
>    [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
>    [i915#435]: https://gitlab.freedesktop.org/drm/intel/issues/435
>    [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
>    [i915#460]: https://gitlab.freedesktop.org/drm/intel/issues/460
>    [i915#470]: https://gitlab.freedesktop.org/drm/intel/issues/470
>    [i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472
>    [i915#474]: https://gitlab.freedesktop.org/drm/intel/issues/474
>    [i915#476]: https://gitlab.freedesktop.org/drm/intel/issues/476
>    [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
>    [i915#534]: https://gitlab.freedesktop.org/drm/intel/issues/534
>    [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
>    [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
>    [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
>    [i915#648]: https://gitlab.freedesktop.org/drm/intel/issues/648
>    [i915#667]: https://gitlab.freedesktop.org/drm/intel/issues/667
>    [i915#679]: https://gitlab.freedesktop.org/drm/intel/issues/679
>    [i915#707]: https://gitlab.freedesktop.org/drm/intel/issues/707
>    [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
>    [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
>    [i915#818]: https://gitlab.freedesktop.org/drm/intel/issues/818
>    [i915#832]: https://gitlab.freedesktop.org/drm/intel/issues/832
>    [i915#84]: https://gitlab.freedesktop.org/drm/intel/issues/84
>    [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
> 
> 
> Participating hosts (10 -> 11)
> ------------------------------
> 
>    Additional (1): pig-hsw-4770r
> 
> 
> Build changes
> -------------
> 
>    * CI: CI-20190529 -> None
>    * Linux: CI_DRM_7578 -> Patchwork_15805
> 
>    CI-20190529: 20190529
>    CI_DRM_7578: cc329d389f5609d2969d0797bc96f754adb26d62 @ git://anongit.freedesktop.org/gfx-ci/linux
>    IGT_5349: 048f58513d8b8ec6bb307a939f0ac959bc0f0e10 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>    Patchwork_15805: ea5f8a3163af3b8faacefeaca30363aeebd40ef7 @ git://anongit.freedesktop.org/gfx-ci/linux
>    piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15805/index.html
> 
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