* [PULL 01/88] ppc/pnv: Add a PNOR model
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
@ 2019-12-17 4:41 ` David Gibson
2020-01-07 14:43 ` Peter Maydell
2019-12-17 4:41 ` [PULL 02/88] ppc/pnv: Add a "/qemu" device tree node David Gibson
` (87 subsequent siblings)
88 siblings, 1 reply; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:41 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, Cédric Le Goater, qemu-ppc,
clg, David Gibson
From: Cédric Le Goater <clg@fr.ibm.com>
On a POWERPC PowerNV system, the host firmware is stored in a PNOR
flash chip which contents is mapped on the LPC bus. This model adds a
simple dummy device to map the contents of a block device in the host
address space.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191021131215.3693-2-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/Makefile.objs | 4 +-
hw/ppc/pnv.c | 14 ++++
hw/ppc/pnv_pnor.c | 135 ++++++++++++++++++++++++++++++++++++++
include/hw/ppc/pnv.h | 3 +
include/hw/ppc/pnv_pnor.h | 25 +++++++
5 files changed, 180 insertions(+), 1 deletion(-)
create mode 100644 hw/ppc/pnv_pnor.c
create mode 100644 include/hw/ppc/pnv_pnor.h
diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs
index 580bb4f0dd..101e9fc591 100644
--- a/hw/ppc/Makefile.objs
+++ b/hw/ppc/Makefile.objs
@@ -9,7 +9,9 @@ obj-$(CONFIG_PSERIES) += spapr_tpm_proxy.o
obj-$(CONFIG_SPAPR_RNG) += spapr_rng.o
# IBM PowerNV
obj-$(CONFIG_POWERNV) += pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o pnv_psi.o pnv_occ.o pnv_bmc.o
-obj-$(CONFIG_POWERNV) += pnv_homer.o
+obj-$(CONFIG_POWERNV) += pnv_homer.o pnv_pnor.o
+
+
ifeq ($(CONFIG_PCI)$(CONFIG_PSERIES)$(CONFIG_LINUX), yyy)
obj-y += spapr_pci_vfio.o spapr_pci_nvlink2.o
endif
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 627c08e5b9..d0c1d42277 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -44,6 +44,7 @@
#include "hw/ppc/xics.h"
#include "hw/qdev-properties.h"
#include "hw/ppc/pnv_xscom.h"
+#include "hw/ppc/pnv_pnor.h"
#include "hw/isa/isa.h"
#include "hw/boards.h"
@@ -633,6 +634,8 @@ static void pnv_init(MachineState *machine)
long fw_size;
int i;
char *chip_typename;
+ DriveInfo *pnor = drive_get(IF_MTD, 0, 0);
+ DeviceState *dev;
/* allocate RAM */
if (machine->ram_size < (1 * GiB)) {
@@ -644,6 +647,17 @@ static void pnv_init(MachineState *machine)
machine->ram_size);
memory_region_add_subregion(get_system_memory(), 0, ram);
+ /*
+ * Create our simple PNOR device
+ */
+ dev = qdev_create(NULL, TYPE_PNV_PNOR);
+ if (pnor) {
+ qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor),
+ &error_abort);
+ }
+ qdev_init_nofail(dev);
+ pnv->pnor = PNV_PNOR(dev);
+
/* load skiboot firmware */
if (bios_name == NULL) {
bios_name = FW_FILE_NAME;
diff --git a/hw/ppc/pnv_pnor.c b/hw/ppc/pnv_pnor.c
new file mode 100644
index 0000000000..bfb1e92b03
--- /dev/null
+++ b/hw/ppc/pnv_pnor.c
@@ -0,0 +1,135 @@
+/*
+ * QEMU PowerNV PNOR simple model
+ *
+ * Copyright (c) 2015-2019, IBM Corporation.
+ *
+ * This code is licensed under the GPL version 2 or later. See the
+ * COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "sysemu/block-backend.h"
+#include "sysemu/blockdev.h"
+#include "hw/loader.h"
+#include "hw/ppc/pnv_pnor.h"
+#include "hw/qdev-properties.h"
+
+static uint64_t pnv_pnor_read(void *opaque, hwaddr addr, unsigned size)
+{
+ PnvPnor *s = PNV_PNOR(opaque);
+ uint64_t ret = 0;
+ int i;
+
+ for (i = 0; i < size; i++) {
+ ret |= (uint64_t) s->storage[addr + i] << (8 * (size - i - 1));
+ }
+
+ return ret;
+}
+
+static void pnv_pnor_update(PnvPnor *s, int offset, int size)
+{
+ int offset_end;
+
+ if (s->blk) {
+ return;
+ }
+
+ offset_end = offset + size;
+ offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE);
+ offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE);
+
+ blk_pwrite(s->blk, offset, s->storage + offset,
+ offset_end - offset, 0);
+}
+
+static void pnv_pnor_write(void *opaque, hwaddr addr, uint64_t data,
+ unsigned size)
+{
+ PnvPnor *s = PNV_PNOR(opaque);
+ int i;
+
+ for (i = 0; i < size; i++) {
+ s->storage[addr + i] = (data >> (8 * (size - i - 1))) & 0xFF;
+ }
+ pnv_pnor_update(s, addr, size);
+}
+
+/*
+ * TODO: Check endianness: skiboot is BIG, Aspeed AHB is LITTLE, flash
+ * is BIG.
+ */
+static const MemoryRegionOps pnv_pnor_ops = {
+ .read = pnv_pnor_read,
+ .write = pnv_pnor_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ },
+};
+
+static void pnv_pnor_realize(DeviceState *dev, Error **errp)
+{
+ PnvPnor *s = PNV_PNOR(dev);
+ int ret;
+
+ if (s->blk) {
+ uint64_t perm = BLK_PERM_CONSISTENT_READ |
+ (blk_is_read_only(s->blk) ? 0 : BLK_PERM_WRITE);
+ ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp);
+ if (ret < 0) {
+ return;
+ }
+
+ s->size = blk_getlength(s->blk);
+ if (s->size <= 0) {
+ error_setg(errp, "failed to get flash size");
+ return;
+ }
+
+ s->storage = blk_blockalign(s->blk, s->size);
+
+ if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) {
+ error_setg(errp, "failed to read the initial flash content");
+ return;
+ }
+ } else {
+ s->storage = blk_blockalign(NULL, s->size);
+ memset(s->storage, 0xFF, s->size);
+ }
+
+ memory_region_init_io(&s->mmio, OBJECT(s), &pnv_pnor_ops, s,
+ TYPE_PNV_PNOR, s->size);
+}
+
+static Property pnv_pnor_properties[] = {
+ DEFINE_PROP_UINT32("size", PnvPnor, size, 128 << 20),
+ DEFINE_PROP_DRIVE("drive", PnvPnor, blk),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void pnv_pnor_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = pnv_pnor_realize;
+ dc->props = pnv_pnor_properties;
+}
+
+static const TypeInfo pnv_pnor_info = {
+ .name = TYPE_PNV_PNOR,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(PnvPnor),
+ .class_init = pnv_pnor_class_init,
+};
+
+static void pnv_pnor_register_types(void)
+{
+ type_register_static(&pnv_pnor_info);
+}
+
+type_init(pnv_pnor_register_types)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 0b4c722e6b..5ecd3ba6ed 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -24,6 +24,7 @@
#include "hw/sysbus.h"
#include "hw/ipmi/ipmi.h"
#include "hw/ppc/pnv_lpc.h"
+#include "hw/ppc/pnv_pnor.h"
#include "hw/ppc/pnv_psi.h"
#include "hw/ppc/pnv_occ.h"
#include "hw/ppc/pnv_homer.h"
@@ -175,6 +176,8 @@ typedef struct PnvMachineState {
IPMIBmc *bmc;
Notifier powerdown_notifier;
+
+ PnvPnor *pnor;
} PnvMachineState;
static inline bool pnv_chip_is_power9(const PnvChip *chip)
diff --git a/include/hw/ppc/pnv_pnor.h b/include/hw/ppc/pnv_pnor.h
new file mode 100644
index 0000000000..dec811695c
--- /dev/null
+++ b/include/hw/ppc/pnv_pnor.h
@@ -0,0 +1,25 @@
+/*
+ * QEMU PowerNV PNOR simple model
+ *
+ * Copyright (c) 2019, IBM Corporation.
+ *
+ * This code is licensed under the GPL version 2 or later. See the
+ * COPYING file in the top-level directory.
+ */
+#ifndef _PPC_PNV_PNOR_H
+#define _PPC_PNV_PNOR_H
+
+#define TYPE_PNV_PNOR "pnv-pnor"
+#define PNV_PNOR(obj) OBJECT_CHECK(PnvPnor, (obj), TYPE_PNV_PNOR)
+
+typedef struct PnvPnor {
+ SysBusDevice parent_obj;
+
+ BlockBackend *blk;
+
+ uint8_t *storage;
+ uint32_t size;
+ MemoryRegion mmio;
+} PnvPnor;
+
+#endif /* _PPC_PNV_PNOR_H */
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* Re: [PULL 01/88] ppc/pnv: Add a PNOR model
2019-12-17 4:41 ` [PULL 01/88] ppc/pnv: Add a PNOR model David Gibson
@ 2020-01-07 14:43 ` Peter Maydell
2020-01-07 16:26 ` Cédric Le Goater
0 siblings, 1 reply; 94+ messages in thread
From: Peter Maydell @ 2020-01-07 14:43 UTC (permalink / raw)
To: David Gibson
Cc: Laurent Vivier, Alexey Kardashevskiy, QEMU Developers, Greg Kurz,
Cédric Le Goater, qemu-ppc, Cédric Le Goater
On Tue, 17 Dec 2019 at 04:43, David Gibson <david@gibson.dropbear.id.au> wrote:
>
> From: Cédric Le Goater <clg@fr.ibm.com>
>
> On a POWERPC PowerNV system, the host firmware is stored in a PNOR
> flash chip which contents is mapped on the LPC bus. This model adds a
> simple dummy device to map the contents of a block device in the host
> address space.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> Message-Id: <20191021131215.3693-2-clg@kaod.org>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> hw/ppc/Makefile.objs | 4 +-
> hw/ppc/pnv.c | 14 ++++
> hw/ppc/pnv_pnor.c | 135 ++++++++++++++++++++++++++++++++++++++
> include/hw/ppc/pnv.h | 3 +
> include/hw/ppc/pnv_pnor.h | 25 +++++++
> 5 files changed, 180 insertions(+), 1 deletion(-)
> create mode 100644 hw/ppc/pnv_pnor.c
> create mode 100644 include/hw/ppc/pnv_pnor.h
Hi; Coverity finds some issues in this patch:
> +static void pnv_pnor_update(PnvPnor *s, int offset, int size)
> +{
> + int offset_end;
> +
> + if (s->blk) {
> + return;
> + }
> +
> + offset_end = offset + size;
> + offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE);
> + offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE);
> +
> + blk_pwrite(s->blk, offset, s->storage + offset,
> + offset_end - offset, 0);
Here we call blk_pwrite() but don't check whether it
succeeded or failed. (CID 1412228)
> +static void pnv_pnor_realize(DeviceState *dev, Error **errp)
> +{
> + PnvPnor *s = PNV_PNOR(dev);
> + int ret;
> +
> + if (s->blk) {
> + uint64_t perm = BLK_PERM_CONSISTENT_READ |
> + (blk_is_read_only(s->blk) ? 0 : BLK_PERM_WRITE);
> + ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp);
> + if (ret < 0) {
> + return;
> + }
> +
> + s->size = blk_getlength(s->blk);
> + if (s->size <= 0) {
blk_getlength() returns an int64_t, but s->size is a uint32_t.
This means that this attempt to check for <= 0 doesn't
actually catch the negative values which are errors...
> + error_setg(errp, "failed to get flash size");
> + return;
> + }
> +
> + s->storage = blk_blockalign(s->blk, s->size);
...so we'll pass a very large positive number to
blk_blockalign() (since it takse a size_t argument), which
Coverity correctly identifies as doing the wrong thing.
(CID 1412226)
Side note: the blk functions here seem a bit inconsistent:
blk_getlength() returns int64_t
blk_blockalign() takes size_t
blk_pread() takes int
> +
> + if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) {
> + error_setg(errp, "failed to read the initial flash content");
> + return;
> + }
> + } else {
> + s->storage = blk_blockalign(NULL, s->size);
> + memset(s->storage, 0xFF, s->size);
> + }
> +
> + memory_region_init_io(&s->mmio, OBJECT(s), &pnv_pnor_ops, s,
> + TYPE_PNV_PNOR, s->size);
> +}
thanks
-- PMM
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PULL 01/88] ppc/pnv: Add a PNOR model
2020-01-07 14:43 ` Peter Maydell
@ 2020-01-07 16:26 ` Cédric Le Goater
0 siblings, 0 replies; 94+ messages in thread
From: Cédric Le Goater @ 2020-01-07 16:26 UTC (permalink / raw)
To: Peter Maydell, David Gibson
Cc: Laurent Vivier, Alexey Kardashevskiy, QEMU Developers, Greg Kurz,
Cédric Le Goater, qemu-ppc
On 1/7/20 3:43 PM, Peter Maydell wrote:
> On Tue, 17 Dec 2019 at 04:43, David Gibson <david@gibson.dropbear.id.au> wrote:
>>
>> From: Cédric Le Goater <clg@fr.ibm.com>
>>
>> On a POWERPC PowerNV system, the host firmware is stored in a PNOR
>> flash chip which contents is mapped on the LPC bus. This model adds a
>> simple dummy device to map the contents of a block device in the host
>> address space.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> Message-Id: <20191021131215.3693-2-clg@kaod.org>
>> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
>> ---
>> hw/ppc/Makefile.objs | 4 +-
>> hw/ppc/pnv.c | 14 ++++
>> hw/ppc/pnv_pnor.c | 135 ++++++++++++++++++++++++++++++++++++++
>> include/hw/ppc/pnv.h | 3 +
>> include/hw/ppc/pnv_pnor.h | 25 +++++++
>> 5 files changed, 180 insertions(+), 1 deletion(-)
>> create mode 100644 hw/ppc/pnv_pnor.c
>> create mode 100644 include/hw/ppc/pnv_pnor.h
>
> Hi; Coverity finds some issues in this patch:
>
>> +static void pnv_pnor_update(PnvPnor *s, int offset, int size)
>> +{
>> + int offset_end;
>> +
>> + if (s->blk) {
>> + return;
>> + }
>> +
>> + offset_end = offset + size;
>> + offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE);
>> + offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE);
>> +
>> + blk_pwrite(s->blk, offset, s->storage + offset,
>> + offset_end - offset, 0);
>
> Here we call blk_pwrite() but don't check whether it
> succeeded or failed. (CID 1412228)
Yes. I will send fixes for both issues.
Thanks,
C.
>> +static void pnv_pnor_realize(DeviceState *dev, Error **errp)
>> +{
>> + PnvPnor *s = PNV_PNOR(dev);
>> + int ret;
>> +
>> + if (s->blk) {
>> + uint64_t perm = BLK_PERM_CONSISTENT_READ |
>> + (blk_is_read_only(s->blk) ? 0 : BLK_PERM_WRITE);
>> + ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp);
>> + if (ret < 0) {
>> + return;
>> + }
>> +
>> + s->size = blk_getlength(s->blk);
>> + if (s->size <= 0) {
>
> blk_getlength() returns an int64_t, but s->size is a uint32_t.
> This means that this attempt to check for <= 0 doesn't
> actually catch the negative values which are errors...
>
>> + error_setg(errp, "failed to get flash size");
>> + return;
>> + }
>> +
>> + s->storage = blk_blockalign(s->blk, s->size);
>
> ...so we'll pass a very large positive number to
> blk_blockalign() (since it takse a size_t argument), which
> Coverity correctly identifies as doing the wrong thing.
> (CID 1412226)
>
> Side note: the blk functions here seem a bit inconsistent:
> blk_getlength() returns int64_t
> blk_blockalign() takes size_t
> blk_pread() takes int
>
>> +
>> + if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) {
>> + error_setg(errp, "failed to read the initial flash content");
>> + return;
>> + }
>> + } else {
>> + s->storage = blk_blockalign(NULL, s->size);
>> + memset(s->storage, 0xFF, s->size);
>> + }
>> +
>> + memory_region_init_io(&s->mmio, OBJECT(s), &pnv_pnor_ops, s,
>> + TYPE_PNV_PNOR, s->size);
>> +}
>
> thanks
> -- PMM
>
^ permalink raw reply [flat|nested] 94+ messages in thread
* [PULL 02/88] ppc/pnv: Add a "/qemu" device tree node
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
2019-12-17 4:41 ` [PULL 01/88] ppc/pnv: Add a PNOR model David Gibson
@ 2019-12-17 4:41 ` David Gibson
2019-12-17 4:41 ` [PULL 03/88] ppc/pnv: Drop "chip" link from POWER9 PSI object David Gibson
` (86 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:41 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
It helps skiboot identifying that is running on a QEMU platform. The
compatible string will define the POWERPC processor version.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191106142129.4908-1-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index d0c1d42277..416caab6f6 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -480,6 +480,9 @@ static void *pnv_dt_create(MachineState *machine)
fdt = g_malloc0(FDT_MAX_SIZE);
_FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
+ /* /qemu node */
+ _FDT((fdt_add_subnode(fdt, 0, "qemu")));
+
/* Root node */
_FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
_FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 03/88] ppc/pnv: Drop "chip" link from POWER9 PSI object
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
2019-12-17 4:41 ` [PULL 01/88] ppc/pnv: Add a PNOR model David Gibson
2019-12-17 4:41 ` [PULL 02/88] ppc/pnv: Add a "/qemu" device tree node David Gibson
@ 2019-12-17 4:41 ` David Gibson
2019-12-17 4:41 ` [PULL 04/88] xive: Link "cpu" property to XiveTCTX::cs pointer David Gibson
` (85 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:41 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
It has no apparent user.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157383383118.166856.2588933416368211047.stgit@bahia.lan>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 416caab6f6..4e9ddc05ad 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1096,8 +1096,6 @@ static void pnv_chip_power9_instance_init(Object *obj)
object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi),
TYPE_PNV9_PSI, &error_abort, NULL);
- object_property_add_const_link(OBJECT(&chip9->psi), "chip", obj,
- &error_abort);
object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc),
TYPE_PNV9_LPC, &error_abort, NULL);
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 04/88] xive: Link "cpu" property to XiveTCTX::cs pointer
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (2 preceding siblings ...)
2019-12-17 4:41 ` [PULL 03/88] ppc/pnv: Drop "chip" link from POWER9 PSI object David Gibson
@ 2019-12-17 4:41 ` David Gibson
2019-12-17 4:41 ` [PULL 05/88] xive: Link "xive" property to XiveSource::xive pointer David Gibson
` (84 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:41 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
The TCTX object has both a pointer and a "cpu" property pointing to the
vCPU object. Confusing bugs could arise if these ever go out of sync.
Change the property definition so that it explicitely sets the pointer.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157383332669.165747.2484056603605646820.stgit@bahia.lan>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/xive.c | 22 +++++++++-------------
1 file changed, 9 insertions(+), 13 deletions(-)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 75dce82fb2..9376e84aff 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -580,19 +580,11 @@ static void xive_tctx_realize(DeviceState *dev, Error **errp)
XiveTCTX *tctx = XIVE_TCTX(dev);
PowerPCCPU *cpu;
CPUPPCState *env;
- Object *obj;
Error *local_err = NULL;
- obj = object_property_get_link(OBJECT(dev), "cpu", &local_err);
- if (!obj) {
- error_propagate(errp, local_err);
- error_prepend(errp, "required link 'cpu' not found: ");
- return;
- }
-
- cpu = POWERPC_CPU(obj);
- tctx->cs = CPU(obj);
+ assert(tctx->cs);
+ cpu = POWERPC_CPU(tctx->cs);
env = &cpu->env;
switch (PPC_INPUT(env)) {
case PPC_FLAGS_INPUT_POWER9:
@@ -662,6 +654,11 @@ static const VMStateDescription vmstate_xive_tctx = {
},
};
+static Property xive_tctx_properties[] = {
+ DEFINE_PROP_LINK("cpu", XiveTCTX, cs, TYPE_CPU, CPUState *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void xive_tctx_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -669,6 +666,7 @@ static void xive_tctx_class_init(ObjectClass *klass, void *data)
dc->desc = "XIVE Interrupt Thread Context";
dc->realize = xive_tctx_realize;
dc->vmsd = &vmstate_xive_tctx;
+ dc->props = xive_tctx_properties;
/*
* Reason: part of XIVE interrupt controller, needs to be wired up
* by xive_tctx_create().
@@ -691,8 +689,7 @@ Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp)
obj = object_new(TYPE_XIVE_TCTX);
object_property_add_child(cpu, TYPE_XIVE_TCTX, obj, &error_abort);
object_unref(obj);
- object_ref(cpu);
- object_property_add_const_link(obj, "cpu", cpu, &error_abort);
+ object_property_set_link(obj, cpu, "cpu", &error_abort);
object_property_set_bool(obj, true, "realized", &local_err);
if (local_err) {
goto error;
@@ -710,7 +707,6 @@ void xive_tctx_destroy(XiveTCTX *tctx)
{
Object *obj = OBJECT(tctx);
- object_unref(object_property_get_link(obj, "cpu", &error_abort));
object_unparent(obj);
}
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 05/88] xive: Link "xive" property to XiveSource::xive pointer
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (3 preceding siblings ...)
2019-12-17 4:41 ` [PULL 04/88] xive: Link "cpu" property to XiveTCTX::cs pointer David Gibson
@ 2019-12-17 4:41 ` David Gibson
2019-12-17 4:42 ` [PULL 06/88] xive: Link "xive" property to XiveEndSource::xrtr pointer David Gibson
` (83 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:41 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
The source object has both a pointer and a "xive" property pointing to the
notifier object. Confusing bugs could arise if these ever go out of sync.
Change the property definition so that it explicitely sets the pointer.
The property isn't optional : not being able to set the link is a bug
and QEMU should rather abort than exit in this case.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157383333227.165747.12901571295951957951.stgit@bahia.lan>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/pnv_xive.c | 4 ++--
hw/intc/spapr_xive.c | 4 ++--
hw/intc/xive.c | 13 +++----------
hw/ppc/pnv_psi.c | 3 +--
4 files changed, 8 insertions(+), 16 deletions(-)
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index 348f2fdd26..9e23dc705d 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -1695,8 +1695,8 @@ static void pnv_xive_realize(DeviceState *dev, Error **errp)
*/
object_property_set_int(OBJECT(xsrc), PNV_XIVE_NR_IRQS, "nr-irqs",
&error_fatal);
- object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(xive),
- &error_fatal);
+ object_property_set_link(OBJECT(xsrc), OBJECT(xive), "xive",
+ &error_abort);
object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err);
if (local_err) {
error_propagate(errp, local_err);
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index 9cb8d38a3b..10890aeeeb 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -276,8 +276,8 @@ static void spapr_xive_realize(DeviceState *dev, Error **errp)
*/
object_property_set_int(OBJECT(xsrc), xive->nr_irqs, "nr-irqs",
&error_fatal);
- object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(xive),
- &error_fatal);
+ object_property_set_link(OBJECT(xsrc), OBJECT(xive), "xive",
+ &error_abort);
object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err);
if (local_err) {
error_propagate(errp, local_err);
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 9376e84aff..2eac15efa6 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -1060,17 +1060,8 @@ static void xive_source_reset(void *dev)
static void xive_source_realize(DeviceState *dev, Error **errp)
{
XiveSource *xsrc = XIVE_SOURCE(dev);
- Object *obj;
- Error *local_err = NULL;
-
- obj = object_property_get_link(OBJECT(dev), "xive", &local_err);
- if (!obj) {
- error_propagate(errp, local_err);
- error_prepend(errp, "required link 'xive' not found: ");
- return;
- }
- xsrc->xive = XIVE_NOTIFIER(obj);
+ assert(xsrc->xive);
if (!xsrc->nr_irqs) {
error_setg(errp, "Number of interrupt needs to be greater than 0");
@@ -1116,6 +1107,8 @@ static Property xive_source_properties[] = {
DEFINE_PROP_UINT64("flags", XiveSource, esb_flags, 0),
DEFINE_PROP_UINT32("nr-irqs", XiveSource, nr_irqs, 0),
DEFINE_PROP_UINT32("shift", XiveSource, esb_shift, XIVE_ESB_64K_2PAGE),
+ DEFINE_PROP_LINK("xive", XiveSource, xive, TYPE_XIVE_NOTIFIER,
+ XiveNotifier *),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index 68d0dfacfe..a360515a86 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -851,8 +851,7 @@ static void pnv_psi_power9_realize(DeviceState *dev, Error **errp)
&error_fatal);
object_property_set_int(OBJECT(xsrc), PSIHB9_NUM_IRQS, "nr-irqs",
&error_fatal);
- object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(psi),
- &error_fatal);
+ object_property_set_link(OBJECT(xsrc), OBJECT(psi), "xive", &error_abort);
object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err);
if (local_err) {
error_propagate(errp, local_err);
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 06/88] xive: Link "xive" property to XiveEndSource::xrtr pointer
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (4 preceding siblings ...)
2019-12-17 4:41 ` [PULL 05/88] xive: Link "xive" property to XiveSource::xive pointer David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 07/88] ppc/pnv: Link "psi" property to PnvLpc::psi pointer David Gibson
` (82 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
The END source object has both a pointer and a "xive" property pointing to
the router object. Confusing bugs could arise if these ever go out of sync.
Change the property definition so that it explicitely sets the pointer.
The property isn't optional : not being able to set the link is a bug
and QEMU should rather abort than exit in this case.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157383333784.165747.5298512574054268786.stgit@bahia.lan>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/pnv_xive.c | 4 ++--
hw/intc/spapr_xive.c | 4 ++--
hw/intc/xive.c | 13 +++----------
3 files changed, 7 insertions(+), 14 deletions(-)
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index 9e23dc705d..6aa7aeed6f 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -1705,8 +1705,8 @@ static void pnv_xive_realize(DeviceState *dev, Error **errp)
object_property_set_int(OBJECT(end_xsrc), PNV_XIVE_NR_ENDS, "nr-ends",
&error_fatal);
- object_property_add_const_link(OBJECT(end_xsrc), "xive", OBJECT(xive),
- &error_fatal);
+ object_property_set_link(OBJECT(end_xsrc), OBJECT(xive), "xive",
+ &error_abort);
object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err);
if (local_err) {
error_propagate(errp, local_err);
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index 10890aeeeb..729246e906 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -290,8 +290,8 @@ static void spapr_xive_realize(DeviceState *dev, Error **errp)
*/
object_property_set_int(OBJECT(end_xsrc), xive->nr_irqs, "nr-ends",
&error_fatal);
- object_property_add_const_link(OBJECT(end_xsrc), "xive", OBJECT(xive),
- &error_fatal);
+ object_property_set_link(OBJECT(end_xsrc), OBJECT(xive), "xive",
+ &error_abort);
object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err);
if (local_err) {
error_propagate(errp, local_err);
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 2eac15efa6..3d472e29c8 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -1814,17 +1814,8 @@ static const MemoryRegionOps xive_end_source_ops = {
static void xive_end_source_realize(DeviceState *dev, Error **errp)
{
XiveENDSource *xsrc = XIVE_END_SOURCE(dev);
- Object *obj;
- Error *local_err = NULL;
-
- obj = object_property_get_link(OBJECT(dev), "xive", &local_err);
- if (!obj) {
- error_propagate(errp, local_err);
- error_prepend(errp, "required link 'xive' not found: ");
- return;
- }
- xsrc->xrtr = XIVE_ROUTER(obj);
+ assert(xsrc->xrtr);
if (!xsrc->nr_ends) {
error_setg(errp, "Number of interrupt needs to be greater than 0");
@@ -1850,6 +1841,8 @@ static Property xive_end_source_properties[] = {
DEFINE_PROP_UINT8("block-id", XiveENDSource, block_id, 0),
DEFINE_PROP_UINT32("nr-ends", XiveENDSource, nr_ends, 0),
DEFINE_PROP_UINT32("shift", XiveENDSource, esb_shift, XIVE_ESB_64K),
+ DEFINE_PROP_LINK("xive", XiveENDSource, xrtr, TYPE_XIVE_ROUTER,
+ XiveRouter *),
DEFINE_PROP_END_OF_LIST(),
};
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 07/88] ppc/pnv: Link "psi" property to PnvLpc::psi pointer
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (5 preceding siblings ...)
2019-12-17 4:42 ` [PULL 06/88] xive: Link "xive" property to XiveEndSource::xrtr pointer David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 08/88] ppc/pnv: Link "psi" property to PnvOCC::psi pointer David Gibson
` (81 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
The LPC object has both a pointer and a "psi" property pointing to the
PSI object. Confusing bugs could arise if these ever go out of sync.
Change the property definition so that it explicitely sets the pointer.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157383334342.165747.3159314903077305653.stgit@bahia.lan>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 8 ++++----
hw/ppc/pnv_lpc.c | 19 ++++++++-----------
2 files changed, 12 insertions(+), 15 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 4e9ddc05ad..201facc701 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -901,8 +901,6 @@ static void pnv_chip_power8_instance_init(Object *obj)
object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc),
TYPE_PNV8_LPC, &error_abort, NULL);
- object_property_add_const_link(OBJECT(&chip8->lpc), "psi",
- OBJECT(&chip8->psi), &error_abort);
object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ),
TYPE_PNV8_OCC, &error_abort, NULL);
@@ -981,6 +979,8 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
&PNV_PSI(psi8)->xscom_regs);
/* Create LPC controller */
+ object_property_set_link(OBJECT(&chip8->lpc), OBJECT(&chip8->psi), "psi",
+ &error_abort);
object_property_set_bool(OBJECT(&chip8->lpc), true, "realized",
&error_fatal);
pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
@@ -1099,8 +1099,6 @@ static void pnv_chip_power9_instance_init(Object *obj)
object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc),
TYPE_PNV9_LPC, &error_abort, NULL);
- object_property_add_const_link(OBJECT(&chip9->lpc), "psi",
- OBJECT(&chip9->psi), &error_abort);
object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ),
TYPE_PNV9_OCC, &error_abort, NULL);
@@ -1199,6 +1197,8 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
&PNV_PSI(psi9)->xscom_regs);
/* LPC */
+ object_property_set_link(OBJECT(&chip9->lpc), OBJECT(&chip9->psi), "psi",
+ &error_abort);
object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err);
if (local_err) {
error_propagate(errp, local_err);
diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
index 9466d4a1be..fb9f930320 100644
--- a/hw/ppc/pnv_lpc.c
+++ b/hw/ppc/pnv_lpc.c
@@ -24,7 +24,7 @@
#include "qemu/module.h"
#include "hw/irq.h"
#include "hw/isa/isa.h"
-
+#include "hw/qdev-properties.h"
#include "hw/ppc/pnv.h"
#include "hw/ppc/pnv_lpc.h"
#include "hw/ppc/pnv_xscom.h"
@@ -682,17 +682,8 @@ static const TypeInfo pnv_lpc_power9_info = {
static void pnv_lpc_realize(DeviceState *dev, Error **errp)
{
PnvLpcController *lpc = PNV_LPC(dev);
- Object *obj;
- Error *local_err = NULL;
- obj = object_property_get_link(OBJECT(dev), "psi", &local_err);
- if (!obj) {
- error_propagate(errp, local_err);
- error_prepend(errp, "required link 'psi' not found: ");
- return;
- }
- /* The LPC controller needs PSI to generate interrupts */
- lpc->psi = PNV_PSI(obj);
+ assert(lpc->psi);
/* Reg inits */
lpc->lpc_hc_fw_rd_acc_size = LPC_HC_FW_RD_4B;
@@ -734,12 +725,18 @@ static void pnv_lpc_realize(DeviceState *dev, Error **errp)
&lpc->lpc_hc_regs);
}
+static Property pnv_lpc_properties[] = {
+ DEFINE_PROP_LINK("psi", PnvLpcController, psi, TYPE_PNV_PSI, PnvPsi *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void pnv_lpc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = pnv_lpc_realize;
dc->desc = "PowerNV LPC Controller";
+ dc->props = pnv_lpc_properties;
}
static const TypeInfo pnv_lpc_info = {
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 08/88] ppc/pnv: Link "psi" property to PnvOCC::psi pointer
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (6 preceding siblings ...)
2019-12-17 4:42 ` [PULL 07/88] ppc/pnv: Link "psi" property to PnvLpc::psi pointer David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 09/88] ppc/pnv: Link "chip" property to PnvHomer::chip pointer David Gibson
` (80 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
The OCC object has both a pointer and a "psi" property pointing to the
PSI object. Confusing bugs could arise if these ever go out of sync.
Change the property definition so that it explicitely sets the pointer.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157383334894.165747.7617090757862105199.stgit@bahia.lan>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 8 ++++----
hw/ppc/pnv_occ.c | 20 +++++++++-----------
2 files changed, 13 insertions(+), 15 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 201facc701..ce24a4ee99 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -904,8 +904,6 @@ static void pnv_chip_power8_instance_init(Object *obj)
object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ),
TYPE_PNV8_OCC, &error_abort, NULL);
- object_property_add_const_link(OBJECT(&chip8->occ), "psi",
- OBJECT(&chip8->psi), &error_abort);
object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer),
TYPE_PNV8_HOMER, &error_abort, NULL);
@@ -1000,6 +998,8 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
}
/* Create the simplified OCC model */
+ object_property_set_link(OBJECT(&chip8->occ), OBJECT(&chip8->psi), "psi",
+ &error_abort);
object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err);
if (local_err) {
error_propagate(errp, local_err);
@@ -1102,8 +1102,6 @@ static void pnv_chip_power9_instance_init(Object *obj)
object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ),
TYPE_PNV9_OCC, &error_abort, NULL);
- object_property_add_const_link(OBJECT(&chip9->occ), "psi",
- OBJECT(&chip9->psi), &error_abort);
object_initialize_child(obj, "homer", &chip9->homer, sizeof(chip9->homer),
TYPE_PNV9_HOMER, &error_abort, NULL);
@@ -1211,6 +1209,8 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
(uint64_t) PNV9_LPCM_BASE(chip));
/* Create the simplified OCC model */
+ object_property_set_link(OBJECT(&chip9->occ), OBJECT(&chip9->psi), "psi",
+ &error_abort);
object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err);
if (local_err) {
error_propagate(errp, local_err);
diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c
index 785653bb67..765c0a6ce5 100644
--- a/hw/ppc/pnv_occ.c
+++ b/hw/ppc/pnv_occ.c
@@ -21,7 +21,7 @@
#include "qapi/error.h"
#include "qemu/log.h"
#include "qemu/module.h"
-
+#include "hw/qdev-properties.h"
#include "hw/ppc/pnv.h"
#include "hw/ppc/pnv_xscom.h"
#include "hw/ppc/pnv_occ.h"
@@ -257,18 +257,10 @@ static void pnv_occ_realize(DeviceState *dev, Error **errp)
{
PnvOCC *occ = PNV_OCC(dev);
PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
- Object *obj;
- Error *local_err = NULL;
- occ->occmisc = 0;
+ assert(occ->psi);
- obj = object_property_get_link(OBJECT(dev), "psi", &local_err);
- if (!obj) {
- error_propagate(errp, local_err);
- error_prepend(errp, "required link 'psi' not found: ");
- return;
- }
- occ->psi = PNV_PSI(obj);
+ occ->occmisc = 0;
/* XScom region for OCC registers */
pnv_xscom_region_init(&occ->xscom_regs, OBJECT(dev), poc->xscom_ops,
@@ -279,12 +271,18 @@ static void pnv_occ_realize(DeviceState *dev, Error **errp)
occ, "occ-common-area", poc->sram_size);
}
+static Property pnv_occ_properties[] = {
+ DEFINE_PROP_LINK("psi", PnvOCC, psi, TYPE_PNV_PSI, PnvPsi *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void pnv_occ_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = pnv_occ_realize;
dc->desc = "PowerNV OCC Controller";
+ dc->props = pnv_occ_properties;
}
static const TypeInfo pnv_occ_type_info = {
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 09/88] ppc/pnv: Link "chip" property to PnvHomer::chip pointer
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (7 preceding siblings ...)
2019-12-17 4:42 ` [PULL 08/88] ppc/pnv: Link "psi" property to PnvOCC::psi pointer David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 10/88] ppc/pnv: Link "chip" property to PnvCore::chip pointer David Gibson
` (79 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
The homer object has both a pointer and a "chip" property pointing to the
chip object. Confusing bugs could arise if these ever go out of sync.
Change the property definition so that it explicitely sets the pointer.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157383335451.165747.32301068645427993.stgit@bahia.lan>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 8 ++++----
hw/ppc/pnv_homer.c | 20 ++++++++++----------
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index ce24a4ee99..3fa24a2d60 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -907,8 +907,6 @@ static void pnv_chip_power8_instance_init(Object *obj)
object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer),
TYPE_PNV8_HOMER, &error_abort, NULL);
- object_property_add_const_link(OBJECT(&chip8->homer), "chip", obj,
- &error_abort);
}
static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
@@ -1012,6 +1010,8 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
&chip8->occ.sram_regs);
/* HOMER */
+ object_property_set_link(OBJECT(&chip8->homer), OBJECT(chip), "chip",
+ &error_abort);
object_property_set_bool(OBJECT(&chip8->homer), true, "realized",
&local_err);
if (local_err) {
@@ -1105,8 +1105,6 @@ static void pnv_chip_power9_instance_init(Object *obj)
object_initialize_child(obj, "homer", &chip9->homer, sizeof(chip9->homer),
TYPE_PNV9_HOMER, &error_abort, NULL);
- object_property_add_const_link(OBJECT(&chip9->homer), "chip", obj,
- &error_abort);
}
static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
@@ -1223,6 +1221,8 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
&chip9->occ.sram_regs);
/* HOMER */
+ object_property_set_link(OBJECT(&chip9->homer), OBJECT(chip), "chip",
+ &error_abort);
object_property_set_bool(OBJECT(&chip9->homer), true, "realized",
&local_err);
if (local_err) {
diff --git a/hw/ppc/pnv_homer.c b/hw/ppc/pnv_homer.c
index cc881a3b32..994a378108 100644
--- a/hw/ppc/pnv_homer.c
+++ b/hw/ppc/pnv_homer.c
@@ -22,6 +22,7 @@
#include "exec/memory.h"
#include "sysemu/cpus.h"
#include "hw/qdev-core.h"
+#include "hw/qdev-properties.h"
#include "hw/ppc/pnv.h"
#include "hw/ppc/pnv_homer.h"
@@ -229,28 +230,27 @@ static void pnv_homer_realize(DeviceState *dev, Error **errp)
{
PnvHomer *homer = PNV_HOMER(dev);
PnvHomerClass *hmrc = PNV_HOMER_GET_CLASS(homer);
- Object *obj;
- Error *local_err = NULL;
-
- obj = object_property_get_link(OBJECT(dev), "chip", &local_err);
- if (!obj) {
- error_propagate(errp, local_err);
- error_prepend(errp, "required link 'chip' not found: ");
- return;
- }
- homer->chip = PNV_CHIP(obj);
+
+ assert(homer->chip);
+
/* homer region */
memory_region_init_io(&homer->regs, OBJECT(dev),
hmrc->homer_ops, homer, "homer-main-memory",
hmrc->homer_size);
}
+static Property pnv_homer_properties[] = {
+ DEFINE_PROP_LINK("chip", PnvHomer, chip, TYPE_PNV_CHIP, PnvChip *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void pnv_homer_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = pnv_homer_realize;
dc->desc = "PowerNV HOMER Memory";
+ dc->props = pnv_homer_properties;
}
static const TypeInfo pnv_homer_type_info = {
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 10/88] ppc/pnv: Link "chip" property to PnvCore::chip pointer
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (8 preceding siblings ...)
2019-12-17 4:42 ` [PULL 09/88] ppc/pnv: Link "chip" property to PnvHomer::chip pointer David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 11/88] ppc/pnv: Link "chip" property to PnvXive::chip pointer David Gibson
` (78 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
The core object has both a pointer and a "chip" property pointing to the
chip object. Confusing bugs could arise if these ever go out of sync.
Change the property definition so that it explicitely sets the pointer.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157383336007.165747.1524120147081367440.stgit@bahia.lan>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 4 ++--
hw/ppc/pnv_core.c | 10 ++--------
2 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 3fa24a2d60..2bf8a3b23b 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1327,8 +1327,8 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
object_property_set_int(OBJECT(pnv_core),
pcc->core_pir(chip, core_hwid),
"pir", &error_fatal);
- object_property_add_const_link(OBJECT(pnv_core), "chip",
- OBJECT(chip), &error_fatal);
+ object_property_set_link(OBJECT(pnv_core), OBJECT(chip), "chip",
+ &error_abort);
object_property_set_bool(OBJECT(pnv_core), true, "realized",
&error_fatal);
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 61b3d3ce22..5ab75bde6c 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -217,15 +217,8 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
void *obj;
int i, j;
char name[32];
- Object *chip;
- chip = object_property_get_link(OBJECT(dev), "chip", &local_err);
- if (!chip) {
- error_propagate_prepend(errp, local_err,
- "required link 'chip' not found: ");
- return;
- }
- pc->chip = PNV_CHIP(chip);
+ assert(pc->chip);
pc->threads = g_new(PowerPCCPU *, cc->nr_threads);
for (i = 0; i < cc->nr_threads; i++) {
@@ -297,6 +290,7 @@ static void pnv_core_unrealize(DeviceState *dev, Error **errp)
static Property pnv_core_properties[] = {
DEFINE_PROP_UINT32("pir", PnvCore, pir, 0),
+ DEFINE_PROP_LINK("chip", PnvCore, chip, TYPE_PNV_CHIP, PnvChip *),
DEFINE_PROP_END_OF_LIST(),
};
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 11/88] ppc/pnv: Link "chip" property to PnvXive::chip pointer
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (9 preceding siblings ...)
2019-12-17 4:42 ` [PULL 10/88] ppc/pnv: Link "chip" property to PnvCore::chip pointer David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 12/88] xics: Link ICS_PROP_XICS property to ICSState::xics pointer David Gibson
` (77 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
The XIVE object has both a pointer and a "chip" property pointing to the
chip object. Confusing bugs could arise if these ever go out of sync.
Change the property definition so that it explicitely sets the pointer.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157383336564.165747.10250365296928442882.stgit@bahia.lan>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/pnv_xive.c | 13 +++----------
hw/ppc/pnv.c | 4 ++--
2 files changed, 5 insertions(+), 12 deletions(-)
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index 6aa7aeed6f..4e56c2e468 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -1675,17 +1675,8 @@ static void pnv_xive_realize(DeviceState *dev, Error **errp)
XiveSource *xsrc = &xive->ipi_source;
XiveENDSource *end_xsrc = &xive->end_source;
Error *local_err = NULL;
- Object *obj;
- obj = object_property_get_link(OBJECT(dev), "chip", &local_err);
- if (!obj) {
- error_propagate(errp, local_err);
- error_prepend(errp, "required link 'chip' not found: ");
- return;
- }
-
- /* The PnvChip id identifies the XIVE interrupt controller. */
- xive->chip = PNV_CHIP(obj);
+ assert(xive->chip);
/*
* The XiveSource and XiveENDSource objects are realized with the
@@ -1800,6 +1791,8 @@ static Property pnv_xive_properties[] = {
DEFINE_PROP_UINT64("vc-bar", PnvXive, vc_base, 0),
DEFINE_PROP_UINT64("pc-bar", PnvXive, pc_base, 0),
DEFINE_PROP_UINT64("tm-bar", PnvXive, tm_base, 0),
+ /* The PnvChip id identifies the XIVE interrupt controller. */
+ DEFINE_PROP_LINK("chip", PnvXive, chip, TYPE_PNV_CHIP, PnvChip *),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 2bf8a3b23b..a2a8b97330 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1091,8 +1091,6 @@ static void pnv_chip_power9_instance_init(Object *obj)
object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive),
TYPE_PNV_XIVE, &error_abort, NULL);
- object_property_add_const_link(OBJECT(&chip9->xive), "chip", obj,
- &error_abort);
object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi),
TYPE_PNV9_PSI, &error_abort, NULL);
@@ -1172,6 +1170,8 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
"pc-bar", &error_fatal);
object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip),
"tm-bar", &error_fatal);
+ object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip",
+ &error_abort);
object_property_set_bool(OBJECT(&chip9->xive), true, "realized",
&local_err);
if (local_err) {
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 12/88] xics: Link ICS_PROP_XICS property to ICSState::xics pointer
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (10 preceding siblings ...)
2019-12-17 4:42 ` [PULL 11/88] ppc/pnv: Link "chip" property to PnvXive::chip pointer David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 13/88] xics: Link ICP_PROP_XICS property to ICPState::xics pointer David Gibson
` (76 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
The ICS object has both a pointer and an ICS_PROP_XICS property pointing
to the XICS fabric. Confusing bugs could arise if these ever go out of
sync.
Change the property definition so that it explicitely sets the pointer.
The property isn't optional : not being able to set the link is a bug
and QEMU should rather abort than exit in this case.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157403283596.409804.17347207690271971987.stgit@bahia.lan>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/xics.c | 13 +++----------
hw/ppc/pnv_psi.c | 3 +--
hw/ppc/spapr_irq.c | 9 ++-------
3 files changed, 6 insertions(+), 19 deletions(-)
diff --git a/hw/intc/xics.c b/hw/intc/xics.c
index e7ac9ba618..f7a4548089 100644
--- a/hw/intc/xics.c
+++ b/hw/intc/xics.c
@@ -609,17 +609,8 @@ static void ics_reset_handler(void *dev)
static void ics_realize(DeviceState *dev, Error **errp)
{
ICSState *ics = ICS(dev);
- Error *local_err = NULL;
- Object *obj;
- obj = object_property_get_link(OBJECT(dev), ICS_PROP_XICS, &local_err);
- if (!obj) {
- error_propagate_prepend(errp, local_err,
- "required link '" ICS_PROP_XICS
- "' not found: ");
- return;
- }
- ics->xics = XICS_FABRIC(obj);
+ assert(ics->xics);
if (!ics->nr_irqs) {
error_setg(errp, "Number of interrupts needs to be greater 0");
@@ -699,6 +690,8 @@ static const VMStateDescription vmstate_ics = {
static Property ics_properties[] = {
DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0),
+ DEFINE_PROP_LINK(ICS_PROP_XICS, ICSState, xics, TYPE_XICS_FABRIC,
+ XICSFabric *),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index a360515a86..7e725aaf2b 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -497,8 +497,7 @@ static void pnv_psi_power8_realize(DeviceState *dev, Error **errp)
}
/* Create PSI interrupt control source */
- object_property_add_const_link(OBJECT(ics), ICS_PROP_XICS, obj,
- &error_abort);
+ object_property_set_link(OBJECT(ics), obj, ICS_PROP_XICS, &error_abort);
object_property_set_int(OBJECT(ics), PSI_NUM_INTERRUPTS, "nr-irqs", &err);
if (err) {
error_propagate(errp, err);
diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c
index d6bb7fd2d6..fbdda14372 100644
--- a/hw/ppc/spapr_irq.c
+++ b/hw/ppc/spapr_irq.c
@@ -319,13 +319,8 @@ void spapr_irq_init(SpaprMachineState *spapr, Error **errp)
return;
}
- object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr),
- &local_err);
- if (local_err) {
- error_propagate(errp, local_err);
- return;
- }
-
+ object_property_set_link(obj, OBJECT(spapr), ICS_PROP_XICS,
+ &error_abort);
object_property_set_int(obj, smc->nr_xirqs, "nr-irqs", &local_err);
if (local_err) {
error_propagate(errp, local_err);
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 13/88] xics: Link ICP_PROP_XICS property to ICPState::xics pointer
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (11 preceding siblings ...)
2019-12-17 4:42 ` [PULL 12/88] xics: Link ICS_PROP_XICS property to ICSState::xics pointer David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 14/88] xics: Link ICP_PROP_CPU property to ICPState::cs pointer David Gibson
` (75 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
The ICP object has both a pointer and an ICP_PROP_XICS property pointing
to the XICS fabric. Confusing bugs could arise if these ever go out of
sync.
Change the property definition so that it explicitly sets the pointer.
The property isn't optional : not being able to set the link is a bug
and QEMU should rather abort than exit in this case.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157403284152.409804.17114564311521923733.stgit@bahia.lan>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/xics.c | 22 +++++++++-------------
1 file changed, 9 insertions(+), 13 deletions(-)
diff --git a/hw/intc/xics.c b/hw/intc/xics.c
index f7a4548089..35dddb8867 100644
--- a/hw/intc/xics.c
+++ b/hw/intc/xics.c
@@ -310,15 +310,7 @@ static void icp_realize(DeviceState *dev, Error **errp)
Object *obj;
Error *err = NULL;
- obj = object_property_get_link(OBJECT(dev), ICP_PROP_XICS, &err);
- if (!obj) {
- error_propagate_prepend(errp, err,
- "required link '" ICP_PROP_XICS
- "' not found: ");
- return;
- }
-
- icp->xics = XICS_FABRIC(obj);
+ assert(icp->xics);
obj = object_property_get_link(OBJECT(dev), ICP_PROP_CPU, &err);
if (!obj) {
@@ -368,12 +360,19 @@ static void icp_unrealize(DeviceState *dev, Error **errp)
vmstate_unregister(NULL, &vmstate_icp_server, icp);
}
+static Property icp_properties[] = {
+ DEFINE_PROP_LINK(ICP_PROP_XICS, ICPState, xics, TYPE_XICS_FABRIC,
+ XICSFabric *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void icp_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = icp_realize;
dc->unrealize = icp_unrealize;
+ dc->props = icp_properties;
/*
* Reason: part of XICS interrupt controller, needs to be wired up
* by icp_create().
@@ -397,9 +396,7 @@ Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, Error **errp)
obj = object_new(type);
object_property_add_child(cpu, type, obj, &error_abort);
object_unref(obj);
- object_ref(OBJECT(xi));
- object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(xi),
- &error_abort);
+ object_property_set_link(obj, OBJECT(xi), ICP_PROP_XICS, &error_abort);
object_ref(cpu);
object_property_add_const_link(obj, ICP_PROP_CPU, cpu, &error_abort);
object_property_set_bool(obj, true, "realized", &local_err);
@@ -417,7 +414,6 @@ void icp_destroy(ICPState *icp)
Object *obj = OBJECT(icp);
object_unref(object_property_get_link(obj, ICP_PROP_CPU, &error_abort));
- object_unref(object_property_get_link(obj, ICP_PROP_XICS, &error_abort));
object_unparent(obj);
}
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 14/88] xics: Link ICP_PROP_CPU property to ICPState::cs pointer
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (12 preceding siblings ...)
2019-12-17 4:42 ` [PULL 13/88] xics: Link ICP_PROP_XICS property to ICPState::xics pointer David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 15/88] spapr: Abort if XICS interrupt controller cannot be initialized David Gibson
` (74 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
The ICP object has both a pointer and an ICP_PROP_CPU property pointing
to the cpu. Confusing bugs could arise if these ever go out of sync.
Change the property definition so that it explicitly sets the pointer.
The property isn't optional : not being able to set the link is a bug
and QEMU should rather abort than exit in this case.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157403284709.409804.16142099083325945141.stgit@bahia.lan>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/xics.c | 21 ++++-----------------
1 file changed, 4 insertions(+), 17 deletions(-)
diff --git a/hw/intc/xics.c b/hw/intc/xics.c
index 35dddb8867..0b259a09c5 100644
--- a/hw/intc/xics.c
+++ b/hw/intc/xics.c
@@ -305,25 +305,13 @@ void icp_reset(ICPState *icp)
static void icp_realize(DeviceState *dev, Error **errp)
{
ICPState *icp = ICP(dev);
- PowerPCCPU *cpu;
CPUPPCState *env;
- Object *obj;
Error *err = NULL;
assert(icp->xics);
+ assert(icp->cs);
- obj = object_property_get_link(OBJECT(dev), ICP_PROP_CPU, &err);
- if (!obj) {
- error_propagate_prepend(errp, err,
- "required link '" ICP_PROP_CPU
- "' not found: ");
- return;
- }
-
- cpu = POWERPC_CPU(obj);
- icp->cs = CPU(obj);
-
- env = &cpu->env;
+ env = &POWERPC_CPU(icp->cs)->env;
switch (PPC_INPUT(env)) {
case PPC_FLAGS_INPUT_POWER7:
icp->output = env->irq_inputs[POWER7_INPUT_INT];
@@ -363,6 +351,7 @@ static void icp_unrealize(DeviceState *dev, Error **errp)
static Property icp_properties[] = {
DEFINE_PROP_LINK(ICP_PROP_XICS, ICPState, xics, TYPE_XICS_FABRIC,
XICSFabric *),
+ DEFINE_PROP_LINK(ICP_PROP_CPU, ICPState, cs, TYPE_CPU, CPUState *),
DEFINE_PROP_END_OF_LIST(),
};
@@ -397,8 +386,7 @@ Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, Error **errp)
object_property_add_child(cpu, type, obj, &error_abort);
object_unref(obj);
object_property_set_link(obj, OBJECT(xi), ICP_PROP_XICS, &error_abort);
- object_ref(cpu);
- object_property_add_const_link(obj, ICP_PROP_CPU, cpu, &error_abort);
+ object_property_set_link(obj, cpu, ICP_PROP_CPU, &error_abort);
object_property_set_bool(obj, true, "realized", &local_err);
if (local_err) {
object_unparent(obj);
@@ -413,7 +401,6 @@ void icp_destroy(ICPState *icp)
{
Object *obj = OBJECT(icp);
- object_unref(object_property_get_link(obj, ICP_PROP_CPU, &error_abort));
object_unparent(obj);
}
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 15/88] spapr: Abort if XICS interrupt controller cannot be initialized
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (13 preceding siblings ...)
2019-12-17 4:42 ` [PULL 14/88] xics: Link ICP_PROP_CPU property to ICPState::cs pointer David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 16/88] ppc/pnv: Add a LPC "ranges" property David Gibson
` (73 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
Failing to set any of the ICS property should really never happen:
- object_property_add_child() always succeed unless the child object
already has a parent, which isn't the case here obviously since the
ICS has just been created with object_new()
- the ICS has an "nr-irqs" property than can be set as long as the ICS
isn't realized
In both cases, an error indicates there is a bug in QEMU. Propagating the
error, ie. exiting QEMU since spapr_irq_init() is called with &error_fatal
doesn't make much sense. Abort instead. This is consistent with what is
done with XIVE : both qdev_create() and qdev_prop_set_uint32() abort QEMU
on error.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157403285265.409804.8683093665795248192.stgit@bahia.lan>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr_irq.c | 13 ++-----------
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c
index fbdda14372..d4a54afc86 100644
--- a/hw/ppc/spapr_irq.c
+++ b/hw/ppc/spapr_irq.c
@@ -313,20 +313,11 @@ void spapr_irq_init(SpaprMachineState *spapr, Error **errp)
Object *obj;
obj = object_new(TYPE_ICS_SPAPR);
- object_property_add_child(OBJECT(spapr), "ics", obj, &local_err);
- if (local_err) {
- error_propagate(errp, local_err);
- return;
- }
+ object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort);
object_property_set_link(obj, OBJECT(spapr), ICS_PROP_XICS,
&error_abort);
- object_property_set_int(obj, smc->nr_xirqs, "nr-irqs", &local_err);
- if (local_err) {
- error_propagate(errp, local_err);
- return;
- }
-
+ object_property_set_int(obj, smc->nr_xirqs, "nr-irqs", &error_abort);
object_property_set_bool(obj, true, "realized", &local_err);
if (local_err) {
error_propagate(errp, local_err);
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 16/88] ppc/pnv: Add a LPC "ranges" property
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (14 preceding siblings ...)
2019-12-17 4:42 ` [PULL 15/88] spapr: Abort if XICS interrupt controller cannot be initialized David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 17/88] ppc/xive: Record the IPB in the associated NVT David Gibson
` (72 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
And fix a typo in the MEM address space definition.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191118091908.15044-1-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv_lpc.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
index fb9f930320..c5a85c38c7 100644
--- a/hw/ppc/pnv_lpc.c
+++ b/hw/ppc/pnv_lpc.c
@@ -86,7 +86,7 @@ enum {
#define ISA_FW_SIZE 0x10000000
#define LPC_IO_OPB_ADDR 0xd0010000
#define LPC_IO_OPB_SIZE 0x00010000
-#define LPC_MEM_OPB_ADDR 0xe0010000
+#define LPC_MEM_OPB_ADDR 0xe0000000
#define LPC_MEM_OPB_SIZE 0x10000000
#define LPC_FW_OPB_ADDR 0xf0000000
#define LPC_FW_OPB_SIZE 0x10000000
@@ -143,6 +143,16 @@ int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset)
cpu_to_be32(PNV9_LPCM_SIZE >> 32),
cpu_to_be32((uint32_t)PNV9_LPCM_SIZE),
};
+ uint32_t lpc_ranges[12] = { 0, 0,
+ cpu_to_be32(LPC_MEM_OPB_ADDR),
+ cpu_to_be32(LPC_MEM_OPB_SIZE),
+ cpu_to_be32(1), 0,
+ cpu_to_be32(LPC_IO_OPB_ADDR),
+ cpu_to_be32(LPC_IO_OPB_SIZE),
+ cpu_to_be32(3), 0,
+ cpu_to_be32(LPC_FW_OPB_ADDR),
+ cpu_to_be32(LPC_FW_OPB_SIZE),
+ };
uint32_t reg[2];
/*
@@ -211,6 +221,8 @@ int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset)
_FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1)));
_FDT((fdt_setprop(fdt, offset, "compatible", lpc_compat,
sizeof(lpc_compat))));
+ _FDT((fdt_setprop(fdt, offset, "ranges", lpc_ranges,
+ sizeof(lpc_ranges))));
return 0;
}
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 17/88] ppc/xive: Record the IPB in the associated NVT
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (15 preceding siblings ...)
2019-12-17 4:42 ` [PULL 16/88] ppc/pnv: Add a LPC "ranges" property David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 18/88] ppc/xive: Introduce helpers for the NVT id David Gibson
` (71 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
When an interrupt can not be presented to a vCPU, because it is not
running on any of the HW treads, the XIVE presenter updates the
Interrupt Pending Buffer register of the associated XIVE NVT
structure. This is only done if backlog is activated in the END but
this is generally the case.
The current code assumes that the fields of the NVT structure is
architected with the same layout of the thread interrupt context
registers. Fix this assumption and define an offset for the IPB
register backup value in the NVT.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191115162436.30548-2-clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/xive.c | 11 +++++++++--
include/hw/ppc/xive_regs.h | 1 +
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 3d472e29c8..177663d2b4 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -1607,14 +1607,21 @@ static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk,
* - logical server : forward request to IVPE (not supported)
*/
if (xive_end_is_backlog(&end)) {
+ uint8_t ipb;
+
if (format == 1) {
qemu_log_mask(LOG_GUEST_ERROR,
"XIVE: END %x/%x invalid config: F1 & backlog\n",
end_blk, end_idx);
return;
}
- /* Record the IPB in the associated NVT structure */
- ipb_update((uint8_t *) &nvt.w4, priority);
+ /*
+ * Record the IPB in the associated NVT structure for later
+ * use. The presenter will resend the interrupt when the vCPU
+ * is dispatched again on a HW thread.
+ */
+ ipb = xive_get_field32(NVT_W4_IPB, nvt.w4) | priority_to_ipb(priority);
+ nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, ipb);
xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4);
/*
diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h
index 55307cd153..530f232b04 100644
--- a/include/hw/ppc/xive_regs.h
+++ b/include/hw/ppc/xive_regs.h
@@ -255,6 +255,7 @@ typedef struct XiveNVT {
uint32_t w2;
uint32_t w3;
uint32_t w4;
+#define NVT_W4_IPB PPC_BITMASK32(16, 23)
uint32_t w5;
uint32_t w6;
uint32_t w7;
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 18/88] ppc/xive: Introduce helpers for the NVT id
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (16 preceding siblings ...)
2019-12-17 4:42 ` [PULL 17/88] ppc/xive: Record the IPB in the associated NVT David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 19/88] ppc/pnv: Remove pnv_xive_vst_size() routine David Gibson
` (70 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
Each vCPU in the system is identified with an NVT identifier which is
pushed in the OS CAM line (QW1W2) of the HW thread interrupt context
register when the vCPU is dispatched on a HW thread. This identifier
is used by the presenter subengine to find a matching target to notify
of an event. It is also used to fetch the associate NVT structure
which may contain pending interrupts that need a resend.
Add a couple of helpers for the NVT ids. The NVT space is 19 bits
wide, giving a maximum of 512K per chip.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191115162436.30548-3-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
include/hw/ppc/xive.h | 5 -----
include/hw/ppc/xive_regs.h | 21 +++++++++++++++++++++
2 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index 8fd439ec9b..fa7adf87fe 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -418,11 +418,6 @@ Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp);
void xive_tctx_reset(XiveTCTX *tctx);
void xive_tctx_destroy(XiveTCTX *tctx);
-static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx)
-{
- return (nvt_blk << 19) | nvt_idx;
-}
-
/*
* KVM XIVE device helpers
*/
diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h
index 530f232b04..1a5622f8de 100644
--- a/include/hw/ppc/xive_regs.h
+++ b/include/hw/ppc/xive_regs.h
@@ -272,4 +272,25 @@ typedef struct XiveNVT {
#define xive_nvt_is_valid(nvt) (be32_to_cpu((nvt)->w0) & NVT_W0_VALID)
+/*
+ * The VP number space in a block is defined by the END_W6_NVT_INDEX
+ * field of the XIVE END
+ */
+#define XIVE_NVT_SHIFT 19
+
+static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx)
+{
+ return (nvt_blk << XIVE_NVT_SHIFT) | nvt_idx;
+}
+
+static inline uint32_t xive_nvt_idx(uint32_t cam_line)
+{
+ return cam_line & ((1 << XIVE_NVT_SHIFT) - 1);
+}
+
+static inline uint32_t xive_nvt_blk(uint32_t cam_line)
+{
+ return (cam_line >> XIVE_NVT_SHIFT) & 0xf;
+}
+
#endif /* PPC_XIVE_REGS_H */
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 19/88] ppc/pnv: Remove pnv_xive_vst_size() routine
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (17 preceding siblings ...)
2019-12-17 4:42 ` [PULL 18/88] ppc/xive: Introduce helpers for the NVT id David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 20/88] xive/kvm: Trigger interrupts from userspace David Gibson
` (69 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
pnv_xive_vst_size() tries to compute the size of a VSD table from the
information given by FW. The number of entries of the table are
deduced from the result and the MMIO regions of the ESBs and the END
ESBs are then resized accordingly with the computed value. This
reduces the number of elements that can be addressed by the ESB pages.
The maximum number of elements of a direct table can contain is simply:
Table size / sizeof(XIVE structure)
An indirect table is a one page array of VSDs pointing to subpages
containing XIVE virtual structures and the maximum number of elements
an indirect table can contain :
(PAGE_SIZE / sizeof(vsd)) * (PAGE_SIZE / sizeof(XIVE structure))
which gives us 16M for XiveENDs, 8M for XiveNVTs. That's more than the
associated VC and PC BARS can address.
The result returned by pnv_xive_vst_size() for indirect tables is
incorrect and can not be used to reduce the size of the MMIO region of
a XIVE resource using an indirect table, such as ENDs in skiboot.
Remove pnv_xive_vst_size() and use a simpler form for direct tables
only. Keep the resizing of the MMIO region for direct tables only as
this is still useful for the ESB MMIO window.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191115162436.30548-4-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/pnv_xive.c | 112 +++++++++++++++++----------------------------
1 file changed, 43 insertions(+), 69 deletions(-)
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index 4e56c2e468..a4d80fd5e7 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -123,36 +123,22 @@ static uint64_t pnv_xive_vst_page_size_allowed(uint32_t page_shift)
page_shift == 21 || page_shift == 24;
}
-static uint64_t pnv_xive_vst_size(uint64_t vsd)
-{
- uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12);
-
- /*
- * Read the first descriptor to get the page size of the indirect
- * table.
- */
- if (VSD_INDIRECT & vsd) {
- uint32_t nr_pages = vst_tsize / XIVE_VSD_SIZE;
- uint32_t page_shift;
-
- vsd = ldq_be_dma(&address_space_memory, vsd & VSD_ADDRESS_MASK);
- page_shift = GETFIELD(VSD_TSIZE, vsd) + 12;
-
- if (!pnv_xive_vst_page_size_allowed(page_shift)) {
- return 0;
- }
-
- return nr_pages * (1ull << page_shift);
- }
-
- return vst_tsize;
-}
-
static uint64_t pnv_xive_vst_addr_direct(PnvXive *xive, uint32_t type,
uint64_t vsd, uint32_t idx)
{
const XiveVstInfo *info = &vst_infos[type];
uint64_t vst_addr = vsd & VSD_ADDRESS_MASK;
+ uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12);
+ uint32_t idx_max;
+
+ idx_max = vst_tsize / info->size - 1;
+ if (idx > idx_max) {
+#ifdef XIVE_DEBUG
+ xive_error(xive, "VST: %s entry %x out of range [ 0 .. %x ] !?",
+ info->name, idx, idx_max);
+#endif
+ return 0;
+ }
return vst_addr + idx * info->size;
}
@@ -215,7 +201,6 @@ static uint64_t pnv_xive_vst_addr(PnvXive *xive, uint32_t type, uint8_t blk,
{
const XiveVstInfo *info = &vst_infos[type];
uint64_t vsd;
- uint32_t idx_max;
if (blk >= info->max_blocks) {
xive_error(xive, "VST: invalid block id %d for VST %s %d !?",
@@ -232,15 +217,6 @@ static uint64_t pnv_xive_vst_addr(PnvXive *xive, uint32_t type, uint8_t blk,
return xive ? pnv_xive_vst_addr(xive, type, blk, idx) : 0;
}
- idx_max = pnv_xive_vst_size(vsd) / info->size - 1;
- if (idx > idx_max) {
-#ifdef XIVE_DEBUG
- xive_error(xive, "VST: %s entry %x/%x out of range [ 0 .. %x ] !?",
- info->name, blk, idx, idx_max);
-#endif
- return 0;
- }
-
if (VSD_INDIRECT & vsd) {
return pnv_xive_vst_addr_indirect(xive, type, vsd, idx);
}
@@ -453,19 +429,12 @@ static uint64_t pnv_xive_pc_size(PnvXive *xive)
return (~xive->regs[CQ_PC_BARM >> 3] + 1) & CQ_PC_BARM_MASK;
}
-static uint32_t pnv_xive_nr_ipis(PnvXive *xive)
+static uint32_t pnv_xive_nr_ipis(PnvXive *xive, uint8_t blk)
{
- uint8_t blk = xive->chip->chip_id;
-
- return pnv_xive_vst_size(xive->vsds[VST_TSEL_SBE][blk]) * SBE_PER_BYTE;
-}
-
-static uint32_t pnv_xive_nr_ends(PnvXive *xive)
-{
- uint8_t blk = xive->chip->chip_id;
+ uint64_t vsd = xive->vsds[VST_TSEL_SBE][blk];
+ uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12);
- return pnv_xive_vst_size(xive->vsds[VST_TSEL_EQDT][blk])
- / vst_infos[VST_TSEL_EQDT].size;
+ return VSD_INDIRECT & vsd ? 0 : vst_tsize * SBE_PER_BYTE;
}
/*
@@ -598,6 +567,7 @@ static void pnv_xive_vst_set_exclusive(PnvXive *xive, uint8_t type,
XiveSource *xsrc = &xive->ipi_source;
const XiveVstInfo *info = &vst_infos[type];
uint32_t page_shift = GETFIELD(VSD_TSIZE, vsd) + 12;
+ uint64_t vst_tsize = 1ull << page_shift;
uint64_t vst_addr = vsd & VSD_ADDRESS_MASK;
/* Basic checks */
@@ -633,11 +603,16 @@ static void pnv_xive_vst_set_exclusive(PnvXive *xive, uint8_t type,
case VST_TSEL_EQDT:
/*
- * Backing store pages for the END. Compute the number of ENDs
- * provisioned by FW and resize the END ESB window accordingly.
+ * Backing store pages for the END.
+ *
+ * If the table is direct, we can compute the number of PQ
+ * entries provisioned by FW (such as skiboot) and resize the
+ * END ESB window accordingly.
*/
- memory_region_set_size(&end_xsrc->esb_mmio, pnv_xive_nr_ends(xive) *
- (1ull << (end_xsrc->esb_shift + 1)));
+ if (!(VSD_INDIRECT & vsd)) {
+ memory_region_set_size(&end_xsrc->esb_mmio, (vst_tsize / info->size)
+ * (1ull << xsrc->esb_shift));
+ }
memory_region_add_subregion(&xive->end_edt_mmio, 0,
&end_xsrc->esb_mmio);
break;
@@ -646,11 +621,16 @@ static void pnv_xive_vst_set_exclusive(PnvXive *xive, uint8_t type,
/*
* Backing store pages for the source PQ bits. The model does
* not use these PQ bits backed in RAM because the XiveSource
- * model has its own. Compute the number of IRQs provisioned
- * by FW and resize the IPI ESB window accordingly.
+ * model has its own.
+ *
+ * If the table is direct, we can compute the number of PQ
+ * entries provisioned by FW (such as skiboot) and resize the
+ * ESB window accordingly.
*/
- memory_region_set_size(&xsrc->esb_mmio, pnv_xive_nr_ipis(xive) *
- (1ull << xsrc->esb_shift));
+ if (!(VSD_INDIRECT & vsd)) {
+ memory_region_set_size(&xsrc->esb_mmio, vst_tsize * SBE_PER_BYTE
+ * (1ull << xsrc->esb_shift));
+ }
memory_region_add_subregion(&xive->ipi_edt_mmio, 0, &xsrc->esb_mmio);
break;
@@ -1579,8 +1559,7 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon)
XiveRouter *xrtr = XIVE_ROUTER(xive);
uint8_t blk = xive->chip->chip_id;
uint32_t srcno0 = XIVE_EAS(blk, 0);
- uint32_t nr_ipis = pnv_xive_nr_ipis(xive);
- uint32_t nr_ends = pnv_xive_nr_ends(xive);
+ uint32_t nr_ipis = pnv_xive_nr_ipis(xive, blk);
XiveEAS eas;
XiveEND end;
int i;
@@ -1600,21 +1579,16 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon)
}
}
- monitor_printf(mon, "XIVE[%x] ENDT %08x .. %08x\n", blk, 0, nr_ends - 1);
- for (i = 0; i < nr_ends; i++) {
- if (xive_router_get_end(xrtr, blk, i, &end)) {
- break;
- }
- xive_end_pic_print_info(&end, i, mon);
+ monitor_printf(mon, "XIVE[%x] ENDT\n", blk);
+ i = 0;
+ while (!xive_router_get_end(xrtr, blk, i, &end)) {
+ xive_end_pic_print_info(&end, i++, mon);
}
- monitor_printf(mon, "XIVE[%x] END Escalation %08x .. %08x\n", blk, 0,
- nr_ends - 1);
- for (i = 0; i < nr_ends; i++) {
- if (xive_router_get_end(xrtr, blk, i, &end)) {
- break;
- }
- xive_end_eas_pic_print_info(&end, i, mon);
+ monitor_printf(mon, "XIVE[%x] END Escalation EAT\n", blk);
+ i = 0;
+ while (!xive_router_get_end(xrtr, blk, i, &end)) {
+ xive_end_eas_pic_print_info(&end, i++, mon);
}
}
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 20/88] xive/kvm: Trigger interrupts from userspace
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (18 preceding siblings ...)
2019-12-17 4:42 ` [PULL 19/88] ppc/pnv: Remove pnv_xive_vst_size() routine David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 21/88] ppc/pnv: Quiesce some XIVE errors David Gibson
` (68 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
When using the XIVE KVM device, the trigger page is directly accessible
in QEMU. Unlike with XICS, no need to ask KVM to fire the interrupt. A
simple store on the trigger page does the job.
Just call xive_esb_trigger().
This may improve performance of emulated devices that go through
qemu_set_irq(), eg. virtio devices created with ioeventfd=off or
configured by the guest to use LSI interrupts, which aren't really
recommended setups.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157408992731.494439.3405812941731584740.stgit@bahia.lan>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/spapr_xive_kvm.c | 16 ++--------------
1 file changed, 2 insertions(+), 14 deletions(-)
diff --git a/hw/intc/spapr_xive_kvm.c b/hw/intc/spapr_xive_kvm.c
index 08012ac7cd..69e73552f1 100644
--- a/hw/intc/spapr_xive_kvm.c
+++ b/hw/intc/spapr_xive_kvm.c
@@ -354,32 +354,20 @@ static void kvmppc_xive_source_get_state(XiveSource *xsrc)
void kvmppc_xive_source_set_irq(void *opaque, int srcno, int val)
{
XiveSource *xsrc = opaque;
- SpaprXive *xive = SPAPR_XIVE(xsrc->xive);
- struct kvm_irq_level args;
- int rc;
-
- /* The KVM XIVE device should be in use */
- assert(xive->fd != -1);
- args.irq = srcno;
if (!xive_source_irq_is_lsi(xsrc, srcno)) {
if (!val) {
return;
}
- args.level = KVM_INTERRUPT_SET;
} else {
if (val) {
xsrc->status[srcno] |= XIVE_STATUS_ASSERTED;
- args.level = KVM_INTERRUPT_SET_LEVEL;
} else {
xsrc->status[srcno] &= ~XIVE_STATUS_ASSERTED;
- args.level = KVM_INTERRUPT_UNSET;
}
}
- rc = kvm_vm_ioctl(kvm_state, KVM_IRQ_LINE, &args);
- if (rc < 0) {
- error_report("XIVE: kvm_irq_line() failed : %s", strerror(errno));
- }
+
+ xive_esb_trigger(xsrc, srcno);
}
/*
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 21/88] ppc/pnv: Quiesce some XIVE errors
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (19 preceding siblings ...)
2019-12-17 4:42 ` [PULL 20/88] xive/kvm: Trigger interrupts from userspace David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 22/88] ppc/xive: Introduce OS CAM line helpers David Gibson
` (67 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
When dumping the END and NVT tables, the error logging is too noisy.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191115162436.30548-6-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/pnv_xive.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index a4d80fd5e7..9a771f6407 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -29,7 +29,7 @@
#include "pnv_xive_regs.h"
-#define XIVE_DEBUG
+#undef XIVE_DEBUG
/*
* Virtual structures table (VST)
@@ -157,7 +157,9 @@ static uint64_t pnv_xive_vst_addr_indirect(PnvXive *xive, uint32_t type,
vsd = ldq_be_dma(&address_space_memory, vsd_addr);
if (!(vsd & VSD_ADDRESS_MASK)) {
+#ifdef XIVE_DEBUG
xive_error(xive, "VST: invalid %s entry %x !?", info->name, idx);
+#endif
return 0;
}
@@ -178,7 +180,9 @@ static uint64_t pnv_xive_vst_addr_indirect(PnvXive *xive, uint32_t type,
vsd = ldq_be_dma(&address_space_memory, vsd_addr);
if (!(vsd & VSD_ADDRESS_MASK)) {
+#ifdef XIVE_DEBUG
xive_error(xive, "VST: invalid %s entry %x !?", info->name, idx);
+#endif
return 0;
}
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 22/88] ppc/xive: Introduce OS CAM line helpers
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (20 preceding siblings ...)
2019-12-17 4:42 ` [PULL 21/88] ppc/pnv: Quiesce some XIVE errors David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 23/88] ppc/xive: Check V bit in TM_PULL_POOL_CTX David Gibson
` (66 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
The OS CAM line has a special encoding exploited by the HW. Provide
helper routines to hide the details to the TIMA command handlers. This
also clarifies the endianness of different variables : 'qw1w2' is
big-endian and 'cam' is native.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191115162436.30548-7-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/xive.c | 41 ++++++++++++++++++++++++++++++++++++++---
1 file changed, 38 insertions(+), 3 deletions(-)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 177663d2b4..42e9a11ef7 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -337,14 +337,49 @@ static void xive_tm_set_os_pending(XiveTCTX *tctx, hwaddr offset,
xive_tctx_notify(tctx, TM_QW1_OS);
}
+static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk,
+ uint32_t *nvt_idx, bool *vo)
+{
+ if (nvt_blk) {
+ *nvt_blk = xive_nvt_blk(cam);
+ }
+ if (nvt_idx) {
+ *nvt_idx = xive_nvt_idx(cam);
+ }
+ if (vo) {
+ *vo = !!(cam & TM_QW1W2_VO);
+ }
+}
+
+static uint32_t xive_tctx_get_os_cam(XiveTCTX *tctx, uint8_t *nvt_blk,
+ uint32_t *nvt_idx, bool *vo)
+{
+ uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
+ uint32_t cam = be32_to_cpu(qw1w2);
+
+ xive_os_cam_decode(cam, nvt_blk, nvt_idx, vo);
+ return qw1w2;
+}
+
+static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t qw1w2)
+{
+ memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
+}
+
static uint64_t xive_tm_pull_os_ctx(XiveTCTX *tctx, hwaddr offset,
unsigned size)
{
- uint32_t qw1w2_prev = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
uint32_t qw1w2;
+ uint32_t qw1w2_new;
+ uint8_t nvt_blk;
+ uint32_t nvt_idx;
+ bool vo;
- qw1w2 = xive_set_field32(TM_QW1W2_VO, qw1w2_prev, 0);
- memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
+ qw1w2 = xive_tctx_get_os_cam(tctx, &nvt_blk, &nvt_idx, &vo);
+
+ /* Invalidate CAM line */
+ qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0);
+ xive_tctx_set_os_cam(tctx, qw1w2_new);
return qw1w2;
}
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 23/88] ppc/xive: Check V bit in TM_PULL_POOL_CTX
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (21 preceding siblings ...)
2019-12-17 4:42 ` [PULL 22/88] ppc/xive: Introduce OS CAM line helpers David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 24/88] ipmi: Add support to customize OEM functions David Gibson
` (65 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
A context should be 'valid' when pulled from the thread interrupt
context registers.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191115162436.30548-8-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/xive.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 42e9a11ef7..511e1a9363 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -377,6 +377,11 @@ static uint64_t xive_tm_pull_os_ctx(XiveTCTX *tctx, hwaddr offset,
qw1w2 = xive_tctx_get_os_cam(tctx, &nvt_blk, &nvt_idx, &vo);
+ if (!vo) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVT %x/%x !?\n",
+ nvt_blk, nvt_idx);
+ }
+
/* Invalidate CAM line */
qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0);
xive_tctx_set_os_cam(tctx, qw1w2_new);
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 24/88] ipmi: Add support to customize OEM functions
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (22 preceding siblings ...)
2019-12-17 4:42 ` [PULL 23/88] ppc/xive: Check V bit in TM_PULL_POOL_CTX David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 25/88] ppc/pnv: Add HIOMAP commands David Gibson
` (64 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, Corey Minyard, aik, qemu-devel, groug, qemu-ppc, clg,
David Gibson
From: Cédric Le Goater <clg@kaod.org>
The routine ipmi_register_oem_netfn() lets external modules register
command handlers for OEM functions. Required for the PowerNV machine.
Cc: Corey Minyard <cminyard@mvista.com>
Reviewed-by: Corey Minyard <cminyard@mvista.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191028070027.22752-2-clg@kaod.org>
Acked-by: Corey Minyard <cminyard@mvista.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ipmi/ipmi_bmc_sim.c | 50 +++++-------------------------------------
include/hw/ipmi/ipmi.h | 42 +++++++++++++++++++++++++++++++++++
2 files changed, 48 insertions(+), 44 deletions(-)
diff --git a/hw/ipmi/ipmi_bmc_sim.c b/hw/ipmi/ipmi_bmc_sim.c
index 71e56f3b13..6670cf039d 100644
--- a/hw/ipmi/ipmi_bmc_sim.c
+++ b/hw/ipmi/ipmi_bmc_sim.c
@@ -167,32 +167,14 @@ typedef struct IPMISensor {
#define MAX_SENSORS 20
#define IPMI_WATCHDOG_SENSOR 0
-typedef struct IPMIBmcSim IPMIBmcSim;
-typedef struct RspBuffer RspBuffer;
-
#define MAX_NETFNS 64
-typedef struct IPMICmdHandler {
- void (*cmd_handler)(IPMIBmcSim *s,
- uint8_t *cmd, unsigned int cmd_len,
- RspBuffer *rsp);
- unsigned int cmd_len_min;
-} IPMICmdHandler;
-
-typedef struct IPMINetfn {
- unsigned int cmd_nums;
- const IPMICmdHandler *cmd_handlers;
-} IPMINetfn;
-
typedef struct IPMIRcvBufEntry {
QTAILQ_ENTRY(IPMIRcvBufEntry) entry;
uint8_t len;
uint8_t buf[MAX_IPMI_MSG_SIZE];
} IPMIRcvBufEntry;
-#define TYPE_IPMI_BMC_SIMULATOR "ipmi-bmc-sim"
-#define IPMI_BMC_SIMULATOR(obj) OBJECT_CHECK(IPMIBmcSim, (obj), \
- TYPE_IPMI_BMC_SIMULATOR)
struct IPMIBmcSim {
IPMIBmc parent;
@@ -279,28 +261,8 @@ struct IPMIBmcSim {
#define IPMI_BMC_WATCHDOG_ACTION_POWER_DOWN 2
#define IPMI_BMC_WATCHDOG_ACTION_POWER_CYCLE 3
-struct RspBuffer {
- uint8_t buffer[MAX_IPMI_MSG_SIZE];
- unsigned int len;
-};
-
#define RSP_BUFFER_INITIALIZER { }
-static inline void rsp_buffer_set_error(RspBuffer *rsp, uint8_t byte)
-{
- rsp->buffer[2] = byte;
-}
-
-/* Add a byte to the response. */
-static inline void rsp_buffer_push(RspBuffer *rsp, uint8_t byte)
-{
- if (rsp->len >= sizeof(rsp->buffer)) {
- rsp_buffer_set_error(rsp, IPMI_CC_REQUEST_DATA_TRUNCATED);
- return;
- }
- rsp->buffer[rsp->len++] = byte;
-}
-
static inline void rsp_buffer_pushmore(RspBuffer *rsp, uint8_t *bytes,
unsigned int n)
{
@@ -630,8 +592,8 @@ static void ipmi_init_sensors_from_sdrs(IPMIBmcSim *s)
}
}
-static int ipmi_register_netfn(IPMIBmcSim *s, unsigned int netfn,
- const IPMINetfn *netfnd)
+int ipmi_sim_register_netfn(IPMIBmcSim *s, unsigned int netfn,
+ const IPMINetfn *netfnd)
{
if ((netfn & 1) || (netfn >= MAX_NETFNS) || (s->netfns[netfn / 2])) {
return -1;
@@ -1860,10 +1822,10 @@ static const IPMINetfn storage_netfn = {
static void register_cmds(IPMIBmcSim *s)
{
- ipmi_register_netfn(s, IPMI_NETFN_CHASSIS, &chassis_netfn);
- ipmi_register_netfn(s, IPMI_NETFN_SENSOR_EVENT, &sensor_event_netfn);
- ipmi_register_netfn(s, IPMI_NETFN_APP, &app_netfn);
- ipmi_register_netfn(s, IPMI_NETFN_STORAGE, &storage_netfn);
+ ipmi_sim_register_netfn(s, IPMI_NETFN_CHASSIS, &chassis_netfn);
+ ipmi_sim_register_netfn(s, IPMI_NETFN_SENSOR_EVENT, &sensor_event_netfn);
+ ipmi_sim_register_netfn(s, IPMI_NETFN_APP, &app_netfn);
+ ipmi_sim_register_netfn(s, IPMI_NETFN_STORAGE, &storage_netfn);
}
static uint8_t init_sdrs[] = {
diff --git a/include/hw/ipmi/ipmi.h b/include/hw/ipmi/ipmi.h
index 6f2413b39b..8a99d958bb 100644
--- a/include/hw/ipmi/ipmi.h
+++ b/include/hw/ipmi/ipmi.h
@@ -55,6 +55,7 @@ enum ipmi_op {
#define IPMI_CC_COMMAND_NOT_SUPPORTED 0xd5
#define IPMI_NETFN_APP 0x06
+#define IPMI_NETFN_OEM 0x3a
#define IPMI_DEBUG 1
@@ -265,4 +266,45 @@ int ipmi_bmc_sdr_find(IPMIBmc *b, uint16_t recid,
const struct ipmi_sdr_compact **sdr, uint16_t *nextrec);
void ipmi_bmc_gen_event(IPMIBmc *b, uint8_t *evt, bool log);
+#define TYPE_IPMI_BMC_SIMULATOR "ipmi-bmc-sim"
+#define IPMI_BMC_SIMULATOR(obj) OBJECT_CHECK(IPMIBmcSim, (obj), \
+ TYPE_IPMI_BMC_SIMULATOR)
+
+typedef struct IPMIBmcSim IPMIBmcSim;
+
+typedef struct RspBuffer {
+ uint8_t buffer[MAX_IPMI_MSG_SIZE];
+ unsigned int len;
+} RspBuffer;
+
+static inline void rsp_buffer_set_error(RspBuffer *rsp, uint8_t byte)
+{
+ rsp->buffer[2] = byte;
+}
+
+/* Add a byte to the response. */
+static inline void rsp_buffer_push(RspBuffer *rsp, uint8_t byte)
+{
+ if (rsp->len >= sizeof(rsp->buffer)) {
+ rsp_buffer_set_error(rsp, IPMI_CC_REQUEST_DATA_TRUNCATED);
+ return;
+ }
+ rsp->buffer[rsp->len++] = byte;
+}
+
+typedef struct IPMICmdHandler {
+ void (*cmd_handler)(IPMIBmcSim *s,
+ uint8_t *cmd, unsigned int cmd_len,
+ RspBuffer *rsp);
+ unsigned int cmd_len_min;
+} IPMICmdHandler;
+
+typedef struct IPMINetfn {
+ unsigned int cmd_nums;
+ const IPMICmdHandler *cmd_handlers;
+} IPMINetfn;
+
+int ipmi_sim_register_netfn(IPMIBmcSim *s, unsigned int netfn,
+ const IPMINetfn *netfnd);
+
#endif
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 25/88] ppc/pnv: Add HIOMAP commands
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (23 preceding siblings ...)
2019-12-17 4:42 ` [PULL 24/88] ipmi: Add support to customize OEM functions David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 26/88] ppc/pnv: Create BMC devices at machine init David Gibson
` (63 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson,
Joel Stanley
From: Cédric Le Goater <clg@kaod.org>
This activates HIOMAP support on the QEMU PowerNV machine. The PnvPnor
model is used to access the flash contents. The model simply maps the
contents at a fix offset and enables or disables the mapping.
HIOMAP Protocol description :
https://github.com/openbmc/hiomapd/blob/master/Documentation/protocol.md
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191028070027.22752-3-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 1 +
hw/ppc/pnv_bmc.c | 102 ++++++++++++++++++++++++++++++++++++++
hw/ppc/pnv_lpc.c | 13 +++++
include/hw/ppc/pnv.h | 1 +
include/hw/ppc/pnv_pnor.h | 5 ++
5 files changed, 122 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index a2a8b97330..c3ac0d6d5b 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -569,6 +569,7 @@ static void pnv_reset(MachineState *machine)
obj = object_resolve_path_type("", "ipmi-bmc-sim", NULL);
if (obj) {
pnv->bmc = IPMI_BMC(obj);
+ pnv_bmc_hiomap(pnv->bmc);
}
fdt = pnv_dt_create(machine);
diff --git a/hw/ppc/pnv_bmc.c b/hw/ppc/pnv_bmc.c
index dc5e918cb7..aa5c89586c 100644
--- a/hw/ppc/pnv_bmc.c
+++ b/hw/ppc/pnv_bmc.c
@@ -114,3 +114,105 @@ void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt)
sdr->sensor_type)));
}
}
+
+/*
+ * HIOMAP protocol handler
+ */
+#define HIOMAP_C_RESET 1
+#define HIOMAP_C_GET_INFO 2
+#define HIOMAP_C_GET_FLASH_INFO 3
+#define HIOMAP_C_CREATE_READ_WINDOW 4
+#define HIOMAP_C_CLOSE_WINDOW 5
+#define HIOMAP_C_CREATE_WRITE_WINDOW 6
+#define HIOMAP_C_MARK_DIRTY 7
+#define HIOMAP_C_FLUSH 8
+#define HIOMAP_C_ACK 9
+#define HIOMAP_C_ERASE 10
+#define HIOMAP_C_DEVICE_NAME 11
+#define HIOMAP_C_LOCK 12
+
+#define BLOCK_SHIFT 12 /* 4K */
+
+static uint16_t bytes_to_blocks(uint32_t bytes)
+{
+ return bytes >> BLOCK_SHIFT;
+}
+
+static void hiomap_cmd(IPMIBmcSim *ibs, uint8_t *cmd, unsigned int cmd_len,
+ RspBuffer *rsp)
+{
+ PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
+ PnvPnor *pnor = pnv->pnor;
+ uint32_t pnor_size = pnor->size;
+ uint32_t pnor_addr = PNOR_SPI_OFFSET;
+ bool readonly = false;
+
+ rsp_buffer_push(rsp, cmd[2]);
+ rsp_buffer_push(rsp, cmd[3]);
+
+ switch (cmd[2]) {
+ case HIOMAP_C_MARK_DIRTY:
+ case HIOMAP_C_FLUSH:
+ case HIOMAP_C_ERASE:
+ case HIOMAP_C_ACK:
+ break;
+
+ case HIOMAP_C_GET_INFO:
+ rsp_buffer_push(rsp, 2); /* Version 2 */
+ rsp_buffer_push(rsp, BLOCK_SHIFT); /* block size */
+ rsp_buffer_push(rsp, 0); /* Timeout */
+ rsp_buffer_push(rsp, 0); /* Timeout */
+ break;
+
+ case HIOMAP_C_GET_FLASH_INFO:
+ rsp_buffer_push(rsp, bytes_to_blocks(pnor_size) & 0xFF);
+ rsp_buffer_push(rsp, bytes_to_blocks(pnor_size) >> 8);
+ rsp_buffer_push(rsp, 0x01); /* erase size */
+ rsp_buffer_push(rsp, 0x00); /* erase size */
+ break;
+
+ case HIOMAP_C_CREATE_READ_WINDOW:
+ readonly = true;
+ /* Fall through */
+
+ case HIOMAP_C_CREATE_WRITE_WINDOW:
+ memory_region_set_readonly(&pnor->mmio, readonly);
+ memory_region_set_enabled(&pnor->mmio, true);
+
+ rsp_buffer_push(rsp, bytes_to_blocks(pnor_addr) & 0xFF);
+ rsp_buffer_push(rsp, bytes_to_blocks(pnor_addr) >> 8);
+ rsp_buffer_push(rsp, bytes_to_blocks(pnor_size) & 0xFF);
+ rsp_buffer_push(rsp, bytes_to_blocks(pnor_size) >> 8);
+ rsp_buffer_push(rsp, 0x00); /* offset */
+ rsp_buffer_push(rsp, 0x00); /* offset */
+ break;
+
+ case HIOMAP_C_CLOSE_WINDOW:
+ memory_region_set_enabled(&pnor->mmio, false);
+ break;
+
+ case HIOMAP_C_DEVICE_NAME:
+ case HIOMAP_C_RESET:
+ case HIOMAP_C_LOCK:
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "HIOMAP: unknow command %02X\n", cmd[2]);
+ break;
+ }
+}
+
+#define HIOMAP 0x5a
+
+static const IPMICmdHandler hiomap_cmds[] = {
+ [HIOMAP] = { hiomap_cmd, 3 },
+};
+
+static const IPMINetfn hiomap_netfn = {
+ .cmd_nums = ARRAY_SIZE(hiomap_cmds),
+ .cmd_handlers = hiomap_cmds
+};
+
+int pnv_bmc_hiomap(IPMIBmc *bmc)
+{
+ return ipmi_sim_register_netfn(IPMI_BMC_SIMULATOR(bmc),
+ IPMI_NETFN_OEM, &hiomap_netfn);
+}
diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
index c5a85c38c7..dd5374c838 100644
--- a/hw/ppc/pnv_lpc.c
+++ b/hw/ppc/pnv_lpc.c
@@ -810,6 +810,7 @@ ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp)
ISABus *isa_bus;
qemu_irq *irqs;
qemu_irq_handler handler;
+ PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
/* let isa_bus_new() create its own bridge on SysBus otherwise
* devices speficied on the command line won't find the bus and
@@ -834,5 +835,17 @@ ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp)
irqs = qemu_allocate_irqs(handler, lpc, ISA_NUM_IRQS);
isa_bus_irqs(isa_bus, irqs);
+
+ /*
+ * TODO: Map PNOR on the LPC FW address space on demand ?
+ */
+ memory_region_add_subregion(&lpc->isa_fw, PNOR_SPI_OFFSET,
+ &pnv->pnor->mmio);
+ /*
+ * Start disabled. The HIOMAP protocol will activate the mapping
+ * with HIOMAP_C_CREATE_WRITE_WINDOW
+ */
+ memory_region_set_enabled(&pnv->pnor->mmio, false);
+
return isa_bus;
}
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 5ecd3ba6ed..07c56c05ad 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -198,6 +198,7 @@ static inline bool pnv_is_power9(PnvMachineState *pnv)
*/
void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt);
void pnv_bmc_powerdown(IPMIBmc *bmc);
+int pnv_bmc_hiomap(IPMIBmc *bmc);
/*
* POWER8 MMIO base addresses
diff --git a/include/hw/ppc/pnv_pnor.h b/include/hw/ppc/pnv_pnor.h
index dec811695c..c3dd28643c 100644
--- a/include/hw/ppc/pnv_pnor.h
+++ b/include/hw/ppc/pnv_pnor.h
@@ -9,6 +9,11 @@
#ifndef _PPC_PNV_PNOR_H
#define _PPC_PNV_PNOR_H
+/*
+ * PNOR offset on the LPC FW address space
+ */
+#define PNOR_SPI_OFFSET 0x0c000000UL
+
#define TYPE_PNV_PNOR "pnv-pnor"
#define PNV_PNOR(obj) OBJECT_CHECK(PnvPnor, (obj), TYPE_PNV_PNOR)
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 26/88] ppc/pnv: Create BMC devices at machine init
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (24 preceding siblings ...)
2019-12-17 4:42 ` [PULL 25/88] ppc/pnv: Add HIOMAP commands David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 27/88] ppc/xive: Introduce a XivePresenter interface David Gibson
` (62 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
The BMC of the OpenPOWER systems monitors the machine state using
sensors, controls the power and controls the access to the PNOR flash
device containing the firmware image required to boot the host.
QEMU models the power cycle process, access to the sensors and access
to the PNOR device. But, for these features to be available, the QEMU
PowerNV machine needs two extras devices on the command line, an IPMI
BT device for communication and a BMC backend device:
-device ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10
The BMC properties are then defined accordingly in the device tree and
OPAL self adapts. If a BMC device and an IPMI BT device are not
available, OPAL does not try to communicate with the BMC in any
manner. This is not how real systems behave.
To be closer to the default behavior, create an IPMI BMC simulator
device and an IPMI BT device at machine initialization time. We loose
the ability to define an external BMC device but there are benefits:
- a better match with real systems,
- a better test coverage of the OPAL code,
- system powerdown and reset commands that work,
- a QEMU device tree compliant with the specifications (*).
(*) Still needs a MBOX device.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191121162340.11049-1-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 33 ++++++++++++++++-----------------
hw/ppc/pnv_bmc.c | 20 +++++++++++++++++---
include/hw/ppc/pnv.h | 2 +-
3 files changed, 34 insertions(+), 21 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index c3ac0d6d5b..f0adb06c8d 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -551,27 +551,10 @@ static void pnv_powerdown_notify(Notifier *n, void *opaque)
static void pnv_reset(MachineState *machine)
{
- PnvMachineState *pnv = PNV_MACHINE(machine);
void *fdt;
- Object *obj;
qemu_devices_reset();
- /*
- * OpenPOWER systems have a BMC, which can be defined on the
- * command line with:
- *
- * -device ipmi-bmc-sim,id=bmc0
- *
- * This is the internal simulator but it could also be an external
- * BMC.
- */
- obj = object_resolve_path_type("", "ipmi-bmc-sim", NULL);
- if (obj) {
- pnv->bmc = IPMI_BMC(obj);
- pnv_bmc_hiomap(pnv->bmc);
- }
-
fdt = pnv_dt_create(machine);
/* Pack resulting tree */
@@ -629,6 +612,16 @@ static bool pnv_match_cpu(const char *default_type, const char *cpu_type)
return ppc_default->pvr_match(ppc_default, ppc->pvr);
}
+static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq)
+{
+ Object *obj;
+
+ obj = OBJECT(isa_create(bus, "isa-ipmi-bt"));
+ object_property_set_link(obj, OBJECT(bmc), "bmc", &error_fatal);
+ object_property_set_int(obj, irq, "irq", &error_fatal);
+ object_property_set_bool(obj, true, "realized", &error_fatal);
+}
+
static void pnv_init(MachineState *machine)
{
PnvMachineState *pnv = PNV_MACHINE(machine);
@@ -751,6 +744,9 @@ static void pnv_init(MachineState *machine)
}
g_free(chip_typename);
+ /* Create the machine BMC simulator */
+ pnv->bmc = pnv_bmc_create();
+
/* Instantiate ISA bus on chip 0 */
pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal);
@@ -760,6 +756,9 @@ static void pnv_init(MachineState *machine)
/* Create an RTC ISA device too */
mc146818_rtc_init(pnv->isa_bus, 2000, NULL);
+ /* Create the IPMI BT device for communication with the BMC */
+ pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10);
+
/*
* OpenPOWER systems use a IPMI SEL Event message to notify the
* host to powerdown
diff --git a/hw/ppc/pnv_bmc.c b/hw/ppc/pnv_bmc.c
index aa5c89586c..07fa1e1c7e 100644
--- a/hw/ppc/pnv_bmc.c
+++ b/hw/ppc/pnv_bmc.c
@@ -17,6 +17,8 @@
*/
#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "qapi/error.h"
#include "target/ppc/cpu.h"
#include "qemu/log.h"
#include "hw/ipmi/ipmi.h"
@@ -211,8 +213,20 @@ static const IPMINetfn hiomap_netfn = {
.cmd_handlers = hiomap_cmds
};
-int pnv_bmc_hiomap(IPMIBmc *bmc)
+/*
+ * Instantiate the machine BMC. PowerNV uses the QEMU internal
+ * simulator but it could also be external.
+ */
+IPMIBmc *pnv_bmc_create(void)
{
- return ipmi_sim_register_netfn(IPMI_BMC_SIMULATOR(bmc),
- IPMI_NETFN_OEM, &hiomap_netfn);
+ Object *obj;
+
+ obj = object_new(TYPE_IPMI_BMC_SIMULATOR);
+ object_property_set_bool(obj, true, "realized", &error_fatal);
+
+ /* Install the HIOMAP protocol handlers to access the PNOR */
+ ipmi_sim_register_netfn(IPMI_BMC_SIMULATOR(obj), IPMI_NETFN_OEM,
+ &hiomap_netfn);
+
+ return IPMI_BMC(obj);
}
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 07c56c05ad..90f1343ed0 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -198,7 +198,7 @@ static inline bool pnv_is_power9(PnvMachineState *pnv)
*/
void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt);
void pnv_bmc_powerdown(IPMIBmc *bmc);
-int pnv_bmc_hiomap(IPMIBmc *bmc);
+IPMIBmc *pnv_bmc_create(void);
/*
* POWER8 MMIO base addresses
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 27/88] ppc/xive: Introduce a XivePresenter interface
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (25 preceding siblings ...)
2019-12-17 4:42 ` [PULL 26/88] ppc/pnv: Create BMC devices at machine init David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 28/88] ppc/xive: Implement the " David Gibson
` (61 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
When the XIVE IVRE sub-engine (XiveRouter) looks for a Notification
Virtual Target (NVT) to notify, it broadcasts a message on the
PowerBUS to find an XIVE IVPE sub-engine (Presenter) with the NVT
dispatched on one of its HW threads, and then forwards the
notification if any response was received.
The current XIVE presenter model is sufficient for the pseries machine
because it has a single interrupt controller device, but the PowerNV
machine can have multiple chips each having its own interrupt
controller. In this case, the XIVE presenter model is too simple and
the CAM line matching should scan all chips of the system.
To start fixing this issue, we first extend the XIVE Router model with
a new XivePresenter QOM interface representing the XIVE IVPE
sub-engine. This interface exposes a 'match_nvt' handler which the
sPAPR and PowerNV XIVE Router models will need to implement to perform
the CAM line matching.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191125065820.927-2-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/xive.c | 26 +++++++++++++++++---------
include/hw/ppc/xive.h | 32 ++++++++++++++++++++++++++++++++
2 files changed, 49 insertions(+), 9 deletions(-)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 511e1a9363..344bb3f3bc 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -1363,9 +1363,10 @@ static uint32_t xive_tctx_hw_cam_line(XiveTCTX *tctx)
/*
* The thread context register words are in big-endian format.
*/
-static int xive_presenter_tctx_match(XiveTCTX *tctx, uint8_t format,
- uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint32_t logic_serv)
+int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
+ uint8_t format,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ bool cam_ignore, uint32_t logic_serv)
{
uint32_t cam = xive_nvt_cam_line(nvt_blk, nvt_idx);
uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]);
@@ -1422,11 +1423,6 @@ static int xive_presenter_tctx_match(XiveTCTX *tctx, uint8_t format,
return -1;
}
-typedef struct XiveTCTXMatch {
- XiveTCTX *tctx;
- uint8_t ring;
-} XiveTCTXMatch;
-
static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
bool cam_ignore, uint8_t priority,
@@ -1460,7 +1456,8 @@ static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format,
* Check the thread context CAM lines and record matches. We
* will handle CPU exception delivery later
*/
- ring = xive_presenter_tctx_match(tctx, format, nvt_blk, nvt_idx,
+ ring = xive_presenter_tctx_match(XIVE_PRESENTER(xrtr), tctx, format,
+ nvt_blk, nvt_idx,
cam_ignore, logic_serv);
/*
* Save the context and follow on to catch duplicates, that we
@@ -1754,6 +1751,7 @@ static const TypeInfo xive_router_info = {
.class_init = xive_router_class_init,
.interfaces = (InterfaceInfo[]) {
{ TYPE_XIVE_NOTIFIER },
+ { TYPE_XIVE_PRESENTER },
{ }
}
};
@@ -1923,10 +1921,20 @@ static const TypeInfo xive_notifier_info = {
.class_size = sizeof(XiveNotifierClass),
};
+/*
+ * XIVE Presenter
+ */
+static const TypeInfo xive_presenter_info = {
+ .name = TYPE_XIVE_PRESENTER,
+ .parent = TYPE_INTERFACE,
+ .class_size = sizeof(XivePresenterClass),
+};
+
static void xive_register_types(void)
{
type_register_static(&xive_source_info);
type_register_static(&xive_notifier_info);
+ type_register_static(&xive_presenter_info);
type_register_static(&xive_router_info);
type_register_static(&xive_end_source_info);
type_register_static(&xive_tctx_info);
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index fa7adf87fe..f9aa0fa0da 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -367,6 +367,38 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs);
void xive_router_notify(XiveNotifier *xn, uint32_t lisn);
+/*
+ * XIVE Presenter
+ */
+
+typedef struct XiveTCTXMatch {
+ XiveTCTX *tctx;
+ uint8_t ring;
+} XiveTCTXMatch;
+
+typedef struct XivePresenter XivePresenter;
+
+#define TYPE_XIVE_PRESENTER "xive-presenter"
+#define XIVE_PRESENTER(obj) \
+ INTERFACE_CHECK(XivePresenter, (obj), TYPE_XIVE_PRESENTER)
+#define XIVE_PRESENTER_CLASS(klass) \
+ OBJECT_CLASS_CHECK(XivePresenterClass, (klass), TYPE_XIVE_PRESENTER)
+#define XIVE_PRESENTER_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(XivePresenterClass, (obj), TYPE_XIVE_PRESENTER)
+
+typedef struct XivePresenterClass {
+ InterfaceClass parent;
+ int (*match_nvt)(XivePresenter *xptr, uint8_t format,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ bool cam_ignore, uint8_t priority,
+ uint32_t logic_serv, XiveTCTXMatch *match);
+} XivePresenterClass;
+
+int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
+ uint8_t format,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ bool cam_ignore, uint32_t logic_serv);
+
/*
* XIVE END ESBs
*/
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 28/88] ppc/xive: Implement the XivePresenter interface
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (26 preceding siblings ...)
2019-12-17 4:42 ` [PULL 27/88] ppc/xive: Introduce a XivePresenter interface David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 29/88] ppc/pnv: Instantiate cores separately David Gibson
` (60 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
Each XIVE Router model, sPAPR and PowerNV, now implements the 'match_nvt'
handler of the XivePresenter QOM interface. This is simply moving code
and taking into account the new API.
To be noted that the xive_router_get_tctx() helper is not used anymore
when doing CAM matching and will be removed later on after other changes.
The XIVE presenter model is still too simple for the PowerNV machine
and the CAM matching algo is not correct on multichip system. Subsequent
patches will introduce more changes to scan all chips of the system.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191125065820.927-3-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/pnv_xive.c | 41 +++++++++++++++++++++++++++++++++++
hw/intc/spapr_xive.c | 49 ++++++++++++++++++++++++++++++++++++++++++
hw/intc/xive.c | 51 ++++++--------------------------------------
3 files changed, 97 insertions(+), 44 deletions(-)
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index 9a771f6407..8055de89cf 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -372,6 +372,45 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t blk, uint32_t idx,
return pnv_xive_vst_read(xive, VST_TSEL_IVT, blk, idx, eas);
}
+static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ bool cam_ignore, uint8_t priority,
+ uint32_t logic_serv, XiveTCTXMatch *match)
+{
+ CPUState *cs;
+ int count = 0;
+
+ CPU_FOREACH(cs) {
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
+ int ring;
+
+ /*
+ * Check the thread context CAM lines and record matches.
+ */
+ ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, nvt_idx,
+ cam_ignore, logic_serv);
+ /*
+ * Save the context and follow on to catch duplicates, that we
+ * don't support yet.
+ */
+ if (ring != -1) {
+ if (match->tctx) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a "
+ "thread context NVT %x/%x\n",
+ nvt_blk, nvt_idx);
+ return -1;
+ }
+
+ match->ring = ring;
+ match->tctx = tctx;
+ count++;
+ }
+ }
+
+ return count;
+}
+
static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
@@ -1780,6 +1819,7 @@ static void pnv_xive_class_init(ObjectClass *klass, void *data)
PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass);
XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass);
+ XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass);
xdc->dt_xscom = pnv_xive_dt_xscom;
@@ -1795,6 +1835,7 @@ static void pnv_xive_class_init(ObjectClass *klass, void *data)
xrc->get_tctx = pnv_xive_get_tctx;
xnc->notify = pnv_xive_notify;
+ xpc->match_nvt = pnv_xive_match_nvt;
};
static const TypeInfo pnv_xive_info = {
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index 729246e906..bb3b2dfdb7 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -405,6 +405,52 @@ static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
return spapr_cpu_state(cpu)->tctx;
}
+static int spapr_xive_match_nvt(XivePresenter *xptr, uint8_t format,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ bool cam_ignore, uint8_t priority,
+ uint32_t logic_serv, XiveTCTXMatch *match)
+{
+ CPUState *cs;
+ int count = 0;
+
+ CPU_FOREACH(cs) {
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ XiveTCTX *tctx = spapr_cpu_state(cpu)->tctx;
+ int ring;
+
+ /*
+ * Skip partially initialized vCPUs. This can happen when
+ * vCPUs are hotplugged.
+ */
+ if (!tctx) {
+ continue;
+ }
+
+ /*
+ * Check the thread context CAM lines and record matches.
+ */
+ ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, nvt_idx,
+ cam_ignore, logic_serv);
+ /*
+ * Save the matching thread interrupt context and follow on to
+ * check for duplicates which are invalid.
+ */
+ if (ring != -1) {
+ if (match->tctx) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a thread "
+ "context NVT %x/%x\n", nvt_blk, nvt_idx);
+ return -1;
+ }
+
+ match->ring = ring;
+ match->tctx = tctx;
+ count++;
+ }
+ }
+
+ return count;
+}
+
static const VMStateDescription vmstate_spapr_xive_end = {
.name = TYPE_SPAPR_XIVE "/end",
.version_id = 1,
@@ -684,6 +730,7 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass);
SpaprInterruptControllerClass *sicc = SPAPR_INTC_CLASS(klass);
+ XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass);
dc->desc = "sPAPR XIVE Interrupt Controller";
dc->props = spapr_xive_properties;
@@ -708,6 +755,8 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data)
sicc->print_info = spapr_xive_print_info;
sicc->dt = spapr_xive_dt;
sicc->post_load = spapr_xive_post_load;
+
+ xpc->match_nvt = spapr_xive_match_nvt;
}
static const TypeInfo spapr_xive_info = {
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 344bb3f3bc..da6196ca95 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -1428,51 +1428,14 @@ static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format,
bool cam_ignore, uint8_t priority,
uint32_t logic_serv, XiveTCTXMatch *match)
{
- CPUState *cs;
+ XivePresenter *xptr = XIVE_PRESENTER(xrtr);
+ XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
+ int count;
- /*
- * TODO (PowerNV): handle chip_id overwrite of block field for
- * hardwired CAM compares
- */
-
- CPU_FOREACH(cs) {
- XiveTCTX *tctx = xive_router_get_tctx(xrtr, cs);
- int ring;
-
- /*
- * Skip partially initialized vCPUs. This can happen when
- * vCPUs are hotplugged.
- */
- if (!tctx) {
- continue;
- }
-
- /*
- * HW checks that the CPU is enabled in the Physical Thread
- * Enable Register (PTER).
- */
-
- /*
- * Check the thread context CAM lines and record matches. We
- * will handle CPU exception delivery later
- */
- ring = xive_presenter_tctx_match(XIVE_PRESENTER(xrtr), tctx, format,
- nvt_blk, nvt_idx,
- cam_ignore, logic_serv);
- /*
- * Save the context and follow on to catch duplicates, that we
- * don't support yet.
- */
- if (ring != -1) {
- if (match->tctx) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a thread "
- "context NVT %x/%x\n", nvt_blk, nvt_idx);
- return false;
- }
-
- match->ring = ring;
- match->tctx = tctx;
- }
+ count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
+ priority, logic_serv, match);
+ if (count < 0) {
+ return false;
}
if (!match->tctx) {
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 29/88] ppc/pnv: Instantiate cores separately
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (27 preceding siblings ...)
2019-12-17 4:42 ` [PULL 28/88] ppc/xive: Implement the " David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 30/88] ppc/pnv: Loop on the threads of the chip to find a matching NVT David Gibson
` (59 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
Allocating a big void * array to store multiple objects isn't a
recommended practice for various reasons:
- no compile time type checking
- potential dangling pointers if a reference on an individual is
taken and the array is freed later on
- duplicate boiler plate everywhere the array is browsed through
Allocate an array of pointers and populate it instead.
Signed-off-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191125065820.927-4-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 30 ++++++++++++------------------
include/hw/ppc/pnv.h | 2 +-
2 files changed, 13 insertions(+), 19 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index f0adb06c8d..d899c83e52 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -280,14 +280,12 @@ static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
{
- const char *typename = pnv_chip_core_typename(chip);
- size_t typesize = object_type_get_instance_size(typename);
int i;
pnv_dt_xscom(chip, fdt, 0);
for (i = 0; i < chip->nr_cores; i++) {
- PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
+ PnvCore *pnv_core = chip->cores[i];
pnv_dt_core(chip, pnv_core, fdt);
@@ -302,14 +300,12 @@ static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
{
- const char *typename = pnv_chip_core_typename(chip);
- size_t typesize = object_type_get_instance_size(typename);
int i;
pnv_dt_xscom(chip, fdt, 0);
for (i = 0; i < chip->nr_cores; i++) {
- PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
+ PnvCore *pnv_core = chip->cores[i];
pnv_dt_core(chip, pnv_core, fdt);
}
@@ -913,8 +909,6 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
{
PnvChip *chip = PNV_CHIP(chip8);
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
- const char *typename = pnv_chip_core_typename(chip);
- size_t typesize = object_type_get_instance_size(typename);
int i, j;
char *name;
XICSFabric *xi = XICS_FABRIC(qdev_get_machine());
@@ -928,7 +922,7 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
/* Map the ICP registers for each thread */
for (i = 0; i < chip->nr_cores; i++) {
- PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
+ PnvCore *pnv_core = chip->cores[i];
int core_hwid = CPU_CORE(pnv_core)->core_id;
for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
@@ -1108,8 +1102,6 @@ static void pnv_chip_power9_instance_init(Object *obj)
static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
{
PnvChip *chip = PNV_CHIP(chip9);
- const char *typename = pnv_chip_core_typename(chip);
- size_t typesize = object_type_get_instance_size(typename);
int i;
chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
@@ -1118,7 +1110,7 @@ static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
for (i = 0; i < chip9->nr_quads; i++) {
char eq_name[32];
PnvQuad *eq = &chip9->quads[i];
- PnvCore *pnv_core = PNV_CORE(chip->cores + (i * 4) * typesize);
+ PnvCore *pnv_core = chip->cores[i * 4];
int core_id = CPU_CORE(pnv_core)->core_id;
snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
@@ -1290,7 +1282,6 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
Error *error = NULL;
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
const char *typename = pnv_chip_core_typename(chip);
- size_t typesize = object_type_get_instance_size(typename);
int i, core_hwid;
if (!object_class_by_name(typename)) {
@@ -1305,21 +1296,24 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
return;
}
- chip->cores = g_malloc0(typesize * chip->nr_cores);
+ chip->cores = g_new0(PnvCore *, chip->nr_cores);
for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
&& (i < chip->nr_cores); core_hwid++) {
char core_name[32];
- void *pnv_core = chip->cores + i * typesize;
+ PnvCore *pnv_core;
uint64_t xscom_core_base;
if (!(chip->cores_mask & (1ull << core_hwid))) {
continue;
}
+ pnv_core = PNV_CORE(object_new(typename));
+
snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
- object_initialize_child(OBJECT(chip), core_name, pnv_core, typesize,
- typename, &error_fatal, NULL);
+ object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core),
+ &error_abort);
+ chip->cores[i] = pnv_core;
object_property_set_int(OBJECT(pnv_core), ms->smp.threads, "nr-threads",
&error_fatal);
object_property_set_int(OBJECT(pnv_core), core_hwid,
@@ -1340,7 +1334,7 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
}
pnv_xscom_add_subregion(chip, xscom_core_base,
- &PNV_CORE(pnv_core)->xscom_regs);
+ &pnv_core->xscom_regs);
i++;
}
}
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 90f1343ed0..03cb429f21 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -56,7 +56,7 @@ typedef struct PnvChip {
uint32_t nr_cores;
uint64_t cores_mask;
- void *cores;
+ PnvCore **cores;
MemoryRegion xscom_mmio;
MemoryRegion xscom;
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 30/88] ppc/pnv: Loop on the threads of the chip to find a matching NVT
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (28 preceding siblings ...)
2019-12-17 4:42 ` [PULL 29/88] ppc/pnv: Instantiate cores separately David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 31/88] ppc: Introduce a ppc_cpu_pir() helper David Gibson
` (58 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
CPU_FOREACH() loops on all the CPUs of the machine which is incorrect.
Each XIVE Presenter should scan only the HW threads of the chip it
belongs to.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191125065820.927-5-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/pnv_xive.c | 61 ++++++++++++++++++++++++++--------------------
1 file changed, 35 insertions(+), 26 deletions(-)
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index 8055de89cf..9798bd9e72 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -377,34 +377,43 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
bool cam_ignore, uint8_t priority,
uint32_t logic_serv, XiveTCTXMatch *match)
{
- CPUState *cs;
+ PnvXive *xive = PNV_XIVE(xptr);
+ PnvChip *chip = xive->chip;
int count = 0;
-
- CPU_FOREACH(cs) {
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
- int ring;
-
- /*
- * Check the thread context CAM lines and record matches.
- */
- ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, nvt_idx,
- cam_ignore, logic_serv);
- /*
- * Save the context and follow on to catch duplicates, that we
- * don't support yet.
- */
- if (ring != -1) {
- if (match->tctx) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a "
- "thread context NVT %x/%x\n",
- nvt_blk, nvt_idx);
- return -1;
+ int i, j;
+
+ for (i = 0; i < chip->nr_cores; i++) {
+ PnvCore *pc = chip->cores[i];
+ CPUCore *cc = CPU_CORE(pc);
+
+ for (j = 0; j < cc->nr_threads; j++) {
+ PowerPCCPU *cpu = pc->threads[j];
+ XiveTCTX *tctx;
+ int ring;
+
+ tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
+
+ /*
+ * Check the thread context CAM lines and record matches.
+ */
+ ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk,
+ nvt_idx, cam_ignore, logic_serv);
+ /*
+ * Save the context and follow on to catch duplicates, that we
+ * don't support yet.
+ */
+ if (ring != -1) {
+ if (match->tctx) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a "
+ "thread context NVT %x/%x\n",
+ nvt_blk, nvt_idx);
+ return -1;
+ }
+
+ match->ring = ring;
+ match->tctx = tctx;
+ count++;
}
-
- match->ring = ring;
- match->tctx = tctx;
- count++;
}
}
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 31/88] ppc: Introduce a ppc_cpu_pir() helper
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (29 preceding siblings ...)
2019-12-17 4:42 ` [PULL 30/88] ppc/pnv: Loop on the threads of the chip to find a matching NVT David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 32/88] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper David Gibson
` (57 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191125065820.927-6-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/ppc.c | 9 +++++++--
include/hw/ppc/ppc.h | 1 +
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index 52a18eb7d7..8dd982fc1e 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -1495,15 +1495,20 @@ void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
}
}
+int ppc_cpu_pir(PowerPCCPU *cpu)
+{
+ CPUPPCState *env = &cpu->env;
+ return env->spr_cb[SPR_PIR].default_value;
+}
+
PowerPCCPU *ppc_get_vcpu_by_pir(int pir)
{
CPUState *cs;
CPU_FOREACH(cs) {
PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
- if (env->spr_cb[SPR_PIR].default_value == pir) {
+ if (ppc_cpu_pir(cpu) == pir) {
return cpu;
}
}
diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h
index 4bdcb8bacd..585be6ab98 100644
--- a/include/hw/ppc/ppc.h
+++ b/include/hw/ppc/ppc.h
@@ -5,6 +5,7 @@
void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level);
PowerPCCPU *ppc_get_vcpu_by_pir(int pir);
+int ppc_cpu_pir(PowerPCCPU *cpu);
/* PowerPC hardware exceptions management helpers */
typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 32/88] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (30 preceding siblings ...)
2019-12-17 4:42 ` [PULL 31/88] ppc: Introduce a ppc_cpu_pir() helper David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 33/88] ppc/pnv: Fix TIMA indirect access David Gibson
` (56 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
and use this helper to exclude CPUs which are not enabled in the XIVE
controller.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191125065820.927-7-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/pnv_xive.c | 19 +++++++++++++++++++
include/hw/ppc/pnv.h | 5 +++++
2 files changed, 24 insertions(+)
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index 9798bd9e72..ec8349ee4a 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -372,6 +372,21 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t blk, uint32_t idx,
return pnv_xive_vst_read(xive, VST_TSEL_IVT, blk, idx, eas);
}
+/*
+ * One bit per thread id. The first register PC_THREAD_EN_REG0 covers
+ * the first cores 0-15 (normal) of the chip or 0-7 (fused). The
+ * second register covers cores 16-23 (normal) or 8-11 (fused).
+ */
+static bool pnv_xive_is_cpu_enabled(PnvXive *xive, PowerPCCPU *cpu)
+{
+ int pir = ppc_cpu_pir(cpu);
+ uint32_t fc = PNV9_PIR2FUSEDCORE(pir);
+ uint64_t reg = fc < 8 ? PC_THREAD_EN_REG0 : PC_THREAD_EN_REG1;
+ uint32_t bit = pir & 0x3f;
+
+ return xive->regs[reg >> 3] & PPC_BIT(bit);
+}
+
static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
bool cam_ignore, uint8_t priority,
@@ -391,6 +406,10 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
XiveTCTX *tctx;
int ring;
+ if (!pnv_xive_is_cpu_enabled(xive, cpu)) {
+ continue;
+ }
+
tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
/*
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 03cb429f21..12b0169a40 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -99,6 +99,11 @@ typedef struct Pnv9Chip {
PnvQuad *quads;
} Pnv9Chip;
+/*
+ * A SMT8 fused core is a pair of SMT4 cores.
+ */
+#define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
+
typedef struct PnvChipClass {
/*< private >*/
SysBusDeviceClass parent_class;
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 33/88] ppc/pnv: Fix TIMA indirect access
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (31 preceding siblings ...)
2019-12-17 4:42 ` [PULL 32/88] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 34/88] ppc/xive: Introduce a XiveFabric interface David Gibson
` (55 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
When the TIMA of a CPU needs to be accessed from the indirect page,
the thread id of the target CPU is first stored in the PC_TCTXT_INDIR0
register. This thread id is relative to the chip and not to the system.
Introduce a helper routine to look for a CPU of a given PIR and fix
pnv_xive_get_indirect_tctx() to scan only the threads of the local
chip and not the whole machine.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191125065820.927-8-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/pnv_xive.c | 13 +++++++------
hw/ppc/pnv.c | 17 +++++++++++++++++
include/hw/ppc/pnv.h | 2 ++
3 files changed, 26 insertions(+), 6 deletions(-)
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index ec8349ee4a..b2ab2ccc91 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -1400,12 +1400,13 @@ static const MemoryRegionOps pnv_xive_ic_lsi_ops = {
*/
/*
- * When the TIMA is accessed from the indirect page, the thread id
- * (PIR) has to be configured in the IC registers before. This is used
- * for resets and for debug purpose also.
+ * When the TIMA is accessed from the indirect page, the thread id of
+ * the target CPU is configured in the PC_TCTXT_INDIR0 register before
+ * use. This is used for resets and for debug purpose also.
*/
static XiveTCTX *pnv_xive_get_indirect_tctx(PnvXive *xive)
{
+ PnvChip *chip = xive->chip;
uint64_t tctxt_indir = xive->regs[PC_TCTXT_INDIR0 >> 3];
PowerPCCPU *cpu = NULL;
int pir;
@@ -1415,15 +1416,15 @@ static XiveTCTX *pnv_xive_get_indirect_tctx(PnvXive *xive)
return NULL;
}
- pir = GETFIELD(PC_TCTXT_INDIR_THRDID, tctxt_indir) & 0xff;
- cpu = ppc_get_vcpu_by_pir(pir);
+ pir = (chip->chip_id << 8) | GETFIELD(PC_TCTXT_INDIR_THRDID, tctxt_indir);
+ cpu = pnv_chip_find_cpu(chip, pir);
if (!cpu) {
xive_error(xive, "IC: invalid PIR %x for indirect access", pir);
return NULL;
}
/* Check that HW thread is XIVE enabled */
- if (!(xive->regs[PC_THREAD_EN_REG0 >> 3] & PPC_BIT(pir & 0x3f))) {
+ if (!pnv_xive_is_cpu_enabled(xive, cpu)) {
xive_error(xive, "IC: CPU %x is not enabled", pir);
}
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index d899c83e52..8f688f4efc 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1371,6 +1371,23 @@ static void pnv_chip_class_init(ObjectClass *klass, void *data)
dc->desc = "PowerNV Chip";
}
+PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir)
+{
+ int i, j;
+
+ for (i = 0; i < chip->nr_cores; i++) {
+ PnvCore *pc = chip->cores[i];
+ CPUCore *cc = CPU_CORE(pc);
+
+ for (j = 0; j < cc->nr_threads; j++) {
+ if (ppc_cpu_pir(pc->threads[j]) == pir) {
+ return pc->threads[j];
+ }
+ }
+ }
+ return NULL;
+}
+
static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
{
PnvMachineState *pnv = PNV_MACHINE(xi);
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 12b0169a40..a58cfea3f2 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -162,6 +162,8 @@ typedef struct PnvChipClass {
#define PNV_CHIP_INDEX(chip) \
(((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3))
+PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
+
#define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
#define PNV_MACHINE(obj) \
OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE)
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 34/88] ppc/xive: Introduce a XiveFabric interface
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (32 preceding siblings ...)
2019-12-17 4:42 ` [PULL 33/88] ppc/pnv: Fix TIMA indirect access David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 35/88] ppc/pnv: Implement the " David Gibson
` (54 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
The XiveFabric QOM interface acts as the PowerBUS interface between
the interrupt controller and the system and should be implemented by
the QEMU machine. On HW, the XIVE sub-engine is responsible for the
communication with the other chip is the Common Queue (CQ) bridge
unit.
This interface offers a 'match_nvt' handler to perform the CAM line
matching when looking for a XIVE Presenter with a dispatched NVT.
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191125065820.927-9-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/xive.c | 10 ++++++++++
include/hw/ppc/xive.h | 22 ++++++++++++++++++++++
2 files changed, 32 insertions(+)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index da6196ca95..1c9e58f8de 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -1893,8 +1893,18 @@ static const TypeInfo xive_presenter_info = {
.class_size = sizeof(XivePresenterClass),
};
+/*
+ * XIVE Fabric
+ */
+static const TypeInfo xive_fabric_info = {
+ .name = TYPE_XIVE_FABRIC,
+ .parent = TYPE_INTERFACE,
+ .class_size = sizeof(XiveFabricClass),
+};
+
static void xive_register_types(void)
{
+ type_register_static(&xive_fabric_info);
type_register_static(&xive_source_info);
type_register_static(&xive_notifier_info);
type_register_static(&xive_presenter_info);
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index f9aa0fa0da..b00af98877 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -399,6 +399,28 @@ int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
uint8_t nvt_blk, uint32_t nvt_idx,
bool cam_ignore, uint32_t logic_serv);
+/*
+ * XIVE Fabric (Interface between Interrupt Controller and Machine)
+ */
+
+typedef struct XiveFabric XiveFabric;
+
+#define TYPE_XIVE_FABRIC "xive-fabric"
+#define XIVE_FABRIC(obj) \
+ INTERFACE_CHECK(XiveFabric, (obj), TYPE_XIVE_FABRIC)
+#define XIVE_FABRIC_CLASS(klass) \
+ OBJECT_CLASS_CHECK(XiveFabricClass, (klass), TYPE_XIVE_FABRIC)
+#define XIVE_FABRIC_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(XiveFabricClass, (obj), TYPE_XIVE_FABRIC)
+
+typedef struct XiveFabricClass {
+ InterfaceClass parent;
+ int (*match_nvt)(XiveFabric *xfb, uint8_t format,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ bool cam_ignore, uint8_t priority,
+ uint32_t logic_serv, XiveTCTXMatch *match);
+} XiveFabricClass;
+
/*
* XIVE END ESBs
*/
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 35/88] ppc/pnv: Implement the XiveFabric interface
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (33 preceding siblings ...)
2019-12-17 4:42 ` [PULL 34/88] ppc/xive: Introduce a XiveFabric interface David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 36/88] ppc/spapr: " David Gibson
` (53 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
The CAM line matching on the PowerNV machine now scans all chips of
the system and all CPUs of a chip to find a dispatched NVT in the
thread contexts.
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191125065820.927-10-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 8f688f4efc..5b8b07f6ae 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1443,6 +1443,35 @@ static void pnv_pic_print_info(InterruptStatsProvider *obj,
}
}
+static int pnv_match_nvt(XiveFabric *xfb, uint8_t format,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ bool cam_ignore, uint8_t priority,
+ uint32_t logic_serv,
+ XiveTCTXMatch *match)
+{
+ PnvMachineState *pnv = PNV_MACHINE(xfb);
+ int total_count = 0;
+ int i;
+
+ for (i = 0; i < pnv->num_chips; i++) {
+ Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]);
+ XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive);
+ XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
+ int count;
+
+ count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
+ priority, logic_serv, match);
+
+ if (count < 0) {
+ return count;
+ }
+
+ total_count += count;
+ }
+
+ return total_count;
+}
+
static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
@@ -1506,9 +1535,11 @@ static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
+ XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
+ xfc->match_nvt = pnv_match_nvt;
mc->alias = "powernv";
}
@@ -1555,6 +1586,10 @@ static const TypeInfo types[] = {
.name = MACHINE_TYPE_NAME("powernv9"),
.parent = TYPE_PNV_MACHINE,
.class_init = pnv_machine_power9_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { TYPE_XIVE_FABRIC },
+ { },
+ },
},
{
.name = MACHINE_TYPE_NAME("powernv8"),
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 36/88] ppc/spapr: Implement the XiveFabric interface
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (34 preceding siblings ...)
2019-12-17 4:42 ` [PULL 35/88] ppc/pnv: Implement the " David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 37/88] ppc/xive: Use the XiveFabric and XivePresenter interfaces David Gibson
` (52 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
The CAM line matching sequence in the pseries machine does not change
much apart from the use of the new QOM interfaces. There is an extra
indirection because of the sPAPR IRQ backend of the machine. Only the
XIVE backend implements the new 'match_nvt' handler.
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191125065820.927-11-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr.c | 39 +++++++++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 3ae7db1563..d9c9a2bcee 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -4275,6 +4275,42 @@ static void spapr_pic_print_info(InterruptStatsProvider *obj,
kvm_irqchip_in_kernel() ? "in-kernel" : "emulated");
}
+static int spapr_match_nvt(XiveFabric *xfb, uint8_t format,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ bool cam_ignore, uint8_t priority,
+ uint32_t logic_serv, XiveTCTXMatch *match)
+{
+ SpaprMachineState *spapr = SPAPR_MACHINE(xfb);
+ XivePresenter *xptr = XIVE_PRESENTER(spapr->xive);
+ XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
+ int count;
+
+ /* This is a XIVE only operation */
+ assert(spapr->active_intc == SPAPR_INTC(spapr->xive));
+
+ count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
+ priority, logic_serv, match);
+ if (count < 0) {
+ return count;
+ }
+
+ /*
+ * When we implement the save and restore of the thread interrupt
+ * contexts in the enter/exit CPU handlers of the machine and the
+ * escalations in QEMU, we should be able to handle non dispatched
+ * vCPUs.
+ *
+ * Until this is done, the sPAPR machine should find at least one
+ * matching context always.
+ */
+ if (count == 0) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n",
+ nvt_blk, nvt_idx);
+ }
+
+ return count;
+}
+
int spapr_get_vcpu_id(PowerPCCPU *cpu)
{
return cpu->vcpu_id;
@@ -4371,6 +4407,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
+ XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
mc->desc = "pSeries Logical Partition (PAPR compliant)";
mc->ignore_boot_device_suffixes = true;
@@ -4447,6 +4484,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
smc->linux_pci_probe = true;
smc->smp_threads_vsmt = true;
smc->nr_xirqs = SPAPR_NR_XIRQS;
+ xfc->match_nvt = spapr_match_nvt;
}
static const TypeInfo spapr_machine_info = {
@@ -4465,6 +4503,7 @@ static const TypeInfo spapr_machine_info = {
{ TYPE_PPC_VIRTUAL_HYPERVISOR },
{ TYPE_XICS_FABRIC },
{ TYPE_INTERRUPT_STATS_PROVIDER },
+ { TYPE_XIVE_FABRIC },
{ }
},
};
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 37/88] ppc/xive: Use the XiveFabric and XivePresenter interfaces
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (35 preceding siblings ...)
2019-12-17 4:42 ` [PULL 36/88] ppc/spapr: " David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 38/88] ppc/xive: Extend the TIMA operation with a XivePresenter parameter David Gibson
` (51 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
Now that the machines have handlers implementing the XiveFabric and
XivePresenter interfaces, remove xive_presenter_match() and make use
of the 'match_nvt' handler of the machine.
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191125065820.927-12-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/xive.c | 48 +++++++++++++++++-------------------------------
1 file changed, 17 insertions(+), 31 deletions(-)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 1c9e58f8de..8e683847bf 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -1423,30 +1423,6 @@ int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
return -1;
}
-static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format,
- uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint8_t priority,
- uint32_t logic_serv, XiveTCTXMatch *match)
-{
- XivePresenter *xptr = XIVE_PRESENTER(xrtr);
- XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
- int count;
-
- count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
- priority, logic_serv, match);
- if (count < 0) {
- return false;
- }
-
- if (!match->tctx) {
- qemu_log_mask(LOG_UNIMP, "XIVE: NVT %x/%x is not dispatched\n",
- nvt_blk, nvt_idx);
- return false;
- }
-
- return true;
-}
-
/*
* This is our simple Xive Presenter Engine model. It is merged in the
* Router as it does not require an extra object.
@@ -1462,22 +1438,32 @@ static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format,
*
* The parameters represent what is sent on the PowerBus
*/
-static bool xive_presenter_notify(XiveRouter *xrtr, uint8_t format,
+static bool xive_presenter_notify(uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
bool cam_ignore, uint8_t priority,
uint32_t logic_serv)
{
+ XiveFabric *xfb = XIVE_FABRIC(qdev_get_machine());
+ XiveFabricClass *xfc = XIVE_FABRIC_GET_CLASS(xfb);
XiveTCTXMatch match = { .tctx = NULL, .ring = 0 };
- bool found;
+ int count;
- found = xive_presenter_match(xrtr, format, nvt_blk, nvt_idx, cam_ignore,
- priority, logic_serv, &match);
- if (found) {
+ /*
+ * Ask the machine to scan the interrupt controllers for a match
+ */
+ count = xfc->match_nvt(xfb, format, nvt_blk, nvt_idx, cam_ignore,
+ priority, logic_serv, &match);
+ if (count < 0) {
+ return false;
+ }
+
+ /* handle CPU exception delivery */
+ if (count) {
ipb_update(&match.tctx->regs[match.ring], priority);
xive_tctx_notify(match.tctx, match.ring);
}
- return found;
+ return !!count;
}
/*
@@ -1590,7 +1576,7 @@ static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk,
return;
}
- found = xive_presenter_notify(xrtr, format, nvt_blk, nvt_idx,
+ found = xive_presenter_notify(format, nvt_blk, nvt_idx,
xive_get_field32(END_W7_F0_IGNORE, end.w7),
priority,
xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7));
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 38/88] ppc/xive: Extend the TIMA operation with a XivePresenter parameter
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (36 preceding siblings ...)
2019-12-17 4:42 ` [PULL 37/88] ppc/xive: Use the XiveFabric and XivePresenter interfaces David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 39/88] linux-headers: Update David Gibson
` (50 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
The TIMA operations are performed on behalf of the XIVE IVPE sub-engine
(Presenter) on the thread interrupt context registers. The current
operations supported by the model are simple and do not require access
to the controller but more complex operations will need access to the
controller NVT table and to its configuration.
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191125065820.927-13-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/pnv_xive.c | 4 +--
hw/intc/xive.c | 58 ++++++++++++++++++++++++-------------------
include/hw/ppc/xive.h | 7 +++---
3 files changed, 38 insertions(+), 31 deletions(-)
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index b2ab2ccc91..95e9de312c 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -1436,7 +1436,7 @@ static void xive_tm_indirect_write(void *opaque, hwaddr offset,
{
XiveTCTX *tctx = pnv_xive_get_indirect_tctx(PNV_XIVE(opaque));
- xive_tctx_tm_write(tctx, offset, value, size);
+ xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size);
}
static uint64_t xive_tm_indirect_read(void *opaque, hwaddr offset,
@@ -1444,7 +1444,7 @@ static uint64_t xive_tm_indirect_read(void *opaque, hwaddr offset,
{
XiveTCTX *tctx = pnv_xive_get_indirect_tctx(PNV_XIVE(opaque));
- return xive_tctx_tm_read(tctx, offset, size);
+ return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size);
}
static const MemoryRegionOps xive_tm_indirect_ops = {
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 8e683847bf..9e7e5ea57c 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -144,19 +144,20 @@ static inline uint32_t xive_tctx_word2(uint8_t *ring)
* XIVE Thread Interrupt Management Area (TIMA)
*/
-static void xive_tm_set_hv_cppr(XiveTCTX *tctx, hwaddr offset,
- uint64_t value, unsigned size)
+static void xive_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, uint64_t value, unsigned size)
{
xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff);
}
-static uint64_t xive_tm_ack_hv_reg(XiveTCTX *tctx, hwaddr offset, unsigned size)
+static uint64_t xive_tm_ack_hv_reg(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, unsigned size)
{
return xive_tctx_accept(tctx, TM_QW3_HV_PHYS);
}
-static uint64_t xive_tm_pull_pool_ctx(XiveTCTX *tctx, hwaddr offset,
- unsigned size)
+static uint64_t xive_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, unsigned size)
{
uint32_t qw2w2_prev = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]);
uint32_t qw2w2;
@@ -166,13 +167,14 @@ static uint64_t xive_tm_pull_pool_ctx(XiveTCTX *tctx, hwaddr offset,
return qw2w2;
}
-static void xive_tm_vt_push(XiveTCTX *tctx, hwaddr offset,
+static void xive_tm_vt_push(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
uint64_t value, unsigned size)
{
tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff;
}
-static uint64_t xive_tm_vt_poll(XiveTCTX *tctx, hwaddr offset, unsigned size)
+static uint64_t xive_tm_vt_poll(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, unsigned size)
{
return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff;
}
@@ -315,13 +317,14 @@ static uint64_t xive_tm_raw_read(XiveTCTX *tctx, hwaddr offset, unsigned size)
* state changes (side effects) in addition to setting/returning the
* interrupt management area context of the processor thread.
*/
-static uint64_t xive_tm_ack_os_reg(XiveTCTX *tctx, hwaddr offset, unsigned size)
+static uint64_t xive_tm_ack_os_reg(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, unsigned size)
{
return xive_tctx_accept(tctx, TM_QW1_OS);
}
-static void xive_tm_set_os_cppr(XiveTCTX *tctx, hwaddr offset,
- uint64_t value, unsigned size)
+static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, uint64_t value, unsigned size)
{
xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff);
}
@@ -330,8 +333,8 @@ static void xive_tm_set_os_cppr(XiveTCTX *tctx, hwaddr offset,
* Adjust the IPB to allow a CPU to process event queues of other
* priorities during one physical interrupt cycle.
*/
-static void xive_tm_set_os_pending(XiveTCTX *tctx, hwaddr offset,
- uint64_t value, unsigned size)
+static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, uint64_t value, unsigned size)
{
ipb_update(&tctx->regs[TM_QW1_OS], value & 0xff);
xive_tctx_notify(tctx, TM_QW1_OS);
@@ -366,8 +369,8 @@ static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t qw1w2)
memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
}
-static uint64_t xive_tm_pull_os_ctx(XiveTCTX *tctx, hwaddr offset,
- unsigned size)
+static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, unsigned size)
{
uint32_t qw1w2;
uint32_t qw1w2_new;
@@ -396,9 +399,11 @@ typedef struct XiveTmOp {
uint8_t page_offset;
uint32_t op_offset;
unsigned size;
- void (*write_handler)(XiveTCTX *tctx, hwaddr offset, uint64_t value,
- unsigned size);
- uint64_t (*read_handler)(XiveTCTX *tctx, hwaddr offset, unsigned size);
+ void (*write_handler)(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset,
+ uint64_t value, unsigned size);
+ uint64_t (*read_handler)(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
+ unsigned size);
} XiveTmOp;
static const XiveTmOp xive_tm_operations[] = {
@@ -444,8 +449,8 @@ static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool write)
/*
* TIMA MMIO handlers
*/
-void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value,
- unsigned size)
+void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
+ uint64_t value, unsigned size)
{
const XiveTmOp *xto;
@@ -462,7 +467,7 @@ void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value,
qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA "
"@%"HWADDR_PRIx"\n", offset);
} else {
- xto->write_handler(tctx, offset, value, size);
+ xto->write_handler(xptr, tctx, offset, value, size);
}
return;
}
@@ -472,7 +477,7 @@ void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value,
*/
xto = xive_tm_find_op(offset, size, true);
if (xto) {
- xto->write_handler(tctx, offset, value, size);
+ xto->write_handler(xptr, tctx, offset, value, size);
return;
}
@@ -482,7 +487,8 @@ void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value,
xive_tm_raw_write(tctx, offset, value, size);
}
-uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size)
+uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
+ unsigned size)
{
const XiveTmOp *xto;
@@ -500,7 +506,7 @@ uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size)
"@%"HWADDR_PRIx"\n", offset);
return -1;
}
- return xto->read_handler(tctx, offset, size);
+ return xto->read_handler(xptr, tctx, offset, size);
}
/*
@@ -508,7 +514,7 @@ uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size)
*/
xto = xive_tm_find_op(offset, size, false);
if (xto) {
- return xto->read_handler(tctx, offset, size);
+ return xto->read_handler(xptr, tctx, offset, size);
}
/*
@@ -522,14 +528,14 @@ static void xive_tm_write(void *opaque, hwaddr offset,
{
XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
- xive_tctx_tm_write(tctx, offset, value, size);
+ xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size);
}
static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size)
{
XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
- return xive_tctx_tm_read(tctx, offset, size);
+ return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size);
}
const MemoryRegionOps xive_tm_ops = {
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index b00af98877..97bbcddb38 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -463,9 +463,10 @@ typedef struct XiveENDSource {
#define XIVE_TM_USER_PAGE 0x3
extern const MemoryRegionOps xive_tm_ops;
-void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value,
- unsigned size);
-uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size);
+void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
+ uint64_t value, unsigned size);
+uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
+ unsigned size);
void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon);
Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp);
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 39/88] linux-headers: Update
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (37 preceding siblings ...)
2019-12-17 4:42 ` [PULL 38/88] ppc/xive: Extend the TIMA operation with a XivePresenter parameter David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 40/88] spapr: Pass the maximum number of vCPUs to the KVM interrupt controller David Gibson
` (49 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
Update to mainline commit be2eca94d144 ("Merge tag 'for-linus-5.5-1'`
of git://github.com/cminyard/linux-ipmi")
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157478677756.67101.11558821804418331832.stgit@bahia.tlslab.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
include/standard-headers/linux/ethtool.h | 6 ++++++
include/standard-headers/linux/virtio_ring.h | 2 +-
| 3 ++-
| 5 ++++-
| 1 +
| 1 +
| 1 +
| 3 +++
| 11 +++++++++++
| 3 +++
10 files changed, 33 insertions(+), 3 deletions(-)
diff --git a/include/standard-headers/linux/ethtool.h b/include/standard-headers/linux/ethtool.h
index 4ff422b635..6e8a10ee10 100644
--- a/include/standard-headers/linux/ethtool.h
+++ b/include/standard-headers/linux/ethtool.h
@@ -1507,6 +1507,11 @@ enum ethtool_link_mode_bit_indices {
ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT = 66,
ETHTOOL_LINK_MODE_100baseT1_Full_BIT = 67,
ETHTOOL_LINK_MODE_1000baseT1_Full_BIT = 68,
+ ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT = 69,
+ ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT = 70,
+ ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT = 71,
+ ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT = 72,
+ ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT = 73,
/* must be last entry */
__ETHTOOL_LINK_MODE_MASK_NBITS
@@ -1618,6 +1623,7 @@ enum ethtool_link_mode_bit_indices {
#define SPEED_56000 56000
#define SPEED_100000 100000
#define SPEED_200000 200000
+#define SPEED_400000 400000
#define SPEED_UNKNOWN -1
diff --git a/include/standard-headers/linux/virtio_ring.h b/include/standard-headers/linux/virtio_ring.h
index 306cd41147..f230fed479 100644
--- a/include/standard-headers/linux/virtio_ring.h
+++ b/include/standard-headers/linux/virtio_ring.h
@@ -167,7 +167,7 @@ static inline void vring_init(struct vring *vr, unsigned int num, void *p,
{
vr->num = num;
vr->desc = p;
- vr->avail = p + num*sizeof(struct vring_desc);
+ vr->avail = (struct vring_avail *)((char *)p + num * sizeof(struct vring_desc));
vr->used = (void *)(((uintptr_t)&vr->avail->ring[num] + sizeof(__virtio16)
+ align-1) & ~(align - 1));
}
--git a/linux-headers/asm-arm/kvm.h b/linux-headers/asm-arm/kvm.h
index 9d379d3372..0db5644e27 100644
--- a/linux-headers/asm-arm/kvm.h
+++ b/linux-headers/asm-arm/kvm.h
@@ -131,8 +131,9 @@ struct kvm_vcpu_events {
struct {
__u8 serror_pending;
__u8 serror_has_esr;
+ __u8 ext_dabt_pending;
/* Align it to 8 bytes */
- __u8 pad[6];
+ __u8 pad[5];
__u64 serror_esr;
} exception;
__u32 reserved[12];
--git a/linux-headers/asm-arm64/kvm.h b/linux-headers/asm-arm64/kvm.h
index 0ce6e49f3a..920af01c8b 100644
--- a/linux-headers/asm-arm64/kvm.h
+++ b/linux-headers/asm-arm64/kvm.h
@@ -164,8 +164,9 @@ struct kvm_vcpu_events {
struct {
__u8 serror_pending;
__u8 serror_has_esr;
+ __u8 ext_dabt_pending;
/* Align it to 8 bytes */
- __u8 pad[6];
+ __u8 pad[5];
__u64 serror_esr;
} exception;
__u32 reserved[12];
@@ -323,6 +324,8 @@ struct kvm_vcpu_events {
#define KVM_ARM_VCPU_TIMER_CTRL 1
#define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0
#define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1
+#define KVM_ARM_VCPU_PVTIME_CTRL 2
+#define KVM_ARM_VCPU_PVTIME_IPA 0
/* KVM_IRQ_LINE irq field index values */
#define KVM_ARM_IRQ_VCPU2_SHIFT 28
--git a/linux-headers/asm-mips/unistd_n32.h b/linux-headers/asm-mips/unistd_n32.h
index 7dffe8e34e..659d5c9ade 100644
--- a/linux-headers/asm-mips/unistd_n32.h
+++ b/linux-headers/asm-mips/unistd_n32.h
@@ -364,6 +364,7 @@
#define __NR_fsmount (__NR_Linux + 432)
#define __NR_fspick (__NR_Linux + 433)
#define __NR_pidfd_open (__NR_Linux + 434)
+#define __NR_clone3 (__NR_Linux + 435)
#endif /* _ASM_MIPS_UNISTD_N32_H */
--git a/linux-headers/asm-mips/unistd_n64.h b/linux-headers/asm-mips/unistd_n64.h
index f4592d6fc5..4b6310a05c 100644
--- a/linux-headers/asm-mips/unistd_n64.h
+++ b/linux-headers/asm-mips/unistd_n64.h
@@ -340,6 +340,7 @@
#define __NR_fsmount (__NR_Linux + 432)
#define __NR_fspick (__NR_Linux + 433)
#define __NR_pidfd_open (__NR_Linux + 434)
+#define __NR_clone3 (__NR_Linux + 435)
#endif /* _ASM_MIPS_UNISTD_N64_H */
--git a/linux-headers/asm-mips/unistd_o32.h b/linux-headers/asm-mips/unistd_o32.h
index 04c6728352..4ce7b4e288 100644
--- a/linux-headers/asm-mips/unistd_o32.h
+++ b/linux-headers/asm-mips/unistd_o32.h
@@ -410,6 +410,7 @@
#define __NR_fsmount (__NR_Linux + 432)
#define __NR_fspick (__NR_Linux + 433)
#define __NR_pidfd_open (__NR_Linux + 434)
+#define __NR_clone3 (__NR_Linux + 435)
#endif /* _ASM_MIPS_UNISTD_O32_H */
--git a/linux-headers/asm-powerpc/kvm.h b/linux-headers/asm-powerpc/kvm.h
index b0f72dea8b..264e266a85 100644
--- a/linux-headers/asm-powerpc/kvm.h
+++ b/linux-headers/asm-powerpc/kvm.h
@@ -667,6 +667,8 @@ struct kvm_ppc_cpu_char {
/* PPC64 eXternal Interrupt Controller Specification */
#define KVM_DEV_XICS_GRP_SOURCES 1 /* 64-bit source attributes */
+#define KVM_DEV_XICS_GRP_CTRL 2
+#define KVM_DEV_XICS_NR_SERVERS 1
/* Layout of 64-bit source attribute values */
#define KVM_XICS_DESTINATION_SHIFT 0
@@ -683,6 +685,7 @@ struct kvm_ppc_cpu_char {
#define KVM_DEV_XIVE_GRP_CTRL 1
#define KVM_DEV_XIVE_RESET 1
#define KVM_DEV_XIVE_EQ_SYNC 2
+#define KVM_DEV_XIVE_NR_SERVERS 3
#define KVM_DEV_XIVE_GRP_SOURCE 2 /* 64-bit source identifier */
#define KVM_DEV_XIVE_GRP_SOURCE_CONFIG 3 /* 64-bit source identifier */
#define KVM_DEV_XIVE_GRP_EQ_CONFIG 4 /* 64-bit EQ identifier */
--git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index 3d9b18f7f8..3b27a1ae85 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -235,6 +235,7 @@ struct kvm_hyperv_exit {
#define KVM_EXIT_S390_STSI 25
#define KVM_EXIT_IOAPIC_EOI 26
#define KVM_EXIT_HYPERV 27
+#define KVM_EXIT_ARM_NISV 28
/* For KVM_EXIT_INTERNAL_ERROR */
/* Emulate instruction failed. */
@@ -394,6 +395,11 @@ struct kvm_run {
} eoi;
/* KVM_EXIT_HYPERV */
struct kvm_hyperv_exit hyperv;
+ /* KVM_EXIT_ARM_NISV */
+ struct {
+ __u64 esr_iss;
+ __u64 fault_ipa;
+ } arm_nisv;
/* Fix the size of the union. */
char padding[256];
};
@@ -1000,6 +1006,9 @@ struct kvm_ppc_resize_hpt {
#define KVM_CAP_PMU_EVENT_FILTER 173
#define KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 174
#define KVM_CAP_HYPERV_DIRECT_TLBFLUSH 175
+#define KVM_CAP_PPC_GUEST_DEBUG_SSTEP 176
+#define KVM_CAP_ARM_NISV_TO_USER 177
+#define KVM_CAP_ARM_INJECT_EXT_DABT 178
#ifdef KVM_CAP_IRQ_ROUTING
@@ -1227,6 +1236,8 @@ enum kvm_device_type {
#define KVM_DEV_TYPE_ARM_VGIC_ITS KVM_DEV_TYPE_ARM_VGIC_ITS
KVM_DEV_TYPE_XIVE,
#define KVM_DEV_TYPE_XIVE KVM_DEV_TYPE_XIVE
+ KVM_DEV_TYPE_ARM_PV_TIME,
+#define KVM_DEV_TYPE_ARM_PV_TIME KVM_DEV_TYPE_ARM_PV_TIME
KVM_DEV_TYPE_MAX,
};
--git a/linux-headers/linux/psp-sev.h b/linux-headers/linux/psp-sev.h
index 34c39690c0..31f971e896 100644
--- a/linux-headers/linux/psp-sev.h
+++ b/linux-headers/linux/psp-sev.h
@@ -58,6 +58,9 @@ typedef enum {
SEV_RET_HWSEV_RET_PLATFORM,
SEV_RET_HWSEV_RET_UNSAFE,
SEV_RET_UNSUPPORTED,
+ SEV_RET_INVALID_PARAM,
+ SEV_RET_RESOURCE_LIMIT,
+ SEV_RET_SECURE_DATA_INVALID,
SEV_RET_MAX,
} sev_ret_code;
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 40/88] spapr: Pass the maximum number of vCPUs to the KVM interrupt controller
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (38 preceding siblings ...)
2019-12-17 4:42 ` [PULL 39/88] linux-headers: Update David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 41/88] spapr/xics: Configure number of servers in KVM David Gibson
` (48 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
The XIVE and XICS-on-XIVE KVM devices on POWER9 hosts can greatly reduce
their consumption of some scarce HW resources, namely Virtual Presenter
identifiers, if they know the maximum number of vCPUs that may run in the
VM.
Prepare ground for this by passing the value down to xics_kvm_connect()
and kvmppc_xive_connect(). This is purely mechanical, no functional
change.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157478678301.67101.2717368060417156338.stgit@bahia.tlslab.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/spapr_xive.c | 6 ++++--
hw/intc/spapr_xive_kvm.c | 3 ++-
hw/intc/xics_kvm.c | 3 ++-
hw/intc/xics_spapr.c | 5 +++--
hw/ppc/spapr_irq.c | 8 +++++---
include/hw/ppc/spapr_irq.h | 10 ++++++++--
include/hw/ppc/spapr_xive.h | 3 ++-
include/hw/ppc/xics_spapr.h | 3 ++-
8 files changed, 28 insertions(+), 13 deletions(-)
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index bb3b2dfdb7..18a043a277 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -697,12 +697,14 @@ static void spapr_xive_dt(SpaprInterruptController *intc, uint32_t nr_servers,
plat_res_int_priorities, sizeof(plat_res_int_priorities)));
}
-static int spapr_xive_activate(SpaprInterruptController *intc, Error **errp)
+static int spapr_xive_activate(SpaprInterruptController *intc,
+ uint32_t nr_servers, Error **errp)
{
SpaprXive *xive = SPAPR_XIVE(intc);
if (kvm_enabled()) {
- int rc = spapr_irq_init_kvm(kvmppc_xive_connect, intc, errp);
+ int rc = spapr_irq_init_kvm(kvmppc_xive_connect, intc, nr_servers,
+ errp);
if (rc < 0) {
return rc;
}
diff --git a/hw/intc/spapr_xive_kvm.c b/hw/intc/spapr_xive_kvm.c
index 69e73552f1..46c7609bd8 100644
--- a/hw/intc/spapr_xive_kvm.c
+++ b/hw/intc/spapr_xive_kvm.c
@@ -728,7 +728,8 @@ static void *kvmppc_xive_mmap(SpaprXive *xive, int pgoff, size_t len,
* All the XIVE memory regions are now backed by mappings from the KVM
* XIVE device.
*/
-int kvmppc_xive_connect(SpaprInterruptController *intc, Error **errp)
+int kvmppc_xive_connect(SpaprInterruptController *intc, uint32_t nr_servers,
+ Error **errp)
{
SpaprXive *xive = SPAPR_XIVE(intc);
XiveSource *xsrc = &xive->source;
diff --git a/hw/intc/xics_kvm.c b/hw/intc/xics_kvm.c
index 954c424b36..a1f1b7b0d3 100644
--- a/hw/intc/xics_kvm.c
+++ b/hw/intc/xics_kvm.c
@@ -342,7 +342,8 @@ void ics_kvm_set_irq(ICSState *ics, int srcno, int val)
}
}
-int xics_kvm_connect(SpaprInterruptController *intc, Error **errp)
+int xics_kvm_connect(SpaprInterruptController *intc, uint32_t nr_servers,
+ Error **errp)
{
ICSState *ics = ICS_SPAPR(intc);
int rc;
diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c
index b3705dab0e..8ae4f41459 100644
--- a/hw/intc/xics_spapr.c
+++ b/hw/intc/xics_spapr.c
@@ -422,10 +422,11 @@ static int xics_spapr_post_load(SpaprInterruptController *intc, int version_id)
return 0;
}
-static int xics_spapr_activate(SpaprInterruptController *intc, Error **errp)
+static int xics_spapr_activate(SpaprInterruptController *intc,
+ uint32_t nr_servers, Error **errp)
{
if (kvm_enabled()) {
- return spapr_irq_init_kvm(xics_kvm_connect, intc, errp);
+ return spapr_irq_init_kvm(xics_kvm_connect, intc, nr_servers, errp);
}
return 0;
}
diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c
index d4a54afc86..07e08d6544 100644
--- a/hw/ppc/spapr_irq.c
+++ b/hw/ppc/spapr_irq.c
@@ -70,15 +70,16 @@ void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num)
bitmap_clear(spapr->irq_map, irq - SPAPR_IRQ_MSI, num);
}
-int spapr_irq_init_kvm(int (*fn)(SpaprInterruptController *, Error **),
+int spapr_irq_init_kvm(SpaprInterruptControllerInitKvm fn,
SpaprInterruptController *intc,
+ uint32_t nr_servers,
Error **errp)
{
MachineState *machine = MACHINE(qdev_get_machine());
Error *local_err = NULL;
if (kvm_enabled() && machine_kernel_irqchip_allowed(machine)) {
- if (fn(intc, &local_err) < 0) {
+ if (fn(intc, nr_servers, &local_err) < 0) {
if (machine_kernel_irqchip_required(machine)) {
error_prepend(&local_err,
"kernel_irqchip requested but unavailable: ");
@@ -481,6 +482,7 @@ static void set_active_intc(SpaprMachineState *spapr,
SpaprInterruptController *new_intc)
{
SpaprInterruptControllerClass *sicc;
+ uint32_t nr_servers = spapr_max_server_number(spapr);
assert(new_intc);
@@ -498,7 +500,7 @@ static void set_active_intc(SpaprMachineState *spapr,
sicc = SPAPR_INTC_GET_CLASS(new_intc);
if (sicc->activate) {
- sicc->activate(new_intc, &error_fatal);
+ sicc->activate(new_intc, nr_servers, &error_fatal);
}
spapr->active_intc = new_intc;
diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h
index ff814d13de..ca8cb44213 100644
--- a/include/hw/ppc/spapr_irq.h
+++ b/include/hw/ppc/spapr_irq.h
@@ -43,7 +43,8 @@ typedef struct SpaprInterruptController SpaprInterruptController;
typedef struct SpaprInterruptControllerClass {
InterfaceClass parent;
- int (*activate)(SpaprInterruptController *intc, Error **errp);
+ int (*activate)(SpaprInterruptController *intc, uint32_t nr_servers,
+ Error **errp);
void (*deactivate)(SpaprInterruptController *intc);
/*
@@ -98,8 +99,13 @@ qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq);
int spapr_irq_post_load(SpaprMachineState *spapr, int version_id);
void spapr_irq_reset(SpaprMachineState *spapr, Error **errp);
int spapr_irq_get_phandle(SpaprMachineState *spapr, void *fdt, Error **errp);
-int spapr_irq_init_kvm(int (*fn)(SpaprInterruptController *, Error **),
+
+typedef int (*SpaprInterruptControllerInitKvm)(SpaprInterruptController *,
+ uint32_t, Error **);
+
+int spapr_irq_init_kvm(SpaprInterruptControllerInitKvm fn,
SpaprInterruptController *intc,
+ uint32_t nr_servers,
Error **errp);
/*
diff --git a/include/hw/ppc/spapr_xive.h b/include/hw/ppc/spapr_xive.h
index 742b7e834f..3a103c224d 100644
--- a/include/hw/ppc/spapr_xive.h
+++ b/include/hw/ppc/spapr_xive.h
@@ -66,7 +66,8 @@ int spapr_xive_end_to_target(uint8_t end_blk, uint32_t end_idx,
/*
* KVM XIVE device helpers
*/
-int kvmppc_xive_connect(SpaprInterruptController *intc, Error **errp);
+int kvmppc_xive_connect(SpaprInterruptController *intc, uint32_t nr_servers,
+ Error **errp);
void kvmppc_xive_disconnect(SpaprInterruptController *intc);
void kvmppc_xive_reset(SpaprXive *xive, Error **errp);
void kvmppc_xive_set_source_config(SpaprXive *xive, uint32_t lisn, XiveEAS *eas,
diff --git a/include/hw/ppc/xics_spapr.h b/include/hw/ppc/xics_spapr.h
index 28b87038c8..1c65c96e3c 100644
--- a/include/hw/ppc/xics_spapr.h
+++ b/include/hw/ppc/xics_spapr.h
@@ -32,7 +32,8 @@
#define TYPE_ICS_SPAPR "ics-spapr"
#define ICS_SPAPR(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_SPAPR)
-int xics_kvm_connect(SpaprInterruptController *intc, Error **errp);
+int xics_kvm_connect(SpaprInterruptController *intc, uint32_t nr_servers,
+ Error **errp);
void xics_kvm_disconnect(SpaprInterruptController *intc);
bool xics_kvm_has_broken_disconnect(SpaprMachineState *spapr);
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 41/88] spapr/xics: Configure number of servers in KVM
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (39 preceding siblings ...)
2019-12-17 4:42 ` [PULL 40/88] spapr: Pass the maximum number of vCPUs to the KVM interrupt controller David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 42/88] spapr/xive: " David Gibson
` (47 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
The XICS-on-XIVE KVM devices now has an attribute to configure the number
of interrupt servers. This allows to greatly optimize the usage of the VP
space in the XIVE HW, and thus to start a lot more VMs.
Only set this attribute if available in order to support older POWER9 KVM
and pre-POWER9 XICS KVM devices.
The XICS-on-XIVE KVM device now reports the exhaustion of VPs upon the
connection of the first VCPU. Check that in order to have a chance to
provide a hint to the user.
`
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157478678846.67101.9660531022460517710.stgit@bahia.tlslab.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/xics_kvm.c | 21 +++++++++++++++++++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/hw/intc/xics_kvm.c b/hw/intc/xics_kvm.c
index a1f1b7b0d3..8d6156578f 100644
--- a/hw/intc/xics_kvm.c
+++ b/hw/intc/xics_kvm.c
@@ -165,8 +165,15 @@ void icp_kvm_realize(DeviceState *dev, Error **errp)
ret = kvm_vcpu_enable_cap(cs, KVM_CAP_IRQ_XICS, 0, kernel_xics_fd, vcpu_id);
if (ret < 0) {
- error_setg(errp, "Unable to connect CPU%ld to kernel XICS: %s", vcpu_id,
- strerror(errno));
+ Error *local_err = NULL;
+
+ error_setg(&local_err, "Unable to connect CPU%ld to kernel XICS: %s",
+ vcpu_id, strerror(errno));
+ if (errno == ENOSPC) {
+ error_append_hint(&local_err, "Try -smp maxcpus=N with N < %u\n",
+ MACHINE(qdev_get_machine())->smp.max_cpus);
+ }
+ error_propagate(errp, local_err);
return;
}
enabled_icp = g_malloc(sizeof(*enabled_icp));
@@ -399,6 +406,16 @@ int xics_kvm_connect(SpaprInterruptController *intc, uint32_t nr_servers,
goto fail;
}
+ /* Tell KVM about the # of VCPUs we may have (POWER9 and newer only) */
+ if (kvm_device_check_attr(rc, KVM_DEV_XICS_GRP_CTRL,
+ KVM_DEV_XICS_NR_SERVERS)) {
+ if (kvm_device_access(rc, KVM_DEV_XICS_GRP_CTRL,
+ KVM_DEV_XICS_NR_SERVERS, &nr_servers, true,
+ &local_err)) {
+ goto fail;
+ }
+ }
+
kernel_xics_fd = rc;
kvm_kernel_irqchip = true;
kvm_msi_via_irqfd_allowed = true;
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 42/88] spapr/xive: Configure number of servers in KVM
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (40 preceding siblings ...)
2019-12-17 4:42 ` [PULL 41/88] spapr/xics: Configure number of servers in KVM David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 43/88] ppc/pnv: Clarify how the TIMA is accessed on a multichip system David Gibson
` (46 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
The XIVE KVM devices now has an attribute to configure the number of
interrupt servers. This allows to greatly optimize the usage of the VP
space in the XIVE HW, and thus to start a lot more VMs.
Only set this attribute if available in order to support older POWER9
KVM.
The XIVE KVM device now reports the exhaustion of VPs upon the
connection of the first VCPU. Check that in order to have a chance
to provide a hint to the user.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157478679392.67101.7843580591407950866.stgit@bahia.tlslab.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/spapr_xive_kvm.c | 23 +++++++++++++++++++++--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/hw/intc/spapr_xive_kvm.c b/hw/intc/spapr_xive_kvm.c
index 46c7609bd8..32b2809210 100644
--- a/hw/intc/spapr_xive_kvm.c
+++ b/hw/intc/spapr_xive_kvm.c
@@ -152,7 +152,8 @@ void kvmppc_xive_cpu_synchronize_state(XiveTCTX *tctx, Error **errp)
void kvmppc_xive_cpu_connect(XiveTCTX *tctx, Error **errp)
{
- SpaprXive *xive = SPAPR_MACHINE(qdev_get_machine())->xive;
+ MachineState *ms = MACHINE(qdev_get_machine());
+ SpaprXive *xive = SPAPR_MACHINE(ms)->xive;
unsigned long vcpu_id;
int ret;
@@ -171,8 +172,16 @@ void kvmppc_xive_cpu_connect(XiveTCTX *tctx, Error **errp)
ret = kvm_vcpu_enable_cap(tctx->cs, KVM_CAP_PPC_IRQ_XIVE, 0, xive->fd,
vcpu_id, 0);
if (ret < 0) {
- error_setg(errp, "XIVE: unable to connect CPU%ld to KVM device: %s",
+ Error *local_err = NULL;
+
+ error_setg(&local_err,
+ "XIVE: unable to connect CPU%ld to KVM device: %s",
vcpu_id, strerror(errno));
+ if (errno == ENOSPC) {
+ error_append_hint(&local_err, "Try -smp maxcpus=N with N < %u\n",
+ ms->smp.max_cpus);
+ }
+ error_propagate(errp, local_err);
return;
}
@@ -758,6 +767,16 @@ int kvmppc_xive_connect(SpaprInterruptController *intc, uint32_t nr_servers,
return -1;
}
+ /* Tell KVM about the # of VCPUs we may have */
+ if (kvm_device_check_attr(xive->fd, KVM_DEV_XIVE_GRP_CTRL,
+ KVM_DEV_XIVE_NR_SERVERS)) {
+ if (kvm_device_access(xive->fd, KVM_DEV_XIVE_GRP_CTRL,
+ KVM_DEV_XIVE_NR_SERVERS, &nr_servers, true,
+ &local_err)) {
+ goto fail;
+ }
+ }
+
/*
* 1. Source ESB pages - KVM mapping
*/
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 43/88] ppc/pnv: Clarify how the TIMA is accessed on a multichip system
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (41 preceding siblings ...)
2019-12-17 4:42 ` [PULL 42/88] spapr/xive: " David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 44/88] ppc/xive: Move the TIMA operations to the controller model David Gibson
` (45 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
The TIMA region gives access to the thread interrupt context registers
of a CPU. It is mapped at the same address on all chips and can be
accessed by any CPU of the system. To identify the chip from which the
access is being done, the PowerBUS uses a 'chip' field in the
load/store messages. QEMU does not model these messages, instead, we
extract the chip id from the CPU PIR and do a lookup at the machine
level to fetch the targeted interrupt controller.
Introduce pnv_get_chip() and pnv_xive_tm_get_xive() helpers to clarify
this process in pnv_xive_get_tctx(). The latter will be removed in the
subsequent patches but the same principle will be kept.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191125065820.927-14-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/pnv_xive.c | 40 +++++++++++++++++++++++-----------------
hw/ppc/pnv.c | 14 ++++++++++++++
include/hw/ppc/pnv.h | 3 +++
3 files changed, 40 insertions(+), 17 deletions(-)
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index 95e9de312c..db9d9c11a8 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -439,31 +439,37 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
return count;
}
+/*
+ * The TIMA MMIO space is shared among the chips and to identify the
+ * chip from which the access is being done, we extract the chip id
+ * from the PIR.
+ */
+static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu)
+{
+ int pir = ppc_cpu_pir(cpu);
+ PnvChip *chip;
+ PnvXive *xive;
+
+ chip = pnv_get_chip(PNV9_PIR2CHIP(pir));
+ assert(chip);
+ xive = &PNV9_CHIP(chip)->xive;
+
+ if (!pnv_xive_is_cpu_enabled(xive, cpu)) {
+ xive_error(xive, "IC: CPU %x is not enabled", pir);
+ }
+ return xive;
+}
+
static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
- XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
- PnvXive *xive = NULL;
- CPUPPCState *env = &cpu->env;
- int pir = env->spr_cb[SPR_PIR].default_value;
+ PnvXive *xive = pnv_xive_tm_get_xive(cpu);
- /*
- * Perform an extra check on the HW thread enablement.
- *
- * The TIMA is shared among the chips and to identify the chip
- * from which the access is being done, we extract the chip id
- * from the PIR.
- */
- xive = pnv_xive_get_ic((pir >> 8) & 0xf);
if (!xive) {
return NULL;
}
- if (!(xive->regs[PC_THREAD_EN_REG0 >> 3] & PPC_BIT(pir & 0x3f))) {
- xive_error(PNV_XIVE(xrtr), "IC: CPU %x is not enabled", pir);
- }
-
- return tctx;
+ return XIVE_TCTX(pnv_cpu_state(cpu)->intc);
}
/*
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 5b8b07f6ae..fa656858b2 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1472,6 +1472,20 @@ static int pnv_match_nvt(XiveFabric *xfb, uint8_t format,
return total_count;
}
+PnvChip *pnv_get_chip(uint32_t chip_id)
+{
+ PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
+ int i;
+
+ for (i = 0; i < pnv->num_chips; i++) {
+ PnvChip *chip = pnv->chips[i];
+ if (chip->chip_id == chip_id) {
+ return chip;
+ }
+ }
+ return NULL;
+}
+
static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index a58cfea3f2..3a7bc3c57e 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -103,6 +103,7 @@ typedef struct Pnv9Chip {
* A SMT8 fused core is a pair of SMT4 cores.
*/
#define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
+#define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
typedef struct PnvChipClass {
/*< private >*/
@@ -197,6 +198,8 @@ static inline bool pnv_is_power9(PnvMachineState *pnv)
return pnv_chip_is_power9(pnv->chips[0]);
}
+PnvChip *pnv_get_chip(uint32_t chip_id);
+
#define PNV_FDT_ADDR 0x01000000
#define PNV_TIMEBASE_FREQ 512000000ULL
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 44/88] ppc/xive: Move the TIMA operations to the controller model
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (42 preceding siblings ...)
2019-12-17 4:42 ` [PULL 43/88] ppc/pnv: Clarify how the TIMA is accessed on a multichip system David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 45/88] ppc/xive: Remove the get_tctx() XiveRouter handler David Gibson
` (44 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
On the P9 Processor, the thread interrupt context registers of a CPU
can be accessed "directly" when by load/store from the CPU or
"indirectly" by the IC through an indirect TIMA page. This requires to
configure first the PC_TCTXT_INDIRx registers.
Today, we rely on the get_tctx() handler to deduce from the CPU PIR
the chip from which the TIMA access is being done. By handling the
TIMA memory ops under the interrupt controller model of each machine,
we can uniformize the TIMA direct and indirect ops under PowerNV. We
can also check that the CPUs have been enabled in the XIVE controller.
This prepares ground for the future versions of XIVE.
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191125065820.927-15-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/pnv_xive.c | 35 ++++++++++++++++++++++++++++++++++-
hw/intc/spapr_xive.c | 33 +++++++++++++++++++++++++++++++--
hw/intc/xive.c | 29 -----------------------------
include/hw/ppc/xive.h | 1 -
4 files changed, 65 insertions(+), 33 deletions(-)
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index db9d9c11a8..c14a2d1869 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -1467,6 +1467,39 @@ static const MemoryRegionOps xive_tm_indirect_ops = {
},
};
+static void pnv_xive_tm_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
+ PnvXive *xive = pnv_xive_tm_get_xive(cpu);
+ XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
+
+ xive_tctx_tm_write(XIVE_PRESENTER(xive), tctx, offset, value, size);
+}
+
+static uint64_t pnv_xive_tm_read(void *opaque, hwaddr offset, unsigned size)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
+ PnvXive *xive = pnv_xive_tm_get_xive(cpu);
+ XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
+
+ return xive_tctx_tm_read(XIVE_PRESENTER(xive), tctx, offset, size);
+}
+
+const MemoryRegionOps pnv_xive_tm_ops = {
+ .read = pnv_xive_tm_read,
+ .write = pnv_xive_tm_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 8,
+ },
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 8,
+ },
+};
+
/*
* Interrupt controller XSCOM region.
*/
@@ -1809,7 +1842,7 @@ static void pnv_xive_realize(DeviceState *dev, Error **errp)
"xive-pc", PNV9_XIVE_PC_SIZE);
/* Thread Interrupt Management Area (Direct) */
- memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops,
+ memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &pnv_xive_tm_ops,
xive, "xive-tima", PNV9_XIVE_TM_SIZE);
qemu_register_reset(pnv_xive_reset, dev);
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index 18a043a277..40891543e0 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -205,6 +205,35 @@ void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable)
memory_region_set_enabled(&xive->end_source.esb_mmio, false);
}
+static void spapr_xive_tm_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ XiveTCTX *tctx = spapr_cpu_state(POWERPC_CPU(current_cpu))->tctx;
+
+ xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size);
+}
+
+static uint64_t spapr_xive_tm_read(void *opaque, hwaddr offset, unsigned size)
+{
+ XiveTCTX *tctx = spapr_cpu_state(POWERPC_CPU(current_cpu))->tctx;
+
+ return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size);
+}
+
+const MemoryRegionOps spapr_xive_tm_ops = {
+ .read = spapr_xive_tm_read,
+ .write = spapr_xive_tm_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 8,
+ },
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 8,
+ },
+};
+
static void spapr_xive_end_reset(XiveEND *end)
{
memset(end, 0, sizeof(*end));
@@ -314,8 +343,8 @@ static void spapr_xive_realize(DeviceState *dev, Error **errp)
qemu_register_reset(spapr_xive_reset, dev);
/* TIMA initialization */
- memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, xive,
- "xive.tima", 4ull << TM_SHIFT);
+ memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &spapr_xive_tm_ops,
+ xive, "xive.tima", 4ull << TM_SHIFT);
sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio);
/*
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 9e7e5ea57c..0ca7099f4e 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -523,35 +523,6 @@ uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
return xive_tm_raw_read(tctx, offset, size);
}
-static void xive_tm_write(void *opaque, hwaddr offset,
- uint64_t value, unsigned size)
-{
- XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
-
- xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size);
-}
-
-static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size)
-{
- XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
-
- return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size);
-}
-
-const MemoryRegionOps xive_tm_ops = {
- .read = xive_tm_read,
- .write = xive_tm_write,
- .endianness = DEVICE_BIG_ENDIAN,
- .valid = {
- .min_access_size = 1,
- .max_access_size = 8,
- },
- .impl = {
- .min_access_size = 1,
- .max_access_size = 8,
- },
-};
-
static char *xive_tctx_ring_print(uint8_t *ring)
{
uint32_t w2 = xive_tctx_word2(ring);
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index 97bbcddb38..dcf8974515 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -462,7 +462,6 @@ typedef struct XiveENDSource {
#define XIVE_TM_OS_PAGE 0x2
#define XIVE_TM_USER_PAGE 0x3
-extern const MemoryRegionOps xive_tm_ops;
void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
uint64_t value, unsigned size);
uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 45/88] ppc/xive: Remove the get_tctx() XiveRouter handler
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (43 preceding siblings ...)
2019-12-17 4:42 ` [PULL 44/88] ppc/xive: Move the TIMA operations to the controller model David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 46/88] ppc/xive: Introduce a xive_tctx_ipb_update() helper David Gibson
` (43 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
It is now unused.
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191125065820.927-16-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/pnv_xive.c | 13 -------------
hw/intc/spapr_xive.c | 8 --------
hw/intc/xive.c | 7 -------
include/hw/ppc/xive.h | 2 --
4 files changed, 30 deletions(-)
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index c14a2d1869..216ebc150a 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -460,18 +460,6 @@ static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu)
return xive;
}
-static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
-{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- PnvXive *xive = pnv_xive_tm_get_xive(cpu);
-
- if (!xive) {
- return NULL;
- }
-
- return XIVE_TCTX(pnv_cpu_state(cpu)->intc);
-}
-
/*
* The internal sources (IPIs) of the interrupt controller have no
* knowledge of the XIVE chip on which they reside. Encode the block
@@ -1900,7 +1888,6 @@ static void pnv_xive_class_init(ObjectClass *klass, void *data)
xrc->write_end = pnv_xive_write_end;
xrc->get_nvt = pnv_xive_get_nvt;
xrc->write_nvt = pnv_xive_write_nvt;
- xrc->get_tctx = pnv_xive_get_tctx;
xnc->notify = pnv_xive_notify;
xpc->match_nvt = pnv_xive_match_nvt;
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index 40891543e0..b785066da5 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -427,13 +427,6 @@ static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk,
g_assert_not_reached();
}
-static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
-{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
-
- return spapr_cpu_state(cpu)->tctx;
-}
-
static int spapr_xive_match_nvt(XivePresenter *xptr, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
bool cam_ignore, uint8_t priority,
@@ -773,7 +766,6 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data)
xrc->write_end = spapr_xive_write_end;
xrc->get_nvt = spapr_xive_get_nvt;
xrc->write_nvt = spapr_xive_write_nvt;
- xrc->get_tctx = spapr_xive_get_tctx;
sicc->activate = spapr_xive_activate;
sicc->deactivate = spapr_xive_deactivate;
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 0ca7099f4e..4bff3abdc3 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -1317,13 +1317,6 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number);
}
-XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs)
-{
- XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr);
-
- return xrc->get_tctx(xrtr, cs);
-}
-
/*
* Encode the HW CAM line in the block group mode format :
*
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index dcf8974515..24315480e7 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -351,7 +351,6 @@ typedef struct XiveRouterClass {
XiveNVT *nvt);
int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
XiveNVT *nvt, uint8_t word_number);
- XiveTCTX *(*get_tctx)(XiveRouter *xrtr, CPUState *cs);
} XiveRouterClass;
int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
@@ -364,7 +363,6 @@ int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
XiveNVT *nvt);
int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
XiveNVT *nvt, uint8_t word_number);
-XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs);
void xive_router_notify(XiveNotifier *xn, uint32_t lisn);
/*
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 46/88] ppc/xive: Introduce a xive_tctx_ipb_update() helper
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (44 preceding siblings ...)
2019-12-17 4:42 ` [PULL 45/88] ppc/xive: Remove the get_tctx() XiveRouter handler David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 47/88] ppc/xive: Synthesize interrupt from the saved IPB in the NVT David Gibson
` (42 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
We will use it to resend missed interrupts when a vCPU context is
pushed on a HW thread.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191125065820.927-17-clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/xive.c | 21 +++++++++++----------
include/hw/ppc/xive.h | 1 +
2 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 4bff3abdc3..7047e45dac 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -47,12 +47,6 @@ static uint8_t ipb_to_pipr(uint8_t ibp)
return ibp ? clz32((uint32_t)ibp << 24) : 0xff;
}
-static void ipb_update(uint8_t *regs, uint8_t priority)
-{
- regs[TM_IPB] |= priority_to_ipb(priority);
- regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]);
-}
-
static uint8_t exception_mask(uint8_t ring)
{
switch (ring) {
@@ -135,6 +129,15 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr)
xive_tctx_notify(tctx, ring);
}
+void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb)
+{
+ uint8_t *regs = &tctx->regs[ring];
+
+ regs[TM_IPB] |= ipb;
+ regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]);
+ xive_tctx_notify(tctx, ring);
+}
+
static inline uint32_t xive_tctx_word2(uint8_t *ring)
{
return *((uint32_t *) &ring[TM_WORD2]);
@@ -336,8 +339,7 @@ static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx,
static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx,
hwaddr offset, uint64_t value, unsigned size)
{
- ipb_update(&tctx->regs[TM_QW1_OS], value & 0xff);
- xive_tctx_notify(tctx, TM_QW1_OS);
+ xive_tctx_ipb_update(tctx, TM_QW1_OS, priority_to_ipb(value & 0xff));
}
static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk,
@@ -1429,8 +1431,7 @@ static bool xive_presenter_notify(uint8_t format,
/* handle CPU exception delivery */
if (count) {
- ipb_update(&match.tctx->regs[match.ring], priority);
- xive_tctx_notify(match.tctx, match.ring);
+ xive_tctx_ipb_update(match.tctx, match.ring, priority_to_ipb(priority));
}
return !!count;
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index 24315480e7..9c0bf2c301 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -469,6 +469,7 @@ void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon);
Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp);
void xive_tctx_reset(XiveTCTX *tctx);
void xive_tctx_destroy(XiveTCTX *tctx);
+void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb);
/*
* KVM XIVE device helpers
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 47/88] ppc/xive: Synthesize interrupt from the saved IPB in the NVT
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (45 preceding siblings ...)
2019-12-17 4:42 ` [PULL 46/88] ppc/xive: Introduce a xive_tctx_ipb_update() helper David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 48/88] ppc/pnv: Introduce a pnv_xive_block_id() helper David Gibson
` (41 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
When a vCPU is dispatched on a HW thread, its context is pushed in the
thread registers and it is activated by setting the VO bit in the CAM
line word2. The HW grabs the associated NVT, pulls the IPB bits and
merges them with the IPB of the new context. If interrupts were missed
while the vCPU was not dispatched, these are synthesized in this
sequence.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191125065820.927-18-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/xive.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 7047e45dac..e022bb7afd 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -393,6 +393,57 @@ static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
return qw1w2;
}
+static void xive_tctx_need_resend(XiveRouter *xrtr, XiveTCTX *tctx,
+ uint8_t nvt_blk, uint32_t nvt_idx)
+{
+ XiveNVT nvt;
+ uint8_t ipb;
+
+ /*
+ * Grab the associated NVT to pull the pending bits, and merge
+ * them with the IPB of the thread interrupt context registers
+ */
+ if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVT %x/%x\n",
+ nvt_blk, nvt_idx);
+ return;
+ }
+
+ ipb = xive_get_field32(NVT_W4_IPB, nvt.w4);
+
+ if (ipb) {
+ /* Reset the NVT value */
+ nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, 0);
+ xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4);
+
+ /* Merge in current context */
+ xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb);
+ }
+}
+
+/*
+ * Updating the OS CAM line can trigger a resend of interrupt
+ */
+static void xive_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, uint64_t value, unsigned size)
+{
+ uint32_t cam = value;
+ uint32_t qw1w2 = cpu_to_be32(cam);
+ uint8_t nvt_blk;
+ uint32_t nvt_idx;
+ bool vo;
+
+ xive_os_cam_decode(cam, &nvt_blk, &nvt_idx, &vo);
+
+ /* First update the registers */
+ xive_tctx_set_os_cam(tctx, qw1w2);
+
+ /* Check the interrupt pending bits */
+ if (vo) {
+ xive_tctx_need_resend(XIVE_ROUTER(xptr), tctx, nvt_blk, nvt_idx);
+ }
+}
+
/*
* Define a mapping of "special" operations depending on the TIMA page
* offset and the size of the operation.
@@ -414,6 +465,7 @@ static const XiveTmOp xive_tm_operations[] = {
* effects
*/
{ XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL },
+ { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive_tm_push_os_ctx, NULL },
{ XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL },
{ XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL },
{ XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll },
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 48/88] ppc/pnv: Introduce a pnv_xive_block_id() helper
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (46 preceding siblings ...)
2019-12-17 4:42 ` [PULL 47/88] ppc/xive: Synthesize interrupt from the saved IPB in the NVT David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 49/88] ppc/pnv: Extend XiveRouter with a get_block_id() handler David Gibson
` (40 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
When PC_TCTXT_CHIPID_OVERRIDE is configured, the PC_TCTXT_CHIPID field
overrides the hardwired chip ID in the Powerbus operations and for CAM
compares. This is typically used in the one block-per-chip configuration
to associate a unique block id number to each IC of the system.
Simplify the model with a pnv_xive_block_id() helper and remove
'tctx_chipid' which becomes useless.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191125065820.927-19-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/pnv_xive.c | 64 ++++++++++++++++++++-------------------
include/hw/ppc/pnv_xive.h | 3 --
2 files changed, 33 insertions(+), 34 deletions(-)
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index 216ebc150a..23e73641f2 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -85,13 +85,30 @@ static inline uint64_t SETFIELD(uint64_t mask, uint64_t word,
return (word & ~mask) | ((value << ctz64(mask)) & mask);
}
+/*
+ * When PC_TCTXT_CHIPID_OVERRIDE is configured, the PC_TCTXT_CHIPID
+ * field overrides the hardwired chip ID in the Powerbus operations
+ * and for CAM compares
+ */
+static uint8_t pnv_xive_block_id(PnvXive *xive)
+{
+ uint8_t blk = xive->chip->chip_id;
+ uint64_t cfg_val = xive->regs[PC_TCTXT_CFG >> 3];
+
+ if (cfg_val & PC_TCTXT_CHIPID_OVERRIDE) {
+ blk = GETFIELD(PC_TCTXT_CHIPID, cfg_val);
+ }
+
+ return blk;
+}
+
/*
* Remote access to controllers. HW uses MMIOs. For now, a simple scan
* of the chips is good enough.
*
* TODO: Block scope support
*/
-static PnvXive *pnv_xive_get_ic(uint8_t blk)
+static PnvXive *pnv_xive_get_remote(uint8_t blk)
{
PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
int i;
@@ -100,7 +117,7 @@ static PnvXive *pnv_xive_get_ic(uint8_t blk)
Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]);
PnvXive *xive = &chip9->xive;
- if (xive->chip->chip_id == blk) {
+ if (pnv_xive_block_id(xive) == blk) {
return xive;
}
}
@@ -216,7 +233,7 @@ static uint64_t pnv_xive_vst_addr(PnvXive *xive, uint32_t type, uint8_t blk,
/* Remote VST access */
if (GETFIELD(VSD_MODE, vsd) == VSD_MODE_FORWARD) {
- xive = pnv_xive_get_ic(blk);
+ xive = pnv_xive_get_remote(blk);
return xive ? pnv_xive_vst_addr(xive, type, blk, idx) : 0;
}
@@ -364,7 +381,10 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t blk, uint32_t idx,
{
PnvXive *xive = PNV_XIVE(xrtr);
- if (pnv_xive_get_ic(blk) != xive) {
+ /*
+ * EAT lookups should be local to the IC
+ */
+ if (pnv_xive_block_id(xive) != blk) {
xive_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx));
return -1;
}
@@ -470,7 +490,7 @@ static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu)
static void pnv_xive_notify(XiveNotifier *xn, uint32_t srcno)
{
PnvXive *xive = PNV_XIVE(xn);
- uint8_t blk = xive->chip->chip_id;
+ uint8_t blk = pnv_xive_block_id(xive);
xive_router_notify(xn, XIVE_EAS(blk, srcno));
}
@@ -834,20 +854,7 @@ static void pnv_xive_ic_reg_write(void *opaque, hwaddr offset,
case PC_TCTXT_CFG:
/*
* TODO: block group support
- *
- * PC_TCTXT_CFG_BLKGRP_EN
- * PC_TCTXT_CFG_HARD_CHIPID_BLK :
- * Moves the chipid into block field for hardwired CAM compares.
- * Block offset value is adjusted to 0b0..01 & ThrdId
- *
- * Will require changes in xive_presenter_tctx_match(). I am
- * not sure how to handle that yet.
*/
-
- /* Overrides hardwired chip ID with the chip ID field */
- if (val & PC_TCTXT_CHIPID_OVERRIDE) {
- xive->tctx_chipid = GETFIELD(PC_TCTXT_CHIPID, val);
- }
break;
case PC_TCTXT_TRACK:
/*
@@ -1656,19 +1663,20 @@ static const MemoryRegionOps pnv_xive_pc_ops = {
void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon)
{
XiveRouter *xrtr = XIVE_ROUTER(xive);
- uint8_t blk = xive->chip->chip_id;
+ uint8_t blk = pnv_xive_block_id(xive);
+ uint8_t chip_id = xive->chip->chip_id;
uint32_t srcno0 = XIVE_EAS(blk, 0);
uint32_t nr_ipis = pnv_xive_nr_ipis(xive, blk);
XiveEAS eas;
XiveEND end;
int i;
- monitor_printf(mon, "XIVE[%x] Source %08x .. %08x\n", blk, srcno0,
- srcno0 + nr_ipis - 1);
+ monitor_printf(mon, "XIVE[%x] #%d Source %08x .. %08x\n", chip_id, blk,
+ srcno0, srcno0 + nr_ipis - 1);
xive_source_pic_print_info(&xive->ipi_source, srcno0, mon);
- monitor_printf(mon, "XIVE[%x] EAT %08x .. %08x\n", blk, srcno0,
- srcno0 + nr_ipis - 1);
+ monitor_printf(mon, "XIVE[%x] #%d EAT %08x .. %08x\n", chip_id, blk,
+ srcno0, srcno0 + nr_ipis - 1);
for (i = 0; i < nr_ipis; i++) {
if (xive_router_get_eas(xrtr, blk, i, &eas)) {
break;
@@ -1678,13 +1686,13 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon)
}
}
- monitor_printf(mon, "XIVE[%x] ENDT\n", blk);
+ monitor_printf(mon, "XIVE[%x] #%d ENDT\n", chip_id, blk);
i = 0;
while (!xive_router_get_end(xrtr, blk, i, &end)) {
xive_end_pic_print_info(&end, i++, mon);
}
- monitor_printf(mon, "XIVE[%x] END Escalation EAT\n", blk);
+ monitor_printf(mon, "XIVE[%x] #%d END Escalation EAT\n", chip_id, blk);
i = 0;
while (!xive_router_get_end(xrtr, blk, i, &end)) {
xive_end_eas_pic_print_info(&end, i++, mon);
@@ -1697,12 +1705,6 @@ static void pnv_xive_reset(void *dev)
XiveSource *xsrc = &xive->ipi_source;
XiveENDSource *end_xsrc = &xive->end_source;
- /*
- * Use the PnvChip id to identify the XIVE interrupt controller.
- * It can be overriden by configuration at runtime.
- */
- xive->tctx_chipid = xive->chip->chip_id;
-
/* Default page size (Should be changed at runtime to 64k) */
xive->ic_shift = xive->vc_shift = xive->pc_shift = 12;
diff --git a/include/hw/ppc/pnv_xive.h b/include/hw/ppc/pnv_xive.h
index 4fdaa9247d..f4c7caad40 100644
--- a/include/hw/ppc/pnv_xive.h
+++ b/include/hw/ppc/pnv_xive.h
@@ -72,9 +72,6 @@ typedef struct PnvXive {
/* Interrupt controller registers */
uint64_t regs[0x300];
- /* Can be configured by FW */
- uint32_t tctx_chipid;
-
/*
* Virtual Structure Descriptor tables : EAT, SBE, ENDT, NVTT, IRQ
* These are in a SRAM protected by ECC.
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 49/88] ppc/pnv: Extend XiveRouter with a get_block_id() handler
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (47 preceding siblings ...)
2019-12-17 4:42 ` [PULL 48/88] ppc/pnv: Introduce a pnv_xive_block_id() helper David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 50/88] ppc/pnv: Dump the XIVE NVT table David Gibson
` (39 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
When doing CAM line compares, fetch the block id from the interrupt
controller which can have set the PC_TCTXT_CHIPID field.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191125065820.927-20-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/pnv_xive.c | 6 ++++++
hw/intc/spapr_xive.c | 6 ++++++
hw/intc/xive.c | 21 ++++++++++++++++-----
include/hw/ppc/xive.h | 2 +-
4 files changed, 29 insertions(+), 6 deletions(-)
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index 23e73641f2..43c760efd1 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -459,6 +459,11 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
return count;
}
+static uint8_t pnv_xive_get_block_id(XiveRouter *xrtr)
+{
+ return pnv_xive_block_id(PNV_XIVE(xrtr));
+}
+
/*
* The TIMA MMIO space is shared among the chips and to identify the
* chip from which the access is being done, we extract the chip id
@@ -1890,6 +1895,7 @@ static void pnv_xive_class_init(ObjectClass *klass, void *data)
xrc->write_end = pnv_xive_write_end;
xrc->get_nvt = pnv_xive_get_nvt;
xrc->write_nvt = pnv_xive_write_nvt;
+ xrc->get_block_id = pnv_xive_get_block_id;
xnc->notify = pnv_xive_notify;
xpc->match_nvt = pnv_xive_match_nvt;
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index b785066da5..57305c56d7 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -473,6 +473,11 @@ static int spapr_xive_match_nvt(XivePresenter *xptr, uint8_t format,
return count;
}
+static uint8_t spapr_xive_get_block_id(XiveRouter *xrtr)
+{
+ return SPAPR_XIVE_BLOCK_ID;
+}
+
static const VMStateDescription vmstate_spapr_xive_end = {
.name = TYPE_SPAPR_XIVE "/end",
.version_id = 1,
@@ -766,6 +771,7 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data)
xrc->write_end = spapr_xive_write_end;
xrc->get_nvt = spapr_xive_get_nvt;
xrc->write_nvt = spapr_xive_write_nvt;
+ xrc->get_block_id = spapr_xive_get_block_id;
sicc->activate = spapr_xive_activate;
sicc->deactivate = spapr_xive_deactivate;
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index e022bb7afd..d4c6e21703 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -1371,17 +1371,25 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number);
}
+static int xive_router_get_block_id(XiveRouter *xrtr)
+{
+ XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr);
+
+ return xrc->get_block_id(xrtr);
+}
+
/*
* Encode the HW CAM line in the block group mode format :
*
* chip << 19 | 0000000 0 0001 thread (7Bit)
*/
-static uint32_t xive_tctx_hw_cam_line(XiveTCTX *tctx)
+static uint32_t xive_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx)
{
CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env;
uint32_t pir = env->spr_cb[SPR_PIR].default_value;
+ uint8_t blk = xive_router_get_block_id(XIVE_ROUTER(xptr));
- return xive_nvt_cam_line((pir >> 8) & 0xf, 1 << 7 | (pir & 0x7f));
+ return xive_nvt_cam_line(blk, 1 << 7 | (pir & 0x7f));
}
/*
@@ -1418,7 +1426,7 @@ int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
/* PHYS ring */
if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) &&
- cam == xive_tctx_hw_cam_line(tctx)) {
+ cam == xive_tctx_hw_cam_line(xptr, tctx)) {
return TM_QW3_HV_PHYS;
}
@@ -1755,7 +1763,11 @@ static uint64_t xive_end_source_read(void *opaque, hwaddr addr, unsigned size)
uint8_t pq;
uint64_t ret = -1;
- end_blk = xsrc->block_id;
+ /*
+ * The block id should be deduced from the load address on the END
+ * ESB MMIO but our model only supports a single block per XIVE chip.
+ */
+ end_blk = xive_router_get_block_id(xsrc->xrtr);
end_idx = addr >> (xsrc->esb_shift + 1);
if (xive_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) {
@@ -1855,7 +1867,6 @@ static void xive_end_source_realize(DeviceState *dev, Error **errp)
}
static Property xive_end_source_properties[] = {
- DEFINE_PROP_UINT8("block-id", XiveENDSource, block_id, 0),
DEFINE_PROP_UINT32("nr-ends", XiveENDSource, nr_ends, 0),
DEFINE_PROP_UINT32("shift", XiveENDSource, esb_shift, XIVE_ESB_64K),
DEFINE_PROP_LINK("xive", XiveENDSource, xrtr, TYPE_XIVE_ROUTER,
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index 9c0bf2c301..1b7b89098f 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -351,6 +351,7 @@ typedef struct XiveRouterClass {
XiveNVT *nvt);
int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
XiveNVT *nvt, uint8_t word_number);
+ uint8_t (*get_block_id)(XiveRouter *xrtr);
} XiveRouterClass;
int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
@@ -431,7 +432,6 @@ typedef struct XiveENDSource {
DeviceState parent;
uint32_t nr_ends;
- uint8_t block_id;
/* ESB memory region */
uint32_t esb_shift;
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 50/88] ppc/pnv: Dump the XIVE NVT table
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (48 preceding siblings ...)
2019-12-17 4:42 ` [PULL 49/88] ppc/pnv: Extend XiveRouter with a get_block_id() handler David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 51/88] ppc: well form kvmppc_hint_smt_possible error hint helper David Gibson
` (38 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
This is useful to dump the saved contexts of the vCPUs : configuration
of the base END index of the vCPU and the Interrupt Pending Buffer
register, which is updated when an interrupt can not be presented.
When dumping the NVT table, we skip empty indirect pages which are not
necessarily allocated.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191125065820.927-21-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/pnv_xive.c | 64 ++++++++++++++++++++++++++++++++++++++
include/hw/ppc/xive_regs.h | 3 ++
2 files changed, 67 insertions(+)
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index 43c760efd1..a0a69b98a7 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -527,6 +527,44 @@ static uint32_t pnv_xive_nr_ipis(PnvXive *xive, uint8_t blk)
return VSD_INDIRECT & vsd ? 0 : vst_tsize * SBE_PER_BYTE;
}
+/*
+ * Compute the number of entries per indirect subpage.
+ */
+static uint64_t pnv_xive_vst_per_subpage(PnvXive *xive, uint32_t type)
+{
+ uint8_t blk = pnv_xive_block_id(xive);
+ uint64_t vsd = xive->vsds[type][blk];
+ const XiveVstInfo *info = &vst_infos[type];
+ uint64_t vsd_addr;
+ uint32_t page_shift;
+
+ /* For direct tables, fake a valid value */
+ if (!(VSD_INDIRECT & vsd)) {
+ return 1;
+ }
+
+ /* Get the page size of the indirect table. */
+ vsd_addr = vsd & VSD_ADDRESS_MASK;
+ vsd = ldq_be_dma(&address_space_memory, vsd_addr);
+
+ if (!(vsd & VSD_ADDRESS_MASK)) {
+#ifdef XIVE_DEBUG
+ xive_error(xive, "VST: invalid %s entry %x !?", info->name, idx);
+#endif
+ return 0;
+ }
+
+ page_shift = GETFIELD(VSD_TSIZE, vsd) + 12;
+
+ if (!pnv_xive_vst_page_size_allowed(page_shift)) {
+ xive_error(xive, "VST: invalid %s page shift %d", info->name,
+ page_shift);
+ return 0;
+ }
+
+ return (1ull << page_shift) / info->size;
+}
+
/*
* EDT Table
*
@@ -1665,6 +1703,21 @@ static const MemoryRegionOps pnv_xive_pc_ops = {
},
};
+static void xive_nvt_pic_print_info(XiveNVT *nvt, uint32_t nvt_idx,
+ Monitor *mon)
+{
+ uint8_t eq_blk = xive_get_field32(NVT_W1_EQ_BLOCK, nvt->w1);
+ uint32_t eq_idx = xive_get_field32(NVT_W1_EQ_INDEX, nvt->w1);
+
+ if (!xive_nvt_is_valid(nvt)) {
+ return;
+ }
+
+ monitor_printf(mon, " %08x end:%02x/%04x IPB:%02x\n", nvt_idx,
+ eq_blk, eq_idx,
+ xive_get_field32(NVT_W4_IPB, nvt->w4));
+}
+
void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon)
{
XiveRouter *xrtr = XIVE_ROUTER(xive);
@@ -1674,7 +1727,9 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon)
uint32_t nr_ipis = pnv_xive_nr_ipis(xive, blk);
XiveEAS eas;
XiveEND end;
+ XiveNVT nvt;
int i;
+ uint64_t xive_nvt_per_subpage;
monitor_printf(mon, "XIVE[%x] #%d Source %08x .. %08x\n", chip_id, blk,
srcno0, srcno0 + nr_ipis - 1);
@@ -1702,6 +1757,15 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon)
while (!xive_router_get_end(xrtr, blk, i, &end)) {
xive_end_eas_pic_print_info(&end, i++, mon);
}
+
+ monitor_printf(mon, "XIVE[%x] #%d NVTT %08x .. %08x\n", chip_id, blk,
+ 0, XIVE_NVT_COUNT - 1);
+ xive_nvt_per_subpage = pnv_xive_vst_per_subpage(xive, VST_TSEL_VPDT);
+ for (i = 0; i < XIVE_NVT_COUNT; i += xive_nvt_per_subpage) {
+ while (!xive_router_get_nvt(xrtr, blk, i, &nvt)) {
+ xive_nvt_pic_print_info(&nvt, i++, mon);
+ }
+ }
}
static void pnv_xive_reset(void *dev)
diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h
index 1a5622f8de..09f243600c 100644
--- a/include/hw/ppc/xive_regs.h
+++ b/include/hw/ppc/xive_regs.h
@@ -252,6 +252,8 @@ typedef struct XiveNVT {
uint32_t w0;
#define NVT_W0_VALID PPC_BIT32(0)
uint32_t w1;
+#define NVT_W1_EQ_BLOCK PPC_BITMASK32(0, 3)
+#define NVT_W1_EQ_INDEX PPC_BITMASK32(4, 31)
uint32_t w2;
uint32_t w3;
uint32_t w4;
@@ -277,6 +279,7 @@ typedef struct XiveNVT {
* field of the XIVE END
*/
#define XIVE_NVT_SHIFT 19
+#define XIVE_NVT_COUNT (1 << XIVE_NVT_SHIFT)
static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx)
{
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 51/88] ppc: well form kvmppc_hint_smt_possible error hint helper
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (49 preceding siblings ...)
2019-12-17 4:42 ` [PULL 50/88] ppc/pnv: Dump the XIVE NVT table David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 6:32 ` Markus Armbruster
2019-12-17 4:42 ` [PULL 52/88] spapr: Don't trigger a CAS reboot for XICS/XIVE mode changeover David Gibson
` (37 subsequent siblings)
88 siblings, 1 reply; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, Vladimir Sementsov-Ogievskiy, aik, qemu-devel, groug,
qemu-ppc, clg, Marc-André Lureau, David Gibson
From: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Make kvmppc_hint_smt_possible hint append helper well formed:
rename errp to errp_in, as it is IN-parameter here (which is unusual
for errp), rename function to be kvmppc_error_append_*_hint.
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20191127191434.20945-1-vsementsov@virtuozzo.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr.c | 2 +-
target/ppc/kvm.c | 6 +++---
target/ppc/kvm_ppc.h | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index d9c9a2bcee..e3c7d487b8 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -2564,7 +2564,7 @@ static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp)
" requires the use of VSMT mode %d.\n",
smp_threads, kvm_smt, spapr->vsmt);
}
- kvmppc_hint_smt_possible(&local_err);
+ kvmppc_error_append_smt_possible_hint(&local_err);
goto out;
}
}
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index c77f9848ec..7406d18945 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -2076,7 +2076,7 @@ int kvmppc_set_smt_threads(int smt)
return ret;
}
-void kvmppc_hint_smt_possible(Error **errp)
+void kvmppc_error_append_smt_possible_hint(Error **errp_in)
{
int i;
GString *g;
@@ -2091,10 +2091,10 @@ void kvmppc_hint_smt_possible(Error **errp)
}
}
s = g_string_free(g, false);
- error_append_hint(errp, "%s.\n", s);
+ error_append_hint(errp_in, "%s.\n", s);
g_free(s);
} else {
- error_append_hint(errp,
+ error_append_hint(errp_in,
"This KVM seems to be too old to support VSMT.\n");
}
}
diff --git a/target/ppc/kvm_ppc.h b/target/ppc/kvm_ppc.h
index 98bd7d5da6..47b08a4030 100644
--- a/target/ppc/kvm_ppc.h
+++ b/target/ppc/kvm_ppc.h
@@ -28,7 +28,7 @@ void kvmppc_set_papr(PowerPCCPU *cpu);
int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr);
void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy);
int kvmppc_smt_threads(void);
-void kvmppc_hint_smt_possible(Error **errp);
+void kvmppc_error_append_smt_possible_hint(Error **errp_in);
int kvmppc_set_smt_threads(int smt);
int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits);
int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits);
@@ -164,7 +164,7 @@ static inline int kvmppc_smt_threads(void)
return 1;
}
-static inline void kvmppc_hint_smt_possible(Error **errp)
+static inline void kvmppc_error_append_smt_possible_hint(Error **errp_in)
{
return;
}
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* Re: [PULL 51/88] ppc: well form kvmppc_hint_smt_possible error hint helper
2019-12-17 4:42 ` [PULL 51/88] ppc: well form kvmppc_hint_smt_possible error hint helper David Gibson
@ 2019-12-17 6:32 ` Markus Armbruster
2019-12-18 3:12 ` David Gibson
0 siblings, 1 reply; 94+ messages in thread
From: Markus Armbruster @ 2019-12-17 6:32 UTC (permalink / raw)
To: David Gibson
Cc: lvivier, peter.maydell, Vladimir Sementsov-Ogievskiy, aik,
qemu-devel, groug, qemu-ppc, clg, Marc-André Lureau
David Gibson <david@gibson.dropbear.id.au> writes:
> From: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
>
> Make kvmppc_hint_smt_possible hint append helper well formed:
> rename errp to errp_in, as it is IN-parameter here (which is unusual
> for errp), rename function to be kvmppc_error_append_*_hint.
>
> Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
> Message-Id: <20191127191434.20945-1-vsementsov@virtuozzo.com>
> Reviewed-by: Greg Kurz <groug@kaod.org>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Review led to the commit message to be replaced for this and related
patches. It's in my "[PULL 00/34] Error reporting patches for
2019-12-16". No big deal, but if you respin, either steal that message
or drop this patch.
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PULL 51/88] ppc: well form kvmppc_hint_smt_possible error hint helper
2019-12-17 6:32 ` Markus Armbruster
@ 2019-12-18 3:12 ` David Gibson
0 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-18 3:12 UTC (permalink / raw)
To: Markus Armbruster
Cc: lvivier, peter.maydell, Vladimir Sementsov-Ogievskiy, aik,
qemu-devel, groug, qemu-ppc, clg, Marc-André Lureau
[-- Attachment #1: Type: text/plain, Size: 1354 bytes --]
On Tue, Dec 17, 2019 at 07:32:15AM +0100, Markus Armbruster wrote:
> David Gibson <david@gibson.dropbear.id.au> writes:
>
> > From: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
> >
> > Make kvmppc_hint_smt_possible hint append helper well formed:
> > rename errp to errp_in, as it is IN-parameter here (which is unusual
> > for errp), rename function to be kvmppc_error_append_*_hint.
> >
> > Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
> > Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
> > Message-Id: <20191127191434.20945-1-vsementsov@virtuozzo.com>
> > Reviewed-by: Greg Kurz <groug@kaod.org>
> > Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
>
> Review led to the commit message to be replaced for this and related
> patches. It's in my "[PULL 00/34] Error reporting patches for
> 2019-12-16". No big deal, but if you respin, either steal that message
> or drop this patch.
Uh, sorry. I realized moments before sending this that this patch had
been updated. I didn't want to re-do all my pre-pull testing, though
and it's not actually harmful, so I left it.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 94+ messages in thread
* [PULL 52/88] spapr: Don't trigger a CAS reboot for XICS/XIVE mode changeover
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (50 preceding siblings ...)
2019-12-17 4:42 ` [PULL 51/88] ppc: well form kvmppc_hint_smt_possible error hint helper David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 53/88] spapr: Improve handling of fdt buffer size David Gibson
` (36 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, Cedric Le Goater, qemu-ppc, clg,
David Gibson
PAPR allows the interrupt controller used on a POWER9 machine (XICS or
XIVE) to be selected by the guest operating system, by using the
ibm,client-architecture-support (CAS) feature negotiation call.
Currently, if the guest selects an interrupt controller different from the
one selected at initial boot, this causes the system to be reset with the
new model and the boot starts again. This means we run through the SLOF
boot process twice, as well as any other bootloader (e.g. grub) in use
before the OS calls CAS. This can be confusing and/or inconvenient for
users.
Thanks to two fairly recent changes, we no longer need this reboot. 1) we
now completely regenerate the device tree when CAS is called (meaning we
don't need special case updates for all the device tree changes caused by
the interrupt controller mode change), 2) we now have explicit code paths
to activate and deactivate the different interrupt controllers, rather than
just implicitly calling those at machine reset time.
We can therefore eliminate the reboot for changing irq mode, simply by
putting a call to spapr_irq_update_active_intc() before we call
spapr_h_cas_compose_response() (which gives the updated device tree to
the guest firmware and OS).
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cedric Le Goater <clg@fr.ibm.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
---
hw/ppc/spapr_hcall.c | 33 +++++++++++++--------------------
1 file changed, 13 insertions(+), 20 deletions(-)
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 140f05c1c6..05a7ca275b 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -1767,21 +1767,10 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
}
spapr->cas_pre_isa3_guest = !spapr_ovec_test(ov1_guest, OV1_PPC_3_00);
spapr_ovec_cleanup(ov1_guest);
- if (!spapr->cas_reboot) {
- /* If spapr_machine_reset() did not set up a HPT but one is necessary
- * (because the guest isn't going to use radix) then set it up here. */
- if ((spapr->patb_entry & PATE1_GR) && !guest_radix) {
- /* legacy hash or new hash: */
- spapr_setup_hpt_and_vrma(spapr);
- }
- spapr->cas_reboot =
- (spapr_h_cas_compose_response(spapr, args[1], args[2],
- ov5_updates) != 0);
- }
/*
- * Ensure the guest asks for an interrupt mode we support; otherwise
- * terminate the boot.
+ * Ensure the guest asks for an interrupt mode we support;
+ * otherwise terminate the boot.
*/
if (guest_xive) {
if (!spapr->irq->xive) {
@@ -1797,14 +1786,18 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
}
}
- /*
- * Generate a machine reset when we have an update of the
- * interrupt mode. Only required when the machine supports both
- * modes.
- */
+ spapr_irq_update_active_intc(spapr);
+
if (!spapr->cas_reboot) {
- spapr->cas_reboot = spapr_ovec_test(ov5_updates, OV5_XIVE_EXPLOIT)
- && spapr->irq->xics && spapr->irq->xive;
+ /* If spapr_machine_reset() did not set up a HPT but one is necessary
+ * (because the guest isn't going to use radix) then set it up here. */
+ if ((spapr->patb_entry & PATE1_GR) && !guest_radix) {
+ /* legacy hash or new hash: */
+ spapr_setup_hpt_and_vrma(spapr);
+ }
+ spapr->cas_reboot =
+ (spapr_h_cas_compose_response(spapr, args[1], args[2],
+ ov5_updates) != 0);
}
spapr_ovec_cleanup(ov5_updates);
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 53/88] spapr: Improve handling of fdt buffer size
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (51 preceding siblings ...)
2019-12-17 4:42 ` [PULL 52/88] spapr: Don't trigger a CAS reboot for XICS/XIVE mode changeover David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 54/88] spapr: Fold h_cas_compose_response() into h_client_architecture_support() David Gibson
` (35 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, Cedric Le Goater, qemu-ppc, clg,
David Gibson
Previously, spapr_build_fdt() constructed the device tree in a fixed
buffer of size FDT_MAX_SIZE. This is a bit inflexible, but more
importantly it's awkward for the case where we use it during CAS. In
that case the guest firmware supplies a buffer and we have to
awkwardly check that what we generated fits into it afterwards, after
doing a lot of size checks during spapr_build_fdt().
Simplify this by having spapr_build_fdt() take a 'space' parameter.
For the CAS case, we pass in the buffer size provided by SLOF, for the
machine init case, we continue to pass FDT_MAX_SIZE.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cedric Le Goater <clg@fr.ibm.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
---
hw/ppc/spapr.c | 33 +++++++++++----------------------
1 file changed, 11 insertions(+), 22 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index e3c7d487b8..df5bea1bd4 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -917,7 +917,8 @@ static bool spapr_hotplugged_dev_before_cas(void)
return false;
}
-static void *spapr_build_fdt(SpaprMachineState *spapr, bool reset);
+static void *spapr_build_fdt(SpaprMachineState *spapr, bool reset,
+ size_t space);
int spapr_h_cas_compose_response(SpaprMachineState *spapr,
target_ulong addr, target_ulong size,
@@ -930,24 +931,17 @@ int spapr_h_cas_compose_response(SpaprMachineState *spapr,
return 1;
}
- if (size < sizeof(hdr) || size > FW_MAX_SIZE) {
- error_report("SLOF provided an unexpected CAS buffer size "
- TARGET_FMT_lu " (min: %zu, max: %u)",
- size, sizeof(hdr), FW_MAX_SIZE);
+ if (size < sizeof(hdr)) {
+ error_report("SLOF provided insufficient CAS buffer "
+ TARGET_FMT_lu " (min: %zu)", size, sizeof(hdr));
exit(EXIT_FAILURE);
}
size -= sizeof(hdr);
- fdt = spapr_build_fdt(spapr, false);
+ fdt = spapr_build_fdt(spapr, false, size);
_FDT((fdt_pack(fdt)));
- if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
- g_free(fdt);
- trace_spapr_cas_failed(size);
- return -1;
- }
-
cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
@@ -1197,7 +1191,8 @@ static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt)
}
}
-static void *spapr_build_fdt(SpaprMachineState *spapr, bool reset)
+static void *spapr_build_fdt(SpaprMachineState *spapr, bool reset,
+ size_t space)
{
MachineState *machine = MACHINE(spapr);
MachineClass *mc = MACHINE_GET_CLASS(machine);
@@ -1207,8 +1202,8 @@ static void *spapr_build_fdt(SpaprMachineState *spapr, bool reset)
SpaprPhbState *phb;
char *buf;
- fdt = g_malloc0(FDT_MAX_SIZE);
- _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
+ fdt = g_malloc0(space);
+ _FDT((fdt_create_empty_tree(fdt, space)));
/* Root node */
_FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
@@ -1723,19 +1718,13 @@ static void spapr_machine_reset(MachineState *machine)
*/
fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE;
- fdt = spapr_build_fdt(spapr, true);
+ fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE);
rc = fdt_pack(fdt);
/* Should only fail if we've built a corrupted tree */
assert(rc == 0);
- if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
- error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
- fdt_totalsize(fdt), FDT_MAX_SIZE);
- exit(1);
- }
-
/* Load the fdt */
qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 54/88] spapr: Fold h_cas_compose_response() into h_client_architecture_support()
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (52 preceding siblings ...)
2019-12-17 4:42 ` [PULL 53/88] spapr: Improve handling of fdt buffer size David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 55/88] spapr: Simplify ovec diff David Gibson
` (34 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, Cedric Le Goater, qemu-ppc, clg,
David Gibson
spapr_h_cas_compose_response() handles the last piece of the PAPR feature
negotiation process invoked via the ibm,client-architecture-support OF
call. Its only caller is h_client_architecture_support() which handles
most of the rest of that process.
I believe it was placed in a separate file originally to handle some
fiddly dependencies between functions, but mostly it's just confusing
to have the CAS process split into two pieces like this. Now that
compose response is simplified (by just generating the whole device
tree anew), it's cleaner to just fold it into
h_client_architecture_support().
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cedric Le Goater <clg@fr.ibm.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
---
hw/ppc/spapr.c | 61 +-----------------------------------------
hw/ppc/spapr_hcall.c | 55 ++++++++++++++++++++++++++++++++++---
include/hw/ppc/spapr.h | 4 +--
3 files changed, 54 insertions(+), 66 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index df5bea1bd4..3dedb41d48 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -76,7 +76,6 @@
#include "hw/nmi.h"
#include "hw/intc/intc.h"
-#include "qemu/cutils.h"
#include "hw/ppc/spapr_cpu_core.h"
#include "hw/mem/memory-device.h"
#include "hw/ppc/spapr_tpm_proxy.h"
@@ -897,63 +896,6 @@ out:
return ret;
}
-static bool spapr_hotplugged_dev_before_cas(void)
-{
- Object *drc_container, *obj;
- ObjectProperty *prop;
- ObjectPropertyIterator iter;
-
- drc_container = container_get(object_get_root(), "/dr-connector");
- object_property_iter_init(&iter, drc_container);
- while ((prop = object_property_iter_next(&iter))) {
- if (!strstart(prop->type, "link<", NULL)) {
- continue;
- }
- obj = object_property_get_link(drc_container, prop->name, NULL);
- if (spapr_drc_needed(obj)) {
- return true;
- }
- }
- return false;
-}
-
-static void *spapr_build_fdt(SpaprMachineState *spapr, bool reset,
- size_t space);
-
-int spapr_h_cas_compose_response(SpaprMachineState *spapr,
- target_ulong addr, target_ulong size,
- SpaprOptionVector *ov5_updates)
-{
- void *fdt;
- SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 };
-
- if (spapr_hotplugged_dev_before_cas()) {
- return 1;
- }
-
- if (size < sizeof(hdr)) {
- error_report("SLOF provided insufficient CAS buffer "
- TARGET_FMT_lu " (min: %zu)", size, sizeof(hdr));
- exit(EXIT_FAILURE);
- }
-
- size -= sizeof(hdr);
-
- fdt = spapr_build_fdt(spapr, false, size);
- _FDT((fdt_pack(fdt)));
-
- cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
- cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
- trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
-
- g_free(spapr->fdt_blob);
- spapr->fdt_size = fdt_totalsize(fdt);
- spapr->fdt_initial_size = spapr->fdt_size;
- spapr->fdt_blob = fdt;
-
- return 0;
-}
-
static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt)
{
MachineState *ms = MACHINE(spapr);
@@ -1191,8 +1133,7 @@ static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt)
}
}
-static void *spapr_build_fdt(SpaprMachineState *spapr, bool reset,
- size_t space)
+void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space)
{
MachineState *machine = MACHINE(spapr);
MachineClass *mc = MACHINE_GET_CLASS(machine);
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 05a7ca275b..0f19be794c 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -1,4 +1,5 @@
#include "qemu/osdep.h"
+#include "qemu/cutils.h"
#include "qapi/error.h"
#include "sysemu/hw_accel.h"
#include "sysemu/runstate.h"
@@ -15,6 +16,7 @@
#include "cpu-models.h"
#include "trace.h"
#include "kvm_ppc.h"
+#include "hw/ppc/fdt.h"
#include "hw/ppc/spapr_ovec.h"
#include "mmu-book3s-v3.h"
#include "hw/mem/memory-device.h"
@@ -1638,6 +1640,26 @@ static uint32_t cas_check_pvr(SpaprMachineState *spapr, PowerPCCPU *cpu,
return best_compat;
}
+static bool spapr_hotplugged_dev_before_cas(void)
+{
+ Object *drc_container, *obj;
+ ObjectProperty *prop;
+ ObjectPropertyIterator iter;
+
+ drc_container = container_get(object_get_root(), "/dr-connector");
+ object_property_iter_init(&iter, drc_container);
+ while ((prop = object_property_iter_next(&iter))) {
+ if (!strstart(prop->type, "link<", NULL)) {
+ continue;
+ }
+ obj = object_property_get_link(drc_container, prop->name, NULL);
+ if (spapr_drc_needed(obj)) {
+ return true;
+ }
+ }
+ return false;
+}
+
static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
SpaprMachineState *spapr,
target_ulong opcode,
@@ -1645,6 +1667,8 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
{
/* Working address in data buffer */
target_ulong addr = ppc64_phys_to_real(args[0]);
+ target_ulong fdt_buf = args[1];
+ target_ulong fdt_bufsize = args[2];
target_ulong ov_table;
uint32_t cas_pvr;
SpaprOptionVector *ov1_guest, *ov5_guest, *ov5_cas_old, *ov5_updates;
@@ -1788,16 +1812,41 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
spapr_irq_update_active_intc(spapr);
+ if (spapr_hotplugged_dev_before_cas()) {
+ spapr->cas_reboot = true;
+ }
+
if (!spapr->cas_reboot) {
+ void *fdt;
+ SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 };
+
/* If spapr_machine_reset() did not set up a HPT but one is necessary
* (because the guest isn't going to use radix) then set it up here. */
if ((spapr->patb_entry & PATE1_GR) && !guest_radix) {
/* legacy hash or new hash: */
spapr_setup_hpt_and_vrma(spapr);
}
- spapr->cas_reboot =
- (spapr_h_cas_compose_response(spapr, args[1], args[2],
- ov5_updates) != 0);
+
+ if (fdt_bufsize < sizeof(hdr)) {
+ error_report("SLOF provided insufficient CAS buffer "
+ TARGET_FMT_lu " (min: %zu)", fdt_bufsize, sizeof(hdr));
+ exit(EXIT_FAILURE);
+ }
+
+ fdt_bufsize -= sizeof(hdr);
+
+ fdt = spapr_build_fdt(spapr, false, fdt_bufsize);
+ _FDT((fdt_pack(fdt)));
+
+ cpu_physical_memory_write(fdt_buf, &hdr, sizeof(hdr));
+ cpu_physical_memory_write(fdt_buf + sizeof(hdr), fdt,
+ fdt_totalsize(fdt));
+ trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
+
+ g_free(spapr->fdt_blob);
+ spapr->fdt_size = fdt_totalsize(fdt);
+ spapr->fdt_initial_size = spapr->fdt_size;
+ spapr->fdt_blob = fdt;
}
spapr_ovec_cleanup(ov5_updates);
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index d5ab5ea7b2..61f005c6f6 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -766,11 +766,9 @@ struct SpaprEventLogEntry {
QTAILQ_ENTRY(SpaprEventLogEntry) next;
};
+void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space);
void spapr_events_init(SpaprMachineState *sm);
void spapr_dt_events(SpaprMachineState *sm, void *fdt);
-int spapr_h_cas_compose_response(SpaprMachineState *sm,
- target_ulong addr, target_ulong size,
- SpaprOptionVector *ov5_updates);
void close_htab_fd(SpaprMachineState *spapr);
void spapr_setup_hpt_and_vrma(SpaprMachineState *spapr);
void spapr_free_hpt(SpaprMachineState *spapr);
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 55/88] spapr: Simplify ovec diff
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (53 preceding siblings ...)
2019-12-17 4:42 ` [PULL 54/88] spapr: Fold h_cas_compose_response() into h_client_architecture_support() David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 56/88] ppc: Deassert the external interrupt pin in KVM on reset David Gibson
` (33 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, Mike Roth, aik, qemu-devel, groug, Cedric Le Goater,
qemu-ppc, clg, David Gibson
spapr_ovec_diff(ov, old, new) has somewhat complex semantics. ov is set
to those bits which are in new but not old, and it returns as a boolean
whether or not there are any bits in old but not new.
It turns out that both callers only care about the second, not the first.
This is basically equivalent to a bitmap subset operation, which is easier
to understand and implement. So replace spapr_ovec_diff() with
spapr_ovec_subset().
Cc: Mike Roth <mdroth@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cedric Le Goater <clg@fr.ibm.com>
---
hw/ppc/spapr.c | 14 +++-----------
hw/ppc/spapr_hcall.c | 8 ++------
hw/ppc/spapr_ovec.c | 30 ++++++++++--------------------
include/hw/ppc/spapr_ovec.h | 4 +---
4 files changed, 16 insertions(+), 40 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 3dedb41d48..f11422fc41 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1840,8 +1840,6 @@ static bool spapr_ov5_cas_needed(void *opaque)
{
SpaprMachineState *spapr = opaque;
SpaprOptionVector *ov5_mask = spapr_ovec_new();
- SpaprOptionVector *ov5_legacy = spapr_ovec_new();
- SpaprOptionVector *ov5_removed = spapr_ovec_new();
bool cas_needed;
/* Prior to the introduction of SpaprOptionVector, we had two option
@@ -1873,17 +1871,11 @@ static bool spapr_ov5_cas_needed(void *opaque)
spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
spapr_ovec_set(ov5_mask, OV5_DRMEM_V2);
- /* spapr_ovec_diff returns true if bits were removed. we avoid using
- * the mask itself since in the future it's possible "legacy" bits may be
- * removed via machine options, which could generate a false positive
- * that breaks migration.
- */
- spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask);
- cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy);
+ /* We need extra information if we have any bits outside the mask
+ * defined above */
+ cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask);
spapr_ovec_cleanup(ov5_mask);
- spapr_ovec_cleanup(ov5_legacy);
- spapr_ovec_cleanup(ov5_removed);
return cas_needed;
}
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 0f19be794c..f1799b1b70 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -1671,7 +1671,7 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
target_ulong fdt_bufsize = args[2];
target_ulong ov_table;
uint32_t cas_pvr;
- SpaprOptionVector *ov1_guest, *ov5_guest, *ov5_cas_old, *ov5_updates;
+ SpaprOptionVector *ov1_guest, *ov5_guest, *ov5_cas_old;
bool guest_radix;
Error *local_err = NULL;
bool raw_mode_supported = false;
@@ -1770,9 +1770,7 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
/* capabilities that have been added since CAS-generated guest reset.
* if capabilities have since been removed, generate another reset
*/
- ov5_updates = spapr_ovec_new();
- spapr->cas_reboot = spapr_ovec_diff(ov5_updates,
- ov5_cas_old, spapr->ov5_cas);
+ spapr->cas_reboot = !spapr_ovec_subset(ov5_cas_old, spapr->ov5_cas);
spapr_ovec_cleanup(ov5_cas_old);
/* Now that processing is finished, set the radix/hash bit for the
* guest if it requested a valid mode; otherwise terminate the boot. */
@@ -1849,8 +1847,6 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
spapr->fdt_blob = fdt;
}
- spapr_ovec_cleanup(ov5_updates);
-
if (spapr->cas_reboot) {
qemu_system_reset_request(SHUTDOWN_CAUSE_SUBSYSTEM_RESET);
}
diff --git a/hw/ppc/spapr_ovec.c b/hw/ppc/spapr_ovec.c
index 811fadf143..0ff6d1aeae 100644
--- a/hw/ppc/spapr_ovec.c
+++ b/hw/ppc/spapr_ovec.c
@@ -76,31 +76,21 @@ void spapr_ovec_intersect(SpaprOptionVector *ov,
bitmap_and(ov->bitmap, ov1->bitmap, ov2->bitmap, OV_MAXBITS);
}
-/* returns true if options bits were removed, false otherwise */
-bool spapr_ovec_diff(SpaprOptionVector *ov,
- SpaprOptionVector *ov_old,
- SpaprOptionVector *ov_new)
+/* returns true if ov1 has a subset of bits in ov2 */
+bool spapr_ovec_subset(SpaprOptionVector *ov1, SpaprOptionVector *ov2)
{
- unsigned long *change_mask = bitmap_new(OV_MAXBITS);
- unsigned long *removed_bits = bitmap_new(OV_MAXBITS);
- bool bits_were_removed = false;
+ unsigned long *tmp = bitmap_new(OV_MAXBITS);
+ bool result;
- g_assert(ov);
- g_assert(ov_old);
- g_assert(ov_new);
-
- bitmap_xor(change_mask, ov_old->bitmap, ov_new->bitmap, OV_MAXBITS);
- bitmap_and(ov->bitmap, ov_new->bitmap, change_mask, OV_MAXBITS);
- bitmap_and(removed_bits, ov_old->bitmap, change_mask, OV_MAXBITS);
+ g_assert(ov1);
+ g_assert(ov2);
- if (!bitmap_empty(removed_bits, OV_MAXBITS)) {
- bits_were_removed = true;
- }
+ bitmap_andnot(tmp, ov1->bitmap, ov2->bitmap, OV_MAXBITS);
+ result = bitmap_empty(tmp, OV_MAXBITS);
- g_free(change_mask);
- g_free(removed_bits);
+ g_free(tmp);
- return bits_were_removed;
+ return result;
}
void spapr_ovec_cleanup(SpaprOptionVector *ov)
diff --git a/include/hw/ppc/spapr_ovec.h b/include/hw/ppc/spapr_ovec.h
index 7891e9caac..2bed517a2b 100644
--- a/include/hw/ppc/spapr_ovec.h
+++ b/include/hw/ppc/spapr_ovec.h
@@ -66,9 +66,7 @@ SpaprOptionVector *spapr_ovec_clone(SpaprOptionVector *ov_orig);
void spapr_ovec_intersect(SpaprOptionVector *ov,
SpaprOptionVector *ov1,
SpaprOptionVector *ov2);
-bool spapr_ovec_diff(SpaprOptionVector *ov,
- SpaprOptionVector *ov_old,
- SpaprOptionVector *ov_new);
+bool spapr_ovec_subset(SpaprOptionVector *ov1, SpaprOptionVector *ov2);
void spapr_ovec_cleanup(SpaprOptionVector *ov);
void spapr_ovec_set(SpaprOptionVector *ov, long bitnr);
void spapr_ovec_clear(SpaprOptionVector *ov, long bitnr);
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 56/88] ppc: Deassert the external interrupt pin in KVM on reset
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (54 preceding siblings ...)
2019-12-17 4:42 ` [PULL 55/88] spapr: Simplify ovec diff David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 57/88] xics: Don't deassert outputs David Gibson
` (32 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg,
Satheesh Rajendran, David Gibson
From: Greg Kurz <groug@kaod.org>
When a CPU is reset, QEMU makes sure no interrupt is pending by clearing
CPUPPCstate::pending_interrupts in ppc_cpu_reset(). In the case of a
complete machine emulation, eg. a sPAPR machine, an external interrupt
request could still be pending in KVM though, eg. an IPI. It will be
eventually presented to the guest, which is supposed to acknowledge it at
the interrupt controller. If the interrupt controller is emulated in QEMU,
either XICS or XIVE, ppc_set_irq() won't deassert the external interrupt
pin in KVM since it isn't pending anymore for QEMU. When the vCPU re-enters
the guest, the interrupt request is still pending and the vCPU will try
again to acknowledge it. This causes an infinite loop and eventually hangs
the guest.
The code has been broken since the beginning. The issue wasn't hit before
because accel=kvm,kernel-irqchip=off is an awkward setup that never got
used until recently with the LC92x IBM systems (aka, Boston).
Add a ppc_irq_reset() function to do the necessary cleanup, ie. deassert
the IRQ pins of the CPU in QEMU and most importantly the external interrupt
pin for this vCPU in KVM.
Reported-by: Satheesh Rajendran <sathnaga@linux.vnet.ibm.com>
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157548861740.3650476.16879693165328764758.stgit@bahia.lan>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/ppc.c | 8 ++++++++
include/hw/ppc/ppc.h | 2 ++
target/ppc/translate_init.inc.c | 1 +
3 files changed, 11 insertions(+)
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index 8dd982fc1e..fab73f1b1f 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -1515,3 +1515,11 @@ PowerPCCPU *ppc_get_vcpu_by_pir(int pir)
return NULL;
}
+
+void ppc_irq_reset(PowerPCCPU *cpu)
+{
+ CPUPPCState *env = &cpu->env;
+
+ env->irq_input_state = 0;
+ kvmppc_set_interrupt(cpu, PPC_INTERRUPT_EXT, 0);
+}
diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h
index 585be6ab98..89e1dd065a 100644
--- a/include/hw/ppc/ppc.h
+++ b/include/hw/ppc/ppc.h
@@ -77,6 +77,7 @@ static inline void ppc970_irq_init(PowerPCCPU *cpu) {}
static inline void ppcPOWER7_irq_init(PowerPCCPU *cpu) {}
static inline void ppcPOWER9_irq_init(PowerPCCPU *cpu) {}
static inline void ppce500_irq_init(PowerPCCPU *cpu) {}
+static inline void ppc_irq_reset(PowerPCCPU *cpu) {}
#else
void ppc40x_irq_init(PowerPCCPU *cpu);
void ppce500_irq_init(PowerPCCPU *cpu);
@@ -84,6 +85,7 @@ void ppc6xx_irq_init(PowerPCCPU *cpu);
void ppc970_irq_init(PowerPCCPU *cpu);
void ppcPOWER7_irq_init(PowerPCCPU *cpu);
void ppcPOWER9_irq_init(PowerPCCPU *cpu);
+void ppc_irq_reset(PowerPCCPU *cpu);
#endif
/* PPC machines for OpenBIOS */
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index ba726dec4d..64a838095c 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -10461,6 +10461,7 @@ static void ppc_cpu_reset(CPUState *s)
env->pending_interrupts = 0;
s->exception_index = POWERPC_EXCP_NONE;
env->error_code = 0;
+ ppc_irq_reset(cpu);
/* tininess for underflow is detected before rounding */
set_float_detect_tininess(float_tininess_before_rounding,
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 57/88] xics: Don't deassert outputs
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (55 preceding siblings ...)
2019-12-17 4:42 ` [PULL 56/88] ppc: Deassert the external interrupt pin in KVM on reset David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 58/88] ppc: Don't use CPUPPCState::irq_input_state with modern Book3s CPU models David Gibson
` (31 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
The correct way to do this is to deassert the input pins on the CPU side.
This is the case since a previous change.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157548862298.3650476.1228720391270249433.stgit@bahia.lan>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/xics.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/hw/intc/xics.c b/hw/intc/xics.c
index 0b259a09c5..1952009e6d 100644
--- a/hw/intc/xics.c
+++ b/hw/intc/xics.c
@@ -289,9 +289,6 @@ void icp_reset(ICPState *icp)
icp->pending_priority = 0xff;
icp->mfrr = 0xff;
- /* Make all outputs are deasserted */
- qemu_set_irq(icp->output, 0);
-
if (kvm_irqchip_in_kernel()) {
Error *local_err = NULL;
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 58/88] ppc: Don't use CPUPPCState::irq_input_state with modern Book3s CPU models
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (56 preceding siblings ...)
2019-12-17 4:42 ` [PULL 57/88] xics: Don't deassert outputs David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 59/88] ppc: Ignore the CPU_INTERRUPT_EXITTB interrupt with KVM David Gibson
` (30 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
The power7_set_irq() and power9_set_irq() functions set this but it is
never used actually. Modern Book3s compatible CPUs are only supported
by the pnv and spapr machines. They have an interrupt controller, XICS
for POWER7/8 and XIVE for POWER9, whose models don't require to track
IRQ input states at the CPU level.
Drop these lines to avoid confusion.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157548862861.3650476.16622818876928044450.stgit@bahia.lan>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/ppc.c | 16 ++--------------
target/ppc/cpu.h | 4 +++-
2 files changed, 5 insertions(+), 15 deletions(-)
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index fab73f1b1f..45834f98d1 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -275,10 +275,9 @@ void ppc970_irq_init(PowerPCCPU *cpu)
static void power7_set_irq(void *opaque, int pin, int level)
{
PowerPCCPU *cpu = opaque;
- CPUPPCState *env = &cpu->env;
LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
- env, pin, level);
+ &cpu->env, pin, level);
switch (pin) {
case POWER7_INPUT_INT:
@@ -292,11 +291,6 @@ static void power7_set_irq(void *opaque, int pin, int level)
LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
return;
}
- if (level) {
- env->irq_input_state |= 1 << pin;
- } else {
- env->irq_input_state &= ~(1 << pin);
- }
}
void ppcPOWER7_irq_init(PowerPCCPU *cpu)
@@ -311,10 +305,9 @@ void ppcPOWER7_irq_init(PowerPCCPU *cpu)
static void power9_set_irq(void *opaque, int pin, int level)
{
PowerPCCPU *cpu = opaque;
- CPUPPCState *env = &cpu->env;
LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
- env, pin, level);
+ &cpu->env, pin, level);
switch (pin) {
case POWER9_INPUT_INT:
@@ -334,11 +327,6 @@ static void power9_set_irq(void *opaque, int pin, int level)
LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
return;
}
- if (level) {
- env->irq_input_state |= 1 << pin;
- } else {
- env->irq_input_state &= ~(1 << pin);
- }
}
void ppcPOWER9_irq_init(PowerPCCPU *cpu)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index e3e82327b7..f9528fc29d 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1090,7 +1090,9 @@ struct CPUPPCState {
#if !defined(CONFIG_USER_ONLY)
/*
* This is the IRQ controller, which is implementation dependent
- * and only relevant when emulating a complete machine.
+ * and only relevant when emulating a complete machine. Note that
+ * this isn't used by recent Book3s compatible CPUs (POWER7 and
+ * newer).
*/
uint32_t irq_input_state;
void **irq_inputs;
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 59/88] ppc: Ignore the CPU_INTERRUPT_EXITTB interrupt with KVM
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (57 preceding siblings ...)
2019-12-17 4:42 ` [PULL 58/88] ppc: Don't use CPUPPCState::irq_input_state with modern Book3s CPU models David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 60/88] ppc: Make PPCVirtualHypervisor an incomplete type David Gibson
` (29 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
This only makes sense with an emulated CPU. Don't set the bit in
CPUState::interrupt_request when using KVM to avoid confusions.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157548863423.3650476.16424649423510075159.stgit@bahia.lan>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/helper_regs.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/ppc/helper_regs.h b/target/ppc/helper_regs.h
index 85dfe7687f..d78c2af63e 100644
--- a/target/ppc/helper_regs.h
+++ b/target/ppc/helper_regs.h
@@ -22,6 +22,7 @@
#include "qemu/main-loop.h"
#include "exec/exec-all.h"
+#include "sysemu/kvm.h"
/* Swap temporary saved registers with GPRs */
static inline void hreg_swap_gpr_tgpr(CPUPPCState *env)
@@ -102,6 +103,10 @@ static inline void hreg_compute_hflags(CPUPPCState *env)
static inline void cpu_interrupt_exittb(CPUState *cs)
{
+ if (!kvm_enabled()) {
+ return;
+ }
+
if (!qemu_mutex_iothread_locked()) {
qemu_mutex_lock_iothread();
cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 60/88] ppc: Make PPCVirtualHypervisor an incomplete type
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (58 preceding siblings ...)
2019-12-17 4:42 ` [PULL 59/88] ppc: Ignore the CPU_INTERRUPT_EXITTB interrupt with KVM David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 61/88] target/ppc: Add POWER10 DD1.0 model information David Gibson
` (28 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
PPCVirtualHypervisor is an interface instance. It should never be
dereferenced. Drop the dummy type definition for extra safety, which
is the common practice with QOM interfaces.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157589808041.21182.18121655959115011353.stgit@bahia.lan>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu.h | 4 ----
1 file changed, 4 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index f9528fc29d..60cf030ce6 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1222,10 +1222,6 @@ PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc);
-struct PPCVirtualHypervisor {
- Object parent;
-};
-
struct PPCVirtualHypervisorClass {
InterfaceClass parent;
void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 61/88] target/ppc: Add POWER10 DD1.0 model information
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (59 preceding siblings ...)
2019-12-17 4:42 ` [PULL 60/88] ppc: Make PPCVirtualHypervisor an incomplete type David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 62/88] ppc/pnv: Introduce a POWER10 PnvChip and a powernv10 machine David Gibson
` (27 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
This includes in QEMU a new CPU model for the POWER10 processor with
the same capabilities of a POWER9 process. The model will be extended
when support is completed.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191205184454.10722-2-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/compat.c | 21 +++-
target/ppc/cpu-models.c | 3 +
target/ppc/cpu-models.h | 3 +
target/ppc/cpu.h | 1 +
target/ppc/translate_init.inc.c | 215 ++++++++++++++++++++++++++++++++
5 files changed, 237 insertions(+), 6 deletions(-)
diff --git a/target/ppc/compat.c b/target/ppc/compat.c
index 7de4bf3122..f48df25944 100644
--- a/target/ppc/compat.c
+++ b/target/ppc/compat.c
@@ -51,36 +51,38 @@ static const CompatInfo compat_table[] = {
{ /* POWER6, ISA2.05 */
.name = "power6",
.pvr = CPU_POWERPC_LOGICAL_2_05,
- .pcr = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
- PCR_COMPAT_2_05 | PCR_TM_DIS | PCR_VSX_DIS,
+ .pcr = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 |
+ PCR_COMPAT_2_06 | PCR_COMPAT_2_05 | PCR_TM_DIS | PCR_VSX_DIS,
.pcr_level = PCR_COMPAT_2_05,
.max_vthreads = 2,
},
{ /* POWER7, ISA2.06 */
.name = "power7",
.pvr = CPU_POWERPC_LOGICAL_2_06,
- .pcr = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_TM_DIS,
+ .pcr = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 |
+ PCR_COMPAT_2_06 | PCR_TM_DIS,
.pcr_level = PCR_COMPAT_2_06,
.max_vthreads = 4,
},
{
.name = "power7+",
.pvr = CPU_POWERPC_LOGICAL_2_06_PLUS,
- .pcr = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_TM_DIS,
+ .pcr = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 |
+ PCR_COMPAT_2_06 | PCR_TM_DIS,
.pcr_level = PCR_COMPAT_2_06,
.max_vthreads = 4,
},
{ /* POWER8, ISA2.07 */
.name = "power8",
.pvr = CPU_POWERPC_LOGICAL_2_07,
- .pcr = PCR_COMPAT_3_00 | PCR_COMPAT_2_07,
+ .pcr = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07,
.pcr_level = PCR_COMPAT_2_07,
.max_vthreads = 8,
},
{ /* POWER9, ISA3.00 */
.name = "power9",
.pvr = CPU_POWERPC_LOGICAL_3_00,
- .pcr = PCR_COMPAT_3_00,
+ .pcr = PCR_COMPAT_3_10 | PCR_COMPAT_3_00,
.pcr_level = PCR_COMPAT_3_00,
/*
* POWER9 hardware only supports 4 threads / core, but this
@@ -91,6 +93,13 @@ static const CompatInfo compat_table[] = {
*/
.max_vthreads = 8,
},
+ { /* POWER10, ISA3.10 */
+ .name = "power10",
+ .pvr = CPU_POWERPC_LOGICAL_3_10,
+ .pcr = PCR_COMPAT_3_10,
+ .pcr_level = PCR_COMPAT_3_10,
+ .max_vthreads = 8,
+ },
};
static const CompatInfo *compat_by_pvr(uint32_t pvr)
diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c
index 086548e9b9..4ad16863c0 100644
--- a/target/ppc/cpu-models.c
+++ b/target/ppc/cpu-models.c
@@ -774,6 +774,8 @@
"POWER9 v1.0")
POWERPC_DEF("power9_v2.0", CPU_POWERPC_POWER9_DD20, POWER9,
"POWER9 v2.0")
+ POWERPC_DEF("power10_v1.0", CPU_POWERPC_POWER10_DD1, POWER10,
+ "POWER10 v1.0")
#endif /* defined (TARGET_PPC64) */
/***************************************************************************/
@@ -950,6 +952,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "power8", "power8_v2.0" },
{ "power8nvl", "power8nvl_v1.0" },
{ "power9", "power9_v2.0" },
+ { "power10", "power10_v1.0" },
#endif
/* Generic PowerPCs */
diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h
index 4fdb73034d..ce750b2d55 100644
--- a/target/ppc/cpu-models.h
+++ b/target/ppc/cpu-models.h
@@ -373,6 +373,8 @@ enum {
CPU_POWERPC_POWER9_BASE = 0x004E0000,
CPU_POWERPC_POWER9_DD1 = 0x004E0100,
CPU_POWERPC_POWER9_DD20 = 0x004E1200,
+ CPU_POWERPC_POWER10_BASE = 0x00800000,
+ CPU_POWERPC_POWER10_DD1 = 0x00800100,
CPU_POWERPC_970_v22 = 0x00390202,
CPU_POWERPC_970FX_v10 = 0x00391100,
CPU_POWERPC_970FX_v20 = 0x003C0200,
@@ -409,6 +411,7 @@ enum {
CPU_POWERPC_LOGICAL_2_06_PLUS = 0x0F100003,
CPU_POWERPC_LOGICAL_2_07 = 0x0F000004,
CPU_POWERPC_LOGICAL_3_00 = 0x0F000005,
+ CPU_POWERPC_LOGICAL_3_10 = 0x0F000006,
};
/* System version register (used on MPC 8xxx) */
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 60cf030ce6..fbec1b0cd5 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2364,6 +2364,7 @@ enum {
PCR_COMPAT_2_06 = PPC_BIT(61),
PCR_COMPAT_2_07 = PPC_BIT(60),
PCR_COMPAT_3_00 = PPC_BIT(59),
+ PCR_COMPAT_3_10 = PPC_BIT(58),
PCR_VEC_DIS = PPC_BIT(0), /* Vec. disable (bit NA since POWER8) */
PCR_VSX_DIS = PPC_BIT(1), /* VSX disable (bit NA since POWER8) */
PCR_TM_DIS = PPC_BIT(2), /* Trans. memory disable (POWER8) */
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index 64a838095c..7364d36b07 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -3354,6 +3354,11 @@ static void init_excp_POWER9(CPUPPCState *env)
#endif
}
+static void init_excp_POWER10(CPUPPCState *env)
+{
+ init_excp_POWER9(env);
+}
+
#endif
/*****************************************************************************/
@@ -8996,6 +9001,216 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
}
+#ifdef CONFIG_SOFTMMU
+/*
+ * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
+ * Encoded as array of int_32s in the form:
+ * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
+ * x -> AP encoding
+ * y -> radix mode supported page size (encoded as a shift)
+ */
+static struct ppc_radix_page_info POWER10_radix_page_info = {
+ .count = 4,
+ .entries = {
+ 0x0000000c, /* 4K - enc: 0x0 */
+ 0xa0000010, /* 64K - enc: 0x5 */
+ 0x20000015, /* 2M - enc: 0x1 */
+ 0x4000001e /* 1G - enc: 0x2 */
+ }
+};
+#endif /* CONFIG_SOFTMMU */
+
+static void init_proc_POWER10(CPUPPCState *env)
+{
+ /* Common Registers */
+ init_proc_book3s_common(env);
+ gen_spr_book3s_207_dbg(env);
+
+ /* POWER8 Specific Registers */
+ gen_spr_book3s_ids(env);
+ gen_spr_amr(env);
+ gen_spr_iamr(env);
+ gen_spr_book3s_purr(env);
+ gen_spr_power5p_common(env);
+ gen_spr_power5p_lpar(env);
+ gen_spr_power5p_ear(env);
+ gen_spr_power6_common(env);
+ gen_spr_power6_dbg(env);
+ gen_spr_power8_tce_address_control(env);
+ gen_spr_power8_ids(env);
+ gen_spr_power8_ebb(env);
+ gen_spr_power8_fscr(env);
+ gen_spr_power8_pmu_sup(env);
+ gen_spr_power8_pmu_user(env);
+ gen_spr_power8_tm(env);
+ gen_spr_power8_pspb(env);
+ gen_spr_vtb(env);
+ gen_spr_power8_ic(env);
+ gen_spr_power8_book4(env);
+ gen_spr_power8_rpr(env);
+ gen_spr_power9_mmu(env);
+
+ /* POWER9 Specific registers */
+ spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
+ spr_read_generic, spr_write_generic,
+ KVM_REG_PPC_TIDR, 0);
+
+ /* FIXME: Filter fields properly based on privilege level */
+ spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
+ spr_read_generic, spr_write_generic,
+ KVM_REG_PPC_PSSCR, 0);
+
+ /* env variables */
+ env->dcache_line_size = 128;
+ env->icache_line_size = 128;
+
+ /* Allocate hardware IRQ controller */
+ init_excp_POWER10(env);
+ ppcPOWER9_irq_init(env_archcpu(env));
+}
+
+static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr)
+{
+ if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) {
+ return true;
+ }
+ return false;
+}
+
+static bool cpu_has_work_POWER10(CPUState *cs)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
+
+ if (cs->halted) {
+ uint64_t psscr = env->spr[SPR_PSSCR];
+
+ if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
+ return false;
+ }
+
+ /* If EC is clear, just return true on any pending interrupt */
+ if (!(psscr & PSSCR_EC)) {
+ return true;
+ }
+ /* External Exception */
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
+ (env->spr[SPR_LPCR] & LPCR_EEE)) {
+ bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
+ if (heic == 0 || !msr_hv || msr_pr) {
+ return true;
+ }
+ }
+ /* Decrementer Exception */
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
+ (env->spr[SPR_LPCR] & LPCR_DEE)) {
+ return true;
+ }
+ /* Machine Check or Hypervisor Maintenance Exception */
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
+ 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
+ return true;
+ }
+ /* Privileged Doorbell Exception */
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
+ (env->spr[SPR_LPCR] & LPCR_PDEE)) {
+ return true;
+ }
+ /* Hypervisor Doorbell Exception */
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
+ (env->spr[SPR_LPCR] & LPCR_HDEE)) {
+ return true;
+ }
+ /* Hypervisor virtualization exception */
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
+ (env->spr[SPR_LPCR] & LPCR_HVEE)) {
+ return true;
+ }
+ if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
+ return true;
+ }
+ return false;
+ } else {
+ return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
+ }
+}
+
+POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ CPUClass *cc = CPU_CLASS(oc);
+
+ dc->fw_name = "PowerPC,POWER10";
+ dc->desc = "POWER10";
+ dc->props = powerpc_servercpu_properties;
+ pcc->pvr_match = ppc_pvr_match_power10;
+ pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 |
+ PCR_COMPAT_3_00;
+ pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 |
+ PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
+ pcc->init_proc = init_proc_POWER10;
+ pcc->check_pow = check_pow_nocheck;
+ cc->has_work = cpu_has_work_POWER10;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_FRSQRTES |
+ PPC_FLOAT_STFIWX |
+ PPC_FLOAT_EXT |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBSYNC |
+ PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
+ PPC_SEGMENT_64B | PPC_SLBI |
+ PPC_POPCNTB | PPC_POPCNTWD |
+ PPC_CILDST;
+ pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
+ PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
+ PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
+ PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
+ PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
+ PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
+ PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
+ pcc->msr_mask = (1ull << MSR_SF) |
+ (1ull << MSR_SHV) |
+ (1ull << MSR_TM) |
+ (1ull << MSR_VR) |
+ (1ull << MSR_VSX) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_PMM) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_3_00;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
+ /* segment page size remain the same */
+ pcc->hash64_opts = &ppc_hash64_opts_POWER7;
+ pcc->radix_page_info = &POWER10_radix_page_info;
+ pcc->lrg_decr_bits = 56;
+#endif
+ pcc->excp_model = POWERPC_EXCP_POWER9;
+ pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
+ pcc->bfd_mach = bfd_mach_ppc64;
+ pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
+ POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
+ POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
+ pcc->l1_dcache_size = 0x8000;
+ pcc->l1_icache_size = 0x8000;
+ pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+ pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
+}
+
#if !defined(CONFIG_USER_ONLY)
void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
{
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 62/88] ppc/pnv: Introduce a POWER10 PnvChip and a powernv10 machine
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (60 preceding siblings ...)
2019-12-17 4:42 ` [PULL 61/88] target/ppc: Add POWER10 DD1.0 model information David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 63/88] ppc/psi: cleanup definitions David Gibson
` (26 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
This is an empty shell with the XSCOM bus and cores. The chip controllers
will come later.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191205184454.10722-3-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 158 +++++++++++++++++++++++++++++++++++--
hw/ppc/pnv_core.c | 10 +++
hw/ppc/pnv_xscom.c | 23 ++++--
include/hw/ppc/pnv.h | 33 ++++++++
include/hw/ppc/pnv_xscom.h | 19 +++++
5 files changed, 232 insertions(+), 11 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index fa656858b2..d99cd72840 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -317,6 +317,23 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
pnv_dt_lpc(chip, fdt, 0);
}
+static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
+{
+ int i;
+
+ pnv_dt_xscom(chip, fdt, 0);
+
+ for (i = 0; i < chip->nr_cores; i++) {
+ PnvCore *pnv_core = chip->cores[i];
+
+ pnv_dt_core(chip, pnv_core, fdt);
+ }
+
+ if (chip->ram_size) {
+ pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
+ }
+}
+
static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
{
uint32_t io_base = d->ioport_id;
@@ -467,6 +484,7 @@ static void *pnv_dt_create(MachineState *machine)
{
const char plat_compat8[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
const char plat_compat9[] = "qemu,powernv9\0ibm,powernv";
+ const char plat_compat10[] = "qemu,powernv10\0ibm,powernv";
PnvMachineState *pnv = PNV_MACHINE(machine);
void *fdt;
char *buf;
@@ -484,7 +502,10 @@ static void *pnv_dt_create(MachineState *machine)
_FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
_FDT((fdt_setprop_string(fdt, 0, "model",
"IBM PowerNV (emulated by qemu)")));
- if (pnv_is_power9(pnv)) {
+ if (pnv_is_power10(pnv)) {
+ _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat10,
+ sizeof(plat_compat10))));
+ } else if (pnv_is_power9(pnv)) {
_FDT((fdt_setprop(fdt, 0, "compatible", plat_compat9,
sizeof(plat_compat9))));
} else {
@@ -528,8 +549,8 @@ static void *pnv_dt_create(MachineState *machine)
pnv_dt_bmc_sensors(pnv->bmc, fdt);
}
- /* Create an extra node for power management on Power9 */
- if (pnv_is_power9(pnv)) {
+ /* Create an extra node for power management on Power9 and Power10 */
+ if (pnv_is_power9(pnv) || pnv_is_power10(pnv)) {
pnv_dt_power_mgt(fdt);
}
@@ -578,6 +599,12 @@ static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
return pnv_lpc_isa_create(&chip9->lpc, false, errp);
}
+static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
+{
+ error_setg(errp, "No ISA bus!");
+ return NULL;
+}
+
static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
{
return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
@@ -618,6 +645,13 @@ static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq)
object_property_set_bool(obj, true, "realized", &error_fatal);
}
+static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon)
+{
+ /*
+ * No interrupt controller yet
+ */;
+}
+
static void pnv_init(MachineState *machine)
{
PnvMachineState *pnv = PNV_MACHINE(machine);
@@ -822,6 +856,11 @@ static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
return (chip->chip_id << 8) | (core_id << 2);
}
+static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id)
+{
+ return (chip->chip_id << 8) | (core_id << 2);
+}
+
static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
Error **errp)
{
@@ -859,6 +898,27 @@ static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
pnv_cpu->intc = NULL;
}
+static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu,
+ Error **errp)
+{
+ PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
+
+ /* Will be defined when the interrupt controller is */
+ pnv_cpu->intc = NULL;
+}
+
+static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
+{
+ ;
+}
+
+static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
+{
+ PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
+
+ pnv_cpu->intc = NULL;
+}
+
/*
* Allowed core identifiers on a POWER8 Processor Chip :
*
@@ -886,6 +946,9 @@ static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
*/
#define POWER9_CORE_MASK (0xffffffffffffffull)
+
+#define POWER10_CORE_MASK (0xffffffffffffffull)
+
static void pnv_chip_power8_instance_init(Object *obj)
{
Pnv8Chip *chip8 = PNV8_CHIP(obj);
@@ -1246,6 +1309,56 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
&k->parent_realize);
}
+static void pnv_chip_power10_instance_init(Object *obj)
+{
+ /*
+ * No controllers yet
+ */
+ ;
+}
+
+static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
+{
+ PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
+ PnvChip *chip = PNV_CHIP(dev);
+ Error *local_err = NULL;
+
+ /* XSCOM bridge is first */
+ pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip));
+
+ pcc->parent_realize(dev, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+}
+
+static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PnvChipClass *k = PNV_CHIP_CLASS(klass);
+
+ k->chip_type = PNV_CHIP_POWER10;
+ k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */
+ k->cores_mask = POWER10_CORE_MASK;
+ k->core_pir = pnv_chip_core_pir_p10;
+ k->intc_create = pnv_chip_power10_intc_create;
+ k->intc_reset = pnv_chip_power10_intc_reset;
+ k->intc_destroy = pnv_chip_power10_intc_destroy;
+ k->isa_create = pnv_chip_power10_isa_create;
+ k->dt_populate = pnv_chip_power10_dt_populate;
+ k->pic_print_info = pnv_chip_power10_pic_print_info;
+ dc->desc = "PowerNV Chip POWER10";
+
+ device_class_set_parent_realize(dc, pnv_chip_power10_realize,
+ &k->parent_realize);
+}
+
static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
{
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
@@ -1327,10 +1440,12 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
&error_fatal);
/* Each core has an XSCOM MMIO region */
- if (!pnv_chip_is_power9(chip)) {
- xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid);
- } else {
+ if (pnv_chip_is_power10(chip)) {
+ xscom_core_base = PNV10_XSCOM_EC_BASE(core_hwid);
+ } else if (pnv_chip_is_power9(chip)) {
xscom_core_base = PNV9_XSCOM_EC_BASE(core_hwid);
+ } else {
+ xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid);
}
pnv_xscom_add_subregion(chip, xscom_core_base,
@@ -1558,6 +1673,14 @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
mc->alias = "powernv";
}
+static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
+ mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0");
+}
+
static void pnv_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -1595,7 +1718,19 @@ static void pnv_machine_class_init(ObjectClass *oc, void *data)
.parent = TYPE_PNV9_CHIP, \
}
+#define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \
+ { \
+ .name = type, \
+ .class_init = class_initfn, \
+ .parent = TYPE_PNV10_CHIP, \
+ }
+
static const TypeInfo types[] = {
+ {
+ .name = MACHINE_TYPE_NAME("powernv10"),
+ .parent = TYPE_PNV_MACHINE,
+ .class_init = pnv_machine_power10_class_init,
+ },
{
.name = MACHINE_TYPE_NAME("powernv9"),
.parent = TYPE_PNV_MACHINE,
@@ -1635,6 +1770,17 @@ static const TypeInfo types[] = {
.abstract = true,
},
+ /*
+ * P10 chip and variants
+ */
+ {
+ .name = TYPE_PNV10_CHIP,
+ .parent = TYPE_PNV_CHIP,
+ .instance_init = pnv_chip_power10_instance_init,
+ .instance_size = sizeof(Pnv10Chip),
+ },
+ DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init),
+
/*
* P9 chip and variants
*/
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 5ab75bde6c..2651044278 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -247,6 +247,7 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
}
snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id);
+ /* TODO: check PNV_XSCOM_EX_SIZE for p10 */
pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops,
pc, name, PNV_XSCOM_EX_SIZE);
@@ -308,6 +309,14 @@ static void pnv_core_power9_class_init(ObjectClass *oc, void *data)
pcc->xscom_ops = &pnv_core_power9_xscom_ops;
}
+static void pnv_core_power10_class_init(ObjectClass *oc, void *data)
+{
+ PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
+
+ /* TODO: Use the P9 XSCOMs for now on P10 */
+ pcc->xscom_ops = &pnv_core_power9_xscom_ops;
+}
+
static void pnv_core_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -337,6 +346,7 @@ static const TypeInfo pnv_core_infos[] = {
DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"),
DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"),
DEFINE_PNV_CORE_TYPE(power9, "power9_v2.0"),
+ DEFINE_PNV_CORE_TYPE(power10, "power10_v1.0"),
};
DEFINE_TYPES(pnv_core_infos)
diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c
index f01d788a65..b3d3b6e350 100644
--- a/hw/ppc/pnv_xscom.c
+++ b/hw/ppc/pnv_xscom.c
@@ -69,10 +69,16 @@ static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr)
{
addr &= (PNV_XSCOM_SIZE - 1);
- if (pnv_chip_is_power9(chip)) {
- return addr >> 3;
- } else {
+ switch (PNV_CHIP_GET_CLASS(chip)->chip_type) {
+ case PNV_CHIP_POWER8E:
+ case PNV_CHIP_POWER8:
+ case PNV_CHIP_POWER8NVL:
return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
+ case PNV_CHIP_POWER9:
+ case PNV_CHIP_POWER10:
+ return addr >> 3;
+ default:
+ g_assert_not_reached();
}
}
@@ -307,6 +313,7 @@ static int xscom_dt_child(Object *child, void *opaque)
static const char compat_p8[] = "ibm,power8-xscom\0ibm,xscom";
static const char compat_p9[] = "ibm,power9-xscom\0ibm,xscom";
+static const char compat_p10[] = "ibm,power10-xscom\0ibm,xscom";
int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset)
{
@@ -315,7 +322,10 @@ int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset)
ForeachPopulateArgs args;
char *name;
- if (pnv_chip_is_power9(chip)) {
+ if (pnv_chip_is_power10(chip)) {
+ reg[0] = cpu_to_be64(PNV10_XSCOM_BASE(chip));
+ reg[1] = cpu_to_be64(PNV10_XSCOM_SIZE);
+ } else if (pnv_chip_is_power9(chip)) {
reg[0] = cpu_to_be64(PNV9_XSCOM_BASE(chip));
reg[1] = cpu_to_be64(PNV9_XSCOM_SIZE);
} else {
@@ -332,7 +342,10 @@ int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset)
_FDT((fdt_setprop_cell(fdt, xscom_offset, "#size-cells", 1)));
_FDT((fdt_setprop(fdt, xscom_offset, "reg", reg, sizeof(reg))));
- if (pnv_chip_is_power9(chip)) {
+ if (pnv_chip_is_power10(chip)) {
+ _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p10,
+ sizeof(compat_p10))));
+ } else if (pnv_chip_is_power9(chip)) {
_FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p9,
sizeof(compat_p9))));
} else {
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 3a7bc3c57e..bfa61edfba 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -43,6 +43,7 @@ typedef enum PnvChipType {
PNV_CHIP_POWER8, /* AKA Venice */
PNV_CHIP_POWER8NVL, /* AKA Naples */
PNV_CHIP_POWER9, /* AKA Nimbus */
+ PNV_CHIP_POWER10, /* AKA TBD */
} PnvChipType;
typedef struct PnvChip {
@@ -105,6 +106,14 @@ typedef struct Pnv9Chip {
#define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
#define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
+#define TYPE_PNV10_CHIP "pnv10-chip"
+#define PNV10_CHIP(obj) OBJECT_CHECK(Pnv10Chip, (obj), TYPE_PNV10_CHIP)
+
+typedef struct Pnv10Chip {
+ /*< private >*/
+ PnvChip parent_obj;
+} Pnv10Chip;
+
typedef struct PnvChipClass {
/*< private >*/
SysBusDeviceClass parent_class;
@@ -144,6 +153,10 @@ typedef struct PnvChipClass {
#define PNV_CHIP_POWER9(obj) \
OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9)
+#define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v1.0")
+#define PNV_CHIP_POWER10(obj) \
+ OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER10)
+
/*
* This generates a HW chip id depending on an index, as found on a
* two socket system with dual chip modules :
@@ -203,6 +216,16 @@ PnvChip *pnv_get_chip(uint32_t chip_id);
#define PNV_FDT_ADDR 0x01000000
#define PNV_TIMEBASE_FREQ 512000000ULL
+static inline bool pnv_chip_is_power10(const PnvChip *chip)
+{
+ return PNV_CHIP_GET_CLASS(chip)->chip_type == PNV_CHIP_POWER10;
+}
+
+static inline bool pnv_is_power10(PnvMachineState *pnv)
+{
+ return pnv_chip_is_power10(pnv->chips[0]);
+}
+
/*
* BMC helpers
*/
@@ -293,4 +316,14 @@ IPMIBmc *pnv_bmc_create(void);
#define PNV9_HOMER_SIZE 0x0000000000300000ull
#define PNV9_HOMER_BASE(chip) \
(0x203ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV9_HOMER_SIZE)
+
+/*
+ * POWER10 MMIO base addresses - 16TB stride per chip
+ */
+#define PNV10_CHIP_BASE(chip, base) \
+ ((base) + ((uint64_t) (chip)->chip_id << 44))
+
+#define PNV10_XSCOM_SIZE 0x0000000400000000ull
+#define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull)
+
#endif /* PPC_PNV_H */
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index 67641ed278..790eb3d8f3 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -70,6 +70,9 @@ typedef struct PnvXScomInterfaceClass {
#define PNV_XSCOM_OCC_BASE 0x0066000
#define PNV_XSCOM_OCC_SIZE 0x6000
+/*
+ * Layout of the XSCOM PCB addresses (POWER 9)
+ */
#define PNV9_XSCOM_EC_BASE(core) \
((uint64_t)(((core) & 0x1F) + 0x20) << 24)
#define PNV9_XSCOM_EC_SIZE 0x100000
@@ -87,6 +90,22 @@ typedef struct PnvXScomInterfaceClass {
#define PNV9_XSCOM_XIVE_BASE 0x5013000
#define PNV9_XSCOM_XIVE_SIZE 0x300
+/*
+ * Layout of the XSCOM PCB addresses (POWER 10)
+ */
+#define PNV10_XSCOM_EQ_CHIPLET(core) (0x20 + ((core) >> 2))
+#define PNV10_XSCOM_EQ(chiplet) ((chiplet) << 24)
+#define PNV10_XSCOM_EC(proc) \
+ ((0x2 << 16) | ((1 << (3 - (proc))) << 12))
+
+#define PNV10_XSCOM_EQ_BASE(core) \
+ ((uint64_t) PNV10_XSCOM_EQ(PNV10_XSCOM_EQ_CHIPLET(core)))
+#define PNV10_XSCOM_EQ_SIZE 0x100000
+
+#define PNV10_XSCOM_EC_BASE(core) \
+ ((uint64_t) PNV10_XSCOM_EQ_BASE(core) | PNV10_XSCOM_EC(core & 0x3))
+#define PNV10_XSCOM_EC_SIZE 0x100000
+
extern void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp);
extern int pnv_dt_xscom(PnvChip *chip, void *fdt, int offset);
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 63/88] ppc/psi: cleanup definitions
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (61 preceding siblings ...)
2019-12-17 4:42 ` [PULL 62/88] ppc/pnv: Introduce a POWER10 PnvChip and a powernv10 machine David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 64/88] ppc/pnv: add a PSI bridge model for POWER10 David Gibson
` (25 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191205184454.10722-4-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv_psi.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index 7e725aaf2b..e6c266ac4a 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -608,9 +608,12 @@ static const TypeInfo pnv_psi_power8_info = {
#define PSIHB9_IRQ_METHOD PPC_BIT(0)
#define PSIHB9_IRQ_RESET PPC_BIT(1)
#define PSIHB9_ESB_CI_BASE 0x60
-#define PSIHB9_ESB_CI_VALID 1
+#define PSIHB9_ESB_CI_64K PPC_BIT(1)
+#define PSIHB9_ESB_CI_ADDR_MASK PPC_BITMASK(8, 47)
+#define PSIHB9_ESB_CI_VALID PPC_BIT(63)
#define PSIHB9_ESB_NOTIF_ADDR 0x68
-#define PSIHB9_ESB_NOTIF_VALID 1
+#define PSIHB9_ESB_NOTIF_ADDR_MASK PPC_BITMASK(8, 60)
+#define PSIHB9_ESB_NOTIF_VALID PPC_BIT(63)
#define PSIHB9_IVT_OFFSET 0x70
#define PSIHB9_IVT_OFF_SHIFT 32
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 64/88] ppc/pnv: add a PSI bridge model for POWER10
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (62 preceding siblings ...)
2019-12-17 4:42 ` [PULL 63/88] ppc/psi: cleanup definitions David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:42 ` [PULL 65/88] ppc/pnv: add a LPC Controller " David Gibson
` (24 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
The POWER10 PSIHB controller is very similar to the one on POWER9. We
should probably introduce a common PnvPsiXive object.
The ESB page size should be changed to 64k when P10 support is ready.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191205184454.10722-5-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 27 ++++++++++++++++++++-------
hw/ppc/pnv_psi.c | 25 ++++++++++++++++++++++++-
include/hw/ppc/pnv.h | 9 +++++++++
include/hw/ppc/pnv_psi.h | 2 ++
include/hw/ppc/pnv_xscom.h | 3 +++
5 files changed, 58 insertions(+), 8 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index d99cd72840..09263ab747 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -647,9 +647,9 @@ static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq)
static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon)
{
- /*
- * No interrupt controller yet
- */;
+ Pnv10Chip *chip10 = PNV10_CHIP(chip);
+
+ pnv_psi_pic_print_info(&chip10->psi, mon);
}
static void pnv_init(MachineState *machine)
@@ -1311,16 +1311,17 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
static void pnv_chip_power10_instance_init(Object *obj)
{
- /*
- * No controllers yet
- */
- ;
+ Pnv10Chip *chip10 = PNV10_CHIP(obj);
+
+ object_initialize_child(obj, "psi", &chip10->psi, sizeof(chip10->psi),
+ TYPE_PNV10_PSI, &error_abort, NULL);
}
static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
{
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
PnvChip *chip = PNV_CHIP(dev);
+ Pnv10Chip *chip10 = PNV10_CHIP(dev);
Error *local_err = NULL;
/* XSCOM bridge is first */
@@ -1336,6 +1337,18 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
error_propagate(errp, local_err);
return;
}
+
+ /* Processor Service Interface (PSI) Host Bridge */
+ object_property_set_int(OBJECT(&chip10->psi), PNV10_PSIHB_BASE(chip),
+ "bar", &error_fatal);
+ object_property_set_bool(OBJECT(&chip10->psi), true, "realized",
+ &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+ pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE,
+ &PNV_PSI(&chip10->psi)->xscom_regs);
}
static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index e6c266ac4a..572924388b 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -538,6 +538,7 @@ static void pnv_psi_power8_realize(DeviceState *dev, Error **errp)
static const char compat_p8[] = "ibm,power8-psihb-x\0ibm,psihb-x";
static const char compat_p9[] = "ibm,power9-psihb-x\0ibm,psihb-x";
+static const char compat_p10[] = "ibm,power10-psihb-x\0ibm,psihb-x";
static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
{
@@ -557,7 +558,10 @@ static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
_FDT(fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)));
_FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 2));
_FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1));
- if (ppc->chip_type == PNV_CHIP_POWER9) {
+ if (ppc->chip_type == PNV_CHIP_POWER10) {
+ _FDT(fdt_setprop(fdt, offset, "compatible", compat_p10,
+ sizeof(compat_p10)));
+ } else if (ppc->chip_type == PNV_CHIP_POWER9) {
_FDT(fdt_setprop(fdt, offset, "compatible", compat_p9,
sizeof(compat_p9)));
} else {
@@ -909,6 +913,24 @@ static const TypeInfo pnv_psi_power9_info = {
},
};
+static void pnv_psi_power10_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PnvPsiClass *ppc = PNV_PSI_CLASS(klass);
+
+ dc->desc = "PowerNV PSI Controller POWER10";
+
+ ppc->chip_type = PNV_CHIP_POWER10;
+ ppc->xscom_pcba = PNV10_XSCOM_PSIHB_BASE;
+ ppc->xscom_size = PNV10_XSCOM_PSIHB_SIZE;
+}
+
+static const TypeInfo pnv_psi_power10_info = {
+ .name = TYPE_PNV10_PSI,
+ .parent = TYPE_PNV9_PSI,
+ .class_init = pnv_psi_power10_class_init,
+};
+
static void pnv_psi_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -938,6 +960,7 @@ static void pnv_psi_register_types(void)
type_register_static(&pnv_psi_info);
type_register_static(&pnv_psi_power8_info);
type_register_static(&pnv_psi_power9_info);
+ type_register_static(&pnv_psi_power10_info);
}
type_init(pnv_psi_register_types);
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index bfa61edfba..47b7370b27 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -112,6 +112,9 @@ typedef struct Pnv9Chip {
typedef struct Pnv10Chip {
/*< private >*/
PnvChip parent_obj;
+
+ /*< public >*/
+ Pnv9Psi psi;
} Pnv10Chip;
typedef struct PnvChipClass {
@@ -326,4 +329,10 @@ IPMIBmc *pnv_bmc_create(void);
#define PNV10_XSCOM_SIZE 0x0000000400000000ull
#define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull)
+#define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull
+#define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull)
+
+#define PNV10_PSIHB_SIZE 0x0000000000100000ull
+#define PNV10_PSIHB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203000000ull)
+
#endif /* PPC_PNV_H */
diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h
index e82df9709f..a044aab304 100644
--- a/include/hw/ppc/pnv_psi.h
+++ b/include/hw/ppc/pnv_psi.h
@@ -69,6 +69,8 @@ typedef struct Pnv9Psi {
XiveSource source;
} Pnv9Psi;
+#define TYPE_PNV10_PSI TYPE_PNV_PSI "-POWER10"
+
#define PNV_PSI_CLASS(klass) \
OBJECT_CLASS_CHECK(PnvPsiClass, (klass), TYPE_PNV_PSI)
#define PNV_PSI_GET_CLASS(obj) \
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index 790eb3d8f3..a40d2a2a2a 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -106,6 +106,9 @@ typedef struct PnvXScomInterfaceClass {
((uint64_t) PNV10_XSCOM_EQ_BASE(core) | PNV10_XSCOM_EC(core & 0x3))
#define PNV10_XSCOM_EC_SIZE 0x100000
+#define PNV10_XSCOM_PSIHB_BASE 0x3011D00
+#define PNV10_XSCOM_PSIHB_SIZE 0x100
+
extern void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp);
extern int pnv_dt_xscom(PnvChip *chip, void *fdt, int offset);
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 65/88] ppc/pnv: add a LPC Controller model for POWER10
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (63 preceding siblings ...)
2019-12-17 4:42 ` [PULL 64/88] ppc/pnv: add a PSI bridge model for POWER10 David Gibson
@ 2019-12-17 4:42 ` David Gibson
2019-12-17 4:43 ` [PULL 66/88] target/ppc: Implement the VTB for HV access David Gibson
` (23 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:42 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
Same a POWER9, only the MMIO window changes.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191205184454.10722-6-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 25 ++++++++++++++++++++++---
hw/ppc/pnv_lpc.c | 30 ++++++++++++++++++++++--------
include/hw/ppc/pnv.h | 4 ++++
include/hw/ppc/pnv_lpc.h | 6 +++++-
4 files changed, 53 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 09263ab747..67d0ad55b8 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -314,7 +314,7 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
}
- pnv_dt_lpc(chip, fdt, 0);
+ pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
}
static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
@@ -332,6 +332,8 @@ static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
if (chip->ram_size) {
pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
}
+
+ pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE);
}
static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
@@ -601,8 +603,8 @@ static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
{
- error_setg(errp, "No ISA bus!");
- return NULL;
+ Pnv10Chip *chip10 = PNV10_CHIP(chip);
+ return pnv_lpc_isa_create(&chip10->lpc, false, errp);
}
static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
@@ -1315,6 +1317,8 @@ static void pnv_chip_power10_instance_init(Object *obj)
object_initialize_child(obj, "psi", &chip10->psi, sizeof(chip10->psi),
TYPE_PNV10_PSI, &error_abort, NULL);
+ object_initialize_child(obj, "lpc", &chip10->lpc, sizeof(chip10->lpc),
+ TYPE_PNV10_LPC, &error_abort, NULL);
}
static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
@@ -1349,6 +1353,21 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
}
pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE,
&PNV_PSI(&chip10->psi)->xscom_regs);
+
+ /* LPC */
+ object_property_set_link(OBJECT(&chip10->lpc), OBJECT(&chip10->psi), "psi",
+ &error_abort);
+ object_property_set_bool(OBJECT(&chip10->lpc), true, "realized",
+ &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+ memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip),
+ &chip10->lpc.xscom_regs);
+
+ chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
+ (uint64_t) PNV10_LPCM_BASE(chip));
}
static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
index dd5374c838..18256d9ba3 100644
--- a/hw/ppc/pnv_lpc.c
+++ b/hw/ppc/pnv_lpc.c
@@ -122,26 +122,26 @@ static int pnv_lpc_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
}
/* POWER9 only */
-int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset)
+int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset, uint64_t lpcm_addr,
+ uint64_t lpcm_size)
{
const char compat[] = "ibm,power9-lpcm-opb\0simple-bus";
const char lpc_compat[] = "ibm,power9-lpc\0ibm,lpc";
char *name;
int offset, lpcm_offset;
- uint64_t lpcm_addr = PNV9_LPCM_BASE(chip);
uint32_t opb_ranges[8] = { 0,
cpu_to_be32(lpcm_addr >> 32),
cpu_to_be32((uint32_t)lpcm_addr),
- cpu_to_be32(PNV9_LPCM_SIZE / 2),
- cpu_to_be32(PNV9_LPCM_SIZE / 2),
+ cpu_to_be32(lpcm_size / 2),
+ cpu_to_be32(lpcm_size / 2),
cpu_to_be32(lpcm_addr >> 32),
- cpu_to_be32(PNV9_LPCM_SIZE / 2),
- cpu_to_be32(PNV9_LPCM_SIZE / 2),
+ cpu_to_be32(lpcm_size / 2),
+ cpu_to_be32(lpcm_size / 2),
};
uint32_t opb_reg[4] = { cpu_to_be32(lpcm_addr >> 32),
cpu_to_be32((uint32_t)lpcm_addr),
- cpu_to_be32(PNV9_LPCM_SIZE >> 32),
- cpu_to_be32((uint32_t)PNV9_LPCM_SIZE),
+ cpu_to_be32(lpcm_size >> 32),
+ cpu_to_be32((uint32_t)lpcm_size),
};
uint32_t lpc_ranges[12] = { 0, 0,
cpu_to_be32(LPC_MEM_OPB_ADDR),
@@ -691,6 +691,19 @@ static const TypeInfo pnv_lpc_power9_info = {
.class_init = pnv_lpc_power9_class_init,
};
+static void pnv_lpc_power10_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "PowerNV LPC Controller POWER10";
+}
+
+static const TypeInfo pnv_lpc_power10_info = {
+ .name = TYPE_PNV10_LPC,
+ .parent = TYPE_PNV9_LPC,
+ .class_init = pnv_lpc_power10_class_init,
+};
+
static void pnv_lpc_realize(DeviceState *dev, Error **errp)
{
PnvLpcController *lpc = PNV_LPC(dev);
@@ -764,6 +777,7 @@ static void pnv_lpc_register_types(void)
type_register_static(&pnv_lpc_info);
type_register_static(&pnv_lpc_power8_info);
type_register_static(&pnv_lpc_power9_info);
+ type_register_static(&pnv_lpc_power10_info);
}
type_init(pnv_lpc_register_types)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 47b7370b27..56d1161515 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -115,6 +115,7 @@ typedef struct Pnv10Chip {
/*< public >*/
Pnv9Psi psi;
+ PnvLpcController lpc;
} Pnv10Chip;
typedef struct PnvChipClass {
@@ -329,6 +330,9 @@ IPMIBmc *pnv_bmc_create(void);
#define PNV10_XSCOM_SIZE 0x0000000400000000ull
#define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull)
+#define PNV10_LPCM_SIZE 0x0000000100000000ull
+#define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030000000000ull)
+
#define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull
#define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull)
diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h
index f659410716..c1ec85d5e2 100644
--- a/include/hw/ppc/pnv_lpc.h
+++ b/include/hw/ppc/pnv_lpc.h
@@ -31,6 +31,9 @@
#define TYPE_PNV9_LPC TYPE_PNV_LPC "-POWER9"
#define PNV9_LPC(obj) OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV9_LPC)
+#define TYPE_PNV10_LPC TYPE_PNV_LPC "-POWER10"
+#define PNV10_LPC(obj) OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV10_LPC)
+
typedef struct PnvLpcController {
DeviceState parent;
@@ -97,6 +100,7 @@ typedef struct PnvLpcClass {
struct PnvChip;
ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp);
-int pnv_dt_lpc(struct PnvChip *chip, void *fdt, int root_offset);
+int pnv_dt_lpc(struct PnvChip *chip, void *fdt, int root_offset,
+ uint64_t lpcm_addr, uint64_t lpcm_size);
#endif /* PPC_PNV_LPC_H */
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 66/88] target/ppc: Implement the VTB for HV access
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (64 preceding siblings ...)
2019-12-17 4:42 ` [PULL 65/88] ppc/pnv: add a LPC Controller " David Gibson
@ 2019-12-17 4:43 ` David Gibson
2019-12-17 4:43 ` [PULL 67/88] target/ppc: Work [S]PURR implementation and add HV support David Gibson
` (22 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:43 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg,
Suraj Jitindar Singh, David Gibson
From: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
The virtual timebase register (VTB) is a 64-bit register which
increments at the same rate as the timebase register, present on POWER8
and later processors.
The register is able to be read/written by the hypervisor and read by
the supervisor. All other accesses are illegal.
Currently the VTB is just an alias for the timebase (TB) register.
Implement the VTB so that is can be read/written independent of the TB.
Make use of the existing method for accessing timebase facilities where
by the compensation is stored and used to compute the value on reads/is
updated on writes.
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
[ clg: rebased on current ppc tree ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191128134700.16091-2-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/ppc.c | 16 ++++++++++++++++
include/hw/ppc/ppc.h | 1 +
linux-user/ppc/cpu_loop.c | 5 +++++
target/ppc/cpu.h | 2 ++
target/ppc/helper.h | 2 ++
target/ppc/timebase_helper.c | 10 ++++++++++
target/ppc/translate_init.inc.c | 19 +++++++++++++++----
7 files changed, 51 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index 45834f98d1..d8c402811f 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -682,6 +682,22 @@ void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value)
&tb_env->atb_offset, ((uint64_t)value << 32) | tb);
}
+uint64_t cpu_ppc_load_vtb(CPUPPCState *env)
+{
+ ppc_tb_t *tb_env = env->tb_env;
+
+ return cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
+ tb_env->vtb_offset);
+}
+
+void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value)
+{
+ ppc_tb_t *tb_env = env->tb_env;
+
+ cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
+ &tb_env->vtb_offset, value);
+}
+
static void cpu_ppc_tb_stop (CPUPPCState *env)
{
ppc_tb_t *tb_env = env->tb_env;
diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h
index 89e1dd065a..d7a95608f6 100644
--- a/include/hw/ppc/ppc.h
+++ b/include/hw/ppc/ppc.h
@@ -24,6 +24,7 @@ struct ppc_tb_t {
/* Time base management */
int64_t tb_offset; /* Compensation */
int64_t atb_offset; /* Compensation */
+ int64_t vtb_offset;
uint32_t tb_freq; /* TB frequency */
/* Decrementer management */
uint64_t decr_next; /* Tick for next decr interrupt */
diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c
index d5704def29..5b27f8603e 100644
--- a/linux-user/ppc/cpu_loop.c
+++ b/linux-user/ppc/cpu_loop.c
@@ -47,6 +47,11 @@ uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
return cpu_ppc_get_tb(env) >> 32;
}
+uint64_t cpu_ppc_load_vtb(CPUPPCState *env)
+{
+ return cpu_ppc_get_tb(env);
+}
+
uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
__attribute__ (( alias ("cpu_ppc_load_tbu") ));
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index fbec1b0cd5..eb7d2c7637 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1303,6 +1303,8 @@ uint64_t cpu_ppc_load_atbl(CPUPPCState *env);
uint32_t cpu_ppc_load_atbu(CPUPPCState *env);
void cpu_ppc_store_atbl(CPUPPCState *env, uint32_t value);
void cpu_ppc_store_atbu(CPUPPCState *env, uint32_t value);
+uint64_t cpu_ppc_load_vtb(CPUPPCState *env);
+void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value);
bool ppc_decr_clear_on_delivery(CPUPPCState *env);
target_ulong cpu_ppc_load_decr(CPUPPCState *env);
void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value);
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index f843814b8a..a5f53bb421 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -649,6 +649,7 @@ DEF_HELPER_FLAGS_1(load_tbl, TCG_CALL_NO_RWG, tl, env)
DEF_HELPER_FLAGS_1(load_tbu, TCG_CALL_NO_RWG, tl, env)
DEF_HELPER_FLAGS_1(load_atbl, TCG_CALL_NO_RWG, tl, env)
DEF_HELPER_FLAGS_1(load_atbu, TCG_CALL_NO_RWG, tl, env)
+DEF_HELPER_FLAGS_1(load_vtb, TCG_CALL_NO_RWG, tl, env)
DEF_HELPER_FLAGS_1(load_601_rtcl, TCG_CALL_NO_RWG, tl, env)
DEF_HELPER_FLAGS_1(load_601_rtcu, TCG_CALL_NO_RWG, tl, env)
#if !defined(CONFIG_USER_ONLY)
@@ -669,6 +670,7 @@ DEF_HELPER_FLAGS_1(load_decr, TCG_CALL_NO_RWG, tl, env)
DEF_HELPER_FLAGS_2(store_decr, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_1(load_hdecr, TCG_CALL_NO_RWG, tl, env)
DEF_HELPER_FLAGS_2(store_hdecr, TCG_CALL_NO_RWG, void, env, tl)
+DEF_HELPER_FLAGS_2(store_vtb, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_2(store_hid0_601, void, env, tl)
DEF_HELPER_3(store_403_pbr, void, env, i32, tl)
DEF_HELPER_FLAGS_1(load_40x_pit, TCG_CALL_NO_RWG, tl, env)
diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c
index 73363e08ae..8c3c2fe67c 100644
--- a/target/ppc/timebase_helper.c
+++ b/target/ppc/timebase_helper.c
@@ -45,6 +45,11 @@ target_ulong helper_load_atbu(CPUPPCState *env)
return cpu_ppc_load_atbu(env);
}
+target_ulong helper_load_vtb(CPUPPCState *env)
+{
+ return cpu_ppc_load_vtb(env);
+}
+
#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
target_ulong helper_load_purr(CPUPPCState *env)
{
@@ -113,6 +118,11 @@ void helper_store_hdecr(CPUPPCState *env, target_ulong val)
cpu_ppc_store_hdecr(env, val);
}
+void helper_store_vtb(CPUPPCState *env, target_ulong val)
+{
+ cpu_ppc_store_vtb(env, val);
+}
+
target_ulong helper_load_40x_pit(CPUPPCState *env)
{
return load_40x_pit(env);
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index 7364d36b07..226aecf8f4 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -312,6 +312,16 @@ static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
}
}
+static void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_helper_load_vtb(cpu_gpr[gprn], cpu_env);
+}
+
+static void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
+}
+
#endif
#endif
@@ -8174,10 +8184,11 @@ static void gen_spr_power8_ebb(CPUPPCState *env)
/* Virtual Time Base */
static void gen_spr_vtb(CPUPPCState *env)
{
- spr_register_kvm(env, SPR_VTB, "VTB",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_tbl, SPR_NOACCESS,
- KVM_REG_PPC_VTB, 0x00000000);
+ spr_register_kvm_hv(env, SPR_VTB, "VTB",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_vtb, SPR_NOACCESS,
+ &spr_read_vtb, &spr_write_vtb,
+ KVM_REG_PPC_VTB, 0x00000000);
}
static void gen_spr_power8_fscr(CPUPPCState *env)
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 67/88] target/ppc: Work [S]PURR implementation and add HV support
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (65 preceding siblings ...)
2019-12-17 4:43 ` [PULL 66/88] target/ppc: Implement the VTB for HV access David Gibson
@ 2019-12-17 4:43 ` David Gibson
2019-12-17 4:43 ` [PULL 68/88] target/ppc: Add SPR ASDR David Gibson
` (21 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:43 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg,
Suraj Jitindar Singh, David Gibson
From: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
The Processor Utilisation of Resources Register (PURR) and Scaled
Processor Utilisation of Resources Register (SPURR) provide an estimate
of the resources used by the thread, present on POWER7 and later
processors.
Currently the [S]PURR registers simply count at the rate of the
timebase.
Preserve this behaviour but rework the implementation to store an offset
like the timebase rather than doing the calculation manually. Also allow
hypervisor write access to the register along with the currently
available read access.
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
[ clg: rebased on current ppc tree ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191128134700.16091-3-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/ppc.c | 17 +++++++----------
include/hw/ppc/ppc.h | 3 +--
target/ppc/cpu.h | 1 +
target/ppc/helper.h | 1 +
target/ppc/timebase_helper.c | 5 +++++
target/ppc/translate_init.inc.c | 23 +++++++++++++++--------
6 files changed, 30 insertions(+), 20 deletions(-)
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index d8c402811f..2856d69495 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -809,12 +809,9 @@ target_ulong cpu_ppc_load_hdecr(CPUPPCState *env)
uint64_t cpu_ppc_load_purr (CPUPPCState *env)
{
ppc_tb_t *tb_env = env->tb_env;
- uint64_t diff;
- diff = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - tb_env->purr_start;
-
- return tb_env->purr_load +
- muldiv64(diff, tb_env->tb_freq, NANOSECONDS_PER_SECOND);
+ return cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
+ tb_env->purr_offset);
}
/* When decrementer expires,
@@ -973,12 +970,12 @@ static void cpu_ppc_hdecr_cb(void *opaque)
cpu_ppc_hdecr_excp(cpu);
}
-static void cpu_ppc_store_purr(PowerPCCPU *cpu, uint64_t value)
+void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value)
{
- ppc_tb_t *tb_env = cpu->env.tb_env;
+ ppc_tb_t *tb_env = env->tb_env;
- tb_env->purr_load = value;
- tb_env->purr_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
+ &tb_env->purr_offset, value);
}
static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
@@ -995,7 +992,7 @@ static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
*/
_cpu_ppc_store_decr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 32);
_cpu_ppc_store_hdecr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 32);
- cpu_ppc_store_purr(cpu, 0x0000000000000000ULL);
+ cpu_ppc_store_purr(env, 0x0000000000000000ULL);
}
static void timebase_save(PPCTimebase *tb)
diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h
index d7a95608f6..4ea5436095 100644
--- a/include/hw/ppc/ppc.h
+++ b/include/hw/ppc/ppc.h
@@ -33,8 +33,7 @@ struct ppc_tb_t {
/* Hypervisor decrementer management */
uint64_t hdecr_next; /* Tick for next hdecr interrupt */
QEMUTimer *hdecr_timer;
- uint64_t purr_load;
- uint64_t purr_start;
+ int64_t purr_offset;
void *opaque;
uint32_t flags;
};
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index eb7d2c7637..da44cc8809 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1311,6 +1311,7 @@ void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value);
target_ulong cpu_ppc_load_hdecr(CPUPPCState *env);
void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value);
uint64_t cpu_ppc_load_purr(CPUPPCState *env);
+void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value);
uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env);
uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env);
#if !defined(CONFIG_USER_ONLY)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index a5f53bb421..356a14d8a6 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -655,6 +655,7 @@ DEF_HELPER_FLAGS_1(load_601_rtcu, TCG_CALL_NO_RWG, tl, env)
#if !defined(CONFIG_USER_ONLY)
#if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_1(load_purr, TCG_CALL_NO_RWG, tl, env)
+DEF_HELPER_FLAGS_2(store_purr, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_2(store_ptcr, void, env, tl)
#endif
DEF_HELPER_2(store_sdr1, void, env, tl)
diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c
index 8c3c2fe67c..2395295b77 100644
--- a/target/ppc/timebase_helper.c
+++ b/target/ppc/timebase_helper.c
@@ -55,6 +55,11 @@ target_ulong helper_load_purr(CPUPPCState *env)
{
return (target_ulong)cpu_ppc_load_purr(env);
}
+
+void helper_store_purr(CPUPPCState *env, target_ulong val)
+{
+ cpu_ppc_store_purr(env, val);
+}
#endif
target_ulong helper_load_601_rtcl(CPUPPCState *env)
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index 226aecf8f4..c5e4d45569 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -287,6 +287,11 @@ static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
}
+static void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_purr(cpu_env, cpu_gpr[gprn]);
+}
+
/* HDECR */
static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
{
@@ -8013,14 +8018,16 @@ static void gen_spr_book3s_purr(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
/* PURR & SPURR: Hack - treat these as aliases for the TB for now */
- spr_register_kvm(env, SPR_PURR, "PURR",
- &spr_read_purr, SPR_NOACCESS,
- &spr_read_purr, SPR_NOACCESS,
- KVM_REG_PPC_PURR, 0x00000000);
- spr_register_kvm(env, SPR_SPURR, "SPURR",
- &spr_read_purr, SPR_NOACCESS,
- &spr_read_purr, SPR_NOACCESS,
- KVM_REG_PPC_SPURR, 0x00000000);
+ spr_register_kvm_hv(env, SPR_PURR, "PURR",
+ &spr_read_purr, SPR_NOACCESS,
+ &spr_read_purr, SPR_NOACCESS,
+ &spr_read_purr, &spr_write_purr,
+ KVM_REG_PPC_PURR, 0x00000000);
+ spr_register_kvm_hv(env, SPR_SPURR, "SPURR",
+ &spr_read_purr, SPR_NOACCESS,
+ &spr_read_purr, SPR_NOACCESS,
+ &spr_read_purr, &spr_write_purr,
+ KVM_REG_PPC_SPURR, 0x00000000);
#endif
}
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 68/88] target/ppc: Add SPR ASDR
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (66 preceding siblings ...)
2019-12-17 4:43 ` [PULL 67/88] target/ppc: Work [S]PURR implementation and add HV support David Gibson
@ 2019-12-17 4:43 ` David Gibson
2019-12-17 4:43 ` [PULL 69/88] target/ppc: Add SPR TBU40 David Gibson
` (20 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:43 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg,
Suraj Jitindar Singh, David Gibson
From: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
The Access Segment Descriptor Register (ASDR) provides information about
the storage element when taking a hypervisor storage interrupt. When
performing nested radix address translation, this is normally the guest
real address. This register is present on POWER9 processors and later.
Implement the ADSR, note read and write access is limited to the
hypervisor.
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191128134700.16091-4-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu.h | 1 +
target/ppc/translate_init.inc.c | 6 ++++++
2 files changed, 7 insertions(+)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index da44cc8809..e99850c3ae 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1778,6 +1778,7 @@ typedef PowerPCCPU ArchCPU;
#define SPR_MPC_MD_DBRAM1 (0x32A)
#define SPR_RCPU_L2U_RA3 (0x32B)
#define SPR_TAR (0x32F)
+#define SPR_ASDR (0x330)
#define SPR_IC (0x350)
#define SPR_VTB (0x351)
#define SPR_MMCRC (0x353)
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index c5e4d45569..c850a9d065 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -8295,6 +8295,12 @@ static void gen_spr_power9_mmu(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_ptcr,
KVM_REG_PPC_PTCR, 0x00000000);
+ /* Address Segment Descriptor Register */
+ spr_register_hv(env, SPR_ASDR, "ASDR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x0000000000000000);
#endif
}
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 69/88] target/ppc: Add SPR TBU40
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (67 preceding siblings ...)
2019-12-17 4:43 ` [PULL 68/88] target/ppc: Add SPR ASDR David Gibson
@ 2019-12-17 4:43 ` David Gibson
2019-12-17 4:43 ` [PULL 70/88] ppc/pnv: Loop on the whole hierarchy to populate the DT with the XSCOM nodes David Gibson
` (19 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:43 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg,
Suraj Jitindar Singh, David Gibson
From: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
The spr TBU40 is used to set the upper 40 bits of the timebase
register, present on POWER5+ and later processors.
This register can only be written by the hypervisor, and cannot be read.
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191128134700.16091-5-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/ppc.c | 13 +++++++++++++
target/ppc/cpu.h | 1 +
target/ppc/helper.h | 1 +
target/ppc/timebase_helper.c | 5 +++++
target/ppc/translate_init.inc.c | 19 +++++++++++++++++++
5 files changed, 39 insertions(+)
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index 2856d69495..4c5fa29399 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -698,6 +698,19 @@ void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value)
&tb_env->vtb_offset, value);
}
+void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value)
+{
+ ppc_tb_t *tb_env = env->tb_env;
+ uint64_t tb;
+
+ tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
+ tb_env->tb_offset);
+ tb &= 0xFFFFFFUL;
+ tb |= (value & ~0xFFFFFFUL);
+ cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
+ &tb_env->tb_offset, tb);
+}
+
static void cpu_ppc_tb_stop (CPUPPCState *env)
{
ppc_tb_t *tb_env = env->tb_env;
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index e99850c3ae..103bfe9dc2 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1310,6 +1310,7 @@ target_ulong cpu_ppc_load_decr(CPUPPCState *env);
void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value);
target_ulong cpu_ppc_load_hdecr(CPUPPCState *env);
void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value);
+void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value);
uint64_t cpu_ppc_load_purr(CPUPPCState *env);
void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value);
uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env);
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 356a14d8a6..cd0dfe383a 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -672,6 +672,7 @@ DEF_HELPER_FLAGS_2(store_decr, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_1(load_hdecr, TCG_CALL_NO_RWG, tl, env)
DEF_HELPER_FLAGS_2(store_hdecr, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(store_vtb, TCG_CALL_NO_RWG, void, env, tl)
+DEF_HELPER_FLAGS_2(store_tbu40, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_2(store_hid0_601, void, env, tl)
DEF_HELPER_3(store_403_pbr, void, env, i32, tl)
DEF_HELPER_FLAGS_1(load_40x_pit, TCG_CALL_NO_RWG, tl, env)
diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c
index 2395295b77..703bd9ed18 100644
--- a/target/ppc/timebase_helper.c
+++ b/target/ppc/timebase_helper.c
@@ -128,6 +128,11 @@ void helper_store_vtb(CPUPPCState *env, target_ulong val)
cpu_ppc_store_vtb(env, val);
}
+void helper_store_tbu40(CPUPPCState *env, target_ulong val)
+{
+ cpu_ppc_store_tbu40(env, val);
+}
+
target_ulong helper_load_40x_pit(CPUPPCState *env)
{
return load_40x_pit(env);
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index c850a9d065..d33d65dff7 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -327,6 +327,11 @@ static void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
}
+static void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
+}
+
#endif
#endif
@@ -7853,6 +7858,16 @@ static void gen_spr_power5p_ear(CPUPPCState *env)
0x00000000);
}
+static void gen_spr_power5p_tb(CPUPPCState *env)
+{
+ /* TBU40 (High 40 bits of the Timebase register */
+ spr_register_hv(env, SPR_TBU40, "TBU40",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, &spr_write_tbu40,
+ 0x00000000);
+}
+
#if !defined(CONFIG_USER_ONLY)
static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
{
@@ -8404,6 +8419,7 @@ static void init_proc_power5plus(CPUPPCState *env)
gen_spr_power5p_common(env);
gen_spr_power5p_lpar(env);
gen_spr_power5p_ear(env);
+ gen_spr_power5p_tb(env);
/* env variables */
env->dcache_line_size = 128;
@@ -8516,6 +8532,7 @@ static void init_proc_POWER7(CPUPPCState *env)
gen_spr_power5p_common(env);
gen_spr_power5p_lpar(env);
gen_spr_power5p_ear(env);
+ gen_spr_power5p_tb(env);
gen_spr_power6_common(env);
gen_spr_power6_dbg(env);
gen_spr_power7_book4(env);
@@ -8657,6 +8674,7 @@ static void init_proc_POWER8(CPUPPCState *env)
gen_spr_power5p_common(env);
gen_spr_power5p_lpar(env);
gen_spr_power5p_ear(env);
+ gen_spr_power5p_tb(env);
gen_spr_power6_common(env);
gen_spr_power6_dbg(env);
gen_spr_power8_tce_address_control(env);
@@ -8847,6 +8865,7 @@ static void init_proc_POWER9(CPUPPCState *env)
gen_spr_power5p_common(env);
gen_spr_power5p_lpar(env);
gen_spr_power5p_ear(env);
+ gen_spr_power5p_tb(env);
gen_spr_power6_common(env);
gen_spr_power6_dbg(env);
gen_spr_power8_tce_address_control(env);
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 70/88] ppc/pnv: Loop on the whole hierarchy to populate the DT with the XSCOM nodes
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (68 preceding siblings ...)
2019-12-17 4:43 ` [PULL 69/88] target/ppc: Add SPR TBU40 David Gibson
@ 2019-12-17 4:43 ` David Gibson
2019-12-17 4:43 ` [PULL 71/88] ppc/pnv: populate the DT with realized XSCOM devices David Gibson
` (18 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:43 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
Some PnvXScomInterface objects lie a bit deeper (PnvPBCQState) than
the first layer, so we need to loop on the whole object hierarchy to
catch them.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191210135845.19773-2-clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
[dwg: Corrected error in comment]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv_xscom.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c
index b3d3b6e350..760571037b 100644
--- a/hw/ppc/pnv_xscom.c
+++ b/hw/ppc/pnv_xscom.c
@@ -358,7 +358,12 @@ int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset)
args.fdt = fdt;
args.xscom_offset = xscom_offset;
- object_child_foreach(OBJECT(chip), xscom_dt_child, &args);
+ /*
+ * Loop on the whole object hierarchy to catch all
+ * PnvXScomInterface objects which can lie a bit deeper than the
+ * first layer.
+ */
+ object_child_foreach_recursive(OBJECT(chip), xscom_dt_child, &args);
return 0;
}
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 71/88] ppc/pnv: populate the DT with realized XSCOM devices
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (69 preceding siblings ...)
2019-12-17 4:43 ` [PULL 70/88] ppc/pnv: Loop on the whole hierarchy to populate the DT with the XSCOM nodes David Gibson
@ 2019-12-17 4:43 ` David Gibson
2019-12-17 4:43 ` [PULL 72/88] ppc/pnv: Make PnvXScomInterface an incomplete type David Gibson
` (17 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:43 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg,
Philippe Mathieu-Daudé,
David Gibson
From: Cédric Le Goater <clg@kaod.org>
Some devices could be initialized in the instance_init handler but not
realized for configuration reasons. Nodes should not be added in the DT
for such devices.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191210135845.19773-3-clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv_xscom.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c
index 760571037b..fd48d4ee37 100644
--- a/hw/ppc/pnv_xscom.c
+++ b/hw/ppc/pnv_xscom.c
@@ -304,7 +304,10 @@ static int xscom_dt_child(Object *child, void *opaque)
PnvXScomInterface *xd = PNV_XSCOM_INTERFACE(child);
PnvXScomInterfaceClass *xc = PNV_XSCOM_INTERFACE_GET_CLASS(xd);
- if (xc->dt_xscom) {
+ /*
+ * Only "realized" devices should be configured in the DT
+ */
+ if (xc->dt_xscom && DEVICE(child)->realized) {
_FDT((xc->dt_xscom(xd, args->fdt, args->xscom_offset)));
}
}
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 72/88] ppc/pnv: Make PnvXScomInterface an incomplete type
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (70 preceding siblings ...)
2019-12-17 4:43 ` [PULL 71/88] ppc/pnv: populate the DT with realized XSCOM devices David Gibson
@ 2019-12-17 4:43 ` David Gibson
2019-12-17 4:43 ` [PULL 73/88] ppc/pnv: Introduce PBA registers David Gibson
` (16 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:43 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg,
Philippe Mathieu-Daudé,
David Gibson
From: Greg Kurz <groug@kaod.org>
PnvXScomInterface is an interface instance. It should never be
dereferenced. Drop the dummy type definition for extra safety,
which is the common practice with QOM interfaces.
While here also convert the bogus OBJECT_CHECK() to INTERFACE_CHECK().
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157608025541.186670.1577861507610404326.stgit@bahia.lan>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
include/hw/ppc/pnv_xscom.h | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index a40d2a2a2a..5ad2735d1a 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -22,13 +22,11 @@
#include "qom/object.h"
-typedef struct PnvXScomInterface {
- Object parent;
-} PnvXScomInterface;
+typedef struct PnvXScomInterface PnvXScomInterface;
#define TYPE_PNV_XSCOM_INTERFACE "pnv-xscom-interface"
#define PNV_XSCOM_INTERFACE(obj) \
- OBJECT_CHECK(PnvXScomInterface, (obj), TYPE_PNV_XSCOM_INTERFACE)
+ INTERFACE_CHECK(PnvXScomInterface, (obj), TYPE_PNV_XSCOM_INTERFACE)
#define PNV_XSCOM_INTERFACE_CLASS(klass) \
OBJECT_CLASS_CHECK(PnvXScomInterfaceClass, (klass), \
TYPE_PNV_XSCOM_INTERFACE)
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 73/88] ppc/pnv: Introduce PBA registers
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (71 preceding siblings ...)
2019-12-17 4:43 ` [PULL 72/88] ppc/pnv: Make PnvXScomInterface an incomplete type David Gibson
@ 2019-12-17 4:43 ` David Gibson
2019-12-17 4:43 ` [PULL 74/88] ppc/pnv: Fix OCC common area region mapping David Gibson
` (15 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:43 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
The PBA bridge unit (Power Bus Access) connects the OCC (On Chip
Controller) to the Power bus and System Memory. The PBA is used to
gather sensor data, for power management, for sleep states, for
initial boot, among other things.
The PBA logic provides a set of four registers PowerBus Access Base
Address Registers (PBABAR0..3) which map the OCC address space to the
PowerBus space. These registers are setup by the initial FW and define
the PowerBus Range of system memory that can be accessed by PBA.
The current modeling of the PBABAR registers is done under the common
XSCOM handlers. We introduce a specific XSCOM regions for these
registers and fix :
- BAR sizes and BAR masks
- The mapping of the OCC common area. It is common to all chips and
should be mapped once. We will address per-OCC area in the next
change.
- OCC common area is in BAR 3 on P8
Inspired by previous work of Balamuruhan S <bala24@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191211082912.2625-2-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 12 +++-
hw/ppc/pnv_homer.c | 109 +++++++++++++++++++++++++++++++++++++
hw/ppc/pnv_xscom.c | 32 -----------
include/hw/ppc/pnv.h | 16 ++----
include/hw/ppc/pnv_homer.h | 3 +
include/hw/ppc/pnv_xscom.h | 6 ++
6 files changed, 134 insertions(+), 44 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 67d0ad55b8..af7317a86d 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1065,7 +1065,7 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
/* OCC SRAM model */
- memory_region_add_subregion(get_system_memory(), PNV_OCC_COMMON_AREA(chip),
+ memory_region_add_subregion(get_system_memory(), PNV_OCC_COMMON_AREA_BASE,
&chip8->occ.sram_regs);
/* HOMER */
@@ -1077,6 +1077,10 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
error_propagate(errp, local_err);
return;
}
+ /* Homer Xscom region */
+ pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs);
+
+ /* Homer mmio region */
memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
&chip8->homer.regs);
}
@@ -1274,7 +1278,7 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
/* OCC SRAM model */
- memory_region_add_subregion(get_system_memory(), PNV9_OCC_COMMON_AREA(chip),
+ memory_region_add_subregion(get_system_memory(), PNV9_OCC_COMMON_AREA_BASE,
&chip9->occ.sram_regs);
/* HOMER */
@@ -1286,6 +1290,10 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
error_propagate(errp, local_err);
return;
}
+ /* Homer Xscom region */
+ pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs);
+
+ /* Homer mmio region */
memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip),
&chip9->homer.regs);
}
diff --git a/hw/ppc/pnv_homer.c b/hw/ppc/pnv_homer.c
index 994a378108..a08b7914f7 100644
--- a/hw/ppc/pnv_homer.c
+++ b/hw/ppc/pnv_homer.c
@@ -17,6 +17,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/log.h"
#include "qapi/error.h"
#include "exec/hwaddr.h"
#include "exec/memory.h"
@@ -25,6 +26,7 @@
#include "hw/qdev-properties.h"
#include "hw/ppc/pnv.h"
#include "hw/ppc/pnv_homer.h"
+#include "hw/ppc/pnv_xscom.h"
static bool core_max_array(PnvHomer *homer, hwaddr addr)
@@ -114,10 +116,67 @@ static const MemoryRegionOps pnv_power8_homer_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
+/* P8 PBA BARs */
+#define PBA_BAR0 0x00
+#define PBA_BAR1 0x01
+#define PBA_BAR2 0x02
+#define PBA_BAR3 0x03
+#define PBA_BARMASK0 0x04
+#define PBA_BARMASK1 0x05
+#define PBA_BARMASK2 0x06
+#define PBA_BARMASK3 0x07
+
+static uint64_t pnv_homer_power8_pba_read(void *opaque, hwaddr addr,
+ unsigned size)
+{
+ PnvHomer *homer = PNV_HOMER(opaque);
+ PnvChip *chip = homer->chip;
+ uint32_t reg = addr >> 3;
+ uint64_t val = 0;
+
+ switch (reg) {
+ case PBA_BAR0:
+ val = PNV_HOMER_BASE(chip);
+ break;
+ case PBA_BARMASK0: /* P8 homer region mask */
+ val = (PNV_HOMER_SIZE - 1) & 0x300000;
+ break;
+ case PBA_BAR3: /* P8 occ common area */
+ val = PNV_OCC_COMMON_AREA_BASE;
+ break;
+ case PBA_BARMASK3: /* P8 occ common area mask */
+ val = (PNV_OCC_COMMON_AREA_SIZE - 1) & 0x700000;
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "PBA: read to unimplemented register: Ox%"
+ HWADDR_PRIx "\n", addr >> 3);
+ }
+ return val;
+}
+
+static void pnv_homer_power8_pba_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+ qemu_log_mask(LOG_UNIMP, "PBA: write to unimplemented register: Ox%"
+ HWADDR_PRIx "\n", addr >> 3);
+}
+
+static const MemoryRegionOps pnv_homer_power8_pba_ops = {
+ .read = pnv_homer_power8_pba_read,
+ .write = pnv_homer_power8_pba_write,
+ .valid.min_access_size = 8,
+ .valid.max_access_size = 8,
+ .impl.min_access_size = 8,
+ .impl.max_access_size = 8,
+ .endianness = DEVICE_BIG_ENDIAN,
+};
+
static void pnv_homer_power8_class_init(ObjectClass *klass, void *data)
{
PnvHomerClass *homer = PNV_HOMER_CLASS(klass);
+ homer->pba_size = PNV_XSCOM_PBA_SIZE;
+ homer->pba_ops = &pnv_homer_power8_pba_ops;
homer->homer_size = PNV_HOMER_SIZE;
homer->homer_ops = &pnv_power8_homer_ops;
homer->core_max_base = PNV8_CORE_MAX_BASE;
@@ -210,10 +269,57 @@ static const MemoryRegionOps pnv_power9_homer_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
+static uint64_t pnv_homer_power9_pba_read(void *opaque, hwaddr addr,
+ unsigned size)
+{
+ PnvHomer *homer = PNV_HOMER(opaque);
+ PnvChip *chip = homer->chip;
+ uint32_t reg = addr >> 3;
+ uint64_t val = 0;
+
+ switch (reg) {
+ case PBA_BAR0:
+ val = PNV9_HOMER_BASE(chip);
+ break;
+ case PBA_BARMASK0: /* P9 homer region mask */
+ val = (PNV9_HOMER_SIZE - 1) & 0x300000;
+ break;
+ case PBA_BAR2: /* P9 occ common area */
+ val = PNV9_OCC_COMMON_AREA_BASE;
+ break;
+ case PBA_BARMASK2: /* P9 occ common area size */
+ val = (PNV9_OCC_COMMON_AREA_SIZE - 1) & 0x700000;
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "PBA: read to unimplemented register: Ox%"
+ HWADDR_PRIx "\n", addr >> 3);
+ }
+ return val;
+}
+
+static void pnv_homer_power9_pba_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+ qemu_log_mask(LOG_UNIMP, "PBA: write to unimplemented register: Ox%"
+ HWADDR_PRIx "\n", addr >> 3);
+}
+
+static const MemoryRegionOps pnv_homer_power9_pba_ops = {
+ .read = pnv_homer_power9_pba_read,
+ .write = pnv_homer_power9_pba_write,
+ .valid.min_access_size = 8,
+ .valid.max_access_size = 8,
+ .impl.min_access_size = 8,
+ .impl.max_access_size = 8,
+ .endianness = DEVICE_BIG_ENDIAN,
+};
+
static void pnv_homer_power9_class_init(ObjectClass *klass, void *data)
{
PnvHomerClass *homer = PNV_HOMER_CLASS(klass);
+ homer->pba_size = PNV9_XSCOM_PBA_SIZE;
+ homer->pba_ops = &pnv_homer_power9_pba_ops;
homer->homer_size = PNV9_HOMER_SIZE;
homer->homer_ops = &pnv_power9_homer_ops;
homer->core_max_base = PNV9_CORE_MAX_BASE;
@@ -233,6 +339,9 @@ static void pnv_homer_realize(DeviceState *dev, Error **errp)
assert(homer->chip);
+ pnv_xscom_region_init(&homer->pba_regs, OBJECT(dev), hmrc->pba_ops,
+ homer, "xscom-pba", hmrc->pba_size);
+
/* homer region */
memory_region_init_io(&homer->regs, OBJECT(dev),
hmrc->homer_ops, homer, "homer-main-memory",
diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c
index fd48d4ee37..df926003f2 100644
--- a/hw/ppc/pnv_xscom.c
+++ b/hw/ppc/pnv_xscom.c
@@ -36,16 +36,6 @@
#define PRD_P9_IPOLL_REG_MASK 0x000F0033
#define PRD_P9_IPOLL_REG_STATUS 0x000F0034
-/* PBA BARs */
-#define P8_PBA_BAR0 0x2013f00
-#define P8_PBA_BAR2 0x2013f02
-#define P8_PBA_BARMASK0 0x2013f04
-#define P8_PBA_BARMASK2 0x2013f06
-#define P9_PBA_BAR0 0x5012b00
-#define P9_PBA_BAR2 0x5012b02
-#define P9_PBA_BARMASK0 0x5012b04
-#define P9_PBA_BARMASK2 0x5012b06
-
static void xscom_complete(CPUState *cs, uint64_t hmer_bits)
{
/*
@@ -90,26 +80,6 @@ static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba)
case 0x18002: /* ECID2 */
return 0;
- case P9_PBA_BAR0:
- return PNV9_HOMER_BASE(chip);
- case P8_PBA_BAR0:
- return PNV_HOMER_BASE(chip);
-
- case P9_PBA_BARMASK0: /* P9 homer region size */
- return PNV9_HOMER_SIZE;
- case P8_PBA_BARMASK0: /* P8 homer region size */
- return PNV_HOMER_SIZE;
-
- case P9_PBA_BAR2: /* P9 occ common area */
- return PNV9_OCC_COMMON_AREA(chip);
- case P8_PBA_BAR2: /* P8 occ common area */
- return PNV_OCC_COMMON_AREA(chip);
-
- case P9_PBA_BARMASK2: /* P9 occ common area size */
- return PNV9_OCC_COMMON_AREA_SIZE;
- case P8_PBA_BARMASK2: /* P8 occ common area size */
- return PNV_OCC_COMMON_AREA_SIZE;
-
case 0x1010c00: /* PIBAM FIR */
case 0x1010c03: /* PIBAM FIR MASK */
@@ -130,9 +100,7 @@ static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba)
case 0x202000f: /* ADU stuff, receive status register*/
return 0;
case 0x2013f01: /* PBA stuff */
- case 0x2013f03: /* PBA stuff */
case 0x2013f05: /* PBA stuff */
- case 0x2013f07: /* PBA stuff */
return 0;
case 0x2013028: /* CAPP stuff */
case 0x201302a: /* CAPP stuff */
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 56d1161515..301c7e62fa 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -244,12 +244,10 @@ IPMIBmc *pnv_bmc_create(void);
#define PNV_XSCOM_BASE(chip) \
(0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE)
-#define PNV_OCC_COMMON_AREA_SIZE 0x0000000000700000ull
-#define PNV_OCC_COMMON_AREA(chip) \
- (0x7fff800000ull + ((uint64_t)PNV_CHIP_INDEX(chip) * \
- PNV_OCC_COMMON_AREA_SIZE))
+#define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
+#define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull
-#define PNV_HOMER_SIZE 0x0000000000300000ull
+#define PNV_HOMER_SIZE 0x0000000000400000ull
#define PNV_HOMER_BASE(chip) \
(0x7ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV_HOMER_SIZE)
@@ -312,12 +310,10 @@ IPMIBmc *pnv_bmc_create(void);
#define PNV9_XSCOM_SIZE 0x0000000400000000ull
#define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull)
-#define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000700000ull
-#define PNV9_OCC_COMMON_AREA(chip) \
- (0x203fff800000ull + ((uint64_t)PNV_CHIP_INDEX(chip) * \
- PNV9_OCC_COMMON_AREA_SIZE))
+#define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
+#define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull
-#define PNV9_HOMER_SIZE 0x0000000000300000ull
+#define PNV9_HOMER_SIZE 0x0000000000400000ull
#define PNV9_HOMER_BASE(chip) \
(0x203ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV9_HOMER_SIZE)
diff --git a/include/hw/ppc/pnv_homer.h b/include/hw/ppc/pnv_homer.h
index abaec43c2d..1e91c950f6 100644
--- a/include/hw/ppc/pnv_homer.h
+++ b/include/hw/ppc/pnv_homer.h
@@ -33,6 +33,7 @@ typedef struct PnvHomer {
DeviceState parent;
struct PnvChip *chip;
+ MemoryRegion pba_regs;
MemoryRegion regs;
} PnvHomer;
@@ -44,6 +45,8 @@ typedef struct PnvHomer {
typedef struct PnvHomerClass {
DeviceClass parent_class;
+ int pba_size;
+ const MemoryRegionOps *pba_ops;
int homer_size;
const MemoryRegionOps *homer_ops;
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index 5ad2735d1a..09188d74b0 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -68,6 +68,9 @@ typedef struct PnvXScomInterfaceClass {
#define PNV_XSCOM_OCC_BASE 0x0066000
#define PNV_XSCOM_OCC_SIZE 0x6000
+#define PNV_XSCOM_PBA_BASE 0x2013f00
+#define PNV_XSCOM_PBA_SIZE 0x40
+
/*
* Layout of the XSCOM PCB addresses (POWER 9)
*/
@@ -82,6 +85,9 @@ typedef struct PnvXScomInterfaceClass {
#define PNV9_XSCOM_OCC_BASE PNV_XSCOM_OCC_BASE
#define PNV9_XSCOM_OCC_SIZE 0x8000
+#define PNV9_XSCOM_PBA_BASE 0x5012b00
+#define PNV9_XSCOM_PBA_SIZE 0x40
+
#define PNV9_XSCOM_PSIHB_BASE 0x5012900
#define PNV9_XSCOM_PSIHB_SIZE 0x100
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 74/88] ppc/pnv: Fix OCC common area region mapping
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (72 preceding siblings ...)
2019-12-17 4:43 ` [PULL 73/88] ppc/pnv: Introduce PBA registers David Gibson
@ 2019-12-17 4:43 ` David Gibson
2019-12-17 4:43 ` [PULL 75/88] ppc: Drop useless extern annotation for functions David Gibson
` (14 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:43 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
The OCC common area is mapped at a unique address on the system and
each OCC is assigned a segment to expose its sensor data :
-------------------------------------------------------------------------
| Start (Offset from | End | Size |Description |
| BAR2 base address) | | | |
-------------------------------------------------------------------------
| 0x00580000 | 0x005A57FF |150kB |OCC 0 Sensor Data Block|
| 0x005A5800 | 0x005CAFFF |150kB |OCC 1 Sensor Data Block|
| : | : | : | : |
| 0x00686800 | 0x006ABFFF |150kB |OCC 7 Sensor Data Block|
| 0x006AC000 | 0x006FFFFF |336kB |Reserved |
-------------------------------------------------------------------------
Maximum size is 1.5MB.
We could define a "OCC common area" memory region at the machine level
and sub regions for each OCC. But it adds some extra complexity to the
models. Fix the current layout with a simpler model.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191211082912.2625-3-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 4 ++--
hw/ppc/pnv_occ.c | 11 ++++-------
include/hw/ppc/pnv.h | 4 ++++
include/hw/ppc/pnv_occ.h | 8 ++++++--
4 files changed, 16 insertions(+), 11 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index af7317a86d..0be0b6b411 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1065,7 +1065,7 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
/* OCC SRAM model */
- memory_region_add_subregion(get_system_memory(), PNV_OCC_COMMON_AREA_BASE,
+ memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
&chip8->occ.sram_regs);
/* HOMER */
@@ -1278,7 +1278,7 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
/* OCC SRAM model */
- memory_region_add_subregion(get_system_memory(), PNV9_OCC_COMMON_AREA_BASE,
+ memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
&chip9->occ.sram_regs);
/* HOMER */
diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c
index 765c0a6ce5..924fdabc9e 100644
--- a/hw/ppc/pnv_occ.c
+++ b/hw/ppc/pnv_occ.c
@@ -167,9 +167,7 @@ static void pnv_occ_power8_class_init(ObjectClass *klass, void *data)
PnvOCCClass *poc = PNV_OCC_CLASS(klass);
poc->xscom_size = PNV_XSCOM_OCC_SIZE;
- poc->sram_size = PNV_OCC_COMMON_AREA_SIZE;
poc->xscom_ops = &pnv_occ_power8_xscom_ops;
- poc->sram_ops = &pnv_occ_sram_ops;
poc->psi_irq = PSIHB_IRQ_OCC;
}
@@ -240,9 +238,7 @@ static void pnv_occ_power9_class_init(ObjectClass *klass, void *data)
PnvOCCClass *poc = PNV_OCC_CLASS(klass);
poc->xscom_size = PNV9_XSCOM_OCC_SIZE;
- poc->sram_size = PNV9_OCC_COMMON_AREA_SIZE;
poc->xscom_ops = &pnv_occ_power9_xscom_ops;
- poc->sram_ops = &pnv_occ_sram_ops;
poc->psi_irq = PSIHB9_IRQ_OCC;
}
@@ -266,9 +262,10 @@ static void pnv_occ_realize(DeviceState *dev, Error **errp)
pnv_xscom_region_init(&occ->xscom_regs, OBJECT(dev), poc->xscom_ops,
occ, "xscom-occ", poc->xscom_size);
- /* XScom region for OCC SRAM registers */
- pnv_xscom_region_init(&occ->sram_regs, OBJECT(dev), poc->sram_ops,
- occ, "occ-common-area", poc->sram_size);
+ /* OCC common area mmio region for OCC SRAM registers */
+ memory_region_init_io(&occ->sram_regs, OBJECT(dev), &pnv_occ_sram_ops,
+ occ, "occ-common-area",
+ PNV_OCC_SENSOR_DATA_BLOCK_SIZE);
}
static Property pnv_occ_properties[] = {
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 301c7e62fa..92f80b1cce 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -246,6 +246,8 @@ IPMIBmc *pnv_bmc_create(void);
#define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
#define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull
+#define PNV_OCC_SENSOR_BASE(chip) (PNV_OCC_COMMON_AREA_BASE + \
+ PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip)))
#define PNV_HOMER_SIZE 0x0000000000400000ull
#define PNV_HOMER_BASE(chip) \
@@ -312,6 +314,8 @@ IPMIBmc *pnv_bmc_create(void);
#define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
#define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull
+#define PNV9_OCC_SENSOR_BASE(chip) (PNV9_OCC_COMMON_AREA_BASE + \
+ PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip)))
#define PNV9_HOMER_SIZE 0x0000000000400000ull
#define PNV9_HOMER_BASE(chip) \
diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h
index 66b0989be6..f8d3061419 100644
--- a/include/hw/ppc/pnv_occ.h
+++ b/include/hw/ppc/pnv_occ.h
@@ -29,6 +29,9 @@
#define TYPE_PNV9_OCC TYPE_PNV_OCC "-POWER9"
#define PNV9_OCC(obj) OBJECT_CHECK(PnvOCC, (obj), TYPE_PNV9_OCC)
+#define PNV_OCC_SENSOR_DATA_BLOCK_OFFSET 0x00580000
+#define PNV_OCC_SENSOR_DATA_BLOCK_SIZE 0x00025800
+
typedef struct PnvOCC {
DeviceState xd;
@@ -50,10 +53,11 @@ typedef struct PnvOCCClass {
DeviceClass parent_class;
int xscom_size;
- int sram_size;
const MemoryRegionOps *xscom_ops;
- const MemoryRegionOps *sram_ops;
int psi_irq;
} PnvOCCClass;
+#define PNV_OCC_SENSOR_DATA_BLOCK_BASE(i) \
+ (PNV_OCC_SENSOR_DATA_BLOCK_OFFSET + (i) * PNV_OCC_SENSOR_DATA_BLOCK_SIZE)
+
#endif /* PPC_PNV_OCC_H */
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 75/88] ppc: Drop useless extern annotation for functions
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (73 preceding siblings ...)
2019-12-17 4:43 ` [PULL 74/88] ppc/pnv: Fix OCC common area region mapping David Gibson
@ 2019-12-17 4:43 ` David Gibson
2019-12-17 4:43 ` [PULL 76/88] ppc/pnv: Introduce PnvPsiClass::compat David Gibson
` (13 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:43 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg,
Philippe Mathieu-Daudé,
David Gibson
From: Greg Kurz <groug@kaod.org>
Signed-off-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <157623837421.360005.412120366652768311.stgit@bahia.lan>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
include/hw/ppc/pnv_xscom.h | 22 +++++++++++-----------
include/hw/ppc/spapr_vio.h | 6 +++---
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index 09188d74b0..2bdb7ae84f 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -113,16 +113,16 @@ typedef struct PnvXScomInterfaceClass {
#define PNV10_XSCOM_PSIHB_BASE 0x3011D00
#define PNV10_XSCOM_PSIHB_SIZE 0x100
-extern void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp);
-extern int pnv_dt_xscom(PnvChip *chip, void *fdt, int offset);
-
-extern void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset,
- MemoryRegion *mr);
-extern void pnv_xscom_region_init(MemoryRegion *mr,
- struct Object *owner,
- const MemoryRegionOps *ops,
- void *opaque,
- const char *name,
- uint64_t size);
+void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp);
+int pnv_dt_xscom(PnvChip *chip, void *fdt, int offset);
+
+void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset,
+ MemoryRegion *mr);
+void pnv_xscom_region_init(MemoryRegion *mr,
+ struct Object *owner,
+ const MemoryRegionOps *ops,
+ void *opaque,
+ const char *name,
+ uint64_t size);
#endif /* PPC_PNV_XSCOM_H */
diff --git a/include/hw/ppc/spapr_vio.h b/include/hw/ppc/spapr_vio.h
index 72762ed16b..ce6d9b0c66 100644
--- a/include/hw/ppc/spapr_vio.h
+++ b/include/hw/ppc/spapr_vio.h
@@ -80,10 +80,10 @@ struct SpaprVioBus {
uint32_t next_reg;
};
-extern SpaprVioBus *spapr_vio_bus_init(void);
-extern SpaprVioDevice *spapr_vio_find_by_reg(SpaprVioBus *bus, uint32_t reg);
+SpaprVioBus *spapr_vio_bus_init(void);
+SpaprVioDevice *spapr_vio_find_by_reg(SpaprVioBus *bus, uint32_t reg);
void spapr_dt_vdevice(SpaprVioBus *bus, void *fdt);
-extern gchar *spapr_vio_stdout_path(SpaprVioBus *bus);
+gchar *spapr_vio_stdout_path(SpaprVioBus *bus);
static inline void spapr_vio_irq_pulse(SpaprVioDevice *dev)
{
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 76/88] ppc/pnv: Introduce PnvPsiClass::compat
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (74 preceding siblings ...)
2019-12-17 4:43 ` [PULL 75/88] ppc: Drop useless extern annotation for functions David Gibson
@ 2019-12-17 4:43 ` David Gibson
2019-12-17 4:43 ` [PULL 77/88] ppc/pnv: Drop PnvPsiClass::chip_type David Gibson
` (12 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:43 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
The Processor Service Interface (PSI) model has a chip_type class level
attribute, which is used to generate the content of the "compatible" DT
property according to the CPU type.
Since the PSI model already has specialized classes for each supported
CPU type, it seems cleaner to achieve this with QOM. Provide the content
of the "compatible" property with a new class level attribute.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157623837974.360005.14706607446188964477.stgit@bahia.lan>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv_psi.c | 25 +++++++++++--------------
include/hw/ppc/pnv_psi.h | 2 ++
2 files changed, 13 insertions(+), 14 deletions(-)
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index 572924388b..98a82b25e0 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -536,10 +536,6 @@ static void pnv_psi_power8_realize(DeviceState *dev, Error **errp)
qemu_register_reset(pnv_psi_reset, dev);
}
-static const char compat_p8[] = "ibm,power8-psihb-x\0ibm,psihb-x";
-static const char compat_p9[] = "ibm,power9-psihb-x\0ibm,psihb-x";
-static const char compat_p10[] = "ibm,power10-psihb-x\0ibm,psihb-x";
-
static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
{
PnvPsiClass *ppc = PNV_PSI_GET_CLASS(dev);
@@ -558,16 +554,8 @@ static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
_FDT(fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)));
_FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 2));
_FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1));
- if (ppc->chip_type == PNV_CHIP_POWER10) {
- _FDT(fdt_setprop(fdt, offset, "compatible", compat_p10,
- sizeof(compat_p10)));
- } else if (ppc->chip_type == PNV_CHIP_POWER9) {
- _FDT(fdt_setprop(fdt, offset, "compatible", compat_p9,
- sizeof(compat_p9)));
- } else {
- _FDT(fdt_setprop(fdt, offset, "compatible", compat_p8,
- sizeof(compat_p8)));
- }
+ _FDT(fdt_setprop(fdt, offset, "compatible", ppc->compat,
+ ppc->compat_size));
return 0;
}
@@ -581,6 +569,7 @@ static void pnv_psi_power8_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PnvPsiClass *ppc = PNV_PSI_CLASS(klass);
+ static const char compat[] = "ibm,power8-psihb-x\0ibm,psihb-x";
dc->desc = "PowerNV PSI Controller POWER8";
dc->realize = pnv_psi_power8_realize;
@@ -590,6 +579,8 @@ static void pnv_psi_power8_class_init(ObjectClass *klass, void *data)
ppc->xscom_size = PNV_XSCOM_PSIHB_SIZE;
ppc->bar_mask = PSIHB_BAR_MASK;
ppc->irq_set = pnv_psi_power8_irq_set;
+ ppc->compat = compat;
+ ppc->compat_size = sizeof(compat);
}
static const TypeInfo pnv_psi_power8_info = {
@@ -888,6 +879,7 @@ static void pnv_psi_power9_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PnvPsiClass *ppc = PNV_PSI_CLASS(klass);
XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass);
+ static const char compat[] = "ibm,power9-psihb-x\0ibm,psihb-x";
dc->desc = "PowerNV PSI Controller POWER9";
dc->realize = pnv_psi_power9_realize;
@@ -897,6 +889,8 @@ static void pnv_psi_power9_class_init(ObjectClass *klass, void *data)
ppc->xscom_size = PNV9_XSCOM_PSIHB_SIZE;
ppc->bar_mask = PSIHB9_BAR_MASK;
ppc->irq_set = pnv_psi_power9_irq_set;
+ ppc->compat = compat;
+ ppc->compat_size = sizeof(compat);
xfc->notify = pnv_psi_notify;
}
@@ -917,12 +911,15 @@ static void pnv_psi_power10_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PnvPsiClass *ppc = PNV_PSI_CLASS(klass);
+ static const char compat[] = "ibm,power10-psihb-x\0ibm,psihb-x";
dc->desc = "PowerNV PSI Controller POWER10";
ppc->chip_type = PNV_CHIP_POWER10;
ppc->xscom_pcba = PNV10_XSCOM_PSIHB_BASE;
ppc->xscom_size = PNV10_XSCOM_PSIHB_SIZE;
+ ppc->compat = compat;
+ ppc->compat_size = sizeof(compat);
}
static const TypeInfo pnv_psi_power10_info = {
diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h
index a044aab304..fc068c95e5 100644
--- a/include/hw/ppc/pnv_psi.h
+++ b/include/hw/ppc/pnv_psi.h
@@ -83,6 +83,8 @@ typedef struct PnvPsiClass {
uint32_t xscom_pcba;
uint32_t xscom_size;
uint64_t bar_mask;
+ const char *compat;
+ int compat_size;
void (*irq_set)(PnvPsi *psi, int, bool state);
} PnvPsiClass;
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 77/88] ppc/pnv: Drop PnvPsiClass::chip_type
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (75 preceding siblings ...)
2019-12-17 4:43 ` [PULL 76/88] ppc/pnv: Introduce PnvPsiClass::compat David Gibson
@ 2019-12-17 4:43 ` David Gibson
2019-12-17 4:43 ` [PULL 78/88] ppc/pnv: Introduce PnvMachineClass and PnvMachineClass::compat David Gibson
` (11 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:43 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
It isn't used anymore.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157623838530.360005.15470128760871845396.stgit@bahia.lan>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv_psi.c | 3 ---
include/hw/ppc/pnv_psi.h | 1 -
2 files changed, 4 deletions(-)
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index 98a82b25e0..75e20d9da0 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -574,7 +574,6 @@ static void pnv_psi_power8_class_init(ObjectClass *klass, void *data)
dc->desc = "PowerNV PSI Controller POWER8";
dc->realize = pnv_psi_power8_realize;
- ppc->chip_type = PNV_CHIP_POWER8;
ppc->xscom_pcba = PNV_XSCOM_PSIHB_BASE;
ppc->xscom_size = PNV_XSCOM_PSIHB_SIZE;
ppc->bar_mask = PSIHB_BAR_MASK;
@@ -884,7 +883,6 @@ static void pnv_psi_power9_class_init(ObjectClass *klass, void *data)
dc->desc = "PowerNV PSI Controller POWER9";
dc->realize = pnv_psi_power9_realize;
- ppc->chip_type = PNV_CHIP_POWER9;
ppc->xscom_pcba = PNV9_XSCOM_PSIHB_BASE;
ppc->xscom_size = PNV9_XSCOM_PSIHB_SIZE;
ppc->bar_mask = PSIHB9_BAR_MASK;
@@ -915,7 +913,6 @@ static void pnv_psi_power10_class_init(ObjectClass *klass, void *data)
dc->desc = "PowerNV PSI Controller POWER10";
- ppc->chip_type = PNV_CHIP_POWER10;
ppc->xscom_pcba = PNV10_XSCOM_PSIHB_BASE;
ppc->xscom_size = PNV10_XSCOM_PSIHB_SIZE;
ppc->compat = compat;
diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h
index fc068c95e5..f0f5b55197 100644
--- a/include/hw/ppc/pnv_psi.h
+++ b/include/hw/ppc/pnv_psi.h
@@ -79,7 +79,6 @@ typedef struct Pnv9Psi {
typedef struct PnvPsiClass {
SysBusDeviceClass parent_class;
- int chip_type;
uint32_t xscom_pcba;
uint32_t xscom_size;
uint64_t bar_mask;
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 78/88] ppc/pnv: Introduce PnvMachineClass and PnvMachineClass::compat
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (76 preceding siblings ...)
2019-12-17 4:43 ` [PULL 77/88] ppc/pnv: Drop PnvPsiClass::chip_type David Gibson
@ 2019-12-17 4:43 ` David Gibson
2019-12-17 4:43 ` [PULL 79/88] ppc/pnv: Introduce PnvMachineClass::dt_power_mgt() David Gibson
` (10 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:43 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
The pnv_dt_create() function generates different contents for the
"compatible" property of the root node in the DT, depending on the
CPU type. This is open coded with multiple ifs using pnv_is_powerXX()
helpers.
It seems cleaner to achieve with QOM. Introduce a base class for the
powernv machine and a compat attribute that each child class can use
to provide the value for the "compatible" property.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157623839085.360005.4046508784077843216.stgit@bahia.lan>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[dwg: Folded in small fix Greg spotted after posting]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 32 ++++++++++++++++++--------------
include/hw/ppc/pnv.h | 13 +++++++++++++
2 files changed, 31 insertions(+), 14 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 0be0b6b411..97845e7bde 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -484,9 +484,7 @@ static void pnv_dt_power_mgt(void *fdt)
static void *pnv_dt_create(MachineState *machine)
{
- const char plat_compat8[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
- const char plat_compat9[] = "qemu,powernv9\0ibm,powernv";
- const char plat_compat10[] = "qemu,powernv10\0ibm,powernv";
+ PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine);
PnvMachineState *pnv = PNV_MACHINE(machine);
void *fdt;
char *buf;
@@ -504,17 +502,7 @@ static void *pnv_dt_create(MachineState *machine)
_FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
_FDT((fdt_setprop_string(fdt, 0, "model",
"IBM PowerNV (emulated by qemu)")));
- if (pnv_is_power10(pnv)) {
- _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat10,
- sizeof(plat_compat10))));
- } else if (pnv_is_power9(pnv)) {
- _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat9,
- sizeof(plat_compat9))));
- } else {
- _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat8,
- sizeof(plat_compat8))));
- }
-
+ _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size)));
buf = qemu_uuid_unparse_strdup(&qemu_uuid);
_FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
@@ -1692,6 +1680,8 @@ static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
+ PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
+ static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
@@ -1699,26 +1689,39 @@ static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
xic->icp_get = pnv_icp_get;
xic->ics_get = pnv_ics_get;
xic->ics_resend = pnv_ics_resend;
+
+ pmc->compat = compat;
+ pmc->compat_size = sizeof(compat);
}
static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
+ PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
+ static const char compat[] = "qemu,powernv9\0ibm,powernv";
mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
xfc->match_nvt = pnv_match_nvt;
mc->alias = "powernv";
+
+ pmc->compat = compat;
+ pmc->compat_size = sizeof(compat);
}
static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
+ PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
+ static const char compat[] = "qemu,powernv10\0ibm,powernv";
mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0");
+
+ pmc->compat = compat;
+ pmc->compat_size = sizeof(compat);
}
static void pnv_machine_class_init(ObjectClass *oc, void *data)
@@ -1796,6 +1799,7 @@ static const TypeInfo types[] = {
.instance_size = sizeof(PnvMachineState),
.instance_init = pnv_machine_instance_init,
.class_init = pnv_machine_class_init,
+ .class_size = sizeof(PnvMachineClass),
.interfaces = (InterfaceInfo[]) {
{ TYPE_INTERRUPT_STATS_PROVIDER },
{ },
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 92f80b1cce..d534746bd4 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -185,6 +185,19 @@ PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
#define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
#define PNV_MACHINE(obj) \
OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE)
+#define PNV_MACHINE_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(PnvMachineClass, obj, TYPE_PNV_MACHINE)
+#define PNV_MACHINE_CLASS(klass) \
+ OBJECT_CLASS_CHECK(PnvMachineClass, klass, TYPE_PNV_MACHINE)
+
+typedef struct PnvMachineClass {
+ /*< private >*/
+ MachineClass parent_class;
+
+ /*< public >*/
+ const char *compat;
+ int compat_size;
+} PnvMachineClass;
typedef struct PnvMachineState {
/*< private >*/
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 79/88] ppc/pnv: Introduce PnvMachineClass::dt_power_mgt()
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (77 preceding siblings ...)
2019-12-17 4:43 ` [PULL 78/88] ppc/pnv: Introduce PnvMachineClass and PnvMachineClass::compat David Gibson
@ 2019-12-17 4:43 ` David Gibson
2019-12-17 4:43 ` [PULL 80/88] ppc/pnv: Drop pnv_is_power9() and pnv_is_power10() helpers David Gibson
` (9 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:43 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
We add an extra node to advertise power management on some machines,
namely powernv9 and powernv10. This is achieved by using the
pnv_is_power9() and pnv_is_power10() helpers.
This can be achieved with QOM. Add a method to the base class for
powernv machines and have it implemented by machine types that
support power management instead.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157623839642.360005.9243510140436689941.stgit@bahia.lan>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 10 ++++++----
include/hw/ppc/pnv.h | 8 ++++++--
2 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 97845e7bde..a2ad7258f8 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -472,7 +472,7 @@ static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
&args);
}
-static void pnv_dt_power_mgt(void *fdt)
+static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt)
{
int off;
@@ -539,9 +539,9 @@ static void *pnv_dt_create(MachineState *machine)
pnv_dt_bmc_sensors(pnv->bmc, fdt);
}
- /* Create an extra node for power management on Power9 and Power10 */
- if (pnv_is_power9(pnv) || pnv_is_power10(pnv)) {
- pnv_dt_power_mgt(fdt);
+ /* Create an extra node for power management on machines that support it */
+ if (pmc->dt_power_mgt) {
+ pmc->dt_power_mgt(pnv, fdt);
}
return fdt;
@@ -1709,6 +1709,7 @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
pmc->compat = compat;
pmc->compat_size = sizeof(compat);
+ pmc->dt_power_mgt = pnv_dt_power_mgt;
}
static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
@@ -1722,6 +1723,7 @@ static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
pmc->compat = compat;
pmc->compat_size = sizeof(compat);
+ pmc->dt_power_mgt = pnv_dt_power_mgt;
}
static void pnv_machine_class_init(ObjectClass *oc, void *data)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index d534746bd4..8a42c199b6 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -190,6 +190,8 @@ PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
#define PNV_MACHINE_CLASS(klass) \
OBJECT_CLASS_CHECK(PnvMachineClass, klass, TYPE_PNV_MACHINE)
+typedef struct PnvMachineState PnvMachineState;
+
typedef struct PnvMachineClass {
/*< private >*/
MachineClass parent_class;
@@ -197,9 +199,11 @@ typedef struct PnvMachineClass {
/*< public >*/
const char *compat;
int compat_size;
+
+ void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt);
} PnvMachineClass;
-typedef struct PnvMachineState {
+struct PnvMachineState {
/*< private >*/
MachineState parent_obj;
@@ -216,7 +220,7 @@ typedef struct PnvMachineState {
Notifier powerdown_notifier;
PnvPnor *pnor;
-} PnvMachineState;
+};
static inline bool pnv_chip_is_power9(const PnvChip *chip)
{
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 80/88] ppc/pnv: Drop pnv_is_power9() and pnv_is_power10() helpers
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (78 preceding siblings ...)
2019-12-17 4:43 ` [PULL 79/88] ppc/pnv: Introduce PnvMachineClass::dt_power_mgt() David Gibson
@ 2019-12-17 4:43 ` David Gibson
2019-12-17 4:43 ` [PULL 81/88] ppc/pnv: Introduce PnvChipClass::intc_print_info() method David Gibson
` (8 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:43 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
They aren't used anymore.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157623840200.360005.1300941274565357363.stgit@bahia.lan>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
include/hw/ppc/pnv.h | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 8a42c199b6..c213bdd5ec 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -227,11 +227,6 @@ static inline bool pnv_chip_is_power9(const PnvChip *chip)
return PNV_CHIP_GET_CLASS(chip)->chip_type == PNV_CHIP_POWER9;
}
-static inline bool pnv_is_power9(PnvMachineState *pnv)
-{
- return pnv_chip_is_power9(pnv->chips[0]);
-}
-
PnvChip *pnv_get_chip(uint32_t chip_id);
#define PNV_FDT_ADDR 0x01000000
@@ -242,11 +237,6 @@ static inline bool pnv_chip_is_power10(const PnvChip *chip)
return PNV_CHIP_GET_CLASS(chip)->chip_type == PNV_CHIP_POWER10;
}
-static inline bool pnv_is_power10(PnvMachineState *pnv)
-{
- return pnv_chip_is_power10(pnv->chips[0]);
-}
-
/*
* BMC helpers
*/
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 81/88] ppc/pnv: Introduce PnvChipClass::intc_print_info() method
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (79 preceding siblings ...)
2019-12-17 4:43 ` [PULL 80/88] ppc/pnv: Drop pnv_is_power9() and pnv_is_power10() helpers David Gibson
@ 2019-12-17 4:43 ` David Gibson
2019-12-17 4:43 ` [PULL 82/88] ppc/pnv: Introduce PnvChipClass::xscom_core_base() method David Gibson
` (7 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:43 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
The pnv_pic_print_info() callback checks the type of the chip in order
to forward to the request appropriate interrupt controller. This can
be achieved with QOM. Introduce a method for this in the base chip class
and implement it in child classes.
This also prepares ground for the upcoming interrupt controller of POWER10
chips.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157623840755.360005.5002022339473369934.stgit@bahia.lan>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 30 +++++++++++++++++++++++++-----
include/hw/ppc/pnv.h | 1 +
2 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index a2ad7258f8..35416d1b3f 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -831,6 +831,12 @@ static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
pnv_cpu->intc = NULL;
}
+static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
+ Monitor *mon)
+{
+ icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon);
+}
+
/*
* 0:48 Reserved - Read as zeroes
* 49:52 Node ID
@@ -888,6 +894,12 @@ static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
pnv_cpu->intc = NULL;
}
+static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
+ Monitor *mon)
+{
+ xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
+}
+
static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu,
Error **errp)
{
@@ -909,6 +921,11 @@ static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
pnv_cpu->intc = NULL;
}
+static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
+ Monitor *mon)
+{
+}
+
/*
* Allowed core identifiers on a POWER8 Processor Chip :
*
@@ -1085,6 +1102,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
k->intc_create = pnv_chip_power8_intc_create;
k->intc_reset = pnv_chip_power8_intc_reset;
k->intc_destroy = pnv_chip_power8_intc_destroy;
+ k->intc_print_info = pnv_chip_power8_intc_print_info;
k->isa_create = pnv_chip_power8_isa_create;
k->dt_populate = pnv_chip_power8_dt_populate;
k->pic_print_info = pnv_chip_power8_pic_print_info;
@@ -1106,6 +1124,7 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
k->intc_create = pnv_chip_power8_intc_create;
k->intc_reset = pnv_chip_power8_intc_reset;
k->intc_destroy = pnv_chip_power8_intc_destroy;
+ k->intc_print_info = pnv_chip_power8_intc_print_info;
k->isa_create = pnv_chip_power8_isa_create;
k->dt_populate = pnv_chip_power8_dt_populate;
k->pic_print_info = pnv_chip_power8_pic_print_info;
@@ -1127,6 +1146,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
k->intc_create = pnv_chip_power8_intc_create;
k->intc_reset = pnv_chip_power8_intc_reset;
k->intc_destroy = pnv_chip_power8_intc_destroy;
+ k->intc_print_info = pnv_chip_power8_intc_print_info;
k->isa_create = pnv_chip_power8nvl_isa_create;
k->dt_populate = pnv_chip_power8_dt_populate;
k->pic_print_info = pnv_chip_power8_pic_print_info;
@@ -1298,6 +1318,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
k->intc_create = pnv_chip_power9_intc_create;
k->intc_reset = pnv_chip_power9_intc_reset;
k->intc_destroy = pnv_chip_power9_intc_destroy;
+ k->intc_print_info = pnv_chip_power9_intc_print_info;
k->isa_create = pnv_chip_power9_isa_create;
k->dt_populate = pnv_chip_power9_dt_populate;
k->pic_print_info = pnv_chip_power9_pic_print_info;
@@ -1378,6 +1399,7 @@ static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
k->intc_create = pnv_chip_power10_intc_create;
k->intc_reset = pnv_chip_power10_intc_reset;
k->intc_destroy = pnv_chip_power10_intc_destroy;
+ k->intc_print_info = pnv_chip_power10_intc_print_info;
k->isa_create = pnv_chip_power10_isa_create;
k->dt_populate = pnv_chip_power10_dt_populate;
k->pic_print_info = pnv_chip_power10_pic_print_info;
@@ -1574,11 +1596,9 @@ static void pnv_pic_print_info(InterruptStatsProvider *obj,
CPU_FOREACH(cs) {
PowerPCCPU *cpu = POWERPC_CPU(cs);
- if (pnv_chip_is_power9(pnv->chips[0])) {
- xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
- } else {
- icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon);
- }
+ /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */
+ PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu,
+ mon);
}
for (i = 0; i < pnv->num_chips; i++) {
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index c213bdd5ec..7d2402784d 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -133,6 +133,7 @@ typedef struct PnvChipClass {
void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu);
void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu);
+ void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon);
ISABus *(*isa_create)(PnvChip *chip, Error **errp);
void (*dt_populate)(PnvChip *chip, void *fdt);
void (*pic_print_info)(PnvChip *chip, Monitor *mon);
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 82/88] ppc/pnv: Introduce PnvChipClass::xscom_core_base() method
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (80 preceding siblings ...)
2019-12-17 4:43 ` [PULL 81/88] ppc/pnv: Introduce PnvChipClass::intc_print_info() method David Gibson
@ 2019-12-17 4:43 ` David Gibson
2019-12-17 4:43 ` [PULL 83/88] ppc/pnv: Pass XSCOM base address and address size to pnv_dt_xscom() David Gibson
` (6 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:43 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
The pnv_chip_core_realize() function configures the XSCOM MMIO subregion
for each core of a single chip. The base address of the subregion depends
on the CPU type. Its computation is currently open-code using the
pnv_chip_is_powerXX() helpers. This can be achieved with QOM. Introduce
a method for this in the base chip class and implement it in child classes.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157623841311.360005.4705705734873339545.stgit@bahia.lan>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 31 ++++++++++++++++++++++++-------
include/hw/ppc/pnv.h | 1 +
2 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 35416d1b3f..16f4e407ee 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -615,6 +615,24 @@ static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
pnv_psi_pic_print_info(&chip9->psi, mon);
}
+static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip,
+ uint32_t core_id)
+{
+ return PNV_XSCOM_EX_BASE(core_id);
+}
+
+static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip,
+ uint32_t core_id)
+{
+ return PNV9_XSCOM_EC_BASE(core_id);
+}
+
+static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip,
+ uint32_t core_id)
+{
+ return PNV10_XSCOM_EC_BASE(core_id);
+}
+
static bool pnv_match_cpu(const char *default_type, const char *cpu_type)
{
PowerPCCPUClass *ppc_default =
@@ -1106,6 +1124,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
k->isa_create = pnv_chip_power8_isa_create;
k->dt_populate = pnv_chip_power8_dt_populate;
k->pic_print_info = pnv_chip_power8_pic_print_info;
+ k->xscom_core_base = pnv_chip_power8_xscom_core_base;
dc->desc = "PowerNV Chip POWER8E";
device_class_set_parent_realize(dc, pnv_chip_power8_realize,
@@ -1128,6 +1147,7 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
k->isa_create = pnv_chip_power8_isa_create;
k->dt_populate = pnv_chip_power8_dt_populate;
k->pic_print_info = pnv_chip_power8_pic_print_info;
+ k->xscom_core_base = pnv_chip_power8_xscom_core_base;
dc->desc = "PowerNV Chip POWER8";
device_class_set_parent_realize(dc, pnv_chip_power8_realize,
@@ -1150,6 +1170,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
k->isa_create = pnv_chip_power8nvl_isa_create;
k->dt_populate = pnv_chip_power8_dt_populate;
k->pic_print_info = pnv_chip_power8_pic_print_info;
+ k->xscom_core_base = pnv_chip_power8_xscom_core_base;
dc->desc = "PowerNV Chip POWER8NVL";
device_class_set_parent_realize(dc, pnv_chip_power8_realize,
@@ -1322,6 +1343,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
k->isa_create = pnv_chip_power9_isa_create;
k->dt_populate = pnv_chip_power9_dt_populate;
k->pic_print_info = pnv_chip_power9_pic_print_info;
+ k->xscom_core_base = pnv_chip_power9_xscom_core_base;
dc->desc = "PowerNV Chip POWER9";
device_class_set_parent_realize(dc, pnv_chip_power9_realize,
@@ -1403,6 +1425,7 @@ static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
k->isa_create = pnv_chip_power10_isa_create;
k->dt_populate = pnv_chip_power10_dt_populate;
k->pic_print_info = pnv_chip_power10_pic_print_info;
+ k->xscom_core_base = pnv_chip_power10_xscom_core_base;
dc->desc = "PowerNV Chip POWER10";
device_class_set_parent_realize(dc, pnv_chip_power10_realize,
@@ -1490,13 +1513,7 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
&error_fatal);
/* Each core has an XSCOM MMIO region */
- if (pnv_chip_is_power10(chip)) {
- xscom_core_base = PNV10_XSCOM_EC_BASE(core_hwid);
- } else if (pnv_chip_is_power9(chip)) {
- xscom_core_base = PNV9_XSCOM_EC_BASE(core_hwid);
- } else {
- xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid);
- }
+ xscom_core_base = pcc->xscom_core_base(chip, core_hwid);
pnv_xscom_add_subregion(chip, xscom_core_base,
&pnv_core->xscom_regs);
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 7d2402784d..17ca9a14ac 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -137,6 +137,7 @@ typedef struct PnvChipClass {
ISABus *(*isa_create)(PnvChip *chip, Error **errp);
void (*dt_populate)(PnvChip *chip, void *fdt);
void (*pic_print_info)(PnvChip *chip, Monitor *mon);
+ uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id);
} PnvChipClass;
#define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 83/88] ppc/pnv: Pass XSCOM base address and address size to pnv_dt_xscom()
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (81 preceding siblings ...)
2019-12-17 4:43 ` [PULL 82/88] ppc/pnv: Introduce PnvChipClass::xscom_core_base() method David Gibson
@ 2019-12-17 4:43 ` David Gibson
2019-12-17 4:43 ` [PULL 84/88] ppc/pnv: Pass content of the "compatible" property " David Gibson
` (5 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:43 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
Since pnv_dt_xscom() is called from chip specific dt_populate() hooks,
it shouldn't have to guess the chip type in order to populate the "reg"
property. Just pass the base address and address size as arguments.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157623841868.360005.17577624823547136435.stgit@bahia.lan>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 12 +++++++++---
hw/ppc/pnv_xscom.c | 16 +++-------------
include/hw/ppc/pnv_xscom.h | 3 ++-
3 files changed, 14 insertions(+), 17 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 16f4e407ee..c0a5703b74 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -282,7 +282,9 @@ static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
{
int i;
- pnv_dt_xscom(chip, fdt, 0);
+ pnv_dt_xscom(chip, fdt, 0,
+ cpu_to_be64(PNV_XSCOM_BASE(chip)),
+ cpu_to_be64(PNV_XSCOM_SIZE));
for (i = 0; i < chip->nr_cores; i++) {
PnvCore *pnv_core = chip->cores[i];
@@ -302,7 +304,9 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
{
int i;
- pnv_dt_xscom(chip, fdt, 0);
+ pnv_dt_xscom(chip, fdt, 0,
+ cpu_to_be64(PNV9_XSCOM_BASE(chip)),
+ cpu_to_be64(PNV9_XSCOM_SIZE));
for (i = 0; i < chip->nr_cores; i++) {
PnvCore *pnv_core = chip->cores[i];
@@ -321,7 +325,9 @@ static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
{
int i;
- pnv_dt_xscom(chip, fdt, 0);
+ pnv_dt_xscom(chip, fdt, 0,
+ cpu_to_be64(PNV10_XSCOM_BASE(chip)),
+ cpu_to_be64(PNV10_XSCOM_SIZE));
for (i = 0; i < chip->nr_cores; i++) {
PnvCore *pnv_core = chip->cores[i];
diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c
index df926003f2..8189767eb0 100644
--- a/hw/ppc/pnv_xscom.c
+++ b/hw/ppc/pnv_xscom.c
@@ -286,24 +286,14 @@ static const char compat_p8[] = "ibm,power8-xscom\0ibm,xscom";
static const char compat_p9[] = "ibm,power9-xscom\0ibm,xscom";
static const char compat_p10[] = "ibm,power10-xscom\0ibm,xscom";
-int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset)
+int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset,
+ uint64_t xscom_base, uint64_t xscom_size)
{
- uint64_t reg[2];
+ uint64_t reg[] = { xscom_base, xscom_size };
int xscom_offset;
ForeachPopulateArgs args;
char *name;
- if (pnv_chip_is_power10(chip)) {
- reg[0] = cpu_to_be64(PNV10_XSCOM_BASE(chip));
- reg[1] = cpu_to_be64(PNV10_XSCOM_SIZE);
- } else if (pnv_chip_is_power9(chip)) {
- reg[0] = cpu_to_be64(PNV9_XSCOM_BASE(chip));
- reg[1] = cpu_to_be64(PNV9_XSCOM_SIZE);
- } else {
- reg[0] = cpu_to_be64(PNV_XSCOM_BASE(chip));
- reg[1] = cpu_to_be64(PNV_XSCOM_SIZE);
- }
-
name = g_strdup_printf("xscom@%" PRIx64, be64_to_cpu(reg[0]));
xscom_offset = fdt_add_subnode(fdt, root_offset, name);
_FDT(xscom_offset);
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index 2bdb7ae84f..ad53f788b4 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -114,7 +114,8 @@ typedef struct PnvXScomInterfaceClass {
#define PNV10_XSCOM_PSIHB_SIZE 0x100
void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp);
-int pnv_dt_xscom(PnvChip *chip, void *fdt, int offset);
+int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset,
+ uint64_t xscom_base, uint64_t xscom_size);
void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset,
MemoryRegion *mr);
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 84/88] ppc/pnv: Pass content of the "compatible" property to pnv_dt_xscom()
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (82 preceding siblings ...)
2019-12-17 4:43 ` [PULL 83/88] ppc/pnv: Pass XSCOM base address and address size to pnv_dt_xscom() David Gibson
@ 2019-12-17 4:43 ` David Gibson
2019-12-17 4:43 ` [PULL 85/88] ppc/pnv: Drop pnv_chip_is_power9() and pnv_chip_is_power10() helpers David Gibson
` (4 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:43 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
Since pnv_dt_xscom() is called from chip specific dt_populate() hooks,
it shouldn't have to guess the chip type in order to populate the
"compatible" property. Just pass the compat string and its size as
arguments.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157623842430.360005.9513965612524265862.stgit@bahia.lan>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 12 +++++++++---
hw/ppc/pnv_xscom.c | 20 +++-----------------
include/hw/ppc/pnv_xscom.h | 3 ++-
3 files changed, 14 insertions(+), 21 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index c0a5703b74..b3388038c6 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -280,11 +280,13 @@ static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
{
+ static const char compat[] = "ibm,power8-xscom\0ibm,xscom";
int i;
pnv_dt_xscom(chip, fdt, 0,
cpu_to_be64(PNV_XSCOM_BASE(chip)),
- cpu_to_be64(PNV_XSCOM_SIZE));
+ cpu_to_be64(PNV_XSCOM_SIZE),
+ compat, sizeof(compat));
for (i = 0; i < chip->nr_cores; i++) {
PnvCore *pnv_core = chip->cores[i];
@@ -302,11 +304,13 @@ static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
{
+ static const char compat[] = "ibm,power9-xscom\0ibm,xscom";
int i;
pnv_dt_xscom(chip, fdt, 0,
cpu_to_be64(PNV9_XSCOM_BASE(chip)),
- cpu_to_be64(PNV9_XSCOM_SIZE));
+ cpu_to_be64(PNV9_XSCOM_SIZE),
+ compat, sizeof(compat));
for (i = 0; i < chip->nr_cores; i++) {
PnvCore *pnv_core = chip->cores[i];
@@ -323,11 +327,13 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
{
+ static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
int i;
pnv_dt_xscom(chip, fdt, 0,
cpu_to_be64(PNV10_XSCOM_BASE(chip)),
- cpu_to_be64(PNV10_XSCOM_SIZE));
+ cpu_to_be64(PNV10_XSCOM_SIZE),
+ compat, sizeof(compat));
for (i = 0; i < chip->nr_cores; i++) {
PnvCore *pnv_core = chip->cores[i];
diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c
index 8189767eb0..5ae9dfbb88 100644
--- a/hw/ppc/pnv_xscom.c
+++ b/hw/ppc/pnv_xscom.c
@@ -282,12 +282,9 @@ static int xscom_dt_child(Object *child, void *opaque)
return 0;
}
-static const char compat_p8[] = "ibm,power8-xscom\0ibm,xscom";
-static const char compat_p9[] = "ibm,power9-xscom\0ibm,xscom";
-static const char compat_p10[] = "ibm,power10-xscom\0ibm,xscom";
-
int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset,
- uint64_t xscom_base, uint64_t xscom_size)
+ uint64_t xscom_base, uint64_t xscom_size,
+ const char *compat, int compat_size)
{
uint64_t reg[] = { xscom_base, xscom_size };
int xscom_offset;
@@ -302,18 +299,7 @@ int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset,
_FDT((fdt_setprop_cell(fdt, xscom_offset, "#address-cells", 1)));
_FDT((fdt_setprop_cell(fdt, xscom_offset, "#size-cells", 1)));
_FDT((fdt_setprop(fdt, xscom_offset, "reg", reg, sizeof(reg))));
-
- if (pnv_chip_is_power10(chip)) {
- _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p10,
- sizeof(compat_p10))));
- } else if (pnv_chip_is_power9(chip)) {
- _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p9,
- sizeof(compat_p9))));
- } else {
- _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p8,
- sizeof(compat_p8))));
- }
-
+ _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat, compat_size)));
_FDT((fdt_setprop(fdt, xscom_offset, "scom-controller", NULL, 0)));
args.fdt = fdt;
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index ad53f788b4..f74c81a980 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -115,7 +115,8 @@ typedef struct PnvXScomInterfaceClass {
void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp);
int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset,
- uint64_t xscom_base, uint64_t xscom_size);
+ uint64_t xscom_base, uint64_t xscom_size,
+ const char *compat, int compat_size);
void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset,
MemoryRegion *mr);
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 85/88] ppc/pnv: Drop pnv_chip_is_power9() and pnv_chip_is_power10() helpers
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (83 preceding siblings ...)
2019-12-17 4:43 ` [PULL 84/88] ppc/pnv: Pass content of the "compatible" property " David Gibson
@ 2019-12-17 4:43 ` David Gibson
2019-12-17 4:43 ` [PULL 86/88] ppc/pnv: Introduce PnvChipClass::xscom_pcba() method David Gibson
` (3 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:43 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
They aren't used anymore.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157623842986.360005.1787401623906380181.stgit@bahia.lan>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
include/hw/ppc/pnv.h | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 17ca9a14ac..7a134a15d3 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -224,21 +224,11 @@ struct PnvMachineState {
PnvPnor *pnor;
};
-static inline bool pnv_chip_is_power9(const PnvChip *chip)
-{
- return PNV_CHIP_GET_CLASS(chip)->chip_type == PNV_CHIP_POWER9;
-}
-
PnvChip *pnv_get_chip(uint32_t chip_id);
#define PNV_FDT_ADDR 0x01000000
#define PNV_TIMEBASE_FREQ 512000000ULL
-static inline bool pnv_chip_is_power10(const PnvChip *chip)
-{
- return PNV_CHIP_GET_CLASS(chip)->chip_type == PNV_CHIP_POWER10;
-}
-
/*
* BMC helpers
*/
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 86/88] ppc/pnv: Introduce PnvChipClass::xscom_pcba() method
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (84 preceding siblings ...)
2019-12-17 4:43 ` [PULL 85/88] ppc/pnv: Drop pnv_chip_is_power9() and pnv_chip_is_power10() helpers David Gibson
@ 2019-12-17 4:43 ` David Gibson
2019-12-17 4:43 ` [PULL 87/88] ppc/pnv: Drop PnvChipClass::type David Gibson
` (2 subsequent siblings)
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:43 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
The XSCOM bus is implemented with a QOM interface, which is mostly
generic from a CPU type standpoint, except for the computation of
addresses on the Pervasive Connect Bus (PCB) network. This is handled
by the pnv_xscom_pcba() function with a switch statement based on
the chip_type class level attribute of the CPU chip.
This can be achieved using QOM. Also the address argument is masked with
PNV_XSCOM_SIZE - 1, which is for POWER8 only. Addresses may have different
sizes with other CPU types. Have each CPU chip type handle the appropriate
computation with a QOM xscom_pcba() method.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157623843543.360005.13996472463887521794.stgit@bahia.lan>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 23 +++++++++++++++++++++++
hw/ppc/pnv_xscom.c | 14 +-------------
include/hw/ppc/pnv.h | 1 +
3 files changed, 25 insertions(+), 13 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index b3388038c6..41e5d762df 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1120,6 +1120,12 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
&chip8->homer.regs);
}
+static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr)
+{
+ addr &= (PNV_XSCOM_SIZE - 1);
+ return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
+}
+
static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -1137,6 +1143,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
k->dt_populate = pnv_chip_power8_dt_populate;
k->pic_print_info = pnv_chip_power8_pic_print_info;
k->xscom_core_base = pnv_chip_power8_xscom_core_base;
+ k->xscom_pcba = pnv_chip_power8_xscom_pcba;
dc->desc = "PowerNV Chip POWER8E";
device_class_set_parent_realize(dc, pnv_chip_power8_realize,
@@ -1160,6 +1167,7 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
k->dt_populate = pnv_chip_power8_dt_populate;
k->pic_print_info = pnv_chip_power8_pic_print_info;
k->xscom_core_base = pnv_chip_power8_xscom_core_base;
+ k->xscom_pcba = pnv_chip_power8_xscom_pcba;
dc->desc = "PowerNV Chip POWER8";
device_class_set_parent_realize(dc, pnv_chip_power8_realize,
@@ -1183,6 +1191,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
k->dt_populate = pnv_chip_power8_dt_populate;
k->pic_print_info = pnv_chip_power8_pic_print_info;
k->xscom_core_base = pnv_chip_power8_xscom_core_base;
+ k->xscom_pcba = pnv_chip_power8_xscom_pcba;
dc->desc = "PowerNV Chip POWER8NVL";
device_class_set_parent_realize(dc, pnv_chip_power8_realize,
@@ -1339,6 +1348,12 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
&chip9->homer.regs);
}
+static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr)
+{
+ addr &= (PNV9_XSCOM_SIZE - 1);
+ return addr >> 3;
+}
+
static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -1356,6 +1371,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
k->dt_populate = pnv_chip_power9_dt_populate;
k->pic_print_info = pnv_chip_power9_pic_print_info;
k->xscom_core_base = pnv_chip_power9_xscom_core_base;
+ k->xscom_pcba = pnv_chip_power9_xscom_pcba;
dc->desc = "PowerNV Chip POWER9";
device_class_set_parent_realize(dc, pnv_chip_power9_realize,
@@ -1421,6 +1437,12 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
(uint64_t) PNV10_LPCM_BASE(chip));
}
+static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr)
+{
+ addr &= (PNV10_XSCOM_SIZE - 1);
+ return addr >> 3;
+}
+
static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -1438,6 +1460,7 @@ static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
k->dt_populate = pnv_chip_power10_dt_populate;
k->pic_print_info = pnv_chip_power10_pic_print_info;
k->xscom_core_base = pnv_chip_power10_xscom_core_base;
+ k->xscom_pcba = pnv_chip_power10_xscom_pcba;
dc->desc = "PowerNV Chip POWER10";
device_class_set_parent_realize(dc, pnv_chip_power10_realize,
diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c
index 5ae9dfbb88..b681c72575 100644
--- a/hw/ppc/pnv_xscom.c
+++ b/hw/ppc/pnv_xscom.c
@@ -57,19 +57,7 @@ static void xscom_complete(CPUState *cs, uint64_t hmer_bits)
static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr)
{
- addr &= (PNV_XSCOM_SIZE - 1);
-
- switch (PNV_CHIP_GET_CLASS(chip)->chip_type) {
- case PNV_CHIP_POWER8E:
- case PNV_CHIP_POWER8:
- case PNV_CHIP_POWER8NVL:
- return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
- case PNV_CHIP_POWER9:
- case PNV_CHIP_POWER10:
- return addr >> 3;
- default:
- g_assert_not_reached();
- }
+ return PNV_CHIP_GET_CLASS(chip)->xscom_pcba(chip, addr);
}
static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 7a134a15d3..4972e93c26 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -138,6 +138,7 @@ typedef struct PnvChipClass {
void (*dt_populate)(PnvChip *chip, void *fdt);
void (*pic_print_info)(PnvChip *chip, Monitor *mon);
uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id);
+ uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr);
} PnvChipClass;
#define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 87/88] ppc/pnv: Drop PnvChipClass::type
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (85 preceding siblings ...)
2019-12-17 4:43 ` [PULL 86/88] ppc/pnv: Introduce PnvChipClass::xscom_pcba() method David Gibson
@ 2019-12-17 4:43 ` David Gibson
2019-12-17 4:43 ` [PULL 88/88] pseries: Update SLOF firmware image David Gibson
2019-12-17 14:32 ` [PULL 00/88] ppc-for-5.0 queue 20191217 Peter Maydell
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:43 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
It isn't used anymore.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157623844102.360005.12070225703151669294.stgit@bahia.lan>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 5 -----
include/hw/ppc/pnv.h | 9 ---------
2 files changed, 14 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 41e5d762df..f77e7ca84e 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1131,7 +1131,6 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PnvChipClass *k = PNV_CHIP_CLASS(klass);
- k->chip_type = PNV_CHIP_POWER8E;
k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
k->cores_mask = POWER8E_CORE_MASK;
k->core_pir = pnv_chip_core_pir_p8;
@@ -1155,7 +1154,6 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PnvChipClass *k = PNV_CHIP_CLASS(klass);
- k->chip_type = PNV_CHIP_POWER8;
k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
k->cores_mask = POWER8_CORE_MASK;
k->core_pir = pnv_chip_core_pir_p8;
@@ -1179,7 +1177,6 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PnvChipClass *k = PNV_CHIP_CLASS(klass);
- k->chip_type = PNV_CHIP_POWER8NVL;
k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
k->cores_mask = POWER8_CORE_MASK;
k->core_pir = pnv_chip_core_pir_p8;
@@ -1359,7 +1356,6 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PnvChipClass *k = PNV_CHIP_CLASS(klass);
- k->chip_type = PNV_CHIP_POWER9;
k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
k->cores_mask = POWER9_CORE_MASK;
k->core_pir = pnv_chip_core_pir_p9;
@@ -1448,7 +1444,6 @@ static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PnvChipClass *k = PNV_CHIP_CLASS(klass);
- k->chip_type = PNV_CHIP_POWER10;
k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */
k->cores_mask = POWER10_CORE_MASK;
k->core_pir = pnv_chip_core_pir_p10;
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 4972e93c26..f78fd0dd96 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -38,14 +38,6 @@
#define PNV_CHIP_GET_CLASS(obj) \
OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP)
-typedef enum PnvChipType {
- PNV_CHIP_POWER8E, /* AKA Murano (default) */
- PNV_CHIP_POWER8, /* AKA Venice */
- PNV_CHIP_POWER8NVL, /* AKA Naples */
- PNV_CHIP_POWER9, /* AKA Nimbus */
- PNV_CHIP_POWER10, /* AKA TBD */
-} PnvChipType;
-
typedef struct PnvChip {
/*< private >*/
SysBusDevice parent_obj;
@@ -123,7 +115,6 @@ typedef struct PnvChipClass {
SysBusDeviceClass parent_class;
/*< public >*/
- PnvChipType chip_type;
uint64_t chip_cfam_id;
uint64_t cores_mask;
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PULL 88/88] pseries: Update SLOF firmware image
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (86 preceding siblings ...)
2019-12-17 4:43 ` [PULL 87/88] ppc/pnv: Drop PnvChipClass::type David Gibson
@ 2019-12-17 4:43 ` David Gibson
2019-12-17 14:32 ` [PULL 00/88] ppc-for-5.0 queue 20191217 Peter Maydell
88 siblings, 0 replies; 94+ messages in thread
From: David Gibson @ 2019-12-17 4:43 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, aik, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Alexey Kardashevskiy <aik@ozlabs.ru>
This fixes PCI bridges support regression.
This enables IOMMU support in virtio drivers.
The full list of changes is:
Alexey Kardashevskiy (12):
allocator: Fix format strings for DEBUG
virtio: Make virtio_set_qaddr static
client: Load initramdisk location
sloffs: Fix -Wunused-result gcc warnings in read/write
pci-phb: Reimplement dma-map-in/out
virtio: Store queue descriptors in virtio_device
virtio-net: Init queues after features negotiation
virtio: Enable IOMMU
ibm,client-architecture-support: Fix stack handling
fdt: Fix updating the tree at H_CAS
version: update to 20191206
version: update to 20191217
Michael Roth (1):
dma: Define default dma methods for using by client/package instances
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
pc-bios/README | 2 +-
pc-bios/slof.bin | Bin 931040 -> 931032 bytes
roms/SLOF | 2 +-
3 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/pc-bios/README b/pc-bios/README
index 91218c69e9..269d99afe0 100644
--- a/pc-bios/README
+++ b/pc-bios/README
@@ -17,7 +17,7 @@
- SLOF (Slimline Open Firmware) is a free IEEE 1275 Open Firmware
implementation for certain IBM POWER hardware. The sources are at
https://github.com/aik/SLOF, and the image currently in qemu is
- built from git tag qemu-slof-20191209.
+ built from git tag qemu-slof-20191217.
- sgabios (the Serial Graphics Adapter option ROM) provides a means for
legacy x86 software to communicate with an attached serial console as
diff --git a/pc-bios/slof.bin b/pc-bios/slof.bin
index 50fc9b1e1cb837809c38fed1e9099b262e8600f1..78d8b26cbb88a1913c3b262fd5be29ff89afd554 100644
GIT binary patch
delta 217484
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diff --git a/roms/SLOF b/roms/SLOF
index 8ebf2f55e1..9546892a80 160000
--- a/roms/SLOF
+++ b/roms/SLOF
@@ -1 +1 @@
-Subproject commit 8ebf2f55e1ba1492b942ba4b682160e644fc0f98
+Subproject commit 9546892a80d5a4c73deea6719de46372f007f4a6
--
2.23.0
^ permalink raw reply related [flat|nested] 94+ messages in thread* Re: [PULL 00/88] ppc-for-5.0 queue 20191217
2019-12-17 4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
` (87 preceding siblings ...)
2019-12-17 4:43 ` [PULL 88/88] pseries: Update SLOF firmware image David Gibson
@ 2019-12-17 14:32 ` Peter Maydell
88 siblings, 0 replies; 94+ messages in thread
From: Peter Maydell @ 2019-12-17 14:32 UTC (permalink / raw)
To: David Gibson
Cc: Laurent Vivier, Alexey Kardashevskiy, QEMU Developers, Greg Kurz,
qemu-ppc, Cédric Le Goater
On Tue, 17 Dec 2019 at 04:43, David Gibson <david@gibson.dropbear.id.au> wrote:
>
> The following changes since commit cb88904a54903ef6ba21a68a61d9cd51e2166304:
>
> Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-dec-16-2019' into staging (2019-12-16 14:07:56 +0000)
>
> are available in the Git repository at:
>
> git://github.com/dgibson/qemu.git tags/ppc-for-5.0-20191217
>
> for you to fetch changes up to a363e9ed8731f45674260932a340a0d81c4b0a6f:
>
> pseries: Update SLOF firmware image (2019-12-17 11:40:23 +1100)
>
> ----------------------------------------------------------------
> ppc patch queue 2019-12-17
>
> This is the first pull request for the qemu-5.0 branch. It has a lot
> of accumulated changes, including:
>
> * SLOF update to support boot using the IOMMU (will become
> necessary for secure guests)
>
> * Clean ups to pnv handling of chip models
>
> * A number of extensions to the powernv machine model
>
> * TCG extensions to allow powernv emulated systems to run KVM guests
>
> * Outline support for POWER10 chips in powernv
>
> * Cleanups to the ibm,client-architecture-support feature negotiation path
>
> * XIVE reworks to better handle the powernv machine
>
> * Improvements to not waste interrupt queues and other semi-scarce
> resources when using XIVE under KVM
>
> ----------------------------------------------------------------
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/5.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 94+ messages in thread