From: Douglas Anderson <dianders@chromium.org>
To: Andrzej Hajda <a.hajda@samsung.com>,
Neil Armstrong <narmstrong@baylibre.com>
Cc: robdclark@chromium.org, linux-arm-msm@vger.kernel.org,
bjorn.andersson@linaro.org, seanpaul@chromium.org,
Jeffrey Hugo <jeffrey.l.hugo@gmail.com>,
Daniel Vetter <daniel@ffwll.ch>,
Douglas Anderson <dianders@chromium.org>,
Rob Clark <robdclark@gmail.com>, Jonas Karlman <jonas@kwiboo.se>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
David Airlie <airlied@linux.ie>,
Jernej Skrabec <jernej.skrabec@siol.net>,
Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Subject: [PATCH v2 4/9] drm/bridge: ti-sn65dsi86: Config number of DP lanes Mo' Betta
Date: Tue, 17 Dec 2019 16:47:36 -0800 [thread overview]
Message-ID: <20191217164702.v2.4.If3e2d0493e7b6e8b510ea90d8724ff760379b3ba@changeid> (raw)
In-Reply-To: <20191218004741.102067-1-dianders@chromium.org>
The driver used to say that the value to program into bridge register
0x93 was dp_lanes - 1. Looking at the datasheet for the bridge, this
is wrong. The data sheet says:
* 1 = 1 lane
* 2 = 2 lanes
* 3 = 4 lanes
A more proper way to express this encoding is min(dp_lanes, 3).
At the moment this change has zero effect because we've hardcoded the
number of DP lanes to 4. ...and (4 - 1) == min(4, 3). How fortunate!
...but soon we'll stop hardcoding the number of lanes.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
---
Changes in v2: None
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
index ab644baaf90c..d55d19759796 100644
--- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
+++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
@@ -523,7 +523,7 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge)
CHA_DSI_LANES_MASK, val);
/* DP lane config */
- val = DP_NUM_LANES(pdata->dp_lanes - 1);
+ val = DP_NUM_LANES(min(pdata->dp_lanes, 3));
regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
val);
--
2.24.1.735.g03f4e72817-goog
WARNING: multiple messages have this Message-ID (diff)
From: Douglas Anderson <dianders@chromium.org>
To: Andrzej Hajda <a.hajda@samsung.com>,
Neil Armstrong <narmstrong@baylibre.com>
Cc: robdclark@chromium.org, Jernej Skrabec <jernej.skrabec@siol.net>,
Jeffrey Hugo <jeffrey.l.hugo@gmail.com>,
David Airlie <airlied@linux.ie>,
linux-arm-msm@vger.kernel.org, Jonas Karlman <jonas@kwiboo.se>,
Douglas Anderson <dianders@chromium.org>,
dri-devel@lists.freedesktop.org, bjorn.andersson@linaro.org,
seanpaul@chromium.org,
Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
linux-kernel@vger.kernel.org
Subject: [PATCH v2 4/9] drm/bridge: ti-sn65dsi86: Config number of DP lanes Mo' Betta
Date: Tue, 17 Dec 2019 16:47:36 -0800 [thread overview]
Message-ID: <20191217164702.v2.4.If3e2d0493e7b6e8b510ea90d8724ff760379b3ba@changeid> (raw)
In-Reply-To: <20191218004741.102067-1-dianders@chromium.org>
The driver used to say that the value to program into bridge register
0x93 was dp_lanes - 1. Looking at the datasheet for the bridge, this
is wrong. The data sheet says:
* 1 = 1 lane
* 2 = 2 lanes
* 3 = 4 lanes
A more proper way to express this encoding is min(dp_lanes, 3).
At the moment this change has zero effect because we've hardcoded the
number of DP lanes to 4. ...and (4 - 1) == min(4, 3). How fortunate!
...but soon we'll stop hardcoding the number of lanes.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
---
Changes in v2: None
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
index ab644baaf90c..d55d19759796 100644
--- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
+++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
@@ -523,7 +523,7 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge)
CHA_DSI_LANES_MASK, val);
/* DP lane config */
- val = DP_NUM_LANES(pdata->dp_lanes - 1);
+ val = DP_NUM_LANES(min(pdata->dp_lanes, 3));
regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
val);
--
2.24.1.735.g03f4e72817-goog
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next prev parent reply other threads:[~2019-12-18 0:49 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-18 0:47 [PATCH v2 0/9] drm/bridge: ti-sn65dsi86: Improve support for AUO B116XAK01 + other DP Douglas Anderson
2019-12-18 0:47 ` Douglas Anderson
2019-12-18 0:47 ` [PATCH v2 1/9] drm/bridge: ti-sn65dsi86: Split the setting of the dp and dsi rates Douglas Anderson
2019-12-18 0:47 ` Douglas Anderson
2019-12-18 0:47 ` [PATCH v2 2/9] drm/bridge: ti-sn65dsi86: zero is never greater than an unsigned int Douglas Anderson
2019-12-18 0:47 ` Douglas Anderson
2019-12-18 0:47 ` [PATCH v2 3/9] drm/bridge: ti-sn65dsi86: Don't use MIPI variables for DP link Douglas Anderson
2019-12-18 0:47 ` Douglas Anderson
2019-12-18 0:47 ` Douglas Anderson [this message]
2019-12-18 0:47 ` [PATCH v2 4/9] drm/bridge: ti-sn65dsi86: Config number of DP lanes Mo' Betta Douglas Anderson
2019-12-18 0:47 ` [PATCH v2 5/9] drm/bridge: ti-sn65dsi86: Read num lanes from the DP sink Douglas Anderson
2019-12-18 0:47 ` Douglas Anderson
2019-12-18 0:47 ` [PATCH v2 6/9] drm/bridge: ti-sn65dsi86: Use 18-bit DP if we can Douglas Anderson
2019-12-18 0:47 ` Douglas Anderson
2019-12-18 0:47 ` [PATCH v2 7/9] drm/bridge: ti-sn65dsi86: Group DP link training bits in a function Douglas Anderson
2019-12-18 0:47 ` Douglas Anderson
2019-12-18 0:47 ` [PATCH v2 8/9] drm/bridge: ti-sn65dsi86: Train at faster rates if slower ones fail Douglas Anderson
2019-12-18 0:47 ` Douglas Anderson
2019-12-18 0:47 ` [PATCH v2 9/9] drm/bridge: ti-sn65dsi86: Avoid invalid rates Douglas Anderson
2019-12-18 0:47 ` Douglas Anderson
2019-12-18 4:01 ` Rob Clark
2019-12-18 4:01 ` Rob Clark
2019-12-18 4:03 ` Rob Clark
2019-12-18 4:03 ` Rob Clark
2019-12-18 22:41 ` Doug Anderson
2019-12-18 22:41 ` Doug Anderson
2019-12-21 13:56 ` kbuild test robot
2019-12-21 13:56 ` kbuild test robot
2019-12-21 13:56 ` kbuild test robot
2020-01-06 22:43 ` Doug Anderson
2020-01-06 22:43 ` Doug Anderson
2020-01-06 22:43 ` Doug Anderson
2020-01-07 0:55 ` [kbuild-all] " Rong Chen
2020-01-07 0:55 ` Rong Chen
2020-01-07 0:55 ` [kbuild-all] " Rong Chen
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