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From: Sukadev Bhattiprolu <sukadev@linux.ibm.com>
To: Michael Ellerman <mpe@ellerman.id.au>,
	Paul Mackerras <paulus@ozlabs.org>,
	 linuxram@us.ibm.com
Cc: linuxppc-dev@ozlabs.org, andmike@linux.ibm.com,
	kvm-ppc@vger.kernel.org, bauerman@linux.ibm.com
Subject: [PATCH 2/2] powerpc/pseries/svm: Disable PMUs in SVMs
Date: Tue, 17 Dec 2019 20:30:48 -0800	[thread overview]
Message-ID: <20191218043048.3400-2-sukadev@linux.ibm.com> (raw)
In-Reply-To: <20191218043048.3400-1-sukadev@linux.ibm.com>

For now, disable hardware PMU facilities in secure virtual
machines (SVMs) to prevent any information leak between SVMs
and the (untrusted) HV.

With this, a simple 'myperf' program that uses the perf_event_open()
fails for SVMs (with the corresponding fix to UV). In normal VMs and
on the bare-metal HV the syscall and performance counters work

Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.ibm.com>
---
 arch/powerpc/kernel/cpu_setup_power.S | 22 ++++++++++++++++++++++
 arch/powerpc/perf/core-book3s.c       |  6 ++++++
 2 files changed, 28 insertions(+)

diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
index a460298c7ddb..d5eb06e20b5a 100644
--- a/arch/powerpc/kernel/cpu_setup_power.S
+++ b/arch/powerpc/kernel/cpu_setup_power.S
@@ -206,14 +206,36 @@ __init_PMU_HV_ISA207:
 	blr
 
 __init_PMU:
+#ifdef CONFIG_PPC_SVM
+	/*
+	 * For now, SVM's are restricted from accessing PMU
+	 * features, so skip accordingly.
+	 */
+	mfmsr	r5
+	rldicl	r5, r5, 64-MSR_S_LG, 62
+	cmpwi	r5,1
+	beq	skip1
+#endif
 	li	r5,0
 	mtspr	SPRN_MMCRA,r5
 	mtspr	SPRN_MMCR0,r5
 	mtspr	SPRN_MMCR1,r5
 	mtspr	SPRN_MMCR2,r5
+skip1:
 	blr
 
 __init_PMU_ISA207:
+#ifdef CONFIG_PPC_SVM
+	/*
+	 * For now, SVM's are restricted from accessing PMU
+	 * features, so skip accordingly.
+	 */
+	mfmsr	r5
+	rldicl	r5, r5, 64-MSR_S_LG, 62
+	cmpwi	r5,1
+	beq	skip2
+#endif
 	li	r5,0
 	mtspr	SPRN_MMCRS,r5
+skip2:
 	blr
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 4e76b2251801..9e6a9f1803f6 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -2275,6 +2275,12 @@ static int power_pmu_prepare_cpu(unsigned int cpu)
 
 int register_power_pmu(struct power_pmu *pmu)
 {
+	/*
+	 * PMU events are not currently supported in SVMs
+	 */
+	if (is_secure_guest())
+		return -ENOSYS;
+
 	if (ppmu)
 		return -EBUSY;		/* something's already registered */
 
-- 
2.17.2


WARNING: multiple messages have this Message-ID (diff)
From: Sukadev Bhattiprolu <sukadev@linux.ibm.com>
To: Michael Ellerman <mpe@ellerman.id.au>,
	Paul Mackerras <paulus@ozlabs.org>,
	linuxram@us.ibm.com
Cc: linuxppc-dev@ozlabs.org, andmike@linux.ibm.com,
	kvm-ppc@vger.kernel.org, bauerman@linux.ibm.com
Subject: [PATCH 2/2] powerpc/pseries/svm: Disable PMUs in SVMs
Date: Wed, 18 Dec 2019 04:30:48 +0000	[thread overview]
Message-ID: <20191218043048.3400-2-sukadev@linux.ibm.com> (raw)
In-Reply-To: <20191218043048.3400-1-sukadev@linux.ibm.com>

For now, disable hardware PMU facilities in secure virtual
machines (SVMs) to prevent any information leak between SVMs
and the (untrusted) HV.

With this, a simple 'myperf' program that uses the perf_event_open()
fails for SVMs (with the corresponding fix to UV). In normal VMs and
on the bare-metal HV the syscall and performance counters work

Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.ibm.com>
---
 arch/powerpc/kernel/cpu_setup_power.S | 22 ++++++++++++++++++++++
 arch/powerpc/perf/core-book3s.c       |  6 ++++++
 2 files changed, 28 insertions(+)

diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
index a460298c7ddb..d5eb06e20b5a 100644
--- a/arch/powerpc/kernel/cpu_setup_power.S
+++ b/arch/powerpc/kernel/cpu_setup_power.S
@@ -206,14 +206,36 @@ __init_PMU_HV_ISA207:
 	blr
 
 __init_PMU:
+#ifdef CONFIG_PPC_SVM
+	/*
+	 * For now, SVM's are restricted from accessing PMU
+	 * features, so skip accordingly.
+	 */
+	mfmsr	r5
+	rldicl	r5, r5, 64-MSR_S_LG, 62
+	cmpwi	r5,1
+	beq	skip1
+#endif
 	li	r5,0
 	mtspr	SPRN_MMCRA,r5
 	mtspr	SPRN_MMCR0,r5
 	mtspr	SPRN_MMCR1,r5
 	mtspr	SPRN_MMCR2,r5
+skip1:
 	blr
 
 __init_PMU_ISA207:
+#ifdef CONFIG_PPC_SVM
+	/*
+	 * For now, SVM's are restricted from accessing PMU
+	 * features, so skip accordingly.
+	 */
+	mfmsr	r5
+	rldicl	r5, r5, 64-MSR_S_LG, 62
+	cmpwi	r5,1
+	beq	skip2
+#endif
 	li	r5,0
 	mtspr	SPRN_MMCRS,r5
+skip2:
 	blr
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 4e76b2251801..9e6a9f1803f6 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -2275,6 +2275,12 @@ static int power_pmu_prepare_cpu(unsigned int cpu)
 
 int register_power_pmu(struct power_pmu *pmu)
 {
+	/*
+	 * PMU events are not currently supported in SVMs
+	 */
+	if (is_secure_guest())
+		return -ENOSYS;
+
 	if (ppmu)
 		return -EBUSY;		/* something's already registered */
 
-- 
2.17.2

  reply	other threads:[~2019-12-18  4:35 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-18  4:30 [PATCH 1/2] powerpc/pseries/svm: Don't access some SPRs Sukadev Bhattiprolu
2019-12-18  4:30 ` Sukadev Bhattiprolu
2019-12-18  4:30 ` Sukadev Bhattiprolu [this message]
2019-12-18  4:30   ` [PATCH 2/2] powerpc/pseries/svm: Disable PMUs in SVMs Sukadev Bhattiprolu
2019-12-18 10:48 ` [PATCH 1/2] powerpc/pseries/svm: Don't access some SPRs Michael Ellerman
2019-12-18 10:48   ` Michael Ellerman
2019-12-18 23:57   ` Sukadev Bhattiprolu
2019-12-18 23:57     ` Sukadev Bhattiprolu
2019-12-19 10:59     ` Michael Ellerman
2019-12-19 10:59       ` Michael Ellerman

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