[linux-next:master 2825/5337] drivers/gpu/drm/i915/display/intel_dp.c:3088:9: sparse: sparse: mixing different enum types:

[linux-next:master 2825/5337] drivers/gpu/drm/i915/display/intel_dp.c:3088:9: sparse: sparse: mixing different enum types:

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 6825 bytes --]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
head:   7ddd09fc4b745fb1d8942f95389583e08412e0cd
commit: b104e8b200974f9d1a431d1ce15f0e6d547dc859 [2825/5337] drm/i915: Pass cpu transcoder to assert_pipe()
reproduce:
        # apt-get install sparse
        # sparse version: v0.6.1-129-g341daf20-dirty
        git checkout b104e8b200974f9d1a431d1ce15f0e6d547dc859
        make ARCH=x86_64 allmodconfig
        make C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__'

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>


sparse warnings: (new ones prefixed by >>)

>> drivers/gpu/drm/i915/display/intel_dp.c:3088:9: sparse: sparse: mixing different enum types:
>> drivers/gpu/drm/i915/display/intel_dp.c:3088:9: sparse:    int enum pipe
>> drivers/gpu/drm/i915/display/intel_dp.c:3088:9: sparse:    int enum transcoder
   drivers/gpu/drm/i915/display/intel_dp.c:3128:9: sparse: sparse: mixing different enum types:
   drivers/gpu/drm/i915/display/intel_dp.c:3128:9: sparse:    int enum pipe
   drivers/gpu/drm/i915/display/intel_dp.c:3128:9: sparse:    int enum transcoder
--
>> drivers/gpu/drm/i915/display/intel_tv.c:1530:9: sparse: sparse: mixing different enum types:
>> drivers/gpu/drm/i915/display/intel_tv.c:1530:9: sparse:    int enum pipe
>> drivers/gpu/drm/i915/display/intel_tv.c:1530:9: sparse:    int enum transcoder

vim +3088 drivers/gpu/drm/i915/display/intel_dp.c

64e1077a1f93d1 drivers/gpu/drm/i915/intel_dp.c         Ville Syrjälä     2015-10-29  3081  
85cb48a1651ee7 drivers/gpu/drm/i915/intel_dp.c         Maarten Lankhorst 2016-08-09  3082  static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
5f88a9c61978b2 drivers/gpu/drm/i915/intel_dp.c         Ville Syrjälä     2017-08-18  3083  				const struct intel_crtc_state *pipe_config)
d240f20f545fa4 drivers/gpu/drm/i915/intel_dp.c         Jesse Barnes      2010-08-13  3084  {
2225f3c6f1d793 drivers/gpu/drm/i915/display/intel_dp.c Maarten Lankhorst 2019-10-31  3085  	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
64e1077a1f93d1 drivers/gpu/drm/i915/intel_dp.c         Ville Syrjälä     2015-10-29  3086  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
d240f20f545fa4 drivers/gpu/drm/i915/intel_dp.c         Jesse Barnes      2010-08-13  3087  
64e1077a1f93d1 drivers/gpu/drm/i915/intel_dp.c         Ville Syrjälä     2015-10-29 @3088  	assert_pipe_disabled(dev_priv, crtc->pipe);
64e1077a1f93d1 drivers/gpu/drm/i915/intel_dp.c         Ville Syrjälä     2015-10-29  3089  	assert_dp_port_disabled(intel_dp);
64e1077a1f93d1 drivers/gpu/drm/i915/intel_dp.c         Ville Syrjälä     2015-10-29  3090  	assert_edp_pll_disabled(dev_priv);
2bd2ad643def79 drivers/gpu/drm/i915/intel_dp.c         Daniel Vetter     2012-09-06  3091  
abfce949052f32 drivers/gpu/drm/i915/intel_dp.c         Ville Syrjälä     2015-10-29  3092  	DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
85cb48a1651ee7 drivers/gpu/drm/i915/intel_dp.c         Maarten Lankhorst 2016-08-09  3093  		      pipe_config->port_clock);
abfce949052f32 drivers/gpu/drm/i915/intel_dp.c         Ville Syrjälä     2015-10-29  3094  
abfce949052f32 drivers/gpu/drm/i915/intel_dp.c         Ville Syrjälä     2015-10-29  3095  	intel_dp->DP &= ~DP_PLL_FREQ_MASK;
abfce949052f32 drivers/gpu/drm/i915/intel_dp.c         Ville Syrjälä     2015-10-29  3096  
85cb48a1651ee7 drivers/gpu/drm/i915/intel_dp.c         Maarten Lankhorst 2016-08-09  3097  	if (pipe_config->port_clock == 162000)
abfce949052f32 drivers/gpu/drm/i915/intel_dp.c         Ville Syrjälä     2015-10-29  3098  		intel_dp->DP |= DP_PLL_FREQ_162MHZ;
abfce949052f32 drivers/gpu/drm/i915/intel_dp.c         Ville Syrjälä     2015-10-29  3099  	else
abfce949052f32 drivers/gpu/drm/i915/intel_dp.c         Ville Syrjälä     2015-10-29  3100  		intel_dp->DP |= DP_PLL_FREQ_270MHZ;
abfce949052f32 drivers/gpu/drm/i915/intel_dp.c         Ville Syrjälä     2015-10-29  3101  
abfce949052f32 drivers/gpu/drm/i915/intel_dp.c         Ville Syrjälä     2015-10-29  3102  	I915_WRITE(DP_A, intel_dp->DP);
abfce949052f32 drivers/gpu/drm/i915/intel_dp.c         Ville Syrjälä     2015-10-29  3103  	POSTING_READ(DP_A);
abfce949052f32 drivers/gpu/drm/i915/intel_dp.c         Ville Syrjälä     2015-10-29  3104  	udelay(500);
abfce949052f32 drivers/gpu/drm/i915/intel_dp.c         Ville Syrjälä     2015-10-29  3105  
6b23f3e8a601d7 drivers/gpu/drm/i915/intel_dp.c         Ville Syrjälä     2016-04-01  3106  	/*
6b23f3e8a601d7 drivers/gpu/drm/i915/intel_dp.c         Ville Syrjälä     2016-04-01  3107  	 * [DevILK] Work around required when enabling DP PLL
6b23f3e8a601d7 drivers/gpu/drm/i915/intel_dp.c         Ville Syrjälä     2016-04-01  3108  	 * while a pipe is enabled going to FDI:
6b23f3e8a601d7 drivers/gpu/drm/i915/intel_dp.c         Ville Syrjälä     2016-04-01  3109  	 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
6b23f3e8a601d7 drivers/gpu/drm/i915/intel_dp.c         Ville Syrjälä     2016-04-01  3110  	 * 2. Program DP PLL enable
6b23f3e8a601d7 drivers/gpu/drm/i915/intel_dp.c         Ville Syrjälä     2016-04-01  3111  	 */
cf819eff907ab4 drivers/gpu/drm/i915/intel_dp.c         Lucas De Marchi   2018-12-12  3112  	if (IS_GEN(dev_priv, 5))
0f0f74bc83aa29 drivers/gpu/drm/i915/intel_dp.c         Ville Syrjälä     2016-10-31  3113  		intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
6b23f3e8a601d7 drivers/gpu/drm/i915/intel_dp.c         Ville Syrjälä     2016-04-01  3114  
0767935e868215 drivers/gpu/drm/i915/intel_dp.c         Daniel Vetter     2012-09-06  3115  	intel_dp->DP |= DP_PLL_ENABLE;
6fec766283333f drivers/gpu/drm/i915/intel_dp.c         Ville Syrjälä     2015-11-10  3116  
0767935e868215 drivers/gpu/drm/i915/intel_dp.c         Daniel Vetter     2012-09-06  3117  	I915_WRITE(DP_A, intel_dp->DP);
298b0b392c7501 drivers/gpu/drm/i915/intel_dp.c         Jesse Barnes      2010-10-07  3118  	POSTING_READ(DP_A);
298b0b392c7501 drivers/gpu/drm/i915/intel_dp.c         Jesse Barnes      2010-10-07  3119  	udelay(200);
d240f20f545fa4 drivers/gpu/drm/i915/intel_dp.c         Jesse Barnes      2010-08-13  3120  }
d240f20f545fa4 drivers/gpu/drm/i915/intel_dp.c         Jesse Barnes      2010-08-13  3121  

:::::: The code at line 3088 was first introduced by commit
:::::: 64e1077a1f93d1f90e096e75232f7284a2b62ca6 drm/i915: Clean up eDP PLL state asserts

:::::: TO: Ville Syrjälä <ville.syrjala@linux.intel.com>
:::::: CC: Ville Syrjälä <ville.syrjala@linux.intel.com>

---
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