From: Vinod Koul <vkoul@kernel.org> To: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: robh+dt@kernel.org, nm@ti.com, ssantosh@kernel.org, dan.j.williams@intel.com, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, grygorii.strashko@ti.com, lokeshvutla@ti.com, t-kristo@ti.com, tony@atomide.com, j-keerthy@ti.com, vigneshr@ti.com Subject: Re: [PATCH v7 08/12] dt-bindings: dma: ti: Add document for K3 UDMA Date: Mon, 23 Dec 2019 12:23:40 +0530 [thread overview] Message-ID: <20191223065340.GU2536@vkoul-mobl> (raw) In-Reply-To: <20191209094332.4047-9-peter.ujfalusi@ti.com> On 09-12-19, 11:43, Peter Ujfalusi wrote: > New binding document for > Texas Instruments K3 NAVSS Unified DMA – Peripheral Root Complex (UDMA-P). > > UDMA-P is introduced as part of the K3 architecture and can be found in > AM654 and j721e. > > Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> > Reviewed-by: Rob Herring <robh@kernel.org> > --- > .../devicetree/bindings/dma/ti/k3-udma.yaml | 185 ++++++++++++++++++ > 1 file changed, 185 insertions(+) > create mode 100644 Documentation/devicetree/bindings/dma/ti/k3-udma.yaml > > diff --git a/Documentation/devicetree/bindings/dma/ti/k3-udma.yaml b/Documentation/devicetree/bindings/dma/ti/k3-udma.yaml > new file mode 100644 > index 000000000000..77aef4a4abce > --- /dev/null > +++ b/Documentation/devicetree/bindings/dma/ti/k3-udma.yaml > @@ -0,0 +1,185 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/dma/ti/k3-udma.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Texas Instruments K3 NAVSS Unified DMA Device Tree Bindings > + > +maintainers: > + - Peter Ujfalusi <peter.ujfalusi@ti.com> > + > +description: | > + The UDMA-P is intended to perform similar (but significantly upgraded) > + functions as the packet-oriented DMA used on previous SoC devices. The UDMA-P > + module supports the transmission and reception of various packet types. > + The UDMA-P is architected to facilitate the segmentation and reassembly of How about: The UDMA-P architecture facilitates the segmentation... > + SoC DMA data structure compliant packets to/from smaller data blocks that are > + natively compatible with the specific requirements of each connected > + peripheral. > + Multiple Tx and Rx channels are provided within the DMA which allow multiple > + segmentation or reassembly operations to be ongoing. The DMA controller > + maintains state information for each of the channels which allows packet > + segmentation and reassembly operations to be time division multiplexed between > + channels in order to share the underlying DMA hardware. An external DMA > + scheduler is used to control the ordering and rate at which this multiplexing > + occurs for Transmit operations. The ordering and rate of Receive operations > + is indirectly controlled by the order in which blocks are pushed into the DMA > + on the Rx PSI-L interface. > + > + The UDMA-P also supports acting as both a UTC and UDMA-C for its internal > + channels. Channels in the UDMA-P can be configured to be either Packet-Based > + or Third-Party channels on a channel by channel basis. > + > + All transfers within NAVSS is done between PSI-L source and destination > + threads. > + The peripherals serviced by UDMA can be PSI-L native (sa2ul, cpsw, etc) or > + legacy, non PSI-L native peripherals. In the later case a special, small PDMA > + is tasked to act as a bridge between the PSI-L fabric and the legacy > + peripheral. > + > + PDMAs can be configured via UDMAP peer registers to match with the > + configuration of the legacy peripheral. > + > +allOf: > + - $ref: "../dma-controller.yaml#" > + > +properties: > + "#dma-cells": > + const: 1 > + description: | > + The cell is the PSI-L thread ID of the remote (to UDMAP) end. > + Valid ranges for thread ID depends on the data movement direction: > + for source thread IDs (rx): 0 - 0x7fff > + for destination thread IDs (tx): 0x8000 - 0xffff > + > + PLease refer to the device documentation for the PSI-L thread map and also s/PLease/Please -- ~Vinod
WARNING: multiple messages have this Message-ID (diff)
From: Vinod Koul <vkoul@kernel.org> To: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: nm@ti.com, devicetree@vger.kernel.org, grygorii.strashko@ti.com, vigneshr@ti.com, lokeshvutla@ti.com, j-keerthy@ti.com, linux-kernel@vger.kernel.org, t-kristo@ti.com, tony@atomide.com, robh+dt@kernel.org, ssantosh@kernel.org, dmaengine@vger.kernel.org, dan.j.williams@intel.com, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v7 08/12] dt-bindings: dma: ti: Add document for K3 UDMA Date: Mon, 23 Dec 2019 12:23:40 +0530 [thread overview] Message-ID: <20191223065340.GU2536@vkoul-mobl> (raw) In-Reply-To: <20191209094332.4047-9-peter.ujfalusi@ti.com> On 09-12-19, 11:43, Peter Ujfalusi wrote: > New binding document for > Texas Instruments K3 NAVSS Unified DMA – Peripheral Root Complex (UDMA-P). > > UDMA-P is introduced as part of the K3 architecture and can be found in > AM654 and j721e. > > Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> > Reviewed-by: Rob Herring <robh@kernel.org> > --- > .../devicetree/bindings/dma/ti/k3-udma.yaml | 185 ++++++++++++++++++ > 1 file changed, 185 insertions(+) > create mode 100644 Documentation/devicetree/bindings/dma/ti/k3-udma.yaml > > diff --git a/Documentation/devicetree/bindings/dma/ti/k3-udma.yaml b/Documentation/devicetree/bindings/dma/ti/k3-udma.yaml > new file mode 100644 > index 000000000000..77aef4a4abce > --- /dev/null > +++ b/Documentation/devicetree/bindings/dma/ti/k3-udma.yaml > @@ -0,0 +1,185 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/dma/ti/k3-udma.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Texas Instruments K3 NAVSS Unified DMA Device Tree Bindings > + > +maintainers: > + - Peter Ujfalusi <peter.ujfalusi@ti.com> > + > +description: | > + The UDMA-P is intended to perform similar (but significantly upgraded) > + functions as the packet-oriented DMA used on previous SoC devices. The UDMA-P > + module supports the transmission and reception of various packet types. > + The UDMA-P is architected to facilitate the segmentation and reassembly of How about: The UDMA-P architecture facilitates the segmentation... > + SoC DMA data structure compliant packets to/from smaller data blocks that are > + natively compatible with the specific requirements of each connected > + peripheral. > + Multiple Tx and Rx channels are provided within the DMA which allow multiple > + segmentation or reassembly operations to be ongoing. The DMA controller > + maintains state information for each of the channels which allows packet > + segmentation and reassembly operations to be time division multiplexed between > + channels in order to share the underlying DMA hardware. An external DMA > + scheduler is used to control the ordering and rate at which this multiplexing > + occurs for Transmit operations. The ordering and rate of Receive operations > + is indirectly controlled by the order in which blocks are pushed into the DMA > + on the Rx PSI-L interface. > + > + The UDMA-P also supports acting as both a UTC and UDMA-C for its internal > + channels. Channels in the UDMA-P can be configured to be either Packet-Based > + or Third-Party channels on a channel by channel basis. > + > + All transfers within NAVSS is done between PSI-L source and destination > + threads. > + The peripherals serviced by UDMA can be PSI-L native (sa2ul, cpsw, etc) or > + legacy, non PSI-L native peripherals. In the later case a special, small PDMA > + is tasked to act as a bridge between the PSI-L fabric and the legacy > + peripheral. > + > + PDMAs can be configured via UDMAP peer registers to match with the > + configuration of the legacy peripheral. > + > +allOf: > + - $ref: "../dma-controller.yaml#" > + > +properties: > + "#dma-cells": > + const: 1 > + description: | > + The cell is the PSI-L thread ID of the remote (to UDMAP) end. > + Valid ranges for thread ID depends on the data movement direction: > + for source thread IDs (rx): 0 - 0x7fff > + for destination thread IDs (tx): 0x8000 - 0xffff > + > + PLease refer to the device documentation for the PSI-L thread map and also s/PLease/Please -- ~Vinod _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-12-23 6:53 UTC|newest] Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-12-09 9:43 [PATCH v7 00/12] dmaengine/soc: Add Texas Instruments UDMA support Peter Ujfalusi 2019-12-09 9:43 ` Peter Ujfalusi 2019-12-09 9:43 ` [PATCH v7 01/12] bindings: soc: ti: add documentation for k3 ringacc Peter Ujfalusi 2019-12-09 9:43 ` Peter Ujfalusi 2019-12-09 9:43 ` [PATCH v7 02/12] soc: ti: k3: add navss ringacc driver Peter Ujfalusi 2019-12-09 9:43 ` Peter Ujfalusi 2019-12-09 9:43 ` [PATCH v7 03/12] dmaengine: doc: Add sections for per descriptor metadata support Peter Ujfalusi 2019-12-09 9:43 ` Peter Ujfalusi 2019-12-20 8:28 ` Vinod Koul 2019-12-20 8:28 ` Vinod Koul 2019-12-20 9:52 ` Peter Ujfalusi 2019-12-20 9:52 ` Peter Ujfalusi 2019-12-20 10:14 ` Vinod Koul 2019-12-20 10:14 ` Vinod Koul 2019-12-09 9:43 ` [PATCH v7 04/12] dmaengine: Add metadata_ops for dma_async_tx_descriptor Peter Ujfalusi 2019-12-09 9:43 ` Peter Ujfalusi 2019-12-20 8:32 ` Vinod Koul 2019-12-20 8:32 ` Vinod Koul 2019-12-20 8:48 ` Peter Ujfalusi 2019-12-20 8:48 ` Peter Ujfalusi 2019-12-09 9:43 ` [PATCH v7 05/12] dmaengine: Add support for reporting DMA cached data amount Peter Ujfalusi 2019-12-09 9:43 ` Peter Ujfalusi 2019-12-20 8:37 ` Vinod Koul 2019-12-20 8:37 ` Vinod Koul 2019-12-20 8:49 ` Peter Ujfalusi 2019-12-20 8:49 ` Peter Ujfalusi 2019-12-20 9:57 ` Vinod Koul 2019-12-20 9:57 ` Vinod Koul 2019-12-20 10:13 ` Peter Ujfalusi 2019-12-20 10:13 ` Peter Ujfalusi 2019-12-09 9:43 ` [PATCH v7 06/12] dmaengine: ti: Add cppi5 header for K3 NAVSS/UDMA Peter Ujfalusi 2019-12-09 9:43 ` Peter Ujfalusi 2019-12-20 9:54 ` Vinod Koul 2019-12-20 9:54 ` Vinod Koul 2019-12-20 10:42 ` Peter Ujfalusi 2019-12-20 10:42 ` Peter Ujfalusi 2019-12-23 7:11 ` Peter Ujfalusi 2019-12-23 7:11 ` Peter Ujfalusi 2019-12-09 9:43 ` [PATCH v7 07/12] dmaengine: ti: k3 PSI-L remote endpoint configuration Peter Ujfalusi 2019-12-09 9:43 ` Peter Ujfalusi 2019-12-09 9:43 ` [PATCH v7 08/12] dt-bindings: dma: ti: Add document for K3 UDMA Peter Ujfalusi 2019-12-09 9:43 ` Peter Ujfalusi 2019-12-23 6:53 ` Vinod Koul [this message] 2019-12-23 6:53 ` Vinod Koul 2019-12-09 9:43 ` [PATCH v7 09/12] dmaengine: ti: New driver " Peter Ujfalusi 2019-12-09 9:43 ` Peter Ujfalusi 2019-12-23 7:34 ` Vinod Koul 2019-12-23 7:34 ` Vinod Koul 2019-12-23 8:59 ` Peter Ujfalusi 2019-12-23 8:59 ` Peter Ujfalusi 2019-12-23 11:26 ` Vinod Koul 2019-12-23 11:26 ` Vinod Koul 2019-12-09 9:43 ` [PATCH v7 10/12] dmaengine: ti: k3-udma: Add glue layer for non DMAengine users Peter Ujfalusi 2019-12-09 9:43 ` Peter Ujfalusi 2019-12-09 9:43 ` [PATCH v7 11/12] firmware: ti_sci: rm: Add support for tx_tdtype parameter for tx channel Peter Ujfalusi 2019-12-09 9:43 ` Peter Ujfalusi 2019-12-11 10:24 ` Tero Kristo 2019-12-11 10:24 ` Tero Kristo 2019-12-09 9:43 ` [PATCH v7 12/12] dmaengine: ti: k3-udma: Wait for peer teardown completion if supported Peter Ujfalusi 2019-12-09 9:43 ` Peter Ujfalusi 2019-12-11 10:43 ` [PATCH v7 00/12] dmaengine/soc: Add Texas Instruments UDMA support Keerthy 2019-12-11 10:43 ` Keerthy 2019-12-12 8:46 ` Peter Ujfalusi 2019-12-12 8:46 ` Peter Ujfalusi 2019-12-12 10:55 ` Tero Kristo 2019-12-12 10:55 ` Tero Kristo 2019-12-12 10:57 ` Tero Kristo 2019-12-12 10:57 ` Tero Kristo 2019-12-16 10:05 ` Peter Ujfalusi 2019-12-16 10:05 ` Peter Ujfalusi 2019-12-12 18:01 ` Grygorii Strashko 2019-12-12 18:01 ` Grygorii Strashko
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20191223065340.GU2536@vkoul-mobl \ --to=vkoul@kernel.org \ --cc=dan.j.williams@intel.com \ --cc=devicetree@vger.kernel.org \ --cc=dmaengine@vger.kernel.org \ --cc=grygorii.strashko@ti.com \ --cc=j-keerthy@ti.com \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=lokeshvutla@ti.com \ --cc=nm@ti.com \ --cc=peter.ujfalusi@ti.com \ --cc=robh+dt@kernel.org \ --cc=ssantosh@kernel.org \ --cc=t-kristo@ti.com \ --cc=tony@atomide.com \ --cc=vigneshr@ti.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.