* [PATCH v3 0/5] rk3399: Add redundant boot support
@ 2019-12-29 19:07 ` Jagan Teki
0 siblings, 0 replies; 21+ messages in thread
From: Jagan Teki @ 2019-12-29 19:07 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich
Cc: u-boot, linux-amarula, Akash Gajjar, linux-rockchip
Boot redundancy is one of the key criteria for switch
recovery or golden partition based on the bootcount
value, which indeed very much needed in production
systems on the fields.
This is v3 patchset support redundant boot on Rockchip
rk3399.
This series skip wdt changes as Marek patches support
the same.
Changes for v3:
- rework of cru.h to include rk3288
- rebase on master
Changes for v2:
- Handle TPL build for watchdog, if TPL won't enable
- Fix comments for dw_wdt driver-model comments from Andy
- Add Kconfig items for WDT_TPL
- Support WDT on TPL as well
- Use SYS_SOC for cpu-info
Any inputs?
Jagan.
Jagan Teki (5):
rockchip: Add cpu-info
rockchip: rk3399: Enable DISPLAY_CPUINFO
arm: rockchip: Add common cru.h
rockchip: Add common reset cause
rockchip: rk3399: Add bootcount support
arch/arm/include/asm/arch-rockchip/clock.h | 4 +-
arch/arm/include/asm/arch-rockchip/cru.h | 28 ++++++++
.../include/asm/arch-rockchip/cru_rk3288.h | 20 ++----
.../include/asm/arch-rockchip/cru_rk3399.h | 10 +--
arch/arm/mach-rockchip/Kconfig | 2 +
arch/arm/mach-rockchip/Makefile | 1 +
arch/arm/mach-rockchip/cpu-info.c | 65 +++++++++++++++++++
arch/arm/mach-rockchip/rk3288/clk_rk3288.c | 2 +-
arch/arm/mach-rockchip/rk3288/rk3288.c | 41 +-----------
arch/arm/mach-rockchip/rk3399/Kconfig | 10 +++
arch/arm/mach-rockchip/rk3399/clk_rk3399.c | 2 +-
arch/arm/mach-rockchip/rk3399/rk3399.c | 2 +-
configs/evb-rk3288_defconfig | 1 -
configs/evb-rk3399_defconfig | 1 -
configs/ficus-rk3399_defconfig | 1 -
configs/firefly-rk3288_defconfig | 1 -
configs/firefly-rk3399_defconfig | 1 -
configs/khadas-edge-captain-rk3399_defconfig | 1 -
configs/khadas-edge-rk3399_defconfig | 1 -
configs/khadas-edge-v-rk3399_defconfig | 1 -
configs/leez-rk3399_defconfig | 1 -
configs/miqi-rk3288_defconfig | 1 -
configs/nanopc-t4-rk3399_defconfig | 1 -
configs/nanopi-m4-rk3399_defconfig | 1 -
configs/nanopi-neo4-rk3399_defconfig | 1 -
configs/orangepi-rk3399_defconfig | 1 -
configs/phycore-rk3288_defconfig | 1 -
configs/popmetal-rk3288_defconfig | 1 -
configs/puma-rk3399_defconfig | 1 -
configs/roc-pc-rk3399_defconfig | 1 -
configs/rock-pi-4-rk3399_defconfig | 1 -
configs/rock960-rk3399_defconfig | 1 -
configs/rockpro64-rk3399_defconfig | 1 -
configs/tinker-rk3288_defconfig | 1 -
configs/tinker-s-rk3288_defconfig | 1 -
configs/vyasa-rk3288_defconfig | 1 -
drivers/clk/rockchip/clk_rk3288.c | 42 ++++++------
drivers/clk/rockchip/clk_rk3399.c | 36 +++++-----
drivers/ram/rockchip/sdram_rk3288.c | 10 +--
drivers/ram/rockchip/sdram_rk3399.c | 10 +--
drivers/video/rockchip/rk3288_mipi.c | 2 +-
drivers/video/rockchip/rk3399_mipi.c | 2 +-
drivers/video/rockchip/rk_mipi.c | 2 +-
include/configs/rk3399_common.h | 5 +-
44 files changed, 177 insertions(+), 143 deletions(-)
create mode 100644 arch/arm/include/asm/arch-rockchip/cru.h
create mode 100644 arch/arm/mach-rockchip/cpu-info.c
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v3 0/5] rk3399: Add redundant boot support
@ 2019-12-29 19:07 ` Jagan Teki
0 siblings, 0 replies; 21+ messages in thread
From: Jagan Teki @ 2019-12-29 19:07 UTC (permalink / raw)
To: u-boot
Boot redundancy is one of the key criteria for switch
recovery or golden partition based on the bootcount
value, which indeed very much needed in production
systems on the fields.
This is v3 patchset support redundant boot on Rockchip
rk3399.
This series skip wdt changes as Marek patches support
the same.
Changes for v3:
- rework of cru.h to include rk3288
- rebase on master
Changes for v2:
- Handle TPL build for watchdog, if TPL won't enable
- Fix comments for dw_wdt driver-model comments from Andy
- Add Kconfig items for WDT_TPL
- Support WDT on TPL as well
- Use SYS_SOC for cpu-info
Any inputs?
Jagan.
Jagan Teki (5):
rockchip: Add cpu-info
rockchip: rk3399: Enable DISPLAY_CPUINFO
arm: rockchip: Add common cru.h
rockchip: Add common reset cause
rockchip: rk3399: Add bootcount support
arch/arm/include/asm/arch-rockchip/clock.h | 4 +-
arch/arm/include/asm/arch-rockchip/cru.h | 28 ++++++++
.../include/asm/arch-rockchip/cru_rk3288.h | 20 ++----
.../include/asm/arch-rockchip/cru_rk3399.h | 10 +--
arch/arm/mach-rockchip/Kconfig | 2 +
arch/arm/mach-rockchip/Makefile | 1 +
arch/arm/mach-rockchip/cpu-info.c | 65 +++++++++++++++++++
arch/arm/mach-rockchip/rk3288/clk_rk3288.c | 2 +-
arch/arm/mach-rockchip/rk3288/rk3288.c | 41 +-----------
arch/arm/mach-rockchip/rk3399/Kconfig | 10 +++
arch/arm/mach-rockchip/rk3399/clk_rk3399.c | 2 +-
arch/arm/mach-rockchip/rk3399/rk3399.c | 2 +-
configs/evb-rk3288_defconfig | 1 -
configs/evb-rk3399_defconfig | 1 -
configs/ficus-rk3399_defconfig | 1 -
configs/firefly-rk3288_defconfig | 1 -
configs/firefly-rk3399_defconfig | 1 -
configs/khadas-edge-captain-rk3399_defconfig | 1 -
configs/khadas-edge-rk3399_defconfig | 1 -
configs/khadas-edge-v-rk3399_defconfig | 1 -
configs/leez-rk3399_defconfig | 1 -
configs/miqi-rk3288_defconfig | 1 -
configs/nanopc-t4-rk3399_defconfig | 1 -
configs/nanopi-m4-rk3399_defconfig | 1 -
configs/nanopi-neo4-rk3399_defconfig | 1 -
configs/orangepi-rk3399_defconfig | 1 -
configs/phycore-rk3288_defconfig | 1 -
configs/popmetal-rk3288_defconfig | 1 -
configs/puma-rk3399_defconfig | 1 -
configs/roc-pc-rk3399_defconfig | 1 -
configs/rock-pi-4-rk3399_defconfig | 1 -
configs/rock960-rk3399_defconfig | 1 -
configs/rockpro64-rk3399_defconfig | 1 -
configs/tinker-rk3288_defconfig | 1 -
configs/tinker-s-rk3288_defconfig | 1 -
configs/vyasa-rk3288_defconfig | 1 -
drivers/clk/rockchip/clk_rk3288.c | 42 ++++++------
drivers/clk/rockchip/clk_rk3399.c | 36 +++++-----
drivers/ram/rockchip/sdram_rk3288.c | 10 +--
drivers/ram/rockchip/sdram_rk3399.c | 10 +--
drivers/video/rockchip/rk3288_mipi.c | 2 +-
drivers/video/rockchip/rk3399_mipi.c | 2 +-
drivers/video/rockchip/rk_mipi.c | 2 +-
include/configs/rk3399_common.h | 5 +-
44 files changed, 177 insertions(+), 143 deletions(-)
create mode 100644 arch/arm/include/asm/arch-rockchip/cru.h
create mode 100644 arch/arm/mach-rockchip/cpu-info.c
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v3 1/5] rockchip: Add cpu-info
2019-12-29 19:07 ` Jagan Teki
@ 2019-12-29 19:07 ` Jagan Teki
-1 siblings, 0 replies; 21+ messages in thread
From: Jagan Teki @ 2019-12-29 19:07 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich
Cc: Jagan Teki, u-boot-0aAXYlwwYIKGBzrmiIFOJg,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Akash Gajjar, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Add cpu information for rockchip soc.
This would help to print the SoC family number, with
associated temparature, clock and reason for reset etc.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Reviewed-by: Kever Yang <kever.yang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
arch/arm/mach-rockchip/Makefile | 1 +
arch/arm/mach-rockchip/cpu-info.c | 16 ++++++++++++++++
2 files changed, 17 insertions(+)
create mode 100644 arch/arm/mach-rockchip/cpu-info.c
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index a728acda24..5b38526fe0 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -22,6 +22,7 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
# we can have the preprocessor correctly recognise both 0x0 and 0
# meaning "turn it off".
obj-y += boot_mode.o
+obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o
obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o
obj-$(CONFIG_MISC_INIT_R) += misc.o
endif
diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c
new file mode 100644
index 0000000000..9bccbd4f68
--- /dev/null
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * (C) Copyright 2019 Amarula Solutions(India)
+ * Author: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
+ */
+
+#include <common.h>
+
+int print_cpuinfo(void)
+{
+ printf("SoC: Rockchip %s\n", CONFIG_SYS_SOC);
+
+ /* TODO print operating temparature and clock */
+
+ return 0;
+}
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 1/5] rockchip: Add cpu-info
@ 2019-12-29 19:07 ` Jagan Teki
0 siblings, 0 replies; 21+ messages in thread
From: Jagan Teki @ 2019-12-29 19:07 UTC (permalink / raw)
To: u-boot
Add cpu information for rockchip soc.
This would help to print the SoC family number, with
associated temparature, clock and reason for reset etc.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
arch/arm/mach-rockchip/Makefile | 1 +
arch/arm/mach-rockchip/cpu-info.c | 16 ++++++++++++++++
2 files changed, 17 insertions(+)
create mode 100644 arch/arm/mach-rockchip/cpu-info.c
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index a728acda24..5b38526fe0 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -22,6 +22,7 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
# we can have the preprocessor correctly recognise both 0x0 and 0
# meaning "turn it off".
obj-y += boot_mode.o
+obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o
obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o
obj-$(CONFIG_MISC_INIT_R) += misc.o
endif
diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c
new file mode 100644
index 0000000000..9bccbd4f68
--- /dev/null
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * (C) Copyright 2019 Amarula Solutions(India)
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+
+int print_cpuinfo(void)
+{
+ printf("SoC: Rockchip %s\n", CONFIG_SYS_SOC);
+
+ /* TODO print operating temparature and clock */
+
+ return 0;
+}
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 2/5] rockchip: rk3399: Enable DISPLAY_CPUINFO
2019-12-29 19:07 ` Jagan Teki
@ 2019-12-29 19:07 ` Jagan Teki
-1 siblings, 0 replies; 21+ messages in thread
From: Jagan Teki @ 2019-12-29 19:07 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich
Cc: Jagan Teki, u-boot-0aAXYlwwYIKGBzrmiIFOJg,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Akash Gajjar, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
RK3288, RK3399 are now support cpu-info, so enable
DISPLAY_CPUINFO by default.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
configs/evb-rk3288_defconfig | 1 -
configs/evb-rk3399_defconfig | 1 -
configs/ficus-rk3399_defconfig | 1 -
configs/firefly-rk3288_defconfig | 1 -
configs/firefly-rk3399_defconfig | 1 -
configs/khadas-edge-captain-rk3399_defconfig | 1 -
configs/khadas-edge-rk3399_defconfig | 1 -
configs/khadas-edge-v-rk3399_defconfig | 1 -
configs/leez-rk3399_defconfig | 1 -
configs/miqi-rk3288_defconfig | 1 -
configs/nanopc-t4-rk3399_defconfig | 1 -
configs/nanopi-m4-rk3399_defconfig | 1 -
configs/nanopi-neo4-rk3399_defconfig | 1 -
configs/orangepi-rk3399_defconfig | 1 -
configs/phycore-rk3288_defconfig | 1 -
configs/popmetal-rk3288_defconfig | 1 -
configs/puma-rk3399_defconfig | 1 -
configs/roc-pc-rk3399_defconfig | 1 -
configs/rock-pi-4-rk3399_defconfig | 1 -
configs/rock960-rk3399_defconfig | 1 -
configs/rockpro64-rk3399_defconfig | 1 -
configs/tinker-rk3288_defconfig | 1 -
configs/tinker-s-rk3288_defconfig | 1 -
configs/vyasa-rk3288_defconfig | 1 -
24 files changed, 24 deletions(-)
diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig
index 1fa4054f5d..59c909e10d 100644
--- a/configs/evb-rk3288_defconfig
+++ b/configs/evb-rk3288_defconfig
@@ -14,7 +14,6 @@ CONFIG_DEBUG_UART=y
CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_DEFAULT_FDT_FILE="rk3288-evb-rk808.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index 8b8cdc5109..896a6050eb 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig
index 6bb030acc1..5b49fe0b7b 100644
--- a/configs/ficus-rk3399_defconfig
+++ b/configs/ficus-rk3399_defconfig
@@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_SPL_TEXT_BASE=0xff8c2000
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index 0c0a51c54f..41a6fc3edd 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -14,7 +14,6 @@ CONFIG_DEBUG_UART=y
CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_DEFAULT_FDT_FILE="rk3288-firefly.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig
index b84d7b9ff0..5d197f5f8a 100644
--- a/configs/firefly-rk3399_defconfig
+++ b/configs/firefly-rk3399_defconfig
@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig
index c408a1a59b..379e21e28d 100644
--- a/configs/khadas-edge-captain-rk3399_defconfig
+++ b/configs/khadas-edge-captain-rk3399_defconfig
@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-captain.dtbi"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig
index 796f94f8d7..9086018cd0 100644
--- a/configs/khadas-edge-rk3399_defconfig
+++ b/configs/khadas-edge-rk3399_defconfig
@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig
index e70e1ec2e6..261d75526b 100644
--- a/configs/khadas-edge-v-rk3399_defconfig
+++ b/configs/khadas-edge-v-rk3399_defconfig
@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-v.dtbi"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig
index 3758d79a1e..1d621fc9ce 100644
--- a/configs/leez-rk3399_defconfig
+++ b/configs/leez-rk3399_defconfig
@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-leez-p710.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig
index cec8e42c5e..25a808eb89 100644
--- a/configs/miqi-rk3288_defconfig
+++ b/configs/miqi-rk3288_defconfig
@@ -15,7 +15,6 @@ CONFIG_SPL_TEXT_BASE=0xff704000
CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_DEFAULT_FDT_FILE="rk3288-miqi.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig
index 504346eb99..bd6d60ff6c 100644
--- a/configs/nanopc-t4-rk3399_defconfig
+++ b/configs/nanopc-t4-rk3399_defconfig
@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig
index 24c8aa401b..74ede13c23 100644
--- a/configs/nanopi-m4-rk3399_defconfig
+++ b/configs/nanopi-m4-rk3399_defconfig
@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig
index 986739f16e..a44124aac0 100644
--- a/configs/nanopi-neo4-rk3399_defconfig
+++ b/configs/nanopi-neo4-rk3399_defconfig
@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig
index bed634b699..4c464de8a6 100644
--- a/configs/orangepi-rk3399_defconfig
+++ b/configs/orangepi-rk3399_defconfig
@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig
index 4c48d42299..2f10c7a3b3 100644
--- a/configs/phycore-rk3288_defconfig
+++ b/configs/phycore-rk3288_defconfig
@@ -16,7 +16,6 @@ CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
CONFIG_DEFAULT_FDT_FILE="rk3288-phycore-rdk.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig
index f732f6b209..512efee1a9 100644
--- a/configs/popmetal-rk3288_defconfig
+++ b/configs/popmetal-rk3288_defconfig
@@ -16,7 +16,6 @@ CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
CONFIG_DEFAULT_FDT_FILE="rk3288-popmetal.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig
index 55255bf6af..30c7ab2751 100644
--- a/configs/puma-rk3399_defconfig
+++ b/configs/puma-rk3399_defconfig
@@ -16,7 +16,6 @@ CONFIG_SPL_TEXT_BASE=0xff8c2000
CONFIG_SPL_FIT_GENERATOR="board/theobroma-systems/puma_rk3399/fit_spl_atf.sh"
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb"
CONFIG_MISC_INIT_R=y
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig
index 305baa712c..bf83b25dbc 100644
--- a/configs/roc-pc-rk3399_defconfig
+++ b/configs/roc-pc-rk3399_defconfig
@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig
index 2c01bf1f87..4429f58fde 100644
--- a/configs/rock-pi-4-rk3399_defconfig
+++ b/configs/rock-pi-4-rk3399_defconfig
@@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4.dtb"
CONFIG_MISC_INIT_R=y
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig
index ec32e6cf05..7b6dc3f83c 100644
--- a/configs/rock960-rk3399_defconfig
+++ b/configs/rock960-rk3399_defconfig
@@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig
index 49e27c91cb..955b717131 100644
--- a/configs/rockpro64-rk3399_defconfig
+++ b/configs/rockpro64-rk3399_defconfig
@@ -10,7 +10,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb"
CONFIG_MISC_INIT_R=y
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
index 83c3450839..894e7d1e12 100644
--- a/configs/tinker-rk3288_defconfig
+++ b/configs/tinker-rk3288_defconfig
@@ -16,7 +16,6 @@ CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
CONFIG_DEFAULT_FDT_FILE="rk3288-tinker.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig
index 4925b14821..6215aa2d61 100644
--- a/configs/tinker-s-rk3288_defconfig
+++ b/configs/tinker-s-rk3288_defconfig
@@ -15,7 +15,6 @@ CONFIG_DEBUG_UART=y
CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_DEFAULT_FDT_FILE="rk3288-tinker-s.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x300000
diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig
index 9497f0dd0f..6cb7f13e49 100644
--- a/configs/vyasa-rk3288_defconfig
+++ b/configs/vyasa-rk3288_defconfig
@@ -14,7 +14,6 @@ CONFIG_DEBUG_UART=y
CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_DEFAULT_FDT_FILE="rk3288-vyasa.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 2/5] rockchip: rk3399: Enable DISPLAY_CPUINFO
@ 2019-12-29 19:07 ` Jagan Teki
0 siblings, 0 replies; 21+ messages in thread
From: Jagan Teki @ 2019-12-29 19:07 UTC (permalink / raw)
To: u-boot
RK3288, RK3399 are now support cpu-info, so enable
DISPLAY_CPUINFO by default.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
configs/evb-rk3288_defconfig | 1 -
configs/evb-rk3399_defconfig | 1 -
configs/ficus-rk3399_defconfig | 1 -
configs/firefly-rk3288_defconfig | 1 -
configs/firefly-rk3399_defconfig | 1 -
configs/khadas-edge-captain-rk3399_defconfig | 1 -
configs/khadas-edge-rk3399_defconfig | 1 -
configs/khadas-edge-v-rk3399_defconfig | 1 -
configs/leez-rk3399_defconfig | 1 -
configs/miqi-rk3288_defconfig | 1 -
configs/nanopc-t4-rk3399_defconfig | 1 -
configs/nanopi-m4-rk3399_defconfig | 1 -
configs/nanopi-neo4-rk3399_defconfig | 1 -
configs/orangepi-rk3399_defconfig | 1 -
configs/phycore-rk3288_defconfig | 1 -
configs/popmetal-rk3288_defconfig | 1 -
configs/puma-rk3399_defconfig | 1 -
configs/roc-pc-rk3399_defconfig | 1 -
configs/rock-pi-4-rk3399_defconfig | 1 -
configs/rock960-rk3399_defconfig | 1 -
configs/rockpro64-rk3399_defconfig | 1 -
configs/tinker-rk3288_defconfig | 1 -
configs/tinker-s-rk3288_defconfig | 1 -
configs/vyasa-rk3288_defconfig | 1 -
24 files changed, 24 deletions(-)
diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig
index 1fa4054f5d..59c909e10d 100644
--- a/configs/evb-rk3288_defconfig
+++ b/configs/evb-rk3288_defconfig
@@ -14,7 +14,6 @@ CONFIG_DEBUG_UART=y
CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_DEFAULT_FDT_FILE="rk3288-evb-rk808.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index 8b8cdc5109..896a6050eb 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig
index 6bb030acc1..5b49fe0b7b 100644
--- a/configs/ficus-rk3399_defconfig
+++ b/configs/ficus-rk3399_defconfig
@@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_SPL_TEXT_BASE=0xff8c2000
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index 0c0a51c54f..41a6fc3edd 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -14,7 +14,6 @@ CONFIG_DEBUG_UART=y
CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_DEFAULT_FDT_FILE="rk3288-firefly.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig
index b84d7b9ff0..5d197f5f8a 100644
--- a/configs/firefly-rk3399_defconfig
+++ b/configs/firefly-rk3399_defconfig
@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig
index c408a1a59b..379e21e28d 100644
--- a/configs/khadas-edge-captain-rk3399_defconfig
+++ b/configs/khadas-edge-captain-rk3399_defconfig
@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-captain.dtbi"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig
index 796f94f8d7..9086018cd0 100644
--- a/configs/khadas-edge-rk3399_defconfig
+++ b/configs/khadas-edge-rk3399_defconfig
@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig
index e70e1ec2e6..261d75526b 100644
--- a/configs/khadas-edge-v-rk3399_defconfig
+++ b/configs/khadas-edge-v-rk3399_defconfig
@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-v.dtbi"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig
index 3758d79a1e..1d621fc9ce 100644
--- a/configs/leez-rk3399_defconfig
+++ b/configs/leez-rk3399_defconfig
@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-leez-p710.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig
index cec8e42c5e..25a808eb89 100644
--- a/configs/miqi-rk3288_defconfig
+++ b/configs/miqi-rk3288_defconfig
@@ -15,7 +15,6 @@ CONFIG_SPL_TEXT_BASE=0xff704000
CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_DEFAULT_FDT_FILE="rk3288-miqi.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig
index 504346eb99..bd6d60ff6c 100644
--- a/configs/nanopc-t4-rk3399_defconfig
+++ b/configs/nanopc-t4-rk3399_defconfig
@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig
index 24c8aa401b..74ede13c23 100644
--- a/configs/nanopi-m4-rk3399_defconfig
+++ b/configs/nanopi-m4-rk3399_defconfig
@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig
index 986739f16e..a44124aac0 100644
--- a/configs/nanopi-neo4-rk3399_defconfig
+++ b/configs/nanopi-neo4-rk3399_defconfig
@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig
index bed634b699..4c464de8a6 100644
--- a/configs/orangepi-rk3399_defconfig
+++ b/configs/orangepi-rk3399_defconfig
@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig
index 4c48d42299..2f10c7a3b3 100644
--- a/configs/phycore-rk3288_defconfig
+++ b/configs/phycore-rk3288_defconfig
@@ -16,7 +16,6 @@ CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
CONFIG_DEFAULT_FDT_FILE="rk3288-phycore-rdk.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig
index f732f6b209..512efee1a9 100644
--- a/configs/popmetal-rk3288_defconfig
+++ b/configs/popmetal-rk3288_defconfig
@@ -16,7 +16,6 @@ CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
CONFIG_DEFAULT_FDT_FILE="rk3288-popmetal.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig
index 55255bf6af..30c7ab2751 100644
--- a/configs/puma-rk3399_defconfig
+++ b/configs/puma-rk3399_defconfig
@@ -16,7 +16,6 @@ CONFIG_SPL_TEXT_BASE=0xff8c2000
CONFIG_SPL_FIT_GENERATOR="board/theobroma-systems/puma_rk3399/fit_spl_atf.sh"
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb"
CONFIG_MISC_INIT_R=y
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig
index 305baa712c..bf83b25dbc 100644
--- a/configs/roc-pc-rk3399_defconfig
+++ b/configs/roc-pc-rk3399_defconfig
@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig
index 2c01bf1f87..4429f58fde 100644
--- a/configs/rock-pi-4-rk3399_defconfig
+++ b/configs/rock-pi-4-rk3399_defconfig
@@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4.dtb"
CONFIG_MISC_INIT_R=y
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig
index ec32e6cf05..7b6dc3f83c 100644
--- a/configs/rock960-rk3399_defconfig
+++ b/configs/rock960-rk3399_defconfig
@@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig
index 49e27c91cb..955b717131 100644
--- a/configs/rockpro64-rk3399_defconfig
+++ b/configs/rockpro64-rk3399_defconfig
@@ -10,7 +10,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb"
CONFIG_MISC_INIT_R=y
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
index 83c3450839..894e7d1e12 100644
--- a/configs/tinker-rk3288_defconfig
+++ b/configs/tinker-rk3288_defconfig
@@ -16,7 +16,6 @@ CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
CONFIG_DEFAULT_FDT_FILE="rk3288-tinker.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig
index 4925b14821..6215aa2d61 100644
--- a/configs/tinker-s-rk3288_defconfig
+++ b/configs/tinker-s-rk3288_defconfig
@@ -15,7 +15,6 @@ CONFIG_DEBUG_UART=y
CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_DEFAULT_FDT_FILE="rk3288-tinker-s.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x300000
diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig
index 9497f0dd0f..6cb7f13e49 100644
--- a/configs/vyasa-rk3288_defconfig
+++ b/configs/vyasa-rk3288_defconfig
@@ -14,7 +14,6 @@ CONFIG_DEBUG_UART=y
CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_DEFAULT_FDT_FILE="rk3288-vyasa.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 3/5] arm: rockchip: Add common cru.h
2019-12-29 19:07 ` Jagan Teki
@ 2019-12-29 19:07 ` Jagan Teki
-1 siblings, 0 replies; 21+ messages in thread
From: Jagan Teki @ 2019-12-29 19:07 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich
Cc: Jagan Teki, u-boot-0aAXYlwwYIKGBzrmiIFOJg,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Akash Gajjar, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Few of the rockchip family SoC atleast rk3288,
rk3399 are sharing some cru register bits so
adding common code between these SoC families
would require to include both cru include files
that indeed resulting function declarations error.
So, create a common cru include as cru.h then
include the rk3399 arch cru include file and move
the common cru register bit definitions into it.
The rest of rockchip cru files will add it in future.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
arch/arm/include/asm/arch-rockchip/clock.h | 4 +-
arch/arm/include/asm/arch-rockchip/cru.h | 16 +++++++
.../include/asm/arch-rockchip/cru_rk3288.h | 6 +--
.../include/asm/arch-rockchip/cru_rk3399.h | 10 ++---
arch/arm/mach-rockchip/rk3288/clk_rk3288.c | 2 +-
arch/arm/mach-rockchip/rk3288/rk3288.c | 4 +-
arch/arm/mach-rockchip/rk3399/clk_rk3399.c | 2 +-
arch/arm/mach-rockchip/rk3399/rk3399.c | 2 +-
drivers/clk/rockchip/clk_rk3288.c | 42 +++++++++----------
drivers/clk/rockchip/clk_rk3399.c | 36 ++++++++--------
drivers/ram/rockchip/sdram_rk3288.c | 10 ++---
drivers/ram/rockchip/sdram_rk3399.c | 10 ++---
drivers/video/rockchip/rk3288_mipi.c | 2 +-
drivers/video/rockchip/rk3399_mipi.c | 2 +-
drivers/video/rockchip/rk_mipi.c | 2 +-
15 files changed, 83 insertions(+), 67 deletions(-)
create mode 100644 arch/arm/include/asm/arch-rockchip/cru.h
diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
index 8f7fc86a9e..22de0aef8d 100644
--- a/arch/arm/include/asm/arch-rockchip/clock.h
+++ b/arch/arm/include/asm/arch-rockchip/clock.h
@@ -153,10 +153,10 @@ void *rockchip_get_cru(void);
*/
void *rockchip_get_pmucru(void);
-struct rk3288_cru;
+struct rockchip_cru;
struct rk3288_grf;
-void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf);
+void rk3288_clk_configure_cpu(struct rockchip_cru *cru, struct rk3288_grf *grf);
int rockchip_get_clk(struct udevice **devp);
diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h
new file mode 100644
index 0000000000..5ed3fbfd07
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * (C) Copyright 2019 Amarula Solutions.
+ * Author: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
+ */
+
+#ifndef _ROCKCHIP_CLOCK_H
+#define _ROCKCHIP_CLOCK_H
+
+#if defined(CONFIG_ROCKCHIP_RK3288)
+# include <asm/arch-rockchip/cru_rk3288.h>
+#elif defined(CONFIG_ROCKCHIP_RK3399)
+# include <asm/arch-rockchip/cru_rk3399.h>
+#endif
+
+#endif /* _ROCKCHIP_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
index e891f20b37..7aa6efe46c 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
@@ -27,11 +27,11 @@
/* Private data for the clock driver - used by rockchip_get_cru() */
struct rk3288_clk_priv {
struct rk3288_grf *grf;
- struct rk3288_cru *cru;
+ struct rockchip_cru *cru;
ulong rate;
};
-struct rk3288_cru {
+struct rockchip_cru {
struct rk3288_pll {
u32 con0;
u32 con1;
@@ -58,7 +58,7 @@ struct rk3288_cru {
u32 cru_sdio1_con[2];
u32 cru_emmc_con[2];
};
-check_member(rk3288_cru, cru_emmc_con[1], 0x021c);
+check_member(rockchip_cru, cru_emmc_con[1], 0x021c);
/* CRU_CLKSEL11_CON */
enum {
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
index 15eeb9c440..33ce190434 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
@@ -10,7 +10,7 @@
/* Private data for the clock driver - used by rockchip_get_cru() */
struct rk3399_clk_priv {
- struct rk3399_cru *cru;
+ struct rockchip_cru *cru;
};
struct rk3399_pmuclk_priv {
@@ -33,7 +33,7 @@ struct rk3399_pmucru {
};
check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134);
-struct rk3399_cru {
+struct rockchip_cru {
u32 apll_l_con[6];
u32 reserved[2];
u32 apll_b_con[6];
@@ -65,7 +65,7 @@ struct rk3399_cru {
u32 sdio0_con[2];
u32 sdio1_con[2];
};
-check_member(rk3399_cru, sdio1_con[1], 0x594);
+check_member(rockchip_cru, sdio1_con[1], 0x594);
#define MHz 1000000
#define KHz 1000
#define OSC_HZ (24*MHz)
@@ -107,9 +107,9 @@ enum apll_b_frequencies {
APLL_B_600_MHZ,
};
-void rk3399_configure_cpu_l(struct rk3399_cru *cru,
+void rk3399_configure_cpu_l(struct rockchip_cru *cru,
enum apll_l_frequencies apll_l_freq);
-void rk3399_configure_cpu_b(struct rk3399_cru *cru,
+void rk3399_configure_cpu_b(struct rockchip_cru *cru,
enum apll_b_frequencies apll_b_freq);
#endif /* __ASM_ARCH_CRU_RK3399_H_ */
diff --git a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c
index e64ee86f08..1730f12443 100644
--- a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c
@@ -8,7 +8,7 @@
#include <dm.h>
#include <syscon.h>
#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/cru_rk3288.h>
+#include <asm/arch-rockchip/cru.h>
int rockchip_get_clk(struct udevice **devp)
{
diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c
index 9572f7ea9c..47ee5d440b 100644
--- a/arch/arm/mach-rockchip/rk3288/rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/rk3288.c
@@ -11,7 +11,7 @@
#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/cru_rk3288.h>
+#include <asm/arch-rockchip/cru.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/grf_rk3288.h>
#include <asm/arch-rockchip/pmu_rk3288.h>
@@ -104,7 +104,7 @@ void board_debug_uart_init(void)
static void rk3288_detect_reset_reason(void)
{
- struct rk3288_cru *cru = rockchip_get_cru();
+ struct rockchip_cru *cru = rockchip_get_cru();
const char *reason;
if (IS_ERR(cru))
diff --git a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c
index f0411c0a21..a80a46f1db 100644
--- a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c
@@ -8,7 +8,7 @@
#include <dm.h>
#include <syscon.h>
#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/cru_rk3399.h>
+#include <asm/arch-rockchip/cru.h>
static int rockchip_get_cruclk(struct udevice **devp)
{
diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c
index 863024d071..dafa142824 100644
--- a/arch/arm/mach-rockchip/rk3399/rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
@@ -240,7 +240,7 @@ static void rk3399_force_power_on_reset(void)
void spl_board_init(void)
{
#if defined(SPL_GPIO_SUPPORT)
- struct rk3399_cru *cru = rockchip_get_cru();
+ struct rockchip_cru *cru = rockchip_get_cru();
/*
* The RK3399 resets only 'almost all logic' (see also in the TRM
diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index 85d1b67e43..cc1c1e81e9 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -14,7 +14,7 @@
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/cru_rk3288.h>
+#include <asm/arch-rockchip/cru.h>
#include <asm/arch-rockchip/grf_rk3288.h>
#include <asm/arch-rockchip/hardware.h>
#include <dt-bindings/clock/rk3288-cru.h>
@@ -141,7 +141,7 @@ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
-static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
+static int rkclk_set_pll(struct rockchip_cru *cru, enum rk_clk_id clk_id,
const struct pll_div *div)
{
int pll_id = rk_pll_id(clk_id);
@@ -172,7 +172,7 @@ static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
return 0;
}
-static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,
+static int rkclk_configure_ddr(struct rockchip_cru *cru, struct rk3288_grf *grf,
unsigned int hz)
{
static const struct pll_div dpll_cfg[] = {
@@ -295,7 +295,7 @@ static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
return 0;
}
-static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq)
+static int rockchip_mac_set_clk(struct rockchip_cru *cru, uint freq)
{
ulong ret;
@@ -333,7 +333,7 @@ static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq)
return ret;
}
-static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
+static int rockchip_vop_set_clk(struct rockchip_cru *cru, struct rk3288_grf *grf,
int periph, unsigned int rate_hz)
{
struct pll_div npll_config = {0};
@@ -384,7 +384,7 @@ static u32 rockchip_clk_gcd(u32 a, u32 b)
return a;
}
-static ulong rockchip_i2s_get_clk(struct rk3288_cru *cru, uint gclk_rate)
+static ulong rockchip_i2s_get_clk(struct rockchip_cru *cru, uint gclk_rate)
{
unsigned long long rate;
uint val;
@@ -400,7 +400,7 @@ static ulong rockchip_i2s_get_clk(struct rk3288_cru *cru, uint gclk_rate)
return (ulong)rate;
}
-static ulong rockchip_i2s_set_clk(struct rk3288_cru *cru, uint gclk_rate,
+static ulong rockchip_i2s_set_clk(struct rockchip_cru *cru, uint gclk_rate,
uint freq)
{
int n, d;
@@ -418,7 +418,7 @@ static ulong rockchip_i2s_set_clk(struct rk3288_cru *cru, uint gclk_rate,
}
#endif /* CONFIG_SPL_BUILD */
-static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
+static void rkclk_init(struct rockchip_cru *cru, struct rk3288_grf *grf)
{
u32 aclk_div;
u32 hclk_div;
@@ -492,7 +492,7 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
}
-void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
+void rk3288_clk_configure_cpu(struct rockchip_cru *cru, struct rk3288_grf *grf)
{
/* pll enter slow-mode */
rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
@@ -534,7 +534,7 @@ void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
}
/* Get pll rate by id */
-static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
+static uint32_t rkclk_pll_get_rate(struct rockchip_cru *cru,
enum rk_clk_id clk_id)
{
uint32_t nr, no, nf;
@@ -567,7 +567,7 @@ static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
}
}
-static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
+static ulong rockchip_mmc_get_clk(struct rockchip_cru *cru, uint gclk_rate,
int periph)
{
uint src_rate;
@@ -601,7 +601,7 @@ static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
return DIV_TO_RATE(src_rate, div);
}
-static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
+static ulong rockchip_mmc_set_clk(struct rockchip_cru *cru, uint gclk_rate,
int periph, uint freq)
{
int src_clk_div;
@@ -651,7 +651,7 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
return rockchip_mmc_get_clk(cru, gclk_rate, periph);
}
-static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
+static ulong rockchip_spi_get_clk(struct rockchip_cru *cru, uint gclk_rate,
int periph)
{
uint div, mux;
@@ -681,7 +681,7 @@ static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
return DIV_TO_RATE(gclk_rate, div);
}
-static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
+static ulong rockchip_spi_set_clk(struct rockchip_cru *cru, uint gclk_rate,
int periph, uint freq)
{
int src_clk_div;
@@ -715,7 +715,7 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
return rockchip_spi_get_clk(cru, gclk_rate, periph);
}
-static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru)
+static ulong rockchip_saradc_get_clk(struct rockchip_cru *cru)
{
u32 div, val;
@@ -726,7 +726,7 @@ static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru)
return DIV_TO_RATE(OSC_HZ, div);
}
-static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz)
+static ulong rockchip_saradc_set_clk(struct rockchip_cru *cru, uint hz)
{
int src_clk_div;
@@ -785,7 +785,7 @@ static ulong rk3288_clk_get_rate(struct clk *clk)
static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
{
struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
- struct rk3288_cru *cru = priv->cru;
+ struct rockchip_cru *cru = priv->cru;
ulong new_rate, gclk_rate;
gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
@@ -892,7 +892,7 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
static int __maybe_unused rk3288_gmac_set_parent(struct clk *clk, struct clk *parent)
{
struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
- struct rk3288_cru *cru = priv->cru;
+ struct rockchip_cru *cru = priv->cru;
const char *clock_output_name;
int ret;
@@ -1008,15 +1008,15 @@ static int rk3288_clk_bind(struct udevice *dev)
debug("Warning: No sysreset driver: ret=%d\n", ret);
} else {
priv = malloc(sizeof(struct sysreset_reg));
- priv->glb_srst_fst_value = offsetof(struct rk3288_cru,
+ priv->glb_srst_fst_value = offsetof(struct rockchip_cru,
cru_glb_srst_fst_value);
- priv->glb_srst_snd_value = offsetof(struct rk3288_cru,
+ priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
cru_glb_srst_snd_value);
sys_child->priv = priv;
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
- ret = offsetof(struct rk3288_cru, cru_softrst_con[0]);
+ ret = offsetof(struct rockchip_cru, cru_softrst_con[0]);
ret = rockchip_reset_bind(dev, ret, 12);
if (ret)
debug("Warning: software reset driver bind faile\n");
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 9020a9f202..37fc142a7a 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -14,7 +14,7 @@
#include <bitfield.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/cru_rk3399.h>
+#include <asm/arch-rockchip/cru.h>
#include <asm/arch-rockchip/hardware.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3399-cru.h>
@@ -418,7 +418,7 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div)
return 0;
}
-void rk3399_configure_cpu_l(struct rk3399_cru *cru,
+void rk3399_configure_cpu_l(struct rockchip_cru *cru,
enum apll_l_frequencies apll_l_freq)
{
u32 aclkm_div;
@@ -453,7 +453,7 @@ void rk3399_configure_cpu_l(struct rk3399_cru *cru,
atclk_div << ATCLK_CORE_L_DIV_SHIFT);
}
-void rk3399_configure_cpu_b(struct rk3399_cru *cru,
+void rk3399_configure_cpu_b(struct rockchip_cru *cru,
enum apll_b_frequencies apll_b_freq)
{
u32 aclkm_div;
@@ -505,7 +505,7 @@ void rk3399_configure_cpu_b(struct rk3399_cru *cru,
#define I2C_PMUCLK_REG_VALUE(bus, clk_div) \
((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT)
-static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id)
+static ulong rk3399_i2c_get_clk(struct rockchip_cru *cru, ulong clk_id)
{
u32 div, con;
@@ -542,7 +542,7 @@ static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id)
return DIV_TO_RATE(GPLL_HZ, div);
}
-static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
+static ulong rk3399_i2c_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
{
int src_clk_div;
@@ -619,7 +619,7 @@ static const struct spi_clkreg spi_clkregs[] = {
.sel_shift = CLK_SPI5_PLL_SEL_SHIFT, },
};
-static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id)
+static ulong rk3399_spi_get_clk(struct rockchip_cru *cru, ulong clk_id)
{
const struct spi_clkreg *spiclk = NULL;
u32 div, val;
@@ -641,7 +641,7 @@ static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id)
return DIV_TO_RATE(GPLL_HZ, div);
}
-static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
+static ulong rk3399_spi_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
{
const struct spi_clkreg *spiclk = NULL;
int src_clk_div;
@@ -668,7 +668,7 @@ static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
return rk3399_spi_get_clk(cru, clk_id);
}
-static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
+static ulong rk3399_vop_set_clk(struct rockchip_cru *cru, ulong clk_id, u32 hz)
{
struct pll_div vpll_config = {0};
int aclk_vop = 198 * MHz;
@@ -712,7 +712,7 @@ static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
return hz;
}
-static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id)
+static ulong rk3399_mmc_get_clk(struct rockchip_cru *cru, uint clk_id)
{
u32 div, con;
@@ -739,7 +739,7 @@ static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id)
return DIV_TO_RATE(GPLL_HZ, div);
}
-static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
+static ulong rk3399_mmc_set_clk(struct rockchip_cru *cru,
ulong clk_id, ulong set_rate)
{
int src_clk_div;
@@ -792,7 +792,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
return rk3399_mmc_get_clk(cru, clk_id);
}
-static ulong rk3399_gmac_set_clk(struct rk3399_cru *cru, ulong rate)
+static ulong rk3399_gmac_set_clk(struct rockchip_cru *cru, ulong rate)
{
ulong ret;
@@ -817,7 +817,7 @@ static ulong rk3399_gmac_set_clk(struct rk3399_cru *cru, ulong rate)
}
#define PMUSGRF_DDR_RGN_CON16 0xff330040
-static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
+static ulong rk3399_ddr_set_clk(struct rockchip_cru *cru,
ulong set_rate)
{
struct pll_div dpll_cfg;
@@ -863,7 +863,7 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
return set_rate;
}
-static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru)
+static ulong rk3399_saradc_get_clk(struct rockchip_cru *cru)
{
u32 div, val;
@@ -874,7 +874,7 @@ static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru)
return DIV_TO_RATE(OSC_HZ, div);
}
-static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz)
+static ulong rk3399_saradc_set_clk(struct rockchip_cru *cru, uint hz)
{
int src_clk_div;
@@ -1071,7 +1071,7 @@ static struct clk_ops rk3399_clk_ops = {
};
#ifdef CONFIG_SPL_BUILD
-static void rkclk_init(struct rk3399_cru *cru)
+static void rkclk_init(struct rockchip_cru *cru)
{
u32 aclk_div;
u32 hclk_div;
@@ -1188,15 +1188,15 @@ static int rk3399_clk_bind(struct udevice *dev)
debug("Warning: No sysreset driver: ret=%d\n", ret);
} else {
priv = malloc(sizeof(struct sysreset_reg));
- priv->glb_srst_fst_value = offsetof(struct rk3399_cru,
+ priv->glb_srst_fst_value = offsetof(struct rockchip_cru,
glb_srst_fst_value);
- priv->glb_srst_snd_value = offsetof(struct rk3399_cru,
+ priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
glb_srst_snd_value);
sys_child->priv = priv;
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
- ret = offsetof(struct rk3399_cru, softrst_con[0]);
+ ret = offsetof(struct rockchip_cru, softrst_con[0]);
ret = rockchip_reset_bind(dev, ret, 21);
if (ret)
debug("Warning: software reset driver bind faile\n");
diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c
index 690751d074..fd5b204e1f 100644
--- a/drivers/ram/rockchip/sdram_rk3288.c
+++ b/drivers/ram/rockchip/sdram_rk3288.c
@@ -16,7 +16,7 @@
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/cru_rk3288.h>
+#include <asm/arch-rockchip/cru.h>
#include <asm/arch-rockchip/ddr_rk3288.h>
#include <asm/arch-rockchip/grf_rk3288.h>
#include <asm/arch-rockchip/pmu_rk3288.h>
@@ -36,7 +36,7 @@ struct dram_info {
struct chan_info chan[2];
struct ram_info info;
struct clk ddr_clk;
- struct rk3288_cru *cru;
+ struct rockchip_cru *cru;
struct rk3288_grf *grf;
struct rk3288_sgrf *sgrf;
struct rk3288_pmu *pmu;
@@ -92,7 +92,7 @@ static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
}
}
-static void ddr_reset(struct rk3288_cru *cru, u32 ch, u32 ctl, u32 phy)
+static void ddr_reset(struct rockchip_cru *cru, u32 ch, u32 ctl, u32 phy)
{
u32 phy_ctl_srstn_shift = 4 + 5 * ch;
u32 ctl_psrstn_shift = 3 + 5 * ch;
@@ -109,7 +109,7 @@ static void ddr_reset(struct rk3288_cru *cru, u32 ch, u32 ctl, u32 phy)
phy << phy_srstn_shift);
}
-static void ddr_phy_ctl_reset(struct rk3288_cru *cru, u32 ch, u32 n)
+static void ddr_phy_ctl_reset(struct rockchip_cru *cru, u32 ch, u32 n)
{
u32 phy_ctl_srstn_shift = 4 + 5 * ch;
@@ -117,7 +117,7 @@ static void ddr_phy_ctl_reset(struct rk3288_cru *cru, u32 ch, u32 n)
1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift);
}
-static void phy_pctrl_reset(struct rk3288_cru *cru,
+static void phy_pctrl_reset(struct rockchip_cru *cru,
struct rk3288_ddr_publ *publ,
int channel)
{
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 7b2bba03fe..08bf0393a7 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -14,7 +14,7 @@
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/cru_rk3399.h>
+#include <asm/arch-rockchip/cru.h>
#include <asm/arch-rockchip/grf_rk3399.h>
#include <asm/arch-rockchip/pmu_rk3399.h>
#include <asm/arch-rockchip/hardware.h>
@@ -66,7 +66,7 @@ struct dram_info {
u32 pwrup_srefresh_exit[2];
struct chan_info chan[2];
struct clk ddr_clk;
- struct rk3399_cru *cru;
+ struct rockchip_cru *cru;
struct rk3399_grf_regs *grf;
struct rk3399_pmu_regs *pmu;
struct rk3399_pmucru *pmucru;
@@ -228,7 +228,7 @@ static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc1_con0;
}
-static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl,
+static void rkclk_ddr_reset(struct rockchip_cru *cru, u32 channel, u32 ctl,
u32 phy)
{
channel &= 0x1;
@@ -239,7 +239,7 @@ static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl,
&cru->softrst_con[4]);
}
-static void phy_pctrl_reset(struct rk3399_cru *cru, u32 channel)
+static void phy_pctrl_reset(struct rockchip_cru *cru, u32 channel)
{
rkclk_ddr_reset(cru, channel, 1, 1);
udelay(10);
@@ -2945,7 +2945,7 @@ static int sdram_init(struct dram_info *dram,
for (channel = 0; channel < 2; channel++) {
const struct chan_info *chan =
&dram->chan[channel];
- struct rk3399_cru *cru = dram->cru;
+ struct rockchip_cru *cru = dram->cru;
struct rk3399_ddr_publ_regs *publ = chan->publ;
phy_pctrl_reset(cru, channel);
diff --git a/drivers/video/rockchip/rk3288_mipi.c b/drivers/video/rockchip/rk3288_mipi.c
index 7c4a4cc53b..65891ce45c 100644
--- a/drivers/video/rockchip/rk3288_mipi.c
+++ b/drivers/video/rockchip/rk3288_mipi.c
@@ -18,7 +18,7 @@
#include <dm/uclass-internal.h>
#include <linux/kernel.h>
#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/cru_rk3288.h>
+#include <asm/arch-rockchip/cru.h>
#include <asm/arch-rockchip/grf_rk3288.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/rockchip_mipi_dsi.h>
diff --git a/drivers/video/rockchip/rk3399_mipi.c b/drivers/video/rockchip/rk3399_mipi.c
index a93b73400b..a5b7ba69a8 100644
--- a/drivers/video/rockchip/rk3399_mipi.c
+++ b/drivers/video/rockchip/rk3399_mipi.c
@@ -18,7 +18,7 @@
#include <dm/uclass-internal.h>
#include <linux/kernel.h>
#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/cru_rk3399.h>
+#include <asm/arch-rockchip/cru.h>
#include <asm/arch-rockchip/grf_rk3399.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/rockchip_mipi_dsi.h>
diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c
index bcd039b7bc..f9280e8607 100644
--- a/drivers/video/rockchip/rk_mipi.c
+++ b/drivers/video/rockchip/rk_mipi.c
@@ -18,7 +18,7 @@
#include <dm/uclass-internal.h>
#include <linux/kernel.h>
#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/cru_rk3399.h>
+#include <asm/arch-rockchip/cru.h>
#include <asm/arch-rockchip/grf_rk3399.h>
#include <asm/arch-rockchip/rockchip_mipi_dsi.h>
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 3/5] arm: rockchip: Add common cru.h
@ 2019-12-29 19:07 ` Jagan Teki
0 siblings, 0 replies; 21+ messages in thread
From: Jagan Teki @ 2019-12-29 19:07 UTC (permalink / raw)
To: u-boot
Few of the rockchip family SoC atleast rk3288,
rk3399 are sharing some cru register bits so
adding common code between these SoC families
would require to include both cru include files
that indeed resulting function declarations error.
So, create a common cru include as cru.h then
include the rk3399 arch cru include file and move
the common cru register bit definitions into it.
The rest of rockchip cru files will add it in future.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/include/asm/arch-rockchip/clock.h | 4 +-
arch/arm/include/asm/arch-rockchip/cru.h | 16 +++++++
.../include/asm/arch-rockchip/cru_rk3288.h | 6 +--
.../include/asm/arch-rockchip/cru_rk3399.h | 10 ++---
arch/arm/mach-rockchip/rk3288/clk_rk3288.c | 2 +-
arch/arm/mach-rockchip/rk3288/rk3288.c | 4 +-
arch/arm/mach-rockchip/rk3399/clk_rk3399.c | 2 +-
arch/arm/mach-rockchip/rk3399/rk3399.c | 2 +-
drivers/clk/rockchip/clk_rk3288.c | 42 +++++++++----------
drivers/clk/rockchip/clk_rk3399.c | 36 ++++++++--------
drivers/ram/rockchip/sdram_rk3288.c | 10 ++---
drivers/ram/rockchip/sdram_rk3399.c | 10 ++---
drivers/video/rockchip/rk3288_mipi.c | 2 +-
drivers/video/rockchip/rk3399_mipi.c | 2 +-
drivers/video/rockchip/rk_mipi.c | 2 +-
15 files changed, 83 insertions(+), 67 deletions(-)
create mode 100644 arch/arm/include/asm/arch-rockchip/cru.h
diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
index 8f7fc86a9e..22de0aef8d 100644
--- a/arch/arm/include/asm/arch-rockchip/clock.h
+++ b/arch/arm/include/asm/arch-rockchip/clock.h
@@ -153,10 +153,10 @@ void *rockchip_get_cru(void);
*/
void *rockchip_get_pmucru(void);
-struct rk3288_cru;
+struct rockchip_cru;
struct rk3288_grf;
-void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf);
+void rk3288_clk_configure_cpu(struct rockchip_cru *cru, struct rk3288_grf *grf);
int rockchip_get_clk(struct udevice **devp);
diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h
new file mode 100644
index 0000000000..5ed3fbfd07
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * (C) Copyright 2019 Amarula Solutions.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#ifndef _ROCKCHIP_CLOCK_H
+#define _ROCKCHIP_CLOCK_H
+
+#if defined(CONFIG_ROCKCHIP_RK3288)
+# include <asm/arch-rockchip/cru_rk3288.h>
+#elif defined(CONFIG_ROCKCHIP_RK3399)
+# include <asm/arch-rockchip/cru_rk3399.h>
+#endif
+
+#endif /* _ROCKCHIP_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
index e891f20b37..7aa6efe46c 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
@@ -27,11 +27,11 @@
/* Private data for the clock driver - used by rockchip_get_cru() */
struct rk3288_clk_priv {
struct rk3288_grf *grf;
- struct rk3288_cru *cru;
+ struct rockchip_cru *cru;
ulong rate;
};
-struct rk3288_cru {
+struct rockchip_cru {
struct rk3288_pll {
u32 con0;
u32 con1;
@@ -58,7 +58,7 @@ struct rk3288_cru {
u32 cru_sdio1_con[2];
u32 cru_emmc_con[2];
};
-check_member(rk3288_cru, cru_emmc_con[1], 0x021c);
+check_member(rockchip_cru, cru_emmc_con[1], 0x021c);
/* CRU_CLKSEL11_CON */
enum {
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
index 15eeb9c440..33ce190434 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
@@ -10,7 +10,7 @@
/* Private data for the clock driver - used by rockchip_get_cru() */
struct rk3399_clk_priv {
- struct rk3399_cru *cru;
+ struct rockchip_cru *cru;
};
struct rk3399_pmuclk_priv {
@@ -33,7 +33,7 @@ struct rk3399_pmucru {
};
check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134);
-struct rk3399_cru {
+struct rockchip_cru {
u32 apll_l_con[6];
u32 reserved[2];
u32 apll_b_con[6];
@@ -65,7 +65,7 @@ struct rk3399_cru {
u32 sdio0_con[2];
u32 sdio1_con[2];
};
-check_member(rk3399_cru, sdio1_con[1], 0x594);
+check_member(rockchip_cru, sdio1_con[1], 0x594);
#define MHz 1000000
#define KHz 1000
#define OSC_HZ (24*MHz)
@@ -107,9 +107,9 @@ enum apll_b_frequencies {
APLL_B_600_MHZ,
};
-void rk3399_configure_cpu_l(struct rk3399_cru *cru,
+void rk3399_configure_cpu_l(struct rockchip_cru *cru,
enum apll_l_frequencies apll_l_freq);
-void rk3399_configure_cpu_b(struct rk3399_cru *cru,
+void rk3399_configure_cpu_b(struct rockchip_cru *cru,
enum apll_b_frequencies apll_b_freq);
#endif /* __ASM_ARCH_CRU_RK3399_H_ */
diff --git a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c
index e64ee86f08..1730f12443 100644
--- a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c
@@ -8,7 +8,7 @@
#include <dm.h>
#include <syscon.h>
#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/cru_rk3288.h>
+#include <asm/arch-rockchip/cru.h>
int rockchip_get_clk(struct udevice **devp)
{
diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c
index 9572f7ea9c..47ee5d440b 100644
--- a/arch/arm/mach-rockchip/rk3288/rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/rk3288.c
@@ -11,7 +11,7 @@
#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/cru_rk3288.h>
+#include <asm/arch-rockchip/cru.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/grf_rk3288.h>
#include <asm/arch-rockchip/pmu_rk3288.h>
@@ -104,7 +104,7 @@ void board_debug_uart_init(void)
static void rk3288_detect_reset_reason(void)
{
- struct rk3288_cru *cru = rockchip_get_cru();
+ struct rockchip_cru *cru = rockchip_get_cru();
const char *reason;
if (IS_ERR(cru))
diff --git a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c
index f0411c0a21..a80a46f1db 100644
--- a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c
@@ -8,7 +8,7 @@
#include <dm.h>
#include <syscon.h>
#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/cru_rk3399.h>
+#include <asm/arch-rockchip/cru.h>
static int rockchip_get_cruclk(struct udevice **devp)
{
diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c
index 863024d071..dafa142824 100644
--- a/arch/arm/mach-rockchip/rk3399/rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
@@ -240,7 +240,7 @@ static void rk3399_force_power_on_reset(void)
void spl_board_init(void)
{
#if defined(SPL_GPIO_SUPPORT)
- struct rk3399_cru *cru = rockchip_get_cru();
+ struct rockchip_cru *cru = rockchip_get_cru();
/*
* The RK3399 resets only 'almost all logic' (see also in the TRM
diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index 85d1b67e43..cc1c1e81e9 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -14,7 +14,7 @@
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/cru_rk3288.h>
+#include <asm/arch-rockchip/cru.h>
#include <asm/arch-rockchip/grf_rk3288.h>
#include <asm/arch-rockchip/hardware.h>
#include <dt-bindings/clock/rk3288-cru.h>
@@ -141,7 +141,7 @@ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
-static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
+static int rkclk_set_pll(struct rockchip_cru *cru, enum rk_clk_id clk_id,
const struct pll_div *div)
{
int pll_id = rk_pll_id(clk_id);
@@ -172,7 +172,7 @@ static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
return 0;
}
-static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,
+static int rkclk_configure_ddr(struct rockchip_cru *cru, struct rk3288_grf *grf,
unsigned int hz)
{
static const struct pll_div dpll_cfg[] = {
@@ -295,7 +295,7 @@ static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
return 0;
}
-static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq)
+static int rockchip_mac_set_clk(struct rockchip_cru *cru, uint freq)
{
ulong ret;
@@ -333,7 +333,7 @@ static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq)
return ret;
}
-static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
+static int rockchip_vop_set_clk(struct rockchip_cru *cru, struct rk3288_grf *grf,
int periph, unsigned int rate_hz)
{
struct pll_div npll_config = {0};
@@ -384,7 +384,7 @@ static u32 rockchip_clk_gcd(u32 a, u32 b)
return a;
}
-static ulong rockchip_i2s_get_clk(struct rk3288_cru *cru, uint gclk_rate)
+static ulong rockchip_i2s_get_clk(struct rockchip_cru *cru, uint gclk_rate)
{
unsigned long long rate;
uint val;
@@ -400,7 +400,7 @@ static ulong rockchip_i2s_get_clk(struct rk3288_cru *cru, uint gclk_rate)
return (ulong)rate;
}
-static ulong rockchip_i2s_set_clk(struct rk3288_cru *cru, uint gclk_rate,
+static ulong rockchip_i2s_set_clk(struct rockchip_cru *cru, uint gclk_rate,
uint freq)
{
int n, d;
@@ -418,7 +418,7 @@ static ulong rockchip_i2s_set_clk(struct rk3288_cru *cru, uint gclk_rate,
}
#endif /* CONFIG_SPL_BUILD */
-static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
+static void rkclk_init(struct rockchip_cru *cru, struct rk3288_grf *grf)
{
u32 aclk_div;
u32 hclk_div;
@@ -492,7 +492,7 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
}
-void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
+void rk3288_clk_configure_cpu(struct rockchip_cru *cru, struct rk3288_grf *grf)
{
/* pll enter slow-mode */
rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
@@ -534,7 +534,7 @@ void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
}
/* Get pll rate by id */
-static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
+static uint32_t rkclk_pll_get_rate(struct rockchip_cru *cru,
enum rk_clk_id clk_id)
{
uint32_t nr, no, nf;
@@ -567,7 +567,7 @@ static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
}
}
-static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
+static ulong rockchip_mmc_get_clk(struct rockchip_cru *cru, uint gclk_rate,
int periph)
{
uint src_rate;
@@ -601,7 +601,7 @@ static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
return DIV_TO_RATE(src_rate, div);
}
-static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
+static ulong rockchip_mmc_set_clk(struct rockchip_cru *cru, uint gclk_rate,
int periph, uint freq)
{
int src_clk_div;
@@ -651,7 +651,7 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
return rockchip_mmc_get_clk(cru, gclk_rate, periph);
}
-static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
+static ulong rockchip_spi_get_clk(struct rockchip_cru *cru, uint gclk_rate,
int periph)
{
uint div, mux;
@@ -681,7 +681,7 @@ static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
return DIV_TO_RATE(gclk_rate, div);
}
-static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
+static ulong rockchip_spi_set_clk(struct rockchip_cru *cru, uint gclk_rate,
int periph, uint freq)
{
int src_clk_div;
@@ -715,7 +715,7 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
return rockchip_spi_get_clk(cru, gclk_rate, periph);
}
-static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru)
+static ulong rockchip_saradc_get_clk(struct rockchip_cru *cru)
{
u32 div, val;
@@ -726,7 +726,7 @@ static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru)
return DIV_TO_RATE(OSC_HZ, div);
}
-static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz)
+static ulong rockchip_saradc_set_clk(struct rockchip_cru *cru, uint hz)
{
int src_clk_div;
@@ -785,7 +785,7 @@ static ulong rk3288_clk_get_rate(struct clk *clk)
static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
{
struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
- struct rk3288_cru *cru = priv->cru;
+ struct rockchip_cru *cru = priv->cru;
ulong new_rate, gclk_rate;
gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
@@ -892,7 +892,7 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
static int __maybe_unused rk3288_gmac_set_parent(struct clk *clk, struct clk *parent)
{
struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
- struct rk3288_cru *cru = priv->cru;
+ struct rockchip_cru *cru = priv->cru;
const char *clock_output_name;
int ret;
@@ -1008,15 +1008,15 @@ static int rk3288_clk_bind(struct udevice *dev)
debug("Warning: No sysreset driver: ret=%d\n", ret);
} else {
priv = malloc(sizeof(struct sysreset_reg));
- priv->glb_srst_fst_value = offsetof(struct rk3288_cru,
+ priv->glb_srst_fst_value = offsetof(struct rockchip_cru,
cru_glb_srst_fst_value);
- priv->glb_srst_snd_value = offsetof(struct rk3288_cru,
+ priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
cru_glb_srst_snd_value);
sys_child->priv = priv;
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
- ret = offsetof(struct rk3288_cru, cru_softrst_con[0]);
+ ret = offsetof(struct rockchip_cru, cru_softrst_con[0]);
ret = rockchip_reset_bind(dev, ret, 12);
if (ret)
debug("Warning: software reset driver bind faile\n");
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 9020a9f202..37fc142a7a 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -14,7 +14,7 @@
#include <bitfield.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/cru_rk3399.h>
+#include <asm/arch-rockchip/cru.h>
#include <asm/arch-rockchip/hardware.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3399-cru.h>
@@ -418,7 +418,7 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div)
return 0;
}
-void rk3399_configure_cpu_l(struct rk3399_cru *cru,
+void rk3399_configure_cpu_l(struct rockchip_cru *cru,
enum apll_l_frequencies apll_l_freq)
{
u32 aclkm_div;
@@ -453,7 +453,7 @@ void rk3399_configure_cpu_l(struct rk3399_cru *cru,
atclk_div << ATCLK_CORE_L_DIV_SHIFT);
}
-void rk3399_configure_cpu_b(struct rk3399_cru *cru,
+void rk3399_configure_cpu_b(struct rockchip_cru *cru,
enum apll_b_frequencies apll_b_freq)
{
u32 aclkm_div;
@@ -505,7 +505,7 @@ void rk3399_configure_cpu_b(struct rk3399_cru *cru,
#define I2C_PMUCLK_REG_VALUE(bus, clk_div) \
((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT)
-static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id)
+static ulong rk3399_i2c_get_clk(struct rockchip_cru *cru, ulong clk_id)
{
u32 div, con;
@@ -542,7 +542,7 @@ static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id)
return DIV_TO_RATE(GPLL_HZ, div);
}
-static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
+static ulong rk3399_i2c_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
{
int src_clk_div;
@@ -619,7 +619,7 @@ static const struct spi_clkreg spi_clkregs[] = {
.sel_shift = CLK_SPI5_PLL_SEL_SHIFT, },
};
-static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id)
+static ulong rk3399_spi_get_clk(struct rockchip_cru *cru, ulong clk_id)
{
const struct spi_clkreg *spiclk = NULL;
u32 div, val;
@@ -641,7 +641,7 @@ static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id)
return DIV_TO_RATE(GPLL_HZ, div);
}
-static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
+static ulong rk3399_spi_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
{
const struct spi_clkreg *spiclk = NULL;
int src_clk_div;
@@ -668,7 +668,7 @@ static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
return rk3399_spi_get_clk(cru, clk_id);
}
-static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
+static ulong rk3399_vop_set_clk(struct rockchip_cru *cru, ulong clk_id, u32 hz)
{
struct pll_div vpll_config = {0};
int aclk_vop = 198 * MHz;
@@ -712,7 +712,7 @@ static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
return hz;
}
-static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id)
+static ulong rk3399_mmc_get_clk(struct rockchip_cru *cru, uint clk_id)
{
u32 div, con;
@@ -739,7 +739,7 @@ static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id)
return DIV_TO_RATE(GPLL_HZ, div);
}
-static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
+static ulong rk3399_mmc_set_clk(struct rockchip_cru *cru,
ulong clk_id, ulong set_rate)
{
int src_clk_div;
@@ -792,7 +792,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
return rk3399_mmc_get_clk(cru, clk_id);
}
-static ulong rk3399_gmac_set_clk(struct rk3399_cru *cru, ulong rate)
+static ulong rk3399_gmac_set_clk(struct rockchip_cru *cru, ulong rate)
{
ulong ret;
@@ -817,7 +817,7 @@ static ulong rk3399_gmac_set_clk(struct rk3399_cru *cru, ulong rate)
}
#define PMUSGRF_DDR_RGN_CON16 0xff330040
-static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
+static ulong rk3399_ddr_set_clk(struct rockchip_cru *cru,
ulong set_rate)
{
struct pll_div dpll_cfg;
@@ -863,7 +863,7 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
return set_rate;
}
-static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru)
+static ulong rk3399_saradc_get_clk(struct rockchip_cru *cru)
{
u32 div, val;
@@ -874,7 +874,7 @@ static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru)
return DIV_TO_RATE(OSC_HZ, div);
}
-static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz)
+static ulong rk3399_saradc_set_clk(struct rockchip_cru *cru, uint hz)
{
int src_clk_div;
@@ -1071,7 +1071,7 @@ static struct clk_ops rk3399_clk_ops = {
};
#ifdef CONFIG_SPL_BUILD
-static void rkclk_init(struct rk3399_cru *cru)
+static void rkclk_init(struct rockchip_cru *cru)
{
u32 aclk_div;
u32 hclk_div;
@@ -1188,15 +1188,15 @@ static int rk3399_clk_bind(struct udevice *dev)
debug("Warning: No sysreset driver: ret=%d\n", ret);
} else {
priv = malloc(sizeof(struct sysreset_reg));
- priv->glb_srst_fst_value = offsetof(struct rk3399_cru,
+ priv->glb_srst_fst_value = offsetof(struct rockchip_cru,
glb_srst_fst_value);
- priv->glb_srst_snd_value = offsetof(struct rk3399_cru,
+ priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
glb_srst_snd_value);
sys_child->priv = priv;
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
- ret = offsetof(struct rk3399_cru, softrst_con[0]);
+ ret = offsetof(struct rockchip_cru, softrst_con[0]);
ret = rockchip_reset_bind(dev, ret, 21);
if (ret)
debug("Warning: software reset driver bind faile\n");
diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c
index 690751d074..fd5b204e1f 100644
--- a/drivers/ram/rockchip/sdram_rk3288.c
+++ b/drivers/ram/rockchip/sdram_rk3288.c
@@ -16,7 +16,7 @@
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/cru_rk3288.h>
+#include <asm/arch-rockchip/cru.h>
#include <asm/arch-rockchip/ddr_rk3288.h>
#include <asm/arch-rockchip/grf_rk3288.h>
#include <asm/arch-rockchip/pmu_rk3288.h>
@@ -36,7 +36,7 @@ struct dram_info {
struct chan_info chan[2];
struct ram_info info;
struct clk ddr_clk;
- struct rk3288_cru *cru;
+ struct rockchip_cru *cru;
struct rk3288_grf *grf;
struct rk3288_sgrf *sgrf;
struct rk3288_pmu *pmu;
@@ -92,7 +92,7 @@ static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
}
}
-static void ddr_reset(struct rk3288_cru *cru, u32 ch, u32 ctl, u32 phy)
+static void ddr_reset(struct rockchip_cru *cru, u32 ch, u32 ctl, u32 phy)
{
u32 phy_ctl_srstn_shift = 4 + 5 * ch;
u32 ctl_psrstn_shift = 3 + 5 * ch;
@@ -109,7 +109,7 @@ static void ddr_reset(struct rk3288_cru *cru, u32 ch, u32 ctl, u32 phy)
phy << phy_srstn_shift);
}
-static void ddr_phy_ctl_reset(struct rk3288_cru *cru, u32 ch, u32 n)
+static void ddr_phy_ctl_reset(struct rockchip_cru *cru, u32 ch, u32 n)
{
u32 phy_ctl_srstn_shift = 4 + 5 * ch;
@@ -117,7 +117,7 @@ static void ddr_phy_ctl_reset(struct rk3288_cru *cru, u32 ch, u32 n)
1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift);
}
-static void phy_pctrl_reset(struct rk3288_cru *cru,
+static void phy_pctrl_reset(struct rockchip_cru *cru,
struct rk3288_ddr_publ *publ,
int channel)
{
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 7b2bba03fe..08bf0393a7 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -14,7 +14,7 @@
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/cru_rk3399.h>
+#include <asm/arch-rockchip/cru.h>
#include <asm/arch-rockchip/grf_rk3399.h>
#include <asm/arch-rockchip/pmu_rk3399.h>
#include <asm/arch-rockchip/hardware.h>
@@ -66,7 +66,7 @@ struct dram_info {
u32 pwrup_srefresh_exit[2];
struct chan_info chan[2];
struct clk ddr_clk;
- struct rk3399_cru *cru;
+ struct rockchip_cru *cru;
struct rk3399_grf_regs *grf;
struct rk3399_pmu_regs *pmu;
struct rk3399_pmucru *pmucru;
@@ -228,7 +228,7 @@ static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc1_con0;
}
-static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl,
+static void rkclk_ddr_reset(struct rockchip_cru *cru, u32 channel, u32 ctl,
u32 phy)
{
channel &= 0x1;
@@ -239,7 +239,7 @@ static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl,
&cru->softrst_con[4]);
}
-static void phy_pctrl_reset(struct rk3399_cru *cru, u32 channel)
+static void phy_pctrl_reset(struct rockchip_cru *cru, u32 channel)
{
rkclk_ddr_reset(cru, channel, 1, 1);
udelay(10);
@@ -2945,7 +2945,7 @@ static int sdram_init(struct dram_info *dram,
for (channel = 0; channel < 2; channel++) {
const struct chan_info *chan =
&dram->chan[channel];
- struct rk3399_cru *cru = dram->cru;
+ struct rockchip_cru *cru = dram->cru;
struct rk3399_ddr_publ_regs *publ = chan->publ;
phy_pctrl_reset(cru, channel);
diff --git a/drivers/video/rockchip/rk3288_mipi.c b/drivers/video/rockchip/rk3288_mipi.c
index 7c4a4cc53b..65891ce45c 100644
--- a/drivers/video/rockchip/rk3288_mipi.c
+++ b/drivers/video/rockchip/rk3288_mipi.c
@@ -18,7 +18,7 @@
#include <dm/uclass-internal.h>
#include <linux/kernel.h>
#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/cru_rk3288.h>
+#include <asm/arch-rockchip/cru.h>
#include <asm/arch-rockchip/grf_rk3288.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/rockchip_mipi_dsi.h>
diff --git a/drivers/video/rockchip/rk3399_mipi.c b/drivers/video/rockchip/rk3399_mipi.c
index a93b73400b..a5b7ba69a8 100644
--- a/drivers/video/rockchip/rk3399_mipi.c
+++ b/drivers/video/rockchip/rk3399_mipi.c
@@ -18,7 +18,7 @@
#include <dm/uclass-internal.h>
#include <linux/kernel.h>
#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/cru_rk3399.h>
+#include <asm/arch-rockchip/cru.h>
#include <asm/arch-rockchip/grf_rk3399.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/rockchip_mipi_dsi.h>
diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c
index bcd039b7bc..f9280e8607 100644
--- a/drivers/video/rockchip/rk_mipi.c
+++ b/drivers/video/rockchip/rk_mipi.c
@@ -18,7 +18,7 @@
#include <dm/uclass-internal.h>
#include <linux/kernel.h>
#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/cru_rk3399.h>
+#include <asm/arch-rockchip/cru.h>
#include <asm/arch-rockchip/grf_rk3399.h>
#include <asm/arch-rockchip/rockchip_mipi_dsi.h>
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 4/5] rockchip: Add common reset cause
2019-12-29 19:07 ` Jagan Teki
@ 2019-12-29 19:07 ` Jagan Teki
-1 siblings, 0 replies; 21+ messages in thread
From: Jagan Teki @ 2019-12-29 19:07 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich
Cc: Jagan Teki, u-boot-0aAXYlwwYIKGBzrmiIFOJg,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Akash Gajjar, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Add cpu reset cause in common cpu-info file.
This would help to print the reset cause for
various resets.
Right now it support rk3288, rk3399. rest of rockchip
platforms doesn't have reset cause support ye but this
code is more feasible to extend the same.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
arch/arm/include/asm/arch-rockchip/cru.h | 12 +++++
.../include/asm/arch-rockchip/cru_rk3288.h | 14 +-----
arch/arm/mach-rockchip/cpu-info.c | 49 +++++++++++++++++++
arch/arm/mach-rockchip/rk3288/rk3288.c | 39 ---------------
4 files changed, 62 insertions(+), 52 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h
index 5ed3fbfd07..e1dd9a89c2 100644
--- a/arch/arm/include/asm/arch-rockchip/cru.h
+++ b/arch/arm/include/asm/arch-rockchip/cru.h
@@ -13,4 +13,16 @@
# include <asm/arch-rockchip/cru_rk3399.h>
#endif
+/* CRU_GLB_RST_ST */
+enum {
+ GLB_POR_RST,
+ FST_GLB_RST_ST = BIT(0),
+ SND_GLB_RST_ST = BIT(1),
+ FST_GLB_TSADC_RST_ST = BIT(2),
+ SND_GLB_TSADC_RST_ST = BIT(3),
+ FST_GLB_WDT_RST_ST = BIT(4),
+ SND_GLB_WDT_RST_ST = BIT(5),
+ GLB_RST_ST_MASK = GENMASK(5, 0),
+};
+
#endif /* _ROCKCHIP_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
index 7aa6efe46c..412b73e55f 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
@@ -51,7 +51,7 @@ struct rockchip_cru {
u32 cru_glb_cnt_th;
u32 cru_glb_rst_con;
u32 reserved3;
- u32 cru_glb_rst_st;
+ u32 glb_rst_st;
u32 reserved4;
u32 cru_sdmmc_con[2];
u32 cru_sdio0_con[2];
@@ -227,16 +227,4 @@ enum {
CLKF_MASK = 0x1fff << CLKF_SHIFT,
};
-/* CRU_GLB_RST_ST */
-enum {
- GLB_POR_RST,
- FST_GLB_RST_ST = BIT(0),
- SND_GLB_RST_ST = BIT(1),
- FST_GLB_TSADC_RST_ST = BIT(2),
- SND_GLB_TSADC_RST_ST = BIT(3),
- FST_GLB_WDT_RST_ST = BIT(4),
- SND_GLB_WDT_RST_ST = BIT(5),
- GLB_RST_ST_MASK = GENMASK(5, 0),
-};
-
#endif
diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c
index 9bccbd4f68..4b0e99299a 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -5,10 +5,59 @@
*/
#include <common.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <linux/err.h>
+
+static char *get_reset_cause(void)
+{
+ struct rockchip_cru *cru = rockchip_get_cru();
+ char *cause = NULL;
+
+ if (IS_ERR(cru))
+ return cause;
+
+ switch (cru->glb_rst_st) {
+ case GLB_POR_RST:
+ cause = "POR";
+ break;
+ case FST_GLB_RST_ST:
+ case SND_GLB_RST_ST:
+ cause = "RST";
+ break;
+ case FST_GLB_TSADC_RST_ST:
+ case SND_GLB_TSADC_RST_ST:
+ cause = "THERMAL";
+ break;
+ case FST_GLB_WDT_RST_ST:
+ case SND_GLB_WDT_RST_ST:
+ cause = "WDOG";
+ break;
+ default:
+ cause = "unknown reset";
+ }
+
+ /**
+ * reset_reason env is used by rk3288, due to special use case
+ * to figure it the boot behavior. so keep this as it is.
+ */
+ env_set("reset_reason", cause);
+
+ /*
+ * Clear glb_rst_st, so we can determine the last reset cause
+ * for following resets.
+ */
+ rk_clrreg(&cru->glb_rst_st, GLB_RST_ST_MASK);
+
+ return cause;
+}
int print_cpuinfo(void)
{
printf("SoC: Rockchip %s\n", CONFIG_SYS_SOC);
+ printf("Reset cause: %s\n", get_reset_cause());
/* TODO print operating temparature and clock */
diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c
index 47ee5d440b..18ea7f35fb 100644
--- a/arch/arm/mach-rockchip/rk3288/rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/rk3288.c
@@ -102,43 +102,6 @@ void board_debug_uart_init(void)
}
#endif
-static void rk3288_detect_reset_reason(void)
-{
- struct rockchip_cru *cru = rockchip_get_cru();
- const char *reason;
-
- if (IS_ERR(cru))
- return;
-
- switch (cru->cru_glb_rst_st) {
- case GLB_POR_RST:
- reason = "POR";
- break;
- case FST_GLB_RST_ST:
- case SND_GLB_RST_ST:
- reason = "RST";
- break;
- case FST_GLB_TSADC_RST_ST:
- case SND_GLB_TSADC_RST_ST:
- reason = "THERMAL";
- break;
- case FST_GLB_WDT_RST_ST:
- case SND_GLB_WDT_RST_ST:
- reason = "WDOG";
- break;
- default:
- reason = "unknown reset";
- }
-
- env_set("reset_reason", reason);
-
- /*
- * Clear cru_glb_rst_st, so we can determine the last reset cause
- * for following resets.
- */
- rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK);
-}
-
__weak int rk3288_board_late_init(void)
{
return 0;
@@ -146,8 +109,6 @@ __weak int rk3288_board_late_init(void)
int rk_board_late_init(void)
{
- rk3288_detect_reset_reason();
-
return rk3288_board_late_init();
}
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 4/5] rockchip: Add common reset cause
@ 2019-12-29 19:07 ` Jagan Teki
0 siblings, 0 replies; 21+ messages in thread
From: Jagan Teki @ 2019-12-29 19:07 UTC (permalink / raw)
To: u-boot
Add cpu reset cause in common cpu-info file.
This would help to print the reset cause for
various resets.
Right now it support rk3288, rk3399. rest of rockchip
platforms doesn't have reset cause support ye but this
code is more feasible to extend the same.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/include/asm/arch-rockchip/cru.h | 12 +++++
.../include/asm/arch-rockchip/cru_rk3288.h | 14 +-----
arch/arm/mach-rockchip/cpu-info.c | 49 +++++++++++++++++++
arch/arm/mach-rockchip/rk3288/rk3288.c | 39 ---------------
4 files changed, 62 insertions(+), 52 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h
index 5ed3fbfd07..e1dd9a89c2 100644
--- a/arch/arm/include/asm/arch-rockchip/cru.h
+++ b/arch/arm/include/asm/arch-rockchip/cru.h
@@ -13,4 +13,16 @@
# include <asm/arch-rockchip/cru_rk3399.h>
#endif
+/* CRU_GLB_RST_ST */
+enum {
+ GLB_POR_RST,
+ FST_GLB_RST_ST = BIT(0),
+ SND_GLB_RST_ST = BIT(1),
+ FST_GLB_TSADC_RST_ST = BIT(2),
+ SND_GLB_TSADC_RST_ST = BIT(3),
+ FST_GLB_WDT_RST_ST = BIT(4),
+ SND_GLB_WDT_RST_ST = BIT(5),
+ GLB_RST_ST_MASK = GENMASK(5, 0),
+};
+
#endif /* _ROCKCHIP_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
index 7aa6efe46c..412b73e55f 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
@@ -51,7 +51,7 @@ struct rockchip_cru {
u32 cru_glb_cnt_th;
u32 cru_glb_rst_con;
u32 reserved3;
- u32 cru_glb_rst_st;
+ u32 glb_rst_st;
u32 reserved4;
u32 cru_sdmmc_con[2];
u32 cru_sdio0_con[2];
@@ -227,16 +227,4 @@ enum {
CLKF_MASK = 0x1fff << CLKF_SHIFT,
};
-/* CRU_GLB_RST_ST */
-enum {
- GLB_POR_RST,
- FST_GLB_RST_ST = BIT(0),
- SND_GLB_RST_ST = BIT(1),
- FST_GLB_TSADC_RST_ST = BIT(2),
- SND_GLB_TSADC_RST_ST = BIT(3),
- FST_GLB_WDT_RST_ST = BIT(4),
- SND_GLB_WDT_RST_ST = BIT(5),
- GLB_RST_ST_MASK = GENMASK(5, 0),
-};
-
#endif
diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c
index 9bccbd4f68..4b0e99299a 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -5,10 +5,59 @@
*/
#include <common.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <linux/err.h>
+
+static char *get_reset_cause(void)
+{
+ struct rockchip_cru *cru = rockchip_get_cru();
+ char *cause = NULL;
+
+ if (IS_ERR(cru))
+ return cause;
+
+ switch (cru->glb_rst_st) {
+ case GLB_POR_RST:
+ cause = "POR";
+ break;
+ case FST_GLB_RST_ST:
+ case SND_GLB_RST_ST:
+ cause = "RST";
+ break;
+ case FST_GLB_TSADC_RST_ST:
+ case SND_GLB_TSADC_RST_ST:
+ cause = "THERMAL";
+ break;
+ case FST_GLB_WDT_RST_ST:
+ case SND_GLB_WDT_RST_ST:
+ cause = "WDOG";
+ break;
+ default:
+ cause = "unknown reset";
+ }
+
+ /**
+ * reset_reason env is used by rk3288, due to special use case
+ * to figure it the boot behavior. so keep this as it is.
+ */
+ env_set("reset_reason", cause);
+
+ /*
+ * Clear glb_rst_st, so we can determine the last reset cause
+ * for following resets.
+ */
+ rk_clrreg(&cru->glb_rst_st, GLB_RST_ST_MASK);
+
+ return cause;
+}
int print_cpuinfo(void)
{
printf("SoC: Rockchip %s\n", CONFIG_SYS_SOC);
+ printf("Reset cause: %s\n", get_reset_cause());
/* TODO print operating temparature and clock */
diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c
index 47ee5d440b..18ea7f35fb 100644
--- a/arch/arm/mach-rockchip/rk3288/rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/rk3288.c
@@ -102,43 +102,6 @@ void board_debug_uart_init(void)
}
#endif
-static void rk3288_detect_reset_reason(void)
-{
- struct rockchip_cru *cru = rockchip_get_cru();
- const char *reason;
-
- if (IS_ERR(cru))
- return;
-
- switch (cru->cru_glb_rst_st) {
- case GLB_POR_RST:
- reason = "POR";
- break;
- case FST_GLB_RST_ST:
- case SND_GLB_RST_ST:
- reason = "RST";
- break;
- case FST_GLB_TSADC_RST_ST:
- case SND_GLB_TSADC_RST_ST:
- reason = "THERMAL";
- break;
- case FST_GLB_WDT_RST_ST:
- case SND_GLB_WDT_RST_ST:
- reason = "WDOG";
- break;
- default:
- reason = "unknown reset";
- }
-
- env_set("reset_reason", reason);
-
- /*
- * Clear cru_glb_rst_st, so we can determine the last reset cause
- * for following resets.
- */
- rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK);
-}
-
__weak int rk3288_board_late_init(void)
{
return 0;
@@ -146,8 +109,6 @@ __weak int rk3288_board_late_init(void)
int rk_board_late_init(void)
{
- rk3288_detect_reset_reason();
-
return rk3288_board_late_init();
}
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 5/5] rockchip: rk3399: Add bootcount support
2019-12-29 19:07 ` Jagan Teki
@ 2019-12-29 19:07 ` Jagan Teki
-1 siblings, 0 replies; 21+ messages in thread
From: Jagan Teki @ 2019-12-29 19:07 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich
Cc: Jagan Teki, u-boot-0aAXYlwwYIKGBzrmiIFOJg,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Akash Gajjar, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Add bootcount support for Rockchip rk3399.
The bootcount value is preserved in PMU_SYS_REG0 register,
this would help to support redundent boot.
Once the redundant boot triggers, the altboot command
will look for extlinux-rollback.conf on particular
bootable partition which supposed to be a recovery
partition where redundant boot required.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
arch/arm/mach-rockchip/Kconfig | 2 ++
arch/arm/mach-rockchip/rk3399/Kconfig | 10 ++++++++++
include/configs/rk3399_common.h | 5 ++++-
3 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index d8d68ba447..9a3c65ec58 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -244,6 +244,8 @@ config ROCKCHIP_RK3399
imply TPL_CLK
imply TPL_TINY_MEMSET
imply TPL_ROCKCHIP_COMMON_BOARD
+ imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT
+ imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT
help
The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
and quad-core Cortex-A53.
diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig
index 868e85fc2a..f994152803 100644
--- a/arch/arm/mach-rockchip/rk3399/Kconfig
+++ b/arch/arm/mach-rockchip/rk3399/Kconfig
@@ -113,6 +113,16 @@ config TPL_TEXT_BASE
config SPL_STACK_R_ADDR
default 0x04000000
+if BOOTCOUNT_LIMIT
+
+config BOOTCOUNT_BOOTLIMIT
+ default 3
+
+config SYS_BOOTCOUNT_ADDR
+ default 0xff3100f0 # PMU_SYS_REG0
+
+endif # BOOTCOUNT_LIMIT
+
source "board/rockchip/evb_rk3399/Kconfig"
source "board/theobroma-systems/puma_rk3399/Kconfig"
source "board/vamrs/rock960_rk3399/Kconfig"
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index 127ca1f09c..89a8a44bbe 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -63,7 +63,10 @@
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
"partitions=" PARTS_DEFAULT \
ROCKCHIP_DEVICE_SETTINGS \
- BOOTENV
+ BOOTENV \
+ "altbootcmd=" \
+ "setenv boot_syslinux_conf extlinux/extlinux-rollback.conf;" \
+ "run distro_bootcmd\0"
#endif
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 5/5] rockchip: rk3399: Add bootcount support
@ 2019-12-29 19:07 ` Jagan Teki
0 siblings, 0 replies; 21+ messages in thread
From: Jagan Teki @ 2019-12-29 19:07 UTC (permalink / raw)
To: u-boot
Add bootcount support for Rockchip rk3399.
The bootcount value is preserved in PMU_SYS_REG0 register,
this would help to support redundent boot.
Once the redundant boot triggers, the altboot command
will look for extlinux-rollback.conf on particular
bootable partition which supposed to be a recovery
partition where redundant boot required.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/mach-rockchip/Kconfig | 2 ++
arch/arm/mach-rockchip/rk3399/Kconfig | 10 ++++++++++
include/configs/rk3399_common.h | 5 ++++-
3 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index d8d68ba447..9a3c65ec58 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -244,6 +244,8 @@ config ROCKCHIP_RK3399
imply TPL_CLK
imply TPL_TINY_MEMSET
imply TPL_ROCKCHIP_COMMON_BOARD
+ imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT
+ imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT
help
The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
and quad-core Cortex-A53.
diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig
index 868e85fc2a..f994152803 100644
--- a/arch/arm/mach-rockchip/rk3399/Kconfig
+++ b/arch/arm/mach-rockchip/rk3399/Kconfig
@@ -113,6 +113,16 @@ config TPL_TEXT_BASE
config SPL_STACK_R_ADDR
default 0x04000000
+if BOOTCOUNT_LIMIT
+
+config BOOTCOUNT_BOOTLIMIT
+ default 3
+
+config SYS_BOOTCOUNT_ADDR
+ default 0xff3100f0 # PMU_SYS_REG0
+
+endif # BOOTCOUNT_LIMIT
+
source "board/rockchip/evb_rk3399/Kconfig"
source "board/theobroma-systems/puma_rk3399/Kconfig"
source "board/vamrs/rock960_rk3399/Kconfig"
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index 127ca1f09c..89a8a44bbe 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -63,7 +63,10 @@
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
"partitions=" PARTS_DEFAULT \
ROCKCHIP_DEVICE_SETTINGS \
- BOOTENV
+ BOOTENV \
+ "altbootcmd=" \
+ "setenv boot_syslinux_conf extlinux/extlinux-rollback.conf;" \
+ "run distro_bootcmd\0"
#endif
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v3 2/5] rockchip: rk3399: Enable DISPLAY_CPUINFO
2019-12-29 19:07 ` Jagan Teki
@ 2020-01-06 9:23 ` Kever Yang
-1 siblings, 0 replies; 21+ messages in thread
From: Kever Yang @ 2020-01-06 9:23 UTC (permalink / raw)
To: Jagan Teki, Simon Glass, Philipp Tomsich
Cc: u-boot, linux-amarula, Akash Gajjar, linux-rockchip
On 2019/12/30 上午3:07, Jagan Teki wrote:
> RK3288, RK3399 are now support cpu-info, so enable
> DISPLAY_CPUINFO by default.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> configs/evb-rk3288_defconfig | 1 -
> configs/evb-rk3399_defconfig | 1 -
> configs/ficus-rk3399_defconfig | 1 -
> configs/firefly-rk3288_defconfig | 1 -
> configs/firefly-rk3399_defconfig | 1 -
> configs/khadas-edge-captain-rk3399_defconfig | 1 -
> configs/khadas-edge-rk3399_defconfig | 1 -
> configs/khadas-edge-v-rk3399_defconfig | 1 -
> configs/leez-rk3399_defconfig | 1 -
> configs/miqi-rk3288_defconfig | 1 -
> configs/nanopc-t4-rk3399_defconfig | 1 -
> configs/nanopi-m4-rk3399_defconfig | 1 -
> configs/nanopi-neo4-rk3399_defconfig | 1 -
> configs/orangepi-rk3399_defconfig | 1 -
> configs/phycore-rk3288_defconfig | 1 -
> configs/popmetal-rk3288_defconfig | 1 -
> configs/puma-rk3399_defconfig | 1 -
> configs/roc-pc-rk3399_defconfig | 1 -
> configs/rock-pi-4-rk3399_defconfig | 1 -
> configs/rock960-rk3399_defconfig | 1 -
> configs/rockpro64-rk3399_defconfig | 1 -
> configs/tinker-rk3288_defconfig | 1 -
> configs/tinker-s-rk3288_defconfig | 1 -
> configs/vyasa-rk3288_defconfig | 1 -
> 24 files changed, 24 deletions(-)
>
> diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig
> index 1fa4054f5d..59c909e10d 100644
> --- a/configs/evb-rk3288_defconfig
> +++ b/configs/evb-rk3288_defconfig
> @@ -14,7 +14,6 @@ CONFIG_DEBUG_UART=y
> CONFIG_USE_PREBOOT=y
> CONFIG_SILENT_CONSOLE=y
> CONFIG_DEFAULT_FDT_FILE="rk3288-evb-rk808.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> CONFIG_SPL_STACK_R=y
> CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
> diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
> index 8b8cdc5109..896a6050eb 100644
> --- a/configs/evb-rk3399_defconfig
> +++ b/configs/evb-rk3399_defconfig
> @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
> CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_DEBUG_UART=y
> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> CONFIG_SPL_STACK_R=y
> diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig
> index 6bb030acc1..5b49fe0b7b 100644
> --- a/configs/ficus-rk3399_defconfig
> +++ b/configs/ficus-rk3399_defconfig
> @@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
> CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_DEBUG_UART=y
> CONFIG_SPL_TEXT_BASE=0xff8c2000
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> CONFIG_SPL_STACK_R=y
> diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
> index 0c0a51c54f..41a6fc3edd 100644
> --- a/configs/firefly-rk3288_defconfig
> +++ b/configs/firefly-rk3288_defconfig
> @@ -14,7 +14,6 @@ CONFIG_DEBUG_UART=y
> CONFIG_USE_PREBOOT=y
> CONFIG_SILENT_CONSOLE=y
> CONFIG_DEFAULT_FDT_FILE="rk3288-firefly.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> CONFIG_SPL_STACK_R=y
> CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
> diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig
> index b84d7b9ff0..5d197f5f8a 100644
> --- a/configs/firefly-rk3399_defconfig
> +++ b/configs/firefly-rk3399_defconfig
> @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
> CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_DEBUG_UART=y
> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> CONFIG_SPL_STACK_R=y
> diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig
> index c408a1a59b..379e21e28d 100644
> --- a/configs/khadas-edge-captain-rk3399_defconfig
> +++ b/configs/khadas-edge-captain-rk3399_defconfig
> @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
> CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_DEBUG_UART=y
> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-captain.dtbi"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> CONFIG_SPL_STACK_R=y
> diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig
> index 796f94f8d7..9086018cd0 100644
> --- a/configs/khadas-edge-rk3399_defconfig
> +++ b/configs/khadas-edge-rk3399_defconfig
> @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
> CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_DEBUG_UART=y
> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> CONFIG_SPL_STACK_R=y
> diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig
> index e70e1ec2e6..261d75526b 100644
> --- a/configs/khadas-edge-v-rk3399_defconfig
> +++ b/configs/khadas-edge-v-rk3399_defconfig
> @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
> CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_DEBUG_UART=y
> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-v.dtbi"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> CONFIG_SPL_STACK_R=y
> diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig
> index 3758d79a1e..1d621fc9ce 100644
> --- a/configs/leez-rk3399_defconfig
> +++ b/configs/leez-rk3399_defconfig
> @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
> CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_DEBUG_UART=y
> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-leez-p710.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> CONFIG_SPL_STACK_R=y
> CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
> diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig
> index cec8e42c5e..25a808eb89 100644
> --- a/configs/miqi-rk3288_defconfig
> +++ b/configs/miqi-rk3288_defconfig
> @@ -15,7 +15,6 @@ CONFIG_SPL_TEXT_BASE=0xff704000
> CONFIG_USE_PREBOOT=y
> CONFIG_SILENT_CONSOLE=y
> CONFIG_DEFAULT_FDT_FILE="rk3288-miqi.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> CONFIG_SPL_STACK_R=y
> CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
> diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig
> index 504346eb99..bd6d60ff6c 100644
> --- a/configs/nanopc-t4-rk3399_defconfig
> +++ b/configs/nanopc-t4-rk3399_defconfig
> @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
> CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_DEBUG_UART=y
> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> CONFIG_SPL_STACK_R=y
> diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig
> index 24c8aa401b..74ede13c23 100644
> --- a/configs/nanopi-m4-rk3399_defconfig
> +++ b/configs/nanopi-m4-rk3399_defconfig
> @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
> CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_DEBUG_UART=y
> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> CONFIG_SPL_STACK_R=y
> diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig
> index 986739f16e..a44124aac0 100644
> --- a/configs/nanopi-neo4-rk3399_defconfig
> +++ b/configs/nanopi-neo4-rk3399_defconfig
> @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
> CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_DEBUG_UART=y
> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> CONFIG_SPL_STACK_R=y
> diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig
> index bed634b699..4c464de8a6 100644
> --- a/configs/orangepi-rk3399_defconfig
> +++ b/configs/orangepi-rk3399_defconfig
> @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
> CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_DEBUG_UART=y
> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> CONFIG_SPL_STACK_R=y
> diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig
> index 4c48d42299..2f10c7a3b3 100644
> --- a/configs/phycore-rk3288_defconfig
> +++ b/configs/phycore-rk3288_defconfig
> @@ -16,7 +16,6 @@ CONFIG_USE_PREBOOT=y
> CONFIG_SILENT_CONSOLE=y
> CONFIG_CONSOLE_MUX=y
> CONFIG_DEFAULT_FDT_FILE="rk3288-phycore-rdk.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> CONFIG_SPL_STACK_R=y
> CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
> diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig
> index f732f6b209..512efee1a9 100644
> --- a/configs/popmetal-rk3288_defconfig
> +++ b/configs/popmetal-rk3288_defconfig
> @@ -16,7 +16,6 @@ CONFIG_USE_PREBOOT=y
> CONFIG_SILENT_CONSOLE=y
> CONFIG_CONSOLE_MUX=y
> CONFIG_DEFAULT_FDT_FILE="rk3288-popmetal.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> CONFIG_SPL_STACK_R=y
> CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
> diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig
> index 55255bf6af..30c7ab2751 100644
> --- a/configs/puma-rk3399_defconfig
> +++ b/configs/puma-rk3399_defconfig
> @@ -16,7 +16,6 @@ CONFIG_SPL_TEXT_BASE=0xff8c2000
> CONFIG_SPL_FIT_GENERATOR="board/theobroma-systems/puma_rk3399/fit_spl_atf.sh"
> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb"
> CONFIG_MISC_INIT_R=y
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> CONFIG_SPL_STACK_R=y
> diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig
> index 305baa712c..bf83b25dbc 100644
> --- a/configs/roc-pc-rk3399_defconfig
> +++ b/configs/roc-pc-rk3399_defconfig
> @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
> CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_DEBUG_UART=y
> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> CONFIG_SPL_STACK_R=y
> diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig
> index 2c01bf1f87..4429f58fde 100644
> --- a/configs/rock-pi-4-rk3399_defconfig
> +++ b/configs/rock-pi-4-rk3399_defconfig
> @@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_DEBUG_UART=y
> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4.dtb"
> CONFIG_MISC_INIT_R=y
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> CONFIG_SPL_STACK_R=y
> diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig
> index ec32e6cf05..7b6dc3f83c 100644
> --- a/configs/rock960-rk3399_defconfig
> +++ b/configs/rock960-rk3399_defconfig
> @@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
> CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_DEBUG_UART=y
> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> CONFIG_SPL_STACK_R=y
> diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig
> index 49e27c91cb..955b717131 100644
> --- a/configs/rockpro64-rk3399_defconfig
> +++ b/configs/rockpro64-rk3399_defconfig
> @@ -10,7 +10,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_DEBUG_UART=y
> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb"
> CONFIG_MISC_INIT_R=y
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> CONFIG_SPL_STACK_R=y
> diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
> index 83c3450839..894e7d1e12 100644
> --- a/configs/tinker-rk3288_defconfig
> +++ b/configs/tinker-rk3288_defconfig
> @@ -16,7 +16,6 @@ CONFIG_USE_PREBOOT=y
> CONFIG_SILENT_CONSOLE=y
> CONFIG_CONSOLE_MUX=y
> CONFIG_DEFAULT_FDT_FILE="rk3288-tinker.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> CONFIG_SPL_STACK_R=y
> CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
> diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig
> index 4925b14821..6215aa2d61 100644
> --- a/configs/tinker-s-rk3288_defconfig
> +++ b/configs/tinker-s-rk3288_defconfig
> @@ -15,7 +15,6 @@ CONFIG_DEBUG_UART=y
> CONFIG_USE_PREBOOT=y
> CONFIG_SILENT_CONSOLE=y
> CONFIG_DEFAULT_FDT_FILE="rk3288-tinker-s.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> CONFIG_SPL_STACK_R=y
> CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x300000
> diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig
> index 9497f0dd0f..6cb7f13e49 100644
> --- a/configs/vyasa-rk3288_defconfig
> +++ b/configs/vyasa-rk3288_defconfig
> @@ -14,7 +14,6 @@ CONFIG_DEBUG_UART=y
> CONFIG_USE_PREBOOT=y
> CONFIG_SILENT_CONSOLE=y
> CONFIG_DEFAULT_FDT_FILE="rk3288-vyasa.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> CONFIG_SPL_STACK_R=y
> CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v3 2/5] rockchip: rk3399: Enable DISPLAY_CPUINFO
@ 2020-01-06 9:23 ` Kever Yang
0 siblings, 0 replies; 21+ messages in thread
From: Kever Yang @ 2020-01-06 9:23 UTC (permalink / raw)
To: u-boot
On 2019/12/30 上午3:07, Jagan Teki wrote:
> RK3288, RK3399 are now support cpu-info, so enable
> DISPLAY_CPUINFO by default.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> configs/evb-rk3288_defconfig | 1 -
> configs/evb-rk3399_defconfig | 1 -
> configs/ficus-rk3399_defconfig | 1 -
> configs/firefly-rk3288_defconfig | 1 -
> configs/firefly-rk3399_defconfig | 1 -
> configs/khadas-edge-captain-rk3399_defconfig | 1 -
> configs/khadas-edge-rk3399_defconfig | 1 -
> configs/khadas-edge-v-rk3399_defconfig | 1 -
> configs/leez-rk3399_defconfig | 1 -
> configs/miqi-rk3288_defconfig | 1 -
> configs/nanopc-t4-rk3399_defconfig | 1 -
> configs/nanopi-m4-rk3399_defconfig | 1 -
> configs/nanopi-neo4-rk3399_defconfig | 1 -
> configs/orangepi-rk3399_defconfig | 1 -
> configs/phycore-rk3288_defconfig | 1 -
> configs/popmetal-rk3288_defconfig | 1 -
> configs/puma-rk3399_defconfig | 1 -
> configs/roc-pc-rk3399_defconfig | 1 -
> configs/rock-pi-4-rk3399_defconfig | 1 -
> configs/rock960-rk3399_defconfig | 1 -
> configs/rockpro64-rk3399_defconfig | 1 -
> configs/tinker-rk3288_defconfig | 1 -
> configs/tinker-s-rk3288_defconfig | 1 -
> configs/vyasa-rk3288_defconfig | 1 -
> 24 files changed, 24 deletions(-)
>
> diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig
> index 1fa4054f5d..59c909e10d 100644
> --- a/configs/evb-rk3288_defconfig
> +++ b/configs/evb-rk3288_defconfig
> @@ -14,7 +14,6 @@ CONFIG_DEBUG_UART=y
> CONFIG_USE_PREBOOT=y
> CONFIG_SILENT_CONSOLE=y
> CONFIG_DEFAULT_FDT_FILE="rk3288-evb-rk808.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> CONFIG_SPL_STACK_R=y
> CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
> diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
> index 8b8cdc5109..896a6050eb 100644
> --- a/configs/evb-rk3399_defconfig
> +++ b/configs/evb-rk3399_defconfig
> @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
> CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_DEBUG_UART=y
> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> CONFIG_SPL_STACK_R=y
> diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig
> index 6bb030acc1..5b49fe0b7b 100644
> --- a/configs/ficus-rk3399_defconfig
> +++ b/configs/ficus-rk3399_defconfig
> @@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
> CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_DEBUG_UART=y
> CONFIG_SPL_TEXT_BASE=0xff8c2000
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> CONFIG_SPL_STACK_R=y
> diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
> index 0c0a51c54f..41a6fc3edd 100644
> --- a/configs/firefly-rk3288_defconfig
> +++ b/configs/firefly-rk3288_defconfig
> @@ -14,7 +14,6 @@ CONFIG_DEBUG_UART=y
> CONFIG_USE_PREBOOT=y
> CONFIG_SILENT_CONSOLE=y
> CONFIG_DEFAULT_FDT_FILE="rk3288-firefly.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> CONFIG_SPL_STACK_R=y
> CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
> diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig
> index b84d7b9ff0..5d197f5f8a 100644
> --- a/configs/firefly-rk3399_defconfig
> +++ b/configs/firefly-rk3399_defconfig
> @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
> CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_DEBUG_UART=y
> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> CONFIG_SPL_STACK_R=y
> diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig
> index c408a1a59b..379e21e28d 100644
> --- a/configs/khadas-edge-captain-rk3399_defconfig
> +++ b/configs/khadas-edge-captain-rk3399_defconfig
> @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
> CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_DEBUG_UART=y
> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-captain.dtbi"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> CONFIG_SPL_STACK_R=y
> diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig
> index 796f94f8d7..9086018cd0 100644
> --- a/configs/khadas-edge-rk3399_defconfig
> +++ b/configs/khadas-edge-rk3399_defconfig
> @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
> CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_DEBUG_UART=y
> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> CONFIG_SPL_STACK_R=y
> diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig
> index e70e1ec2e6..261d75526b 100644
> --- a/configs/khadas-edge-v-rk3399_defconfig
> +++ b/configs/khadas-edge-v-rk3399_defconfig
> @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
> CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_DEBUG_UART=y
> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-v.dtbi"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> CONFIG_SPL_STACK_R=y
> diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig
> index 3758d79a1e..1d621fc9ce 100644
> --- a/configs/leez-rk3399_defconfig
> +++ b/configs/leez-rk3399_defconfig
> @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
> CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_DEBUG_UART=y
> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-leez-p710.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> CONFIG_SPL_STACK_R=y
> CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
> diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig
> index cec8e42c5e..25a808eb89 100644
> --- a/configs/miqi-rk3288_defconfig
> +++ b/configs/miqi-rk3288_defconfig
> @@ -15,7 +15,6 @@ CONFIG_SPL_TEXT_BASE=0xff704000
> CONFIG_USE_PREBOOT=y
> CONFIG_SILENT_CONSOLE=y
> CONFIG_DEFAULT_FDT_FILE="rk3288-miqi.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> CONFIG_SPL_STACK_R=y
> CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
> diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig
> index 504346eb99..bd6d60ff6c 100644
> --- a/configs/nanopc-t4-rk3399_defconfig
> +++ b/configs/nanopc-t4-rk3399_defconfig
> @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
> CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_DEBUG_UART=y
> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> CONFIG_SPL_STACK_R=y
> diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig
> index 24c8aa401b..74ede13c23 100644
> --- a/configs/nanopi-m4-rk3399_defconfig
> +++ b/configs/nanopi-m4-rk3399_defconfig
> @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
> CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_DEBUG_UART=y
> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> CONFIG_SPL_STACK_R=y
> diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig
> index 986739f16e..a44124aac0 100644
> --- a/configs/nanopi-neo4-rk3399_defconfig
> +++ b/configs/nanopi-neo4-rk3399_defconfig
> @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
> CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_DEBUG_UART=y
> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> CONFIG_SPL_STACK_R=y
> diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig
> index bed634b699..4c464de8a6 100644
> --- a/configs/orangepi-rk3399_defconfig
> +++ b/configs/orangepi-rk3399_defconfig
> @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
> CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_DEBUG_UART=y
> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> CONFIG_SPL_STACK_R=y
> diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig
> index 4c48d42299..2f10c7a3b3 100644
> --- a/configs/phycore-rk3288_defconfig
> +++ b/configs/phycore-rk3288_defconfig
> @@ -16,7 +16,6 @@ CONFIG_USE_PREBOOT=y
> CONFIG_SILENT_CONSOLE=y
> CONFIG_CONSOLE_MUX=y
> CONFIG_DEFAULT_FDT_FILE="rk3288-phycore-rdk.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> CONFIG_SPL_STACK_R=y
> CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
> diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig
> index f732f6b209..512efee1a9 100644
> --- a/configs/popmetal-rk3288_defconfig
> +++ b/configs/popmetal-rk3288_defconfig
> @@ -16,7 +16,6 @@ CONFIG_USE_PREBOOT=y
> CONFIG_SILENT_CONSOLE=y
> CONFIG_CONSOLE_MUX=y
> CONFIG_DEFAULT_FDT_FILE="rk3288-popmetal.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> CONFIG_SPL_STACK_R=y
> CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
> diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig
> index 55255bf6af..30c7ab2751 100644
> --- a/configs/puma-rk3399_defconfig
> +++ b/configs/puma-rk3399_defconfig
> @@ -16,7 +16,6 @@ CONFIG_SPL_TEXT_BASE=0xff8c2000
> CONFIG_SPL_FIT_GENERATOR="board/theobroma-systems/puma_rk3399/fit_spl_atf.sh"
> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb"
> CONFIG_MISC_INIT_R=y
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> CONFIG_SPL_STACK_R=y
> diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig
> index 305baa712c..bf83b25dbc 100644
> --- a/configs/roc-pc-rk3399_defconfig
> +++ b/configs/roc-pc-rk3399_defconfig
> @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
> CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_DEBUG_UART=y
> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> CONFIG_SPL_STACK_R=y
> diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig
> index 2c01bf1f87..4429f58fde 100644
> --- a/configs/rock-pi-4-rk3399_defconfig
> +++ b/configs/rock-pi-4-rk3399_defconfig
> @@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_DEBUG_UART=y
> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4.dtb"
> CONFIG_MISC_INIT_R=y
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> CONFIG_SPL_STACK_R=y
> diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig
> index ec32e6cf05..7b6dc3f83c 100644
> --- a/configs/rock960-rk3399_defconfig
> +++ b/configs/rock960-rk3399_defconfig
> @@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000
> CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_DEBUG_UART=y
> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> CONFIG_SPL_STACK_R=y
> diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig
> index 49e27c91cb..955b717131 100644
> --- a/configs/rockpro64-rk3399_defconfig
> +++ b/configs/rockpro64-rk3399_defconfig
> @@ -10,7 +10,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_DEBUG_UART=y
> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb"
> CONFIG_MISC_INIT_R=y
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> CONFIG_SPL_STACK_R=y
> diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
> index 83c3450839..894e7d1e12 100644
> --- a/configs/tinker-rk3288_defconfig
> +++ b/configs/tinker-rk3288_defconfig
> @@ -16,7 +16,6 @@ CONFIG_USE_PREBOOT=y
> CONFIG_SILENT_CONSOLE=y
> CONFIG_CONSOLE_MUX=y
> CONFIG_DEFAULT_FDT_FILE="rk3288-tinker.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> CONFIG_SPL_STACK_R=y
> CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
> diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig
> index 4925b14821..6215aa2d61 100644
> --- a/configs/tinker-s-rk3288_defconfig
> +++ b/configs/tinker-s-rk3288_defconfig
> @@ -15,7 +15,6 @@ CONFIG_DEBUG_UART=y
> CONFIG_USE_PREBOOT=y
> CONFIG_SILENT_CONSOLE=y
> CONFIG_DEFAULT_FDT_FILE="rk3288-tinker-s.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> CONFIG_SPL_STACK_R=y
> CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x300000
> diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig
> index 9497f0dd0f..6cb7f13e49 100644
> --- a/configs/vyasa-rk3288_defconfig
> +++ b/configs/vyasa-rk3288_defconfig
> @@ -14,7 +14,6 @@ CONFIG_DEBUG_UART=y
> CONFIG_USE_PREBOOT=y
> CONFIG_SILENT_CONSOLE=y
> CONFIG_DEFAULT_FDT_FILE="rk3288-vyasa.dtb"
> -# CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> CONFIG_SPL_STACK_R=y
> CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 3/5] arm: rockchip: Add common cru.h
2019-12-29 19:07 ` Jagan Teki
@ 2020-01-06 9:24 ` Kever Yang
-1 siblings, 0 replies; 21+ messages in thread
From: Kever Yang @ 2020-01-06 9:24 UTC (permalink / raw)
To: Jagan Teki, Simon Glass, Philipp Tomsich
Cc: u-boot, linux-amarula, Akash Gajjar, linux-rockchip
On 2019/12/30 上午3:07, Jagan Teki wrote:
> Few of the rockchip family SoC atleast rk3288,
> rk3399 are sharing some cru register bits so
> adding common code between these SoC families
> would require to include both cru include files
> that indeed resulting function declarations error.
>
> So, create a common cru include as cru.h then
> include the rk3399 arch cru include file and move
> the common cru register bit definitions into it.
>
> The rest of rockchip cru files will add it in future.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> arch/arm/include/asm/arch-rockchip/clock.h | 4 +-
> arch/arm/include/asm/arch-rockchip/cru.h | 16 +++++++
> .../include/asm/arch-rockchip/cru_rk3288.h | 6 +--
> .../include/asm/arch-rockchip/cru_rk3399.h | 10 ++---
> arch/arm/mach-rockchip/rk3288/clk_rk3288.c | 2 +-
> arch/arm/mach-rockchip/rk3288/rk3288.c | 4 +-
> arch/arm/mach-rockchip/rk3399/clk_rk3399.c | 2 +-
> arch/arm/mach-rockchip/rk3399/rk3399.c | 2 +-
> drivers/clk/rockchip/clk_rk3288.c | 42 +++++++++----------
> drivers/clk/rockchip/clk_rk3399.c | 36 ++++++++--------
> drivers/ram/rockchip/sdram_rk3288.c | 10 ++---
> drivers/ram/rockchip/sdram_rk3399.c | 10 ++---
> drivers/video/rockchip/rk3288_mipi.c | 2 +-
> drivers/video/rockchip/rk3399_mipi.c | 2 +-
> drivers/video/rockchip/rk_mipi.c | 2 +-
> 15 files changed, 83 insertions(+), 67 deletions(-)
> create mode 100644 arch/arm/include/asm/arch-rockchip/cru.h
>
> diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
> index 8f7fc86a9e..22de0aef8d 100644
> --- a/arch/arm/include/asm/arch-rockchip/clock.h
> +++ b/arch/arm/include/asm/arch-rockchip/clock.h
> @@ -153,10 +153,10 @@ void *rockchip_get_cru(void);
> */
> void *rockchip_get_pmucru(void);
>
> -struct rk3288_cru;
> +struct rockchip_cru;
> struct rk3288_grf;
>
> -void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf);
> +void rk3288_clk_configure_cpu(struct rockchip_cru *cru, struct rk3288_grf *grf);
>
> int rockchip_get_clk(struct udevice **devp);
>
> diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h
> new file mode 100644
> index 0000000000..5ed3fbfd07
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rockchip/cru.h
> @@ -0,0 +1,16 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * (C) Copyright 2019 Amarula Solutions.
> + * Author: Jagan Teki <jagan@amarulasolutions.com>
> + */
> +
> +#ifndef _ROCKCHIP_CLOCK_H
> +#define _ROCKCHIP_CLOCK_H
> +
> +#if defined(CONFIG_ROCKCHIP_RK3288)
> +# include <asm/arch-rockchip/cru_rk3288.h>
> +#elif defined(CONFIG_ROCKCHIP_RK3399)
> +# include <asm/arch-rockchip/cru_rk3399.h>
> +#endif
> +
> +#endif /* _ROCKCHIP_CLOCK_H */
> diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
> index e891f20b37..7aa6efe46c 100644
> --- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
> +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
> @@ -27,11 +27,11 @@
> /* Private data for the clock driver - used by rockchip_get_cru() */
> struct rk3288_clk_priv {
> struct rk3288_grf *grf;
> - struct rk3288_cru *cru;
> + struct rockchip_cru *cru;
> ulong rate;
> };
>
> -struct rk3288_cru {
> +struct rockchip_cru {
> struct rk3288_pll {
> u32 con0;
> u32 con1;
> @@ -58,7 +58,7 @@ struct rk3288_cru {
> u32 cru_sdio1_con[2];
> u32 cru_emmc_con[2];
> };
> -check_member(rk3288_cru, cru_emmc_con[1], 0x021c);
> +check_member(rockchip_cru, cru_emmc_con[1], 0x021c);
>
> /* CRU_CLKSEL11_CON */
> enum {
> diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
> index 15eeb9c440..33ce190434 100644
> --- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
> +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
> @@ -10,7 +10,7 @@
>
> /* Private data for the clock driver - used by rockchip_get_cru() */
> struct rk3399_clk_priv {
> - struct rk3399_cru *cru;
> + struct rockchip_cru *cru;
> };
>
> struct rk3399_pmuclk_priv {
> @@ -33,7 +33,7 @@ struct rk3399_pmucru {
> };
> check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134);
>
> -struct rk3399_cru {
> +struct rockchip_cru {
> u32 apll_l_con[6];
> u32 reserved[2];
> u32 apll_b_con[6];
> @@ -65,7 +65,7 @@ struct rk3399_cru {
> u32 sdio0_con[2];
> u32 sdio1_con[2];
> };
> -check_member(rk3399_cru, sdio1_con[1], 0x594);
> +check_member(rockchip_cru, sdio1_con[1], 0x594);
> #define MHz 1000000
> #define KHz 1000
> #define OSC_HZ (24*MHz)
> @@ -107,9 +107,9 @@ enum apll_b_frequencies {
> APLL_B_600_MHZ,
> };
>
> -void rk3399_configure_cpu_l(struct rk3399_cru *cru,
> +void rk3399_configure_cpu_l(struct rockchip_cru *cru,
> enum apll_l_frequencies apll_l_freq);
> -void rk3399_configure_cpu_b(struct rk3399_cru *cru,
> +void rk3399_configure_cpu_b(struct rockchip_cru *cru,
> enum apll_b_frequencies apll_b_freq);
>
> #endif /* __ASM_ARCH_CRU_RK3399_H_ */
> diff --git a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c
> index e64ee86f08..1730f12443 100644
> --- a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c
> +++ b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c
> @@ -8,7 +8,7 @@
> #include <dm.h>
> #include <syscon.h>
> #include <asm/arch-rockchip/clock.h>
> -#include <asm/arch-rockchip/cru_rk3288.h>
> +#include <asm/arch-rockchip/cru.h>
>
> int rockchip_get_clk(struct udevice **devp)
> {
> diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c
> index 9572f7ea9c..47ee5d440b 100644
> --- a/arch/arm/mach-rockchip/rk3288/rk3288.c
> +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c
> @@ -11,7 +11,7 @@
> #include <asm/io.h>
> #include <asm/arch-rockchip/bootrom.h>
> #include <asm/arch-rockchip/clock.h>
> -#include <asm/arch-rockchip/cru_rk3288.h>
> +#include <asm/arch-rockchip/cru.h>
> #include <asm/arch-rockchip/hardware.h>
> #include <asm/arch-rockchip/grf_rk3288.h>
> #include <asm/arch-rockchip/pmu_rk3288.h>
> @@ -104,7 +104,7 @@ void board_debug_uart_init(void)
>
> static void rk3288_detect_reset_reason(void)
> {
> - struct rk3288_cru *cru = rockchip_get_cru();
> + struct rockchip_cru *cru = rockchip_get_cru();
> const char *reason;
>
> if (IS_ERR(cru))
> diff --git a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c
> index f0411c0a21..a80a46f1db 100644
> --- a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c
> +++ b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c
> @@ -8,7 +8,7 @@
> #include <dm.h>
> #include <syscon.h>
> #include <asm/arch-rockchip/clock.h>
> -#include <asm/arch-rockchip/cru_rk3399.h>
> +#include <asm/arch-rockchip/cru.h>
>
> static int rockchip_get_cruclk(struct udevice **devp)
> {
> diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c
> index 863024d071..dafa142824 100644
> --- a/arch/arm/mach-rockchip/rk3399/rk3399.c
> +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
> @@ -240,7 +240,7 @@ static void rk3399_force_power_on_reset(void)
> void spl_board_init(void)
> {
> #if defined(SPL_GPIO_SUPPORT)
> - struct rk3399_cru *cru = rockchip_get_cru();
> + struct rockchip_cru *cru = rockchip_get_cru();
>
> /*
> * The RK3399 resets only 'almost all logic' (see also in the TRM
> diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
> index 85d1b67e43..cc1c1e81e9 100644
> --- a/drivers/clk/rockchip/clk_rk3288.c
> +++ b/drivers/clk/rockchip/clk_rk3288.c
> @@ -14,7 +14,7 @@
> #include <syscon.h>
> #include <asm/io.h>
> #include <asm/arch-rockchip/clock.h>
> -#include <asm/arch-rockchip/cru_rk3288.h>
> +#include <asm/arch-rockchip/cru.h>
> #include <asm/arch-rockchip/grf_rk3288.h>
> #include <asm/arch-rockchip/hardware.h>
> #include <dt-bindings/clock/rk3288-cru.h>
> @@ -141,7 +141,7 @@ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
> static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
> static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
>
> -static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
> +static int rkclk_set_pll(struct rockchip_cru *cru, enum rk_clk_id clk_id,
> const struct pll_div *div)
> {
> int pll_id = rk_pll_id(clk_id);
> @@ -172,7 +172,7 @@ static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
> return 0;
> }
>
> -static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,
> +static int rkclk_configure_ddr(struct rockchip_cru *cru, struct rk3288_grf *grf,
> unsigned int hz)
> {
> static const struct pll_div dpll_cfg[] = {
> @@ -295,7 +295,7 @@ static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
> return 0;
> }
>
> -static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq)
> +static int rockchip_mac_set_clk(struct rockchip_cru *cru, uint freq)
> {
> ulong ret;
>
> @@ -333,7 +333,7 @@ static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq)
> return ret;
> }
>
> -static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
> +static int rockchip_vop_set_clk(struct rockchip_cru *cru, struct rk3288_grf *grf,
> int periph, unsigned int rate_hz)
> {
> struct pll_div npll_config = {0};
> @@ -384,7 +384,7 @@ static u32 rockchip_clk_gcd(u32 a, u32 b)
> return a;
> }
>
> -static ulong rockchip_i2s_get_clk(struct rk3288_cru *cru, uint gclk_rate)
> +static ulong rockchip_i2s_get_clk(struct rockchip_cru *cru, uint gclk_rate)
> {
> unsigned long long rate;
> uint val;
> @@ -400,7 +400,7 @@ static ulong rockchip_i2s_get_clk(struct rk3288_cru *cru, uint gclk_rate)
> return (ulong)rate;
> }
>
> -static ulong rockchip_i2s_set_clk(struct rk3288_cru *cru, uint gclk_rate,
> +static ulong rockchip_i2s_set_clk(struct rockchip_cru *cru, uint gclk_rate,
> uint freq)
> {
> int n, d;
> @@ -418,7 +418,7 @@ static ulong rockchip_i2s_set_clk(struct rk3288_cru *cru, uint gclk_rate,
> }
> #endif /* CONFIG_SPL_BUILD */
>
> -static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
> +static void rkclk_init(struct rockchip_cru *cru, struct rk3288_grf *grf)
> {
> u32 aclk_div;
> u32 hclk_div;
> @@ -492,7 +492,7 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
> CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
> }
>
> -void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
> +void rk3288_clk_configure_cpu(struct rockchip_cru *cru, struct rk3288_grf *grf)
> {
> /* pll enter slow-mode */
> rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
> @@ -534,7 +534,7 @@ void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
> }
>
> /* Get pll rate by id */
> -static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
> +static uint32_t rkclk_pll_get_rate(struct rockchip_cru *cru,
> enum rk_clk_id clk_id)
> {
> uint32_t nr, no, nf;
> @@ -567,7 +567,7 @@ static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
> }
> }
>
> -static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
> +static ulong rockchip_mmc_get_clk(struct rockchip_cru *cru, uint gclk_rate,
> int periph)
> {
> uint src_rate;
> @@ -601,7 +601,7 @@ static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
> return DIV_TO_RATE(src_rate, div);
> }
>
> -static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
> +static ulong rockchip_mmc_set_clk(struct rockchip_cru *cru, uint gclk_rate,
> int periph, uint freq)
> {
> int src_clk_div;
> @@ -651,7 +651,7 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
> return rockchip_mmc_get_clk(cru, gclk_rate, periph);
> }
>
> -static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
> +static ulong rockchip_spi_get_clk(struct rockchip_cru *cru, uint gclk_rate,
> int periph)
> {
> uint div, mux;
> @@ -681,7 +681,7 @@ static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
> return DIV_TO_RATE(gclk_rate, div);
> }
>
> -static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
> +static ulong rockchip_spi_set_clk(struct rockchip_cru *cru, uint gclk_rate,
> int periph, uint freq)
> {
> int src_clk_div;
> @@ -715,7 +715,7 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
> return rockchip_spi_get_clk(cru, gclk_rate, periph);
> }
>
> -static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru)
> +static ulong rockchip_saradc_get_clk(struct rockchip_cru *cru)
> {
> u32 div, val;
>
> @@ -726,7 +726,7 @@ static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru)
> return DIV_TO_RATE(OSC_HZ, div);
> }
>
> -static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz)
> +static ulong rockchip_saradc_set_clk(struct rockchip_cru *cru, uint hz)
> {
> int src_clk_div;
>
> @@ -785,7 +785,7 @@ static ulong rk3288_clk_get_rate(struct clk *clk)
> static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
> {
> struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
> - struct rk3288_cru *cru = priv->cru;
> + struct rockchip_cru *cru = priv->cru;
> ulong new_rate, gclk_rate;
>
> gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
> @@ -892,7 +892,7 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
> static int __maybe_unused rk3288_gmac_set_parent(struct clk *clk, struct clk *parent)
> {
> struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
> - struct rk3288_cru *cru = priv->cru;
> + struct rockchip_cru *cru = priv->cru;
> const char *clock_output_name;
> int ret;
>
> @@ -1008,15 +1008,15 @@ static int rk3288_clk_bind(struct udevice *dev)
> debug("Warning: No sysreset driver: ret=%d\n", ret);
> } else {
> priv = malloc(sizeof(struct sysreset_reg));
> - priv->glb_srst_fst_value = offsetof(struct rk3288_cru,
> + priv->glb_srst_fst_value = offsetof(struct rockchip_cru,
> cru_glb_srst_fst_value);
> - priv->glb_srst_snd_value = offsetof(struct rk3288_cru,
> + priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
> cru_glb_srst_snd_value);
> sys_child->priv = priv;
> }
>
> #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
> - ret = offsetof(struct rk3288_cru, cru_softrst_con[0]);
> + ret = offsetof(struct rockchip_cru, cru_softrst_con[0]);
> ret = rockchip_reset_bind(dev, ret, 12);
> if (ret)
> debug("Warning: software reset driver bind faile\n");
> diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
> index 9020a9f202..37fc142a7a 100644
> --- a/drivers/clk/rockchip/clk_rk3399.c
> +++ b/drivers/clk/rockchip/clk_rk3399.c
> @@ -14,7 +14,7 @@
> #include <bitfield.h>
> #include <asm/io.h>
> #include <asm/arch-rockchip/clock.h>
> -#include <asm/arch-rockchip/cru_rk3399.h>
> +#include <asm/arch-rockchip/cru.h>
> #include <asm/arch-rockchip/hardware.h>
> #include <dm/lists.h>
> #include <dt-bindings/clock/rk3399-cru.h>
> @@ -418,7 +418,7 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div)
> return 0;
> }
>
> -void rk3399_configure_cpu_l(struct rk3399_cru *cru,
> +void rk3399_configure_cpu_l(struct rockchip_cru *cru,
> enum apll_l_frequencies apll_l_freq)
> {
> u32 aclkm_div;
> @@ -453,7 +453,7 @@ void rk3399_configure_cpu_l(struct rk3399_cru *cru,
> atclk_div << ATCLK_CORE_L_DIV_SHIFT);
> }
>
> -void rk3399_configure_cpu_b(struct rk3399_cru *cru,
> +void rk3399_configure_cpu_b(struct rockchip_cru *cru,
> enum apll_b_frequencies apll_b_freq)
> {
> u32 aclkm_div;
> @@ -505,7 +505,7 @@ void rk3399_configure_cpu_b(struct rk3399_cru *cru,
> #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \
> ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT)
>
> -static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id)
> +static ulong rk3399_i2c_get_clk(struct rockchip_cru *cru, ulong clk_id)
> {
> u32 div, con;
>
> @@ -542,7 +542,7 @@ static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id)
> return DIV_TO_RATE(GPLL_HZ, div);
> }
>
> -static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
> +static ulong rk3399_i2c_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
> {
> int src_clk_div;
>
> @@ -619,7 +619,7 @@ static const struct spi_clkreg spi_clkregs[] = {
> .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, },
> };
>
> -static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id)
> +static ulong rk3399_spi_get_clk(struct rockchip_cru *cru, ulong clk_id)
> {
> const struct spi_clkreg *spiclk = NULL;
> u32 div, val;
> @@ -641,7 +641,7 @@ static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id)
> return DIV_TO_RATE(GPLL_HZ, div);
> }
>
> -static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
> +static ulong rk3399_spi_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
> {
> const struct spi_clkreg *spiclk = NULL;
> int src_clk_div;
> @@ -668,7 +668,7 @@ static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
> return rk3399_spi_get_clk(cru, clk_id);
> }
>
> -static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
> +static ulong rk3399_vop_set_clk(struct rockchip_cru *cru, ulong clk_id, u32 hz)
> {
> struct pll_div vpll_config = {0};
> int aclk_vop = 198 * MHz;
> @@ -712,7 +712,7 @@ static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
> return hz;
> }
>
> -static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id)
> +static ulong rk3399_mmc_get_clk(struct rockchip_cru *cru, uint clk_id)
> {
> u32 div, con;
>
> @@ -739,7 +739,7 @@ static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id)
> return DIV_TO_RATE(GPLL_HZ, div);
> }
>
> -static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
> +static ulong rk3399_mmc_set_clk(struct rockchip_cru *cru,
> ulong clk_id, ulong set_rate)
> {
> int src_clk_div;
> @@ -792,7 +792,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
> return rk3399_mmc_get_clk(cru, clk_id);
> }
>
> -static ulong rk3399_gmac_set_clk(struct rk3399_cru *cru, ulong rate)
> +static ulong rk3399_gmac_set_clk(struct rockchip_cru *cru, ulong rate)
> {
> ulong ret;
>
> @@ -817,7 +817,7 @@ static ulong rk3399_gmac_set_clk(struct rk3399_cru *cru, ulong rate)
> }
>
> #define PMUSGRF_DDR_RGN_CON16 0xff330040
> -static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
> +static ulong rk3399_ddr_set_clk(struct rockchip_cru *cru,
> ulong set_rate)
> {
> struct pll_div dpll_cfg;
> @@ -863,7 +863,7 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
> return set_rate;
> }
>
> -static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru)
> +static ulong rk3399_saradc_get_clk(struct rockchip_cru *cru)
> {
> u32 div, val;
>
> @@ -874,7 +874,7 @@ static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru)
> return DIV_TO_RATE(OSC_HZ, div);
> }
>
> -static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz)
> +static ulong rk3399_saradc_set_clk(struct rockchip_cru *cru, uint hz)
> {
> int src_clk_div;
>
> @@ -1071,7 +1071,7 @@ static struct clk_ops rk3399_clk_ops = {
> };
>
> #ifdef CONFIG_SPL_BUILD
> -static void rkclk_init(struct rk3399_cru *cru)
> +static void rkclk_init(struct rockchip_cru *cru)
> {
> u32 aclk_div;
> u32 hclk_div;
> @@ -1188,15 +1188,15 @@ static int rk3399_clk_bind(struct udevice *dev)
> debug("Warning: No sysreset driver: ret=%d\n", ret);
> } else {
> priv = malloc(sizeof(struct sysreset_reg));
> - priv->glb_srst_fst_value = offsetof(struct rk3399_cru,
> + priv->glb_srst_fst_value = offsetof(struct rockchip_cru,
> glb_srst_fst_value);
> - priv->glb_srst_snd_value = offsetof(struct rk3399_cru,
> + priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
> glb_srst_snd_value);
> sys_child->priv = priv;
> }
>
> #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
> - ret = offsetof(struct rk3399_cru, softrst_con[0]);
> + ret = offsetof(struct rockchip_cru, softrst_con[0]);
> ret = rockchip_reset_bind(dev, ret, 21);
> if (ret)
> debug("Warning: software reset driver bind faile\n");
> diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c
> index 690751d074..fd5b204e1f 100644
> --- a/drivers/ram/rockchip/sdram_rk3288.c
> +++ b/drivers/ram/rockchip/sdram_rk3288.c
> @@ -16,7 +16,7 @@
> #include <syscon.h>
> #include <asm/io.h>
> #include <asm/arch-rockchip/clock.h>
> -#include <asm/arch-rockchip/cru_rk3288.h>
> +#include <asm/arch-rockchip/cru.h>
> #include <asm/arch-rockchip/ddr_rk3288.h>
> #include <asm/arch-rockchip/grf_rk3288.h>
> #include <asm/arch-rockchip/pmu_rk3288.h>
> @@ -36,7 +36,7 @@ struct dram_info {
> struct chan_info chan[2];
> struct ram_info info;
> struct clk ddr_clk;
> - struct rk3288_cru *cru;
> + struct rockchip_cru *cru;
> struct rk3288_grf *grf;
> struct rk3288_sgrf *sgrf;
> struct rk3288_pmu *pmu;
> @@ -92,7 +92,7 @@ static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
> }
> }
>
> -static void ddr_reset(struct rk3288_cru *cru, u32 ch, u32 ctl, u32 phy)
> +static void ddr_reset(struct rockchip_cru *cru, u32 ch, u32 ctl, u32 phy)
> {
> u32 phy_ctl_srstn_shift = 4 + 5 * ch;
> u32 ctl_psrstn_shift = 3 + 5 * ch;
> @@ -109,7 +109,7 @@ static void ddr_reset(struct rk3288_cru *cru, u32 ch, u32 ctl, u32 phy)
> phy << phy_srstn_shift);
> }
>
> -static void ddr_phy_ctl_reset(struct rk3288_cru *cru, u32 ch, u32 n)
> +static void ddr_phy_ctl_reset(struct rockchip_cru *cru, u32 ch, u32 n)
> {
> u32 phy_ctl_srstn_shift = 4 + 5 * ch;
>
> @@ -117,7 +117,7 @@ static void ddr_phy_ctl_reset(struct rk3288_cru *cru, u32 ch, u32 n)
> 1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift);
> }
>
> -static void phy_pctrl_reset(struct rk3288_cru *cru,
> +static void phy_pctrl_reset(struct rockchip_cru *cru,
> struct rk3288_ddr_publ *publ,
> int channel)
> {
> diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
> index 7b2bba03fe..08bf0393a7 100644
> --- a/drivers/ram/rockchip/sdram_rk3399.c
> +++ b/drivers/ram/rockchip/sdram_rk3399.c
> @@ -14,7 +14,7 @@
> #include <syscon.h>
> #include <asm/io.h>
> #include <asm/arch-rockchip/clock.h>
> -#include <asm/arch-rockchip/cru_rk3399.h>
> +#include <asm/arch-rockchip/cru.h>
> #include <asm/arch-rockchip/grf_rk3399.h>
> #include <asm/arch-rockchip/pmu_rk3399.h>
> #include <asm/arch-rockchip/hardware.h>
> @@ -66,7 +66,7 @@ struct dram_info {
> u32 pwrup_srefresh_exit[2];
> struct chan_info chan[2];
> struct clk ddr_clk;
> - struct rk3399_cru *cru;
> + struct rockchip_cru *cru;
> struct rk3399_grf_regs *grf;
> struct rk3399_pmu_regs *pmu;
> struct rk3399_pmucru *pmucru;
> @@ -228,7 +228,7 @@ static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
> return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc1_con0;
> }
>
> -static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl,
> +static void rkclk_ddr_reset(struct rockchip_cru *cru, u32 channel, u32 ctl,
> u32 phy)
> {
> channel &= 0x1;
> @@ -239,7 +239,7 @@ static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl,
> &cru->softrst_con[4]);
> }
>
> -static void phy_pctrl_reset(struct rk3399_cru *cru, u32 channel)
> +static void phy_pctrl_reset(struct rockchip_cru *cru, u32 channel)
> {
> rkclk_ddr_reset(cru, channel, 1, 1);
> udelay(10);
> @@ -2945,7 +2945,7 @@ static int sdram_init(struct dram_info *dram,
> for (channel = 0; channel < 2; channel++) {
> const struct chan_info *chan =
> &dram->chan[channel];
> - struct rk3399_cru *cru = dram->cru;
> + struct rockchip_cru *cru = dram->cru;
> struct rk3399_ddr_publ_regs *publ = chan->publ;
>
> phy_pctrl_reset(cru, channel);
> diff --git a/drivers/video/rockchip/rk3288_mipi.c b/drivers/video/rockchip/rk3288_mipi.c
> index 7c4a4cc53b..65891ce45c 100644
> --- a/drivers/video/rockchip/rk3288_mipi.c
> +++ b/drivers/video/rockchip/rk3288_mipi.c
> @@ -18,7 +18,7 @@
> #include <dm/uclass-internal.h>
> #include <linux/kernel.h>
> #include <asm/arch-rockchip/clock.h>
> -#include <asm/arch-rockchip/cru_rk3288.h>
> +#include <asm/arch-rockchip/cru.h>
> #include <asm/arch-rockchip/grf_rk3288.h>
> #include <asm/arch-rockchip/hardware.h>
> #include <asm/arch-rockchip/rockchip_mipi_dsi.h>
> diff --git a/drivers/video/rockchip/rk3399_mipi.c b/drivers/video/rockchip/rk3399_mipi.c
> index a93b73400b..a5b7ba69a8 100644
> --- a/drivers/video/rockchip/rk3399_mipi.c
> +++ b/drivers/video/rockchip/rk3399_mipi.c
> @@ -18,7 +18,7 @@
> #include <dm/uclass-internal.h>
> #include <linux/kernel.h>
> #include <asm/arch-rockchip/clock.h>
> -#include <asm/arch-rockchip/cru_rk3399.h>
> +#include <asm/arch-rockchip/cru.h>
> #include <asm/arch-rockchip/grf_rk3399.h>
> #include <asm/arch-rockchip/hardware.h>
> #include <asm/arch-rockchip/rockchip_mipi_dsi.h>
> diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c
> index bcd039b7bc..f9280e8607 100644
> --- a/drivers/video/rockchip/rk_mipi.c
> +++ b/drivers/video/rockchip/rk_mipi.c
> @@ -18,7 +18,7 @@
> #include <dm/uclass-internal.h>
> #include <linux/kernel.h>
> #include <asm/arch-rockchip/clock.h>
> -#include <asm/arch-rockchip/cru_rk3399.h>
> +#include <asm/arch-rockchip/cru.h>
> #include <asm/arch-rockchip/grf_rk3399.h>
> #include <asm/arch-rockchip/rockchip_mipi_dsi.h>
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v3 3/5] arm: rockchip: Add common cru.h
@ 2020-01-06 9:24 ` Kever Yang
0 siblings, 0 replies; 21+ messages in thread
From: Kever Yang @ 2020-01-06 9:24 UTC (permalink / raw)
To: u-boot
On 2019/12/30 上午3:07, Jagan Teki wrote:
> Few of the rockchip family SoC atleast rk3288,
> rk3399 are sharing some cru register bits so
> adding common code between these SoC families
> would require to include both cru include files
> that indeed resulting function declarations error.
>
> So, create a common cru include as cru.h then
> include the rk3399 arch cru include file and move
> the common cru register bit definitions into it.
>
> The rest of rockchip cru files will add it in future.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> arch/arm/include/asm/arch-rockchip/clock.h | 4 +-
> arch/arm/include/asm/arch-rockchip/cru.h | 16 +++++++
> .../include/asm/arch-rockchip/cru_rk3288.h | 6 +--
> .../include/asm/arch-rockchip/cru_rk3399.h | 10 ++---
> arch/arm/mach-rockchip/rk3288/clk_rk3288.c | 2 +-
> arch/arm/mach-rockchip/rk3288/rk3288.c | 4 +-
> arch/arm/mach-rockchip/rk3399/clk_rk3399.c | 2 +-
> arch/arm/mach-rockchip/rk3399/rk3399.c | 2 +-
> drivers/clk/rockchip/clk_rk3288.c | 42 +++++++++----------
> drivers/clk/rockchip/clk_rk3399.c | 36 ++++++++--------
> drivers/ram/rockchip/sdram_rk3288.c | 10 ++---
> drivers/ram/rockchip/sdram_rk3399.c | 10 ++---
> drivers/video/rockchip/rk3288_mipi.c | 2 +-
> drivers/video/rockchip/rk3399_mipi.c | 2 +-
> drivers/video/rockchip/rk_mipi.c | 2 +-
> 15 files changed, 83 insertions(+), 67 deletions(-)
> create mode 100644 arch/arm/include/asm/arch-rockchip/cru.h
>
> diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
> index 8f7fc86a9e..22de0aef8d 100644
> --- a/arch/arm/include/asm/arch-rockchip/clock.h
> +++ b/arch/arm/include/asm/arch-rockchip/clock.h
> @@ -153,10 +153,10 @@ void *rockchip_get_cru(void);
> */
> void *rockchip_get_pmucru(void);
>
> -struct rk3288_cru;
> +struct rockchip_cru;
> struct rk3288_grf;
>
> -void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf);
> +void rk3288_clk_configure_cpu(struct rockchip_cru *cru, struct rk3288_grf *grf);
>
> int rockchip_get_clk(struct udevice **devp);
>
> diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h
> new file mode 100644
> index 0000000000..5ed3fbfd07
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rockchip/cru.h
> @@ -0,0 +1,16 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * (C) Copyright 2019 Amarula Solutions.
> + * Author: Jagan Teki <jagan@amarulasolutions.com>
> + */
> +
> +#ifndef _ROCKCHIP_CLOCK_H
> +#define _ROCKCHIP_CLOCK_H
> +
> +#if defined(CONFIG_ROCKCHIP_RK3288)
> +# include <asm/arch-rockchip/cru_rk3288.h>
> +#elif defined(CONFIG_ROCKCHIP_RK3399)
> +# include <asm/arch-rockchip/cru_rk3399.h>
> +#endif
> +
> +#endif /* _ROCKCHIP_CLOCK_H */
> diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
> index e891f20b37..7aa6efe46c 100644
> --- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
> +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
> @@ -27,11 +27,11 @@
> /* Private data for the clock driver - used by rockchip_get_cru() */
> struct rk3288_clk_priv {
> struct rk3288_grf *grf;
> - struct rk3288_cru *cru;
> + struct rockchip_cru *cru;
> ulong rate;
> };
>
> -struct rk3288_cru {
> +struct rockchip_cru {
> struct rk3288_pll {
> u32 con0;
> u32 con1;
> @@ -58,7 +58,7 @@ struct rk3288_cru {
> u32 cru_sdio1_con[2];
> u32 cru_emmc_con[2];
> };
> -check_member(rk3288_cru, cru_emmc_con[1], 0x021c);
> +check_member(rockchip_cru, cru_emmc_con[1], 0x021c);
>
> /* CRU_CLKSEL11_CON */
> enum {
> diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
> index 15eeb9c440..33ce190434 100644
> --- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
> +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
> @@ -10,7 +10,7 @@
>
> /* Private data for the clock driver - used by rockchip_get_cru() */
> struct rk3399_clk_priv {
> - struct rk3399_cru *cru;
> + struct rockchip_cru *cru;
> };
>
> struct rk3399_pmuclk_priv {
> @@ -33,7 +33,7 @@ struct rk3399_pmucru {
> };
> check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134);
>
> -struct rk3399_cru {
> +struct rockchip_cru {
> u32 apll_l_con[6];
> u32 reserved[2];
> u32 apll_b_con[6];
> @@ -65,7 +65,7 @@ struct rk3399_cru {
> u32 sdio0_con[2];
> u32 sdio1_con[2];
> };
> -check_member(rk3399_cru, sdio1_con[1], 0x594);
> +check_member(rockchip_cru, sdio1_con[1], 0x594);
> #define MHz 1000000
> #define KHz 1000
> #define OSC_HZ (24*MHz)
> @@ -107,9 +107,9 @@ enum apll_b_frequencies {
> APLL_B_600_MHZ,
> };
>
> -void rk3399_configure_cpu_l(struct rk3399_cru *cru,
> +void rk3399_configure_cpu_l(struct rockchip_cru *cru,
> enum apll_l_frequencies apll_l_freq);
> -void rk3399_configure_cpu_b(struct rk3399_cru *cru,
> +void rk3399_configure_cpu_b(struct rockchip_cru *cru,
> enum apll_b_frequencies apll_b_freq);
>
> #endif /* __ASM_ARCH_CRU_RK3399_H_ */
> diff --git a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c
> index e64ee86f08..1730f12443 100644
> --- a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c
> +++ b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c
> @@ -8,7 +8,7 @@
> #include <dm.h>
> #include <syscon.h>
> #include <asm/arch-rockchip/clock.h>
> -#include <asm/arch-rockchip/cru_rk3288.h>
> +#include <asm/arch-rockchip/cru.h>
>
> int rockchip_get_clk(struct udevice **devp)
> {
> diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c
> index 9572f7ea9c..47ee5d440b 100644
> --- a/arch/arm/mach-rockchip/rk3288/rk3288.c
> +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c
> @@ -11,7 +11,7 @@
> #include <asm/io.h>
> #include <asm/arch-rockchip/bootrom.h>
> #include <asm/arch-rockchip/clock.h>
> -#include <asm/arch-rockchip/cru_rk3288.h>
> +#include <asm/arch-rockchip/cru.h>
> #include <asm/arch-rockchip/hardware.h>
> #include <asm/arch-rockchip/grf_rk3288.h>
> #include <asm/arch-rockchip/pmu_rk3288.h>
> @@ -104,7 +104,7 @@ void board_debug_uart_init(void)
>
> static void rk3288_detect_reset_reason(void)
> {
> - struct rk3288_cru *cru = rockchip_get_cru();
> + struct rockchip_cru *cru = rockchip_get_cru();
> const char *reason;
>
> if (IS_ERR(cru))
> diff --git a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c
> index f0411c0a21..a80a46f1db 100644
> --- a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c
> +++ b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c
> @@ -8,7 +8,7 @@
> #include <dm.h>
> #include <syscon.h>
> #include <asm/arch-rockchip/clock.h>
> -#include <asm/arch-rockchip/cru_rk3399.h>
> +#include <asm/arch-rockchip/cru.h>
>
> static int rockchip_get_cruclk(struct udevice **devp)
> {
> diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c
> index 863024d071..dafa142824 100644
> --- a/arch/arm/mach-rockchip/rk3399/rk3399.c
> +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
> @@ -240,7 +240,7 @@ static void rk3399_force_power_on_reset(void)
> void spl_board_init(void)
> {
> #if defined(SPL_GPIO_SUPPORT)
> - struct rk3399_cru *cru = rockchip_get_cru();
> + struct rockchip_cru *cru = rockchip_get_cru();
>
> /*
> * The RK3399 resets only 'almost all logic' (see also in the TRM
> diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
> index 85d1b67e43..cc1c1e81e9 100644
> --- a/drivers/clk/rockchip/clk_rk3288.c
> +++ b/drivers/clk/rockchip/clk_rk3288.c
> @@ -14,7 +14,7 @@
> #include <syscon.h>
> #include <asm/io.h>
> #include <asm/arch-rockchip/clock.h>
> -#include <asm/arch-rockchip/cru_rk3288.h>
> +#include <asm/arch-rockchip/cru.h>
> #include <asm/arch-rockchip/grf_rk3288.h>
> #include <asm/arch-rockchip/hardware.h>
> #include <dt-bindings/clock/rk3288-cru.h>
> @@ -141,7 +141,7 @@ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
> static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
> static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
>
> -static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
> +static int rkclk_set_pll(struct rockchip_cru *cru, enum rk_clk_id clk_id,
> const struct pll_div *div)
> {
> int pll_id = rk_pll_id(clk_id);
> @@ -172,7 +172,7 @@ static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
> return 0;
> }
>
> -static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,
> +static int rkclk_configure_ddr(struct rockchip_cru *cru, struct rk3288_grf *grf,
> unsigned int hz)
> {
> static const struct pll_div dpll_cfg[] = {
> @@ -295,7 +295,7 @@ static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
> return 0;
> }
>
> -static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq)
> +static int rockchip_mac_set_clk(struct rockchip_cru *cru, uint freq)
> {
> ulong ret;
>
> @@ -333,7 +333,7 @@ static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq)
> return ret;
> }
>
> -static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
> +static int rockchip_vop_set_clk(struct rockchip_cru *cru, struct rk3288_grf *grf,
> int periph, unsigned int rate_hz)
> {
> struct pll_div npll_config = {0};
> @@ -384,7 +384,7 @@ static u32 rockchip_clk_gcd(u32 a, u32 b)
> return a;
> }
>
> -static ulong rockchip_i2s_get_clk(struct rk3288_cru *cru, uint gclk_rate)
> +static ulong rockchip_i2s_get_clk(struct rockchip_cru *cru, uint gclk_rate)
> {
> unsigned long long rate;
> uint val;
> @@ -400,7 +400,7 @@ static ulong rockchip_i2s_get_clk(struct rk3288_cru *cru, uint gclk_rate)
> return (ulong)rate;
> }
>
> -static ulong rockchip_i2s_set_clk(struct rk3288_cru *cru, uint gclk_rate,
> +static ulong rockchip_i2s_set_clk(struct rockchip_cru *cru, uint gclk_rate,
> uint freq)
> {
> int n, d;
> @@ -418,7 +418,7 @@ static ulong rockchip_i2s_set_clk(struct rk3288_cru *cru, uint gclk_rate,
> }
> #endif /* CONFIG_SPL_BUILD */
>
> -static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
> +static void rkclk_init(struct rockchip_cru *cru, struct rk3288_grf *grf)
> {
> u32 aclk_div;
> u32 hclk_div;
> @@ -492,7 +492,7 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
> CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
> }
>
> -void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
> +void rk3288_clk_configure_cpu(struct rockchip_cru *cru, struct rk3288_grf *grf)
> {
> /* pll enter slow-mode */
> rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
> @@ -534,7 +534,7 @@ void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
> }
>
> /* Get pll rate by id */
> -static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
> +static uint32_t rkclk_pll_get_rate(struct rockchip_cru *cru,
> enum rk_clk_id clk_id)
> {
> uint32_t nr, no, nf;
> @@ -567,7 +567,7 @@ static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
> }
> }
>
> -static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
> +static ulong rockchip_mmc_get_clk(struct rockchip_cru *cru, uint gclk_rate,
> int periph)
> {
> uint src_rate;
> @@ -601,7 +601,7 @@ static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
> return DIV_TO_RATE(src_rate, div);
> }
>
> -static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
> +static ulong rockchip_mmc_set_clk(struct rockchip_cru *cru, uint gclk_rate,
> int periph, uint freq)
> {
> int src_clk_div;
> @@ -651,7 +651,7 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
> return rockchip_mmc_get_clk(cru, gclk_rate, periph);
> }
>
> -static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
> +static ulong rockchip_spi_get_clk(struct rockchip_cru *cru, uint gclk_rate,
> int periph)
> {
> uint div, mux;
> @@ -681,7 +681,7 @@ static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
> return DIV_TO_RATE(gclk_rate, div);
> }
>
> -static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
> +static ulong rockchip_spi_set_clk(struct rockchip_cru *cru, uint gclk_rate,
> int periph, uint freq)
> {
> int src_clk_div;
> @@ -715,7 +715,7 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
> return rockchip_spi_get_clk(cru, gclk_rate, periph);
> }
>
> -static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru)
> +static ulong rockchip_saradc_get_clk(struct rockchip_cru *cru)
> {
> u32 div, val;
>
> @@ -726,7 +726,7 @@ static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru)
> return DIV_TO_RATE(OSC_HZ, div);
> }
>
> -static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz)
> +static ulong rockchip_saradc_set_clk(struct rockchip_cru *cru, uint hz)
> {
> int src_clk_div;
>
> @@ -785,7 +785,7 @@ static ulong rk3288_clk_get_rate(struct clk *clk)
> static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
> {
> struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
> - struct rk3288_cru *cru = priv->cru;
> + struct rockchip_cru *cru = priv->cru;
> ulong new_rate, gclk_rate;
>
> gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
> @@ -892,7 +892,7 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
> static int __maybe_unused rk3288_gmac_set_parent(struct clk *clk, struct clk *parent)
> {
> struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
> - struct rk3288_cru *cru = priv->cru;
> + struct rockchip_cru *cru = priv->cru;
> const char *clock_output_name;
> int ret;
>
> @@ -1008,15 +1008,15 @@ static int rk3288_clk_bind(struct udevice *dev)
> debug("Warning: No sysreset driver: ret=%d\n", ret);
> } else {
> priv = malloc(sizeof(struct sysreset_reg));
> - priv->glb_srst_fst_value = offsetof(struct rk3288_cru,
> + priv->glb_srst_fst_value = offsetof(struct rockchip_cru,
> cru_glb_srst_fst_value);
> - priv->glb_srst_snd_value = offsetof(struct rk3288_cru,
> + priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
> cru_glb_srst_snd_value);
> sys_child->priv = priv;
> }
>
> #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
> - ret = offsetof(struct rk3288_cru, cru_softrst_con[0]);
> + ret = offsetof(struct rockchip_cru, cru_softrst_con[0]);
> ret = rockchip_reset_bind(dev, ret, 12);
> if (ret)
> debug("Warning: software reset driver bind faile\n");
> diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
> index 9020a9f202..37fc142a7a 100644
> --- a/drivers/clk/rockchip/clk_rk3399.c
> +++ b/drivers/clk/rockchip/clk_rk3399.c
> @@ -14,7 +14,7 @@
> #include <bitfield.h>
> #include <asm/io.h>
> #include <asm/arch-rockchip/clock.h>
> -#include <asm/arch-rockchip/cru_rk3399.h>
> +#include <asm/arch-rockchip/cru.h>
> #include <asm/arch-rockchip/hardware.h>
> #include <dm/lists.h>
> #include <dt-bindings/clock/rk3399-cru.h>
> @@ -418,7 +418,7 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div)
> return 0;
> }
>
> -void rk3399_configure_cpu_l(struct rk3399_cru *cru,
> +void rk3399_configure_cpu_l(struct rockchip_cru *cru,
> enum apll_l_frequencies apll_l_freq)
> {
> u32 aclkm_div;
> @@ -453,7 +453,7 @@ void rk3399_configure_cpu_l(struct rk3399_cru *cru,
> atclk_div << ATCLK_CORE_L_DIV_SHIFT);
> }
>
> -void rk3399_configure_cpu_b(struct rk3399_cru *cru,
> +void rk3399_configure_cpu_b(struct rockchip_cru *cru,
> enum apll_b_frequencies apll_b_freq)
> {
> u32 aclkm_div;
> @@ -505,7 +505,7 @@ void rk3399_configure_cpu_b(struct rk3399_cru *cru,
> #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \
> ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT)
>
> -static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id)
> +static ulong rk3399_i2c_get_clk(struct rockchip_cru *cru, ulong clk_id)
> {
> u32 div, con;
>
> @@ -542,7 +542,7 @@ static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id)
> return DIV_TO_RATE(GPLL_HZ, div);
> }
>
> -static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
> +static ulong rk3399_i2c_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
> {
> int src_clk_div;
>
> @@ -619,7 +619,7 @@ static const struct spi_clkreg spi_clkregs[] = {
> .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, },
> };
>
> -static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id)
> +static ulong rk3399_spi_get_clk(struct rockchip_cru *cru, ulong clk_id)
> {
> const struct spi_clkreg *spiclk = NULL;
> u32 div, val;
> @@ -641,7 +641,7 @@ static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id)
> return DIV_TO_RATE(GPLL_HZ, div);
> }
>
> -static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
> +static ulong rk3399_spi_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
> {
> const struct spi_clkreg *spiclk = NULL;
> int src_clk_div;
> @@ -668,7 +668,7 @@ static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
> return rk3399_spi_get_clk(cru, clk_id);
> }
>
> -static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
> +static ulong rk3399_vop_set_clk(struct rockchip_cru *cru, ulong clk_id, u32 hz)
> {
> struct pll_div vpll_config = {0};
> int aclk_vop = 198 * MHz;
> @@ -712,7 +712,7 @@ static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
> return hz;
> }
>
> -static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id)
> +static ulong rk3399_mmc_get_clk(struct rockchip_cru *cru, uint clk_id)
> {
> u32 div, con;
>
> @@ -739,7 +739,7 @@ static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id)
> return DIV_TO_RATE(GPLL_HZ, div);
> }
>
> -static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
> +static ulong rk3399_mmc_set_clk(struct rockchip_cru *cru,
> ulong clk_id, ulong set_rate)
> {
> int src_clk_div;
> @@ -792,7 +792,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
> return rk3399_mmc_get_clk(cru, clk_id);
> }
>
> -static ulong rk3399_gmac_set_clk(struct rk3399_cru *cru, ulong rate)
> +static ulong rk3399_gmac_set_clk(struct rockchip_cru *cru, ulong rate)
> {
> ulong ret;
>
> @@ -817,7 +817,7 @@ static ulong rk3399_gmac_set_clk(struct rk3399_cru *cru, ulong rate)
> }
>
> #define PMUSGRF_DDR_RGN_CON16 0xff330040
> -static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
> +static ulong rk3399_ddr_set_clk(struct rockchip_cru *cru,
> ulong set_rate)
> {
> struct pll_div dpll_cfg;
> @@ -863,7 +863,7 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
> return set_rate;
> }
>
> -static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru)
> +static ulong rk3399_saradc_get_clk(struct rockchip_cru *cru)
> {
> u32 div, val;
>
> @@ -874,7 +874,7 @@ static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru)
> return DIV_TO_RATE(OSC_HZ, div);
> }
>
> -static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz)
> +static ulong rk3399_saradc_set_clk(struct rockchip_cru *cru, uint hz)
> {
> int src_clk_div;
>
> @@ -1071,7 +1071,7 @@ static struct clk_ops rk3399_clk_ops = {
> };
>
> #ifdef CONFIG_SPL_BUILD
> -static void rkclk_init(struct rk3399_cru *cru)
> +static void rkclk_init(struct rockchip_cru *cru)
> {
> u32 aclk_div;
> u32 hclk_div;
> @@ -1188,15 +1188,15 @@ static int rk3399_clk_bind(struct udevice *dev)
> debug("Warning: No sysreset driver: ret=%d\n", ret);
> } else {
> priv = malloc(sizeof(struct sysreset_reg));
> - priv->glb_srst_fst_value = offsetof(struct rk3399_cru,
> + priv->glb_srst_fst_value = offsetof(struct rockchip_cru,
> glb_srst_fst_value);
> - priv->glb_srst_snd_value = offsetof(struct rk3399_cru,
> + priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
> glb_srst_snd_value);
> sys_child->priv = priv;
> }
>
> #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
> - ret = offsetof(struct rk3399_cru, softrst_con[0]);
> + ret = offsetof(struct rockchip_cru, softrst_con[0]);
> ret = rockchip_reset_bind(dev, ret, 21);
> if (ret)
> debug("Warning: software reset driver bind faile\n");
> diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c
> index 690751d074..fd5b204e1f 100644
> --- a/drivers/ram/rockchip/sdram_rk3288.c
> +++ b/drivers/ram/rockchip/sdram_rk3288.c
> @@ -16,7 +16,7 @@
> #include <syscon.h>
> #include <asm/io.h>
> #include <asm/arch-rockchip/clock.h>
> -#include <asm/arch-rockchip/cru_rk3288.h>
> +#include <asm/arch-rockchip/cru.h>
> #include <asm/arch-rockchip/ddr_rk3288.h>
> #include <asm/arch-rockchip/grf_rk3288.h>
> #include <asm/arch-rockchip/pmu_rk3288.h>
> @@ -36,7 +36,7 @@ struct dram_info {
> struct chan_info chan[2];
> struct ram_info info;
> struct clk ddr_clk;
> - struct rk3288_cru *cru;
> + struct rockchip_cru *cru;
> struct rk3288_grf *grf;
> struct rk3288_sgrf *sgrf;
> struct rk3288_pmu *pmu;
> @@ -92,7 +92,7 @@ static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
> }
> }
>
> -static void ddr_reset(struct rk3288_cru *cru, u32 ch, u32 ctl, u32 phy)
> +static void ddr_reset(struct rockchip_cru *cru, u32 ch, u32 ctl, u32 phy)
> {
> u32 phy_ctl_srstn_shift = 4 + 5 * ch;
> u32 ctl_psrstn_shift = 3 + 5 * ch;
> @@ -109,7 +109,7 @@ static void ddr_reset(struct rk3288_cru *cru, u32 ch, u32 ctl, u32 phy)
> phy << phy_srstn_shift);
> }
>
> -static void ddr_phy_ctl_reset(struct rk3288_cru *cru, u32 ch, u32 n)
> +static void ddr_phy_ctl_reset(struct rockchip_cru *cru, u32 ch, u32 n)
> {
> u32 phy_ctl_srstn_shift = 4 + 5 * ch;
>
> @@ -117,7 +117,7 @@ static void ddr_phy_ctl_reset(struct rk3288_cru *cru, u32 ch, u32 n)
> 1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift);
> }
>
> -static void phy_pctrl_reset(struct rk3288_cru *cru,
> +static void phy_pctrl_reset(struct rockchip_cru *cru,
> struct rk3288_ddr_publ *publ,
> int channel)
> {
> diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
> index 7b2bba03fe..08bf0393a7 100644
> --- a/drivers/ram/rockchip/sdram_rk3399.c
> +++ b/drivers/ram/rockchip/sdram_rk3399.c
> @@ -14,7 +14,7 @@
> #include <syscon.h>
> #include <asm/io.h>
> #include <asm/arch-rockchip/clock.h>
> -#include <asm/arch-rockchip/cru_rk3399.h>
> +#include <asm/arch-rockchip/cru.h>
> #include <asm/arch-rockchip/grf_rk3399.h>
> #include <asm/arch-rockchip/pmu_rk3399.h>
> #include <asm/arch-rockchip/hardware.h>
> @@ -66,7 +66,7 @@ struct dram_info {
> u32 pwrup_srefresh_exit[2];
> struct chan_info chan[2];
> struct clk ddr_clk;
> - struct rk3399_cru *cru;
> + struct rockchip_cru *cru;
> struct rk3399_grf_regs *grf;
> struct rk3399_pmu_regs *pmu;
> struct rk3399_pmucru *pmucru;
> @@ -228,7 +228,7 @@ static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
> return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc1_con0;
> }
>
> -static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl,
> +static void rkclk_ddr_reset(struct rockchip_cru *cru, u32 channel, u32 ctl,
> u32 phy)
> {
> channel &= 0x1;
> @@ -239,7 +239,7 @@ static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl,
> &cru->softrst_con[4]);
> }
>
> -static void phy_pctrl_reset(struct rk3399_cru *cru, u32 channel)
> +static void phy_pctrl_reset(struct rockchip_cru *cru, u32 channel)
> {
> rkclk_ddr_reset(cru, channel, 1, 1);
> udelay(10);
> @@ -2945,7 +2945,7 @@ static int sdram_init(struct dram_info *dram,
> for (channel = 0; channel < 2; channel++) {
> const struct chan_info *chan =
> &dram->chan[channel];
> - struct rk3399_cru *cru = dram->cru;
> + struct rockchip_cru *cru = dram->cru;
> struct rk3399_ddr_publ_regs *publ = chan->publ;
>
> phy_pctrl_reset(cru, channel);
> diff --git a/drivers/video/rockchip/rk3288_mipi.c b/drivers/video/rockchip/rk3288_mipi.c
> index 7c4a4cc53b..65891ce45c 100644
> --- a/drivers/video/rockchip/rk3288_mipi.c
> +++ b/drivers/video/rockchip/rk3288_mipi.c
> @@ -18,7 +18,7 @@
> #include <dm/uclass-internal.h>
> #include <linux/kernel.h>
> #include <asm/arch-rockchip/clock.h>
> -#include <asm/arch-rockchip/cru_rk3288.h>
> +#include <asm/arch-rockchip/cru.h>
> #include <asm/arch-rockchip/grf_rk3288.h>
> #include <asm/arch-rockchip/hardware.h>
> #include <asm/arch-rockchip/rockchip_mipi_dsi.h>
> diff --git a/drivers/video/rockchip/rk3399_mipi.c b/drivers/video/rockchip/rk3399_mipi.c
> index a93b73400b..a5b7ba69a8 100644
> --- a/drivers/video/rockchip/rk3399_mipi.c
> +++ b/drivers/video/rockchip/rk3399_mipi.c
> @@ -18,7 +18,7 @@
> #include <dm/uclass-internal.h>
> #include <linux/kernel.h>
> #include <asm/arch-rockchip/clock.h>
> -#include <asm/arch-rockchip/cru_rk3399.h>
> +#include <asm/arch-rockchip/cru.h>
> #include <asm/arch-rockchip/grf_rk3399.h>
> #include <asm/arch-rockchip/hardware.h>
> #include <asm/arch-rockchip/rockchip_mipi_dsi.h>
> diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c
> index bcd039b7bc..f9280e8607 100644
> --- a/drivers/video/rockchip/rk_mipi.c
> +++ b/drivers/video/rockchip/rk_mipi.c
> @@ -18,7 +18,7 @@
> #include <dm/uclass-internal.h>
> #include <linux/kernel.h>
> #include <asm/arch-rockchip/clock.h>
> -#include <asm/arch-rockchip/cru_rk3399.h>
> +#include <asm/arch-rockchip/cru.h>
> #include <asm/arch-rockchip/grf_rk3399.h>
> #include <asm/arch-rockchip/rockchip_mipi_dsi.h>
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 4/5] rockchip: Add common reset cause
2019-12-29 19:07 ` Jagan Teki
@ 2020-01-06 9:24 ` Kever Yang
-1 siblings, 0 replies; 21+ messages in thread
From: Kever Yang @ 2020-01-06 9:24 UTC (permalink / raw)
To: Jagan Teki, Simon Glass, Philipp Tomsich
Cc: u-boot, linux-amarula, Akash Gajjar, linux-rockchip
On 2019/12/30 上午3:07, Jagan Teki wrote:
> Add cpu reset cause in common cpu-info file.
>
> This would help to print the reset cause for
> various resets.
>
> Right now it support rk3288, rk3399. rest of rockchip
> platforms doesn't have reset cause support ye but this
> code is more feasible to extend the same.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> arch/arm/include/asm/arch-rockchip/cru.h | 12 +++++
> .../include/asm/arch-rockchip/cru_rk3288.h | 14 +-----
> arch/arm/mach-rockchip/cpu-info.c | 49 +++++++++++++++++++
> arch/arm/mach-rockchip/rk3288/rk3288.c | 39 ---------------
> 4 files changed, 62 insertions(+), 52 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h
> index 5ed3fbfd07..e1dd9a89c2 100644
> --- a/arch/arm/include/asm/arch-rockchip/cru.h
> +++ b/arch/arm/include/asm/arch-rockchip/cru.h
> @@ -13,4 +13,16 @@
> # include <asm/arch-rockchip/cru_rk3399.h>
> #endif
>
> +/* CRU_GLB_RST_ST */
> +enum {
> + GLB_POR_RST,
> + FST_GLB_RST_ST = BIT(0),
> + SND_GLB_RST_ST = BIT(1),
> + FST_GLB_TSADC_RST_ST = BIT(2),
> + SND_GLB_TSADC_RST_ST = BIT(3),
> + FST_GLB_WDT_RST_ST = BIT(4),
> + SND_GLB_WDT_RST_ST = BIT(5),
> + GLB_RST_ST_MASK = GENMASK(5, 0),
> +};
> +
> #endif /* _ROCKCHIP_CLOCK_H */
> diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
> index 7aa6efe46c..412b73e55f 100644
> --- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
> +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
> @@ -51,7 +51,7 @@ struct rockchip_cru {
> u32 cru_glb_cnt_th;
> u32 cru_glb_rst_con;
> u32 reserved3;
> - u32 cru_glb_rst_st;
> + u32 glb_rst_st;
> u32 reserved4;
> u32 cru_sdmmc_con[2];
> u32 cru_sdio0_con[2];
> @@ -227,16 +227,4 @@ enum {
> CLKF_MASK = 0x1fff << CLKF_SHIFT,
> };
>
> -/* CRU_GLB_RST_ST */
> -enum {
> - GLB_POR_RST,
> - FST_GLB_RST_ST = BIT(0),
> - SND_GLB_RST_ST = BIT(1),
> - FST_GLB_TSADC_RST_ST = BIT(2),
> - SND_GLB_TSADC_RST_ST = BIT(3),
> - FST_GLB_WDT_RST_ST = BIT(4),
> - SND_GLB_WDT_RST_ST = BIT(5),
> - GLB_RST_ST_MASK = GENMASK(5, 0),
> -};
> -
> #endif
> diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c
> index 9bccbd4f68..4b0e99299a 100644
> --- a/arch/arm/mach-rockchip/cpu-info.c
> +++ b/arch/arm/mach-rockchip/cpu-info.c
> @@ -5,10 +5,59 @@
> */
>
> #include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch-rockchip/clock.h>
> +#include <asm/arch-rockchip/cru.h>
> +#include <asm/arch-rockchip/hardware.h>
> +#include <linux/err.h>
> +
> +static char *get_reset_cause(void)
> +{
> + struct rockchip_cru *cru = rockchip_get_cru();
> + char *cause = NULL;
> +
> + if (IS_ERR(cru))
> + return cause;
> +
> + switch (cru->glb_rst_st) {
> + case GLB_POR_RST:
> + cause = "POR";
> + break;
> + case FST_GLB_RST_ST:
> + case SND_GLB_RST_ST:
> + cause = "RST";
> + break;
> + case FST_GLB_TSADC_RST_ST:
> + case SND_GLB_TSADC_RST_ST:
> + cause = "THERMAL";
> + break;
> + case FST_GLB_WDT_RST_ST:
> + case SND_GLB_WDT_RST_ST:
> + cause = "WDOG";
> + break;
> + default:
> + cause = "unknown reset";
> + }
> +
> + /**
> + * reset_reason env is used by rk3288, due to special use case
> + * to figure it the boot behavior. so keep this as it is.
> + */
> + env_set("reset_reason", cause);
> +
> + /*
> + * Clear glb_rst_st, so we can determine the last reset cause
> + * for following resets.
> + */
> + rk_clrreg(&cru->glb_rst_st, GLB_RST_ST_MASK);
> +
> + return cause;
> +}
>
> int print_cpuinfo(void)
> {
> printf("SoC: Rockchip %s\n", CONFIG_SYS_SOC);
> + printf("Reset cause: %s\n", get_reset_cause());
>
> /* TODO print operating temparature and clock */
>
> diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c
> index 47ee5d440b..18ea7f35fb 100644
> --- a/arch/arm/mach-rockchip/rk3288/rk3288.c
> +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c
> @@ -102,43 +102,6 @@ void board_debug_uart_init(void)
> }
> #endif
>
> -static void rk3288_detect_reset_reason(void)
> -{
> - struct rockchip_cru *cru = rockchip_get_cru();
> - const char *reason;
> -
> - if (IS_ERR(cru))
> - return;
> -
> - switch (cru->cru_glb_rst_st) {
> - case GLB_POR_RST:
> - reason = "POR";
> - break;
> - case FST_GLB_RST_ST:
> - case SND_GLB_RST_ST:
> - reason = "RST";
> - break;
> - case FST_GLB_TSADC_RST_ST:
> - case SND_GLB_TSADC_RST_ST:
> - reason = "THERMAL";
> - break;
> - case FST_GLB_WDT_RST_ST:
> - case SND_GLB_WDT_RST_ST:
> - reason = "WDOG";
> - break;
> - default:
> - reason = "unknown reset";
> - }
> -
> - env_set("reset_reason", reason);
> -
> - /*
> - * Clear cru_glb_rst_st, so we can determine the last reset cause
> - * for following resets.
> - */
> - rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK);
> -}
> -
> __weak int rk3288_board_late_init(void)
> {
> return 0;
> @@ -146,8 +109,6 @@ __weak int rk3288_board_late_init(void)
>
> int rk_board_late_init(void)
> {
> - rk3288_detect_reset_reason();
> -
> return rk3288_board_late_init();
> }
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v3 4/5] rockchip: Add common reset cause
@ 2020-01-06 9:24 ` Kever Yang
0 siblings, 0 replies; 21+ messages in thread
From: Kever Yang @ 2020-01-06 9:24 UTC (permalink / raw)
To: u-boot
On 2019/12/30 上午3:07, Jagan Teki wrote:
> Add cpu reset cause in common cpu-info file.
>
> This would help to print the reset cause for
> various resets.
>
> Right now it support rk3288, rk3399. rest of rockchip
> platforms doesn't have reset cause support ye but this
> code is more feasible to extend the same.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> arch/arm/include/asm/arch-rockchip/cru.h | 12 +++++
> .../include/asm/arch-rockchip/cru_rk3288.h | 14 +-----
> arch/arm/mach-rockchip/cpu-info.c | 49 +++++++++++++++++++
> arch/arm/mach-rockchip/rk3288/rk3288.c | 39 ---------------
> 4 files changed, 62 insertions(+), 52 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h
> index 5ed3fbfd07..e1dd9a89c2 100644
> --- a/arch/arm/include/asm/arch-rockchip/cru.h
> +++ b/arch/arm/include/asm/arch-rockchip/cru.h
> @@ -13,4 +13,16 @@
> # include <asm/arch-rockchip/cru_rk3399.h>
> #endif
>
> +/* CRU_GLB_RST_ST */
> +enum {
> + GLB_POR_RST,
> + FST_GLB_RST_ST = BIT(0),
> + SND_GLB_RST_ST = BIT(1),
> + FST_GLB_TSADC_RST_ST = BIT(2),
> + SND_GLB_TSADC_RST_ST = BIT(3),
> + FST_GLB_WDT_RST_ST = BIT(4),
> + SND_GLB_WDT_RST_ST = BIT(5),
> + GLB_RST_ST_MASK = GENMASK(5, 0),
> +};
> +
> #endif /* _ROCKCHIP_CLOCK_H */
> diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
> index 7aa6efe46c..412b73e55f 100644
> --- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
> +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
> @@ -51,7 +51,7 @@ struct rockchip_cru {
> u32 cru_glb_cnt_th;
> u32 cru_glb_rst_con;
> u32 reserved3;
> - u32 cru_glb_rst_st;
> + u32 glb_rst_st;
> u32 reserved4;
> u32 cru_sdmmc_con[2];
> u32 cru_sdio0_con[2];
> @@ -227,16 +227,4 @@ enum {
> CLKF_MASK = 0x1fff << CLKF_SHIFT,
> };
>
> -/* CRU_GLB_RST_ST */
> -enum {
> - GLB_POR_RST,
> - FST_GLB_RST_ST = BIT(0),
> - SND_GLB_RST_ST = BIT(1),
> - FST_GLB_TSADC_RST_ST = BIT(2),
> - SND_GLB_TSADC_RST_ST = BIT(3),
> - FST_GLB_WDT_RST_ST = BIT(4),
> - SND_GLB_WDT_RST_ST = BIT(5),
> - GLB_RST_ST_MASK = GENMASK(5, 0),
> -};
> -
> #endif
> diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c
> index 9bccbd4f68..4b0e99299a 100644
> --- a/arch/arm/mach-rockchip/cpu-info.c
> +++ b/arch/arm/mach-rockchip/cpu-info.c
> @@ -5,10 +5,59 @@
> */
>
> #include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch-rockchip/clock.h>
> +#include <asm/arch-rockchip/cru.h>
> +#include <asm/arch-rockchip/hardware.h>
> +#include <linux/err.h>
> +
> +static char *get_reset_cause(void)
> +{
> + struct rockchip_cru *cru = rockchip_get_cru();
> + char *cause = NULL;
> +
> + if (IS_ERR(cru))
> + return cause;
> +
> + switch (cru->glb_rst_st) {
> + case GLB_POR_RST:
> + cause = "POR";
> + break;
> + case FST_GLB_RST_ST:
> + case SND_GLB_RST_ST:
> + cause = "RST";
> + break;
> + case FST_GLB_TSADC_RST_ST:
> + case SND_GLB_TSADC_RST_ST:
> + cause = "THERMAL";
> + break;
> + case FST_GLB_WDT_RST_ST:
> + case SND_GLB_WDT_RST_ST:
> + cause = "WDOG";
> + break;
> + default:
> + cause = "unknown reset";
> + }
> +
> + /**
> + * reset_reason env is used by rk3288, due to special use case
> + * to figure it the boot behavior. so keep this as it is.
> + */
> + env_set("reset_reason", cause);
> +
> + /*
> + * Clear glb_rst_st, so we can determine the last reset cause
> + * for following resets.
> + */
> + rk_clrreg(&cru->glb_rst_st, GLB_RST_ST_MASK);
> +
> + return cause;
> +}
>
> int print_cpuinfo(void)
> {
> printf("SoC: Rockchip %s\n", CONFIG_SYS_SOC);
> + printf("Reset cause: %s\n", get_reset_cause());
>
> /* TODO print operating temparature and clock */
>
> diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c
> index 47ee5d440b..18ea7f35fb 100644
> --- a/arch/arm/mach-rockchip/rk3288/rk3288.c
> +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c
> @@ -102,43 +102,6 @@ void board_debug_uart_init(void)
> }
> #endif
>
> -static void rk3288_detect_reset_reason(void)
> -{
> - struct rockchip_cru *cru = rockchip_get_cru();
> - const char *reason;
> -
> - if (IS_ERR(cru))
> - return;
> -
> - switch (cru->cru_glb_rst_st) {
> - case GLB_POR_RST:
> - reason = "POR";
> - break;
> - case FST_GLB_RST_ST:
> - case SND_GLB_RST_ST:
> - reason = "RST";
> - break;
> - case FST_GLB_TSADC_RST_ST:
> - case SND_GLB_TSADC_RST_ST:
> - reason = "THERMAL";
> - break;
> - case FST_GLB_WDT_RST_ST:
> - case SND_GLB_WDT_RST_ST:
> - reason = "WDOG";
> - break;
> - default:
> - reason = "unknown reset";
> - }
> -
> - env_set("reset_reason", reason);
> -
> - /*
> - * Clear cru_glb_rst_st, so we can determine the last reset cause
> - * for following resets.
> - */
> - rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK);
> -}
> -
> __weak int rk3288_board_late_init(void)
> {
> return 0;
> @@ -146,8 +109,6 @@ __weak int rk3288_board_late_init(void)
>
> int rk_board_late_init(void)
> {
> - rk3288_detect_reset_reason();
> -
> return rk3288_board_late_init();
> }
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 5/5] rockchip: rk3399: Add bootcount support
2019-12-29 19:07 ` Jagan Teki
@ 2020-01-06 9:25 ` Kever Yang
-1 siblings, 0 replies; 21+ messages in thread
From: Kever Yang @ 2020-01-06 9:25 UTC (permalink / raw)
To: Jagan Teki, Simon Glass, Philipp Tomsich
Cc: u-boot-0aAXYlwwYIKGBzrmiIFOJg,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Akash Gajjar, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On 2019/12/30 上午3:07, Jagan Teki wrote:
> Add bootcount support for Rockchip rk3399.
>
> The bootcount value is preserved in PMU_SYS_REG0 register,
> this would help to support redundent boot.
>
> Once the redundant boot triggers, the altboot command
> will look for extlinux-rollback.conf on particular
> bootable partition which supposed to be a recovery
> partition where redundant boot required.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> arch/arm/mach-rockchip/Kconfig | 2 ++
> arch/arm/mach-rockchip/rk3399/Kconfig | 10 ++++++++++
> include/configs/rk3399_common.h | 5 ++++-
> 3 files changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
> index d8d68ba447..9a3c65ec58 100644
> --- a/arch/arm/mach-rockchip/Kconfig
> +++ b/arch/arm/mach-rockchip/Kconfig
> @@ -244,6 +244,8 @@ config ROCKCHIP_RK3399
> imply TPL_CLK
> imply TPL_TINY_MEMSET
> imply TPL_ROCKCHIP_COMMON_BOARD
> + imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT
> + imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT
> help
> The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
> and quad-core Cortex-A53.
> diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig
> index 868e85fc2a..f994152803 100644
> --- a/arch/arm/mach-rockchip/rk3399/Kconfig
> +++ b/arch/arm/mach-rockchip/rk3399/Kconfig
> @@ -113,6 +113,16 @@ config TPL_TEXT_BASE
> config SPL_STACK_R_ADDR
> default 0x04000000
>
> +if BOOTCOUNT_LIMIT
> +
> +config BOOTCOUNT_BOOTLIMIT
> + default 3
> +
> +config SYS_BOOTCOUNT_ADDR
> + default 0xff3100f0 # PMU_SYS_REG0
> +
> +endif # BOOTCOUNT_LIMIT
> +
> source "board/rockchip/evb_rk3399/Kconfig"
> source "board/theobroma-systems/puma_rk3399/Kconfig"
> source "board/vamrs/rock960_rk3399/Kconfig"
> diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
> index 127ca1f09c..89a8a44bbe 100644
> --- a/include/configs/rk3399_common.h
> +++ b/include/configs/rk3399_common.h
> @@ -63,7 +63,10 @@
> "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
> "partitions=" PARTS_DEFAULT \
> ROCKCHIP_DEVICE_SETTINGS \
> - BOOTENV
> + BOOTENV \
> + "altbootcmd=" \
> + "setenv boot_syslinux_conf extlinux/extlinux-rollback.conf;" \
> + "run distro_bootcmd\0"
>
> #endif
>
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v3 5/5] rockchip: rk3399: Add bootcount support
@ 2020-01-06 9:25 ` Kever Yang
0 siblings, 0 replies; 21+ messages in thread
From: Kever Yang @ 2020-01-06 9:25 UTC (permalink / raw)
To: u-boot
On 2019/12/30 上午3:07, Jagan Teki wrote:
> Add bootcount support for Rockchip rk3399.
>
> The bootcount value is preserved in PMU_SYS_REG0 register,
> this would help to support redundent boot.
>
> Once the redundant boot triggers, the altboot command
> will look for extlinux-rollback.conf on particular
> bootable partition which supposed to be a recovery
> partition where redundant boot required.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> arch/arm/mach-rockchip/Kconfig | 2 ++
> arch/arm/mach-rockchip/rk3399/Kconfig | 10 ++++++++++
> include/configs/rk3399_common.h | 5 ++++-
> 3 files changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
> index d8d68ba447..9a3c65ec58 100644
> --- a/arch/arm/mach-rockchip/Kconfig
> +++ b/arch/arm/mach-rockchip/Kconfig
> @@ -244,6 +244,8 @@ config ROCKCHIP_RK3399
> imply TPL_CLK
> imply TPL_TINY_MEMSET
> imply TPL_ROCKCHIP_COMMON_BOARD
> + imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT
> + imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT
> help
> The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
> and quad-core Cortex-A53.
> diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig
> index 868e85fc2a..f994152803 100644
> --- a/arch/arm/mach-rockchip/rk3399/Kconfig
> +++ b/arch/arm/mach-rockchip/rk3399/Kconfig
> @@ -113,6 +113,16 @@ config TPL_TEXT_BASE
> config SPL_STACK_R_ADDR
> default 0x04000000
>
> +if BOOTCOUNT_LIMIT
> +
> +config BOOTCOUNT_BOOTLIMIT
> + default 3
> +
> +config SYS_BOOTCOUNT_ADDR
> + default 0xff3100f0 # PMU_SYS_REG0
> +
> +endif # BOOTCOUNT_LIMIT
> +
> source "board/rockchip/evb_rk3399/Kconfig"
> source "board/theobroma-systems/puma_rk3399/Kconfig"
> source "board/vamrs/rock960_rk3399/Kconfig"
> diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
> index 127ca1f09c..89a8a44bbe 100644
> --- a/include/configs/rk3399_common.h
> +++ b/include/configs/rk3399_common.h
> @@ -63,7 +63,10 @@
> "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
> "partitions=" PARTS_DEFAULT \
> ROCKCHIP_DEVICE_SETTINGS \
> - BOOTENV
> + BOOTENV \
> + "altbootcmd=" \
> + "setenv boot_syslinux_conf extlinux/extlinux-rollback.conf;" \
> + "run distro_bootcmd\0"
>
> #endif
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v3 3/5] arm: rockchip: Add common cru.h
2019-12-29 19:07 ` Jagan Teki
(?)
(?)
@ 2020-01-07 9:45 ` Kever Yang
-1 siblings, 0 replies; 21+ messages in thread
From: Kever Yang @ 2020-01-07 9:45 UTC (permalink / raw)
To: u-boot
Hi Jagan,
This patch seems like will cause below error, could you help to have a look:
arm: + evb-rk3288
+drivers/video/rockchip/rk_mipi.c: In function ‘rk_mipi_phy_enable’:
+drivers/video/rockchip/rk_mipi.c:232:42: error: ‘MHz’ undeclared (first
use in this function)
Thanks,
- Kever
On 2019/12/30 上午3:07, Jagan Teki wrote:
> Few of the rockchip family SoC atleast rk3288,
> rk3399 are sharing some cru register bits so
> adding common code between these SoC families
> would require to include both cru include files
> that indeed resulting function declarations error.
>
> So, create a common cru include as cru.h then
> include the rk3399 arch cru include file and move
> the common cru register bit definitions into it.
>
> The rest of rockchip cru files will add it in future.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
> arch/arm/include/asm/arch-rockchip/clock.h | 4 +-
> arch/arm/include/asm/arch-rockchip/cru.h | 16 +++++++
> .../include/asm/arch-rockchip/cru_rk3288.h | 6 +--
> .../include/asm/arch-rockchip/cru_rk3399.h | 10 ++---
> arch/arm/mach-rockchip/rk3288/clk_rk3288.c | 2 +-
> arch/arm/mach-rockchip/rk3288/rk3288.c | 4 +-
> arch/arm/mach-rockchip/rk3399/clk_rk3399.c | 2 +-
> arch/arm/mach-rockchip/rk3399/rk3399.c | 2 +-
> drivers/clk/rockchip/clk_rk3288.c | 42 +++++++++----------
> drivers/clk/rockchip/clk_rk3399.c | 36 ++++++++--------
> drivers/ram/rockchip/sdram_rk3288.c | 10 ++---
> drivers/ram/rockchip/sdram_rk3399.c | 10 ++---
> drivers/video/rockchip/rk3288_mipi.c | 2 +-
> drivers/video/rockchip/rk3399_mipi.c | 2 +-
> drivers/video/rockchip/rk_mipi.c | 2 +-
> 15 files changed, 83 insertions(+), 67 deletions(-)
> create mode 100644 arch/arm/include/asm/arch-rockchip/cru.h
>
> diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
> index 8f7fc86a9e..22de0aef8d 100644
> --- a/arch/arm/include/asm/arch-rockchip/clock.h
> +++ b/arch/arm/include/asm/arch-rockchip/clock.h
> @@ -153,10 +153,10 @@ void *rockchip_get_cru(void);
> */
> void *rockchip_get_pmucru(void);
>
> -struct rk3288_cru;
> +struct rockchip_cru;
> struct rk3288_grf;
>
> -void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf);
> +void rk3288_clk_configure_cpu(struct rockchip_cru *cru, struct rk3288_grf *grf);
>
> int rockchip_get_clk(struct udevice **devp);
>
> diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h
> new file mode 100644
> index 0000000000..5ed3fbfd07
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rockchip/cru.h
> @@ -0,0 +1,16 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * (C) Copyright 2019 Amarula Solutions.
> + * Author: Jagan Teki <jagan@amarulasolutions.com>
> + */
> +
> +#ifndef _ROCKCHIP_CLOCK_H
> +#define _ROCKCHIP_CLOCK_H
> +
> +#if defined(CONFIG_ROCKCHIP_RK3288)
> +# include <asm/arch-rockchip/cru_rk3288.h>
> +#elif defined(CONFIG_ROCKCHIP_RK3399)
> +# include <asm/arch-rockchip/cru_rk3399.h>
> +#endif
> +
> +#endif /* _ROCKCHIP_CLOCK_H */
> diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
> index e891f20b37..7aa6efe46c 100644
> --- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
> +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
> @@ -27,11 +27,11 @@
> /* Private data for the clock driver - used by rockchip_get_cru() */
> struct rk3288_clk_priv {
> struct rk3288_grf *grf;
> - struct rk3288_cru *cru;
> + struct rockchip_cru *cru;
> ulong rate;
> };
>
> -struct rk3288_cru {
> +struct rockchip_cru {
> struct rk3288_pll {
> u32 con0;
> u32 con1;
> @@ -58,7 +58,7 @@ struct rk3288_cru {
> u32 cru_sdio1_con[2];
> u32 cru_emmc_con[2];
> };
> -check_member(rk3288_cru, cru_emmc_con[1], 0x021c);
> +check_member(rockchip_cru, cru_emmc_con[1], 0x021c);
>
> /* CRU_CLKSEL11_CON */
> enum {
> diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
> index 15eeb9c440..33ce190434 100644
> --- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
> +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
> @@ -10,7 +10,7 @@
>
> /* Private data for the clock driver - used by rockchip_get_cru() */
> struct rk3399_clk_priv {
> - struct rk3399_cru *cru;
> + struct rockchip_cru *cru;
> };
>
> struct rk3399_pmuclk_priv {
> @@ -33,7 +33,7 @@ struct rk3399_pmucru {
> };
> check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134);
>
> -struct rk3399_cru {
> +struct rockchip_cru {
> u32 apll_l_con[6];
> u32 reserved[2];
> u32 apll_b_con[6];
> @@ -65,7 +65,7 @@ struct rk3399_cru {
> u32 sdio0_con[2];
> u32 sdio1_con[2];
> };
> -check_member(rk3399_cru, sdio1_con[1], 0x594);
> +check_member(rockchip_cru, sdio1_con[1], 0x594);
> #define MHz 1000000
> #define KHz 1000
> #define OSC_HZ (24*MHz)
> @@ -107,9 +107,9 @@ enum apll_b_frequencies {
> APLL_B_600_MHZ,
> };
>
> -void rk3399_configure_cpu_l(struct rk3399_cru *cru,
> +void rk3399_configure_cpu_l(struct rockchip_cru *cru,
> enum apll_l_frequencies apll_l_freq);
> -void rk3399_configure_cpu_b(struct rk3399_cru *cru,
> +void rk3399_configure_cpu_b(struct rockchip_cru *cru,
> enum apll_b_frequencies apll_b_freq);
>
> #endif /* __ASM_ARCH_CRU_RK3399_H_ */
> diff --git a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c
> index e64ee86f08..1730f12443 100644
> --- a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c
> +++ b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c
> @@ -8,7 +8,7 @@
> #include <dm.h>
> #include <syscon.h>
> #include <asm/arch-rockchip/clock.h>
> -#include <asm/arch-rockchip/cru_rk3288.h>
> +#include <asm/arch-rockchip/cru.h>
>
> int rockchip_get_clk(struct udevice **devp)
> {
> diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c
> index 9572f7ea9c..47ee5d440b 100644
> --- a/arch/arm/mach-rockchip/rk3288/rk3288.c
> +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c
> @@ -11,7 +11,7 @@
> #include <asm/io.h>
> #include <asm/arch-rockchip/bootrom.h>
> #include <asm/arch-rockchip/clock.h>
> -#include <asm/arch-rockchip/cru_rk3288.h>
> +#include <asm/arch-rockchip/cru.h>
> #include <asm/arch-rockchip/hardware.h>
> #include <asm/arch-rockchip/grf_rk3288.h>
> #include <asm/arch-rockchip/pmu_rk3288.h>
> @@ -104,7 +104,7 @@ void board_debug_uart_init(void)
>
> static void rk3288_detect_reset_reason(void)
> {
> - struct rk3288_cru *cru = rockchip_get_cru();
> + struct rockchip_cru *cru = rockchip_get_cru();
> const char *reason;
>
> if (IS_ERR(cru))
> diff --git a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c
> index f0411c0a21..a80a46f1db 100644
> --- a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c
> +++ b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c
> @@ -8,7 +8,7 @@
> #include <dm.h>
> #include <syscon.h>
> #include <asm/arch-rockchip/clock.h>
> -#include <asm/arch-rockchip/cru_rk3399.h>
> +#include <asm/arch-rockchip/cru.h>
>
> static int rockchip_get_cruclk(struct udevice **devp)
> {
> diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c
> index 863024d071..dafa142824 100644
> --- a/arch/arm/mach-rockchip/rk3399/rk3399.c
> +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
> @@ -240,7 +240,7 @@ static void rk3399_force_power_on_reset(void)
> void spl_board_init(void)
> {
> #if defined(SPL_GPIO_SUPPORT)
> - struct rk3399_cru *cru = rockchip_get_cru();
> + struct rockchip_cru *cru = rockchip_get_cru();
>
> /*
> * The RK3399 resets only 'almost all logic' (see also in the TRM
> diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
> index 85d1b67e43..cc1c1e81e9 100644
> --- a/drivers/clk/rockchip/clk_rk3288.c
> +++ b/drivers/clk/rockchip/clk_rk3288.c
> @@ -14,7 +14,7 @@
> #include <syscon.h>
> #include <asm/io.h>
> #include <asm/arch-rockchip/clock.h>
> -#include <asm/arch-rockchip/cru_rk3288.h>
> +#include <asm/arch-rockchip/cru.h>
> #include <asm/arch-rockchip/grf_rk3288.h>
> #include <asm/arch-rockchip/hardware.h>
> #include <dt-bindings/clock/rk3288-cru.h>
> @@ -141,7 +141,7 @@ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
> static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
> static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
>
> -static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
> +static int rkclk_set_pll(struct rockchip_cru *cru, enum rk_clk_id clk_id,
> const struct pll_div *div)
> {
> int pll_id = rk_pll_id(clk_id);
> @@ -172,7 +172,7 @@ static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
> return 0;
> }
>
> -static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,
> +static int rkclk_configure_ddr(struct rockchip_cru *cru, struct rk3288_grf *grf,
> unsigned int hz)
> {
> static const struct pll_div dpll_cfg[] = {
> @@ -295,7 +295,7 @@ static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
> return 0;
> }
>
> -static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq)
> +static int rockchip_mac_set_clk(struct rockchip_cru *cru, uint freq)
> {
> ulong ret;
>
> @@ -333,7 +333,7 @@ static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq)
> return ret;
> }
>
> -static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
> +static int rockchip_vop_set_clk(struct rockchip_cru *cru, struct rk3288_grf *grf,
> int periph, unsigned int rate_hz)
> {
> struct pll_div npll_config = {0};
> @@ -384,7 +384,7 @@ static u32 rockchip_clk_gcd(u32 a, u32 b)
> return a;
> }
>
> -static ulong rockchip_i2s_get_clk(struct rk3288_cru *cru, uint gclk_rate)
> +static ulong rockchip_i2s_get_clk(struct rockchip_cru *cru, uint gclk_rate)
> {
> unsigned long long rate;
> uint val;
> @@ -400,7 +400,7 @@ static ulong rockchip_i2s_get_clk(struct rk3288_cru *cru, uint gclk_rate)
> return (ulong)rate;
> }
>
> -static ulong rockchip_i2s_set_clk(struct rk3288_cru *cru, uint gclk_rate,
> +static ulong rockchip_i2s_set_clk(struct rockchip_cru *cru, uint gclk_rate,
> uint freq)
> {
> int n, d;
> @@ -418,7 +418,7 @@ static ulong rockchip_i2s_set_clk(struct rk3288_cru *cru, uint gclk_rate,
> }
> #endif /* CONFIG_SPL_BUILD */
>
> -static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
> +static void rkclk_init(struct rockchip_cru *cru, struct rk3288_grf *grf)
> {
> u32 aclk_div;
> u32 hclk_div;
> @@ -492,7 +492,7 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
> CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
> }
>
> -void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
> +void rk3288_clk_configure_cpu(struct rockchip_cru *cru, struct rk3288_grf *grf)
> {
> /* pll enter slow-mode */
> rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
> @@ -534,7 +534,7 @@ void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
> }
>
> /* Get pll rate by id */
> -static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
> +static uint32_t rkclk_pll_get_rate(struct rockchip_cru *cru,
> enum rk_clk_id clk_id)
> {
> uint32_t nr, no, nf;
> @@ -567,7 +567,7 @@ static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
> }
> }
>
> -static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
> +static ulong rockchip_mmc_get_clk(struct rockchip_cru *cru, uint gclk_rate,
> int periph)
> {
> uint src_rate;
> @@ -601,7 +601,7 @@ static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
> return DIV_TO_RATE(src_rate, div);
> }
>
> -static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
> +static ulong rockchip_mmc_set_clk(struct rockchip_cru *cru, uint gclk_rate,
> int periph, uint freq)
> {
> int src_clk_div;
> @@ -651,7 +651,7 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
> return rockchip_mmc_get_clk(cru, gclk_rate, periph);
> }
>
> -static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
> +static ulong rockchip_spi_get_clk(struct rockchip_cru *cru, uint gclk_rate,
> int periph)
> {
> uint div, mux;
> @@ -681,7 +681,7 @@ static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
> return DIV_TO_RATE(gclk_rate, div);
> }
>
> -static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
> +static ulong rockchip_spi_set_clk(struct rockchip_cru *cru, uint gclk_rate,
> int periph, uint freq)
> {
> int src_clk_div;
> @@ -715,7 +715,7 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
> return rockchip_spi_get_clk(cru, gclk_rate, periph);
> }
>
> -static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru)
> +static ulong rockchip_saradc_get_clk(struct rockchip_cru *cru)
> {
> u32 div, val;
>
> @@ -726,7 +726,7 @@ static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru)
> return DIV_TO_RATE(OSC_HZ, div);
> }
>
> -static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz)
> +static ulong rockchip_saradc_set_clk(struct rockchip_cru *cru, uint hz)
> {
> int src_clk_div;
>
> @@ -785,7 +785,7 @@ static ulong rk3288_clk_get_rate(struct clk *clk)
> static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
> {
> struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
> - struct rk3288_cru *cru = priv->cru;
> + struct rockchip_cru *cru = priv->cru;
> ulong new_rate, gclk_rate;
>
> gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
> @@ -892,7 +892,7 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
> static int __maybe_unused rk3288_gmac_set_parent(struct clk *clk, struct clk *parent)
> {
> struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
> - struct rk3288_cru *cru = priv->cru;
> + struct rockchip_cru *cru = priv->cru;
> const char *clock_output_name;
> int ret;
>
> @@ -1008,15 +1008,15 @@ static int rk3288_clk_bind(struct udevice *dev)
> debug("Warning: No sysreset driver: ret=%d\n", ret);
> } else {
> priv = malloc(sizeof(struct sysreset_reg));
> - priv->glb_srst_fst_value = offsetof(struct rk3288_cru,
> + priv->glb_srst_fst_value = offsetof(struct rockchip_cru,
> cru_glb_srst_fst_value);
> - priv->glb_srst_snd_value = offsetof(struct rk3288_cru,
> + priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
> cru_glb_srst_snd_value);
> sys_child->priv = priv;
> }
>
> #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
> - ret = offsetof(struct rk3288_cru, cru_softrst_con[0]);
> + ret = offsetof(struct rockchip_cru, cru_softrst_con[0]);
> ret = rockchip_reset_bind(dev, ret, 12);
> if (ret)
> debug("Warning: software reset driver bind faile\n");
> diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
> index 9020a9f202..37fc142a7a 100644
> --- a/drivers/clk/rockchip/clk_rk3399.c
> +++ b/drivers/clk/rockchip/clk_rk3399.c
> @@ -14,7 +14,7 @@
> #include <bitfield.h>
> #include <asm/io.h>
> #include <asm/arch-rockchip/clock.h>
> -#include <asm/arch-rockchip/cru_rk3399.h>
> +#include <asm/arch-rockchip/cru.h>
> #include <asm/arch-rockchip/hardware.h>
> #include <dm/lists.h>
> #include <dt-bindings/clock/rk3399-cru.h>
> @@ -418,7 +418,7 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div)
> return 0;
> }
>
> -void rk3399_configure_cpu_l(struct rk3399_cru *cru,
> +void rk3399_configure_cpu_l(struct rockchip_cru *cru,
> enum apll_l_frequencies apll_l_freq)
> {
> u32 aclkm_div;
> @@ -453,7 +453,7 @@ void rk3399_configure_cpu_l(struct rk3399_cru *cru,
> atclk_div << ATCLK_CORE_L_DIV_SHIFT);
> }
>
> -void rk3399_configure_cpu_b(struct rk3399_cru *cru,
> +void rk3399_configure_cpu_b(struct rockchip_cru *cru,
> enum apll_b_frequencies apll_b_freq)
> {
> u32 aclkm_div;
> @@ -505,7 +505,7 @@ void rk3399_configure_cpu_b(struct rk3399_cru *cru,
> #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \
> ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT)
>
> -static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id)
> +static ulong rk3399_i2c_get_clk(struct rockchip_cru *cru, ulong clk_id)
> {
> u32 div, con;
>
> @@ -542,7 +542,7 @@ static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id)
> return DIV_TO_RATE(GPLL_HZ, div);
> }
>
> -static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
> +static ulong rk3399_i2c_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
> {
> int src_clk_div;
>
> @@ -619,7 +619,7 @@ static const struct spi_clkreg spi_clkregs[] = {
> .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, },
> };
>
> -static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id)
> +static ulong rk3399_spi_get_clk(struct rockchip_cru *cru, ulong clk_id)
> {
> const struct spi_clkreg *spiclk = NULL;
> u32 div, val;
> @@ -641,7 +641,7 @@ static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id)
> return DIV_TO_RATE(GPLL_HZ, div);
> }
>
> -static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
> +static ulong rk3399_spi_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
> {
> const struct spi_clkreg *spiclk = NULL;
> int src_clk_div;
> @@ -668,7 +668,7 @@ static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
> return rk3399_spi_get_clk(cru, clk_id);
> }
>
> -static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
> +static ulong rk3399_vop_set_clk(struct rockchip_cru *cru, ulong clk_id, u32 hz)
> {
> struct pll_div vpll_config = {0};
> int aclk_vop = 198 * MHz;
> @@ -712,7 +712,7 @@ static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
> return hz;
> }
>
> -static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id)
> +static ulong rk3399_mmc_get_clk(struct rockchip_cru *cru, uint clk_id)
> {
> u32 div, con;
>
> @@ -739,7 +739,7 @@ static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id)
> return DIV_TO_RATE(GPLL_HZ, div);
> }
>
> -static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
> +static ulong rk3399_mmc_set_clk(struct rockchip_cru *cru,
> ulong clk_id, ulong set_rate)
> {
> int src_clk_div;
> @@ -792,7 +792,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
> return rk3399_mmc_get_clk(cru, clk_id);
> }
>
> -static ulong rk3399_gmac_set_clk(struct rk3399_cru *cru, ulong rate)
> +static ulong rk3399_gmac_set_clk(struct rockchip_cru *cru, ulong rate)
> {
> ulong ret;
>
> @@ -817,7 +817,7 @@ static ulong rk3399_gmac_set_clk(struct rk3399_cru *cru, ulong rate)
> }
>
> #define PMUSGRF_DDR_RGN_CON16 0xff330040
> -static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
> +static ulong rk3399_ddr_set_clk(struct rockchip_cru *cru,
> ulong set_rate)
> {
> struct pll_div dpll_cfg;
> @@ -863,7 +863,7 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
> return set_rate;
> }
>
> -static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru)
> +static ulong rk3399_saradc_get_clk(struct rockchip_cru *cru)
> {
> u32 div, val;
>
> @@ -874,7 +874,7 @@ static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru)
> return DIV_TO_RATE(OSC_HZ, div);
> }
>
> -static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz)
> +static ulong rk3399_saradc_set_clk(struct rockchip_cru *cru, uint hz)
> {
> int src_clk_div;
>
> @@ -1071,7 +1071,7 @@ static struct clk_ops rk3399_clk_ops = {
> };
>
> #ifdef CONFIG_SPL_BUILD
> -static void rkclk_init(struct rk3399_cru *cru)
> +static void rkclk_init(struct rockchip_cru *cru)
> {
> u32 aclk_div;
> u32 hclk_div;
> @@ -1188,15 +1188,15 @@ static int rk3399_clk_bind(struct udevice *dev)
> debug("Warning: No sysreset driver: ret=%d\n", ret);
> } else {
> priv = malloc(sizeof(struct sysreset_reg));
> - priv->glb_srst_fst_value = offsetof(struct rk3399_cru,
> + priv->glb_srst_fst_value = offsetof(struct rockchip_cru,
> glb_srst_fst_value);
> - priv->glb_srst_snd_value = offsetof(struct rk3399_cru,
> + priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
> glb_srst_snd_value);
> sys_child->priv = priv;
> }
>
> #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
> - ret = offsetof(struct rk3399_cru, softrst_con[0]);
> + ret = offsetof(struct rockchip_cru, softrst_con[0]);
> ret = rockchip_reset_bind(dev, ret, 21);
> if (ret)
> debug("Warning: software reset driver bind faile\n");
> diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c
> index 690751d074..fd5b204e1f 100644
> --- a/drivers/ram/rockchip/sdram_rk3288.c
> +++ b/drivers/ram/rockchip/sdram_rk3288.c
> @@ -16,7 +16,7 @@
> #include <syscon.h>
> #include <asm/io.h>
> #include <asm/arch-rockchip/clock.h>
> -#include <asm/arch-rockchip/cru_rk3288.h>
> +#include <asm/arch-rockchip/cru.h>
> #include <asm/arch-rockchip/ddr_rk3288.h>
> #include <asm/arch-rockchip/grf_rk3288.h>
> #include <asm/arch-rockchip/pmu_rk3288.h>
> @@ -36,7 +36,7 @@ struct dram_info {
> struct chan_info chan[2];
> struct ram_info info;
> struct clk ddr_clk;
> - struct rk3288_cru *cru;
> + struct rockchip_cru *cru;
> struct rk3288_grf *grf;
> struct rk3288_sgrf *sgrf;
> struct rk3288_pmu *pmu;
> @@ -92,7 +92,7 @@ static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
> }
> }
>
> -static void ddr_reset(struct rk3288_cru *cru, u32 ch, u32 ctl, u32 phy)
> +static void ddr_reset(struct rockchip_cru *cru, u32 ch, u32 ctl, u32 phy)
> {
> u32 phy_ctl_srstn_shift = 4 + 5 * ch;
> u32 ctl_psrstn_shift = 3 + 5 * ch;
> @@ -109,7 +109,7 @@ static void ddr_reset(struct rk3288_cru *cru, u32 ch, u32 ctl, u32 phy)
> phy << phy_srstn_shift);
> }
>
> -static void ddr_phy_ctl_reset(struct rk3288_cru *cru, u32 ch, u32 n)
> +static void ddr_phy_ctl_reset(struct rockchip_cru *cru, u32 ch, u32 n)
> {
> u32 phy_ctl_srstn_shift = 4 + 5 * ch;
>
> @@ -117,7 +117,7 @@ static void ddr_phy_ctl_reset(struct rk3288_cru *cru, u32 ch, u32 n)
> 1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift);
> }
>
> -static void phy_pctrl_reset(struct rk3288_cru *cru,
> +static void phy_pctrl_reset(struct rockchip_cru *cru,
> struct rk3288_ddr_publ *publ,
> int channel)
> {
> diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
> index 7b2bba03fe..08bf0393a7 100644
> --- a/drivers/ram/rockchip/sdram_rk3399.c
> +++ b/drivers/ram/rockchip/sdram_rk3399.c
> @@ -14,7 +14,7 @@
> #include <syscon.h>
> #include <asm/io.h>
> #include <asm/arch-rockchip/clock.h>
> -#include <asm/arch-rockchip/cru_rk3399.h>
> +#include <asm/arch-rockchip/cru.h>
> #include <asm/arch-rockchip/grf_rk3399.h>
> #include <asm/arch-rockchip/pmu_rk3399.h>
> #include <asm/arch-rockchip/hardware.h>
> @@ -66,7 +66,7 @@ struct dram_info {
> u32 pwrup_srefresh_exit[2];
> struct chan_info chan[2];
> struct clk ddr_clk;
> - struct rk3399_cru *cru;
> + struct rockchip_cru *cru;
> struct rk3399_grf_regs *grf;
> struct rk3399_pmu_regs *pmu;
> struct rk3399_pmucru *pmucru;
> @@ -228,7 +228,7 @@ static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
> return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc1_con0;
> }
>
> -static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl,
> +static void rkclk_ddr_reset(struct rockchip_cru *cru, u32 channel, u32 ctl,
> u32 phy)
> {
> channel &= 0x1;
> @@ -239,7 +239,7 @@ static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl,
> &cru->softrst_con[4]);
> }
>
> -static void phy_pctrl_reset(struct rk3399_cru *cru, u32 channel)
> +static void phy_pctrl_reset(struct rockchip_cru *cru, u32 channel)
> {
> rkclk_ddr_reset(cru, channel, 1, 1);
> udelay(10);
> @@ -2945,7 +2945,7 @@ static int sdram_init(struct dram_info *dram,
> for (channel = 0; channel < 2; channel++) {
> const struct chan_info *chan =
> &dram->chan[channel];
> - struct rk3399_cru *cru = dram->cru;
> + struct rockchip_cru *cru = dram->cru;
> struct rk3399_ddr_publ_regs *publ = chan->publ;
>
> phy_pctrl_reset(cru, channel);
> diff --git a/drivers/video/rockchip/rk3288_mipi.c b/drivers/video/rockchip/rk3288_mipi.c
> index 7c4a4cc53b..65891ce45c 100644
> --- a/drivers/video/rockchip/rk3288_mipi.c
> +++ b/drivers/video/rockchip/rk3288_mipi.c
> @@ -18,7 +18,7 @@
> #include <dm/uclass-internal.h>
> #include <linux/kernel.h>
> #include <asm/arch-rockchip/clock.h>
> -#include <asm/arch-rockchip/cru_rk3288.h>
> +#include <asm/arch-rockchip/cru.h>
> #include <asm/arch-rockchip/grf_rk3288.h>
> #include <asm/arch-rockchip/hardware.h>
> #include <asm/arch-rockchip/rockchip_mipi_dsi.h>
> diff --git a/drivers/video/rockchip/rk3399_mipi.c b/drivers/video/rockchip/rk3399_mipi.c
> index a93b73400b..a5b7ba69a8 100644
> --- a/drivers/video/rockchip/rk3399_mipi.c
> +++ b/drivers/video/rockchip/rk3399_mipi.c
> @@ -18,7 +18,7 @@
> #include <dm/uclass-internal.h>
> #include <linux/kernel.h>
> #include <asm/arch-rockchip/clock.h>
> -#include <asm/arch-rockchip/cru_rk3399.h>
> +#include <asm/arch-rockchip/cru.h>
> #include <asm/arch-rockchip/grf_rk3399.h>
> #include <asm/arch-rockchip/hardware.h>
> #include <asm/arch-rockchip/rockchip_mipi_dsi.h>
> diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c
> index bcd039b7bc..f9280e8607 100644
> --- a/drivers/video/rockchip/rk_mipi.c
> +++ b/drivers/video/rockchip/rk_mipi.c
> @@ -18,7 +18,7 @@
> #include <dm/uclass-internal.h>
> #include <linux/kernel.h>
> #include <asm/arch-rockchip/clock.h>
> -#include <asm/arch-rockchip/cru_rk3399.h>
> +#include <asm/arch-rockchip/cru.h>
> #include <asm/arch-rockchip/grf_rk3399.h>
> #include <asm/arch-rockchip/rockchip_mipi_dsi.h>
>
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2020-01-07 9:45 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-12-29 19:07 [PATCH v3 0/5] rk3399: Add redundant boot support Jagan Teki
2019-12-29 19:07 ` Jagan Teki
[not found] ` <20191229190726.29266-1-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
2019-12-29 19:07 ` [PATCH v3 1/5] rockchip: Add cpu-info Jagan Teki
2019-12-29 19:07 ` Jagan Teki
2019-12-29 19:07 ` [PATCH v3 2/5] rockchip: rk3399: Enable DISPLAY_CPUINFO Jagan Teki
2019-12-29 19:07 ` Jagan Teki
2020-01-06 9:23 ` Kever Yang
2020-01-06 9:23 ` Kever Yang
2019-12-29 19:07 ` [PATCH v3 3/5] arm: rockchip: Add common cru.h Jagan Teki
2019-12-29 19:07 ` Jagan Teki
2020-01-06 9:24 ` Kever Yang
2020-01-06 9:24 ` Kever Yang
2020-01-07 9:45 ` Kever Yang
2019-12-29 19:07 ` [PATCH v3 4/5] rockchip: Add common reset cause Jagan Teki
2019-12-29 19:07 ` Jagan Teki
2020-01-06 9:24 ` Kever Yang
2020-01-06 9:24 ` Kever Yang
2019-12-29 19:07 ` [PATCH v3 5/5] rockchip: rk3399: Add bootcount support Jagan Teki
2019-12-29 19:07 ` Jagan Teki
[not found] ` <20191229190726.29266-6-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
2020-01-06 9:25 ` Kever Yang
2020-01-06 9:25 ` Kever Yang
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