* Rework DF to prepare for VBIOS that turns on channel hashing
@ 2020-01-10 2:02 Joseph Greathouse
2020-01-10 2:02 ` [PATCH 1/3] drm/amdgpu: Create generic DF struct in adev Joseph Greathouse
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Joseph Greathouse @ 2020-01-10 2:02 UTC (permalink / raw)
To: amd-gfx
When we start receiving Arcturus VBIOS that turns on channel hashing in the data fabric, we need to make sure that the texture cache's channel hashing setting match up. To do this, we query the DF's settings and cache them in adev, then mirror them into the cache confirmation on init.
This requires some rework of adev. Rather than just holding some function pointers, this series adds in a new DF data structure which will contain
the function pointer struct as well as any new structs we need. It then adds in the structs for holding the DF's current hash settings info.
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^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/3] drm/amdgpu: Create generic DF struct in adev
2020-01-10 2:02 Rework DF to prepare for VBIOS that turns on channel hashing Joseph Greathouse
@ 2020-01-10 2:02 ` Joseph Greathouse
2020-01-10 14:39 ` Alex Deucher
2020-01-10 2:02 ` [PATCH 2/3] drm/amdgpu: add defines for DF and TCP Hashing Joseph Greathouse
2020-01-10 2:02 ` [PATCH 3/3] drm/amdgpu: Match TC hash settings to DF settings Joseph Greathouse
2 siblings, 1 reply; 5+ messages in thread
From: Joseph Greathouse @ 2020-01-10 2:02 UTC (permalink / raw)
To: amd-gfx; +Cc: Joseph Greathouse
The only data fabric information the adev struct currently
contains is a function pointer table. In the near future,
we will be adding some cached DF information into adev. As
such, this patch creates a new amdgpu_df struct for adev
to old. Right now, it only containst the old function pointer
table, but new stuff will be added soon.
Change-Id: I0359344297a740782efd35e902f9638bc9e67da8
Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 29 ++---------
drivers/gpu/drm/amd/amdgpu/amdgpu_df.h | 62 ++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c | 12 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 6 +--
drivers/gpu/drm/amd/amdgpu/df_v1_7.c | 6 +--
drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 6 +--
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 +--
drivers/gpu/drm/amd/amdgpu/soc15.c | 12 ++---
8 files changed, 90 insertions(+), 49 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_df.h
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 863bf45ba198..63eab0c135db 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -91,6 +91,7 @@
#include "amdgpu_umc.h"
#include "amdgpu_mmhub.h"
#include "amdgpu_tmz.h"
+#include "amdgpu_df.h"
#define MAX_GPU_INSTANCE 16
@@ -670,29 +671,6 @@ struct amdgpu_mmio_remap {
resource_size_t bus_addr;
};
-struct amdgpu_df_funcs {
- void (*sw_init)(struct amdgpu_device *adev);
- void (*sw_fini)(struct amdgpu_device *adev);
- void (*enable_broadcast_mode)(struct amdgpu_device *adev,
- bool enable);
- u32 (*get_fb_channel_number)(struct amdgpu_device *adev);
- u32 (*get_hbm_channel_number)(struct amdgpu_device *adev);
- void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
- bool enable);
- void (*get_clockgating_state)(struct amdgpu_device *adev,
- u32 *flags);
- void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,
- bool enable);
- int (*pmc_start)(struct amdgpu_device *adev, uint64_t config,
- int is_enable);
- int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config,
- int is_disable);
- void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config,
- uint64_t *count);
- uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val);
- void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val,
- uint32_t ficadl_val, uint32_t ficadh_val);
-};
/* Define the HW IP blocks will be used in driver , add more if necessary */
enum amd_hw_ip_block_type {
GC_HWIP = 1,
@@ -939,6 +917,9 @@ struct amdgpu_device {
/* tmz */
struct amdgpu_tmz tmz;
+ /* df */
+ struct amdgpu_df df;
+
struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
int num_ip_blocks;
struct mutex mn_lock;
@@ -952,8 +933,6 @@ struct amdgpu_device {
/* soc15 register offset based on ip, instance and segment */
uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
- const struct amdgpu_df_funcs *df_funcs;
-
/* delayed work_func for deferring clockgating during resume */
struct delayed_work delayed_init_work;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_df.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_df.h
new file mode 100644
index 000000000000..61a26c15c8dd
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_df.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __AMDGPU_DF_H__
+#define __AMDGPU_DF_H__
+
+struct amdgpu_df_hash_status {
+ bool hash_64k;
+ bool hash_2m;
+ bool hash_1g;
+};
+
+struct amdgpu_df_funcs {
+ void (*sw_init)(struct amdgpu_device *adev);
+ void (*sw_fini)(struct amdgpu_device *adev);
+ void (*enable_broadcast_mode)(struct amdgpu_device *adev,
+ bool enable);
+ u32 (*get_fb_channel_number)(struct amdgpu_device *adev);
+ u32 (*get_hbm_channel_number)(struct amdgpu_device *adev);
+ void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
+ bool enable);
+ void (*get_clockgating_state)(struct amdgpu_device *adev,
+ u32 *flags);
+ void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,
+ bool enable);
+ int (*pmc_start)(struct amdgpu_device *adev, uint64_t config,
+ int is_enable);
+ int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config,
+ int is_disable);
+ void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config,
+ uint64_t *count);
+ uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val);
+ void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val,
+ uint32_t ficadl_val, uint32_t ficadh_val);
+};
+
+struct amdgpu_df {
+ struct amdgpu_df_hash_status hash_status;
+ const struct amdgpu_df_funcs *funcs;
+};
+
+#endif /* __AMDGPU_DF_H__ */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
index cf21ad0cad9a..07914e34bc25 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
@@ -74,9 +74,9 @@ static void amdgpu_perf_start(struct perf_event *event, int flags)
switch (pe->pmu_perf_type) {
case PERF_TYPE_AMDGPU_DF:
if (!(flags & PERF_EF_RELOAD))
- pe->adev->df_funcs->pmc_start(pe->adev, hwc->conf, 1);
+ pe->adev->df.funcs->pmc_start(pe->adev, hwc->conf, 1);
- pe->adev->df_funcs->pmc_start(pe->adev, hwc->conf, 0);
+ pe->adev->df.funcs->pmc_start(pe->adev, hwc->conf, 0);
break;
default:
break;
@@ -101,7 +101,7 @@ static void amdgpu_perf_read(struct perf_event *event)
switch (pe->pmu_perf_type) {
case PERF_TYPE_AMDGPU_DF:
- pe->adev->df_funcs->pmc_get_count(pe->adev, hwc->conf,
+ pe->adev->df.funcs->pmc_get_count(pe->adev, hwc->conf,
&count);
break;
default:
@@ -126,7 +126,7 @@ static void amdgpu_perf_stop(struct perf_event *event, int flags)
switch (pe->pmu_perf_type) {
case PERF_TYPE_AMDGPU_DF:
- pe->adev->df_funcs->pmc_stop(pe->adev, hwc->conf, 0);
+ pe->adev->df.funcs->pmc_stop(pe->adev, hwc->conf, 0);
break;
default:
break;
@@ -156,7 +156,7 @@ static int amdgpu_perf_add(struct perf_event *event, int flags)
switch (pe->pmu_perf_type) {
case PERF_TYPE_AMDGPU_DF:
- retval = pe->adev->df_funcs->pmc_start(pe->adev, hwc->conf, 1);
+ retval = pe->adev->df.funcs->pmc_start(pe->adev, hwc->conf, 1);
break;
default:
return 0;
@@ -184,7 +184,7 @@ static void amdgpu_perf_del(struct perf_event *event, int flags)
switch (pe->pmu_perf_type) {
case PERF_TYPE_AMDGPU_DF:
- pe->adev->df_funcs->pmc_stop(pe->adev, hwc->conf, 1);
+ pe->adev->df.funcs->pmc_stop(pe->adev, hwc->conf, 1);
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index c626f3e59ff9..a97af422575a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
@@ -146,16 +146,16 @@ static ssize_t amdgpu_xgmi_show_error(struct device *dev,
ficaa_pie_ctl_in = AMDGPU_XGMI_SET_FICAA(0x200);
ficaa_pie_status_in = AMDGPU_XGMI_SET_FICAA(0x208);
- fica_out = adev->df_funcs->get_fica(adev, ficaa_pie_ctl_in);
+ fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_ctl_in);
if (fica_out != 0x1f)
pr_err("xGMI error counters not enabled!\n");
- fica_out = adev->df_funcs->get_fica(adev, ficaa_pie_status_in);
+ fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_status_in);
if ((fica_out & 0xffff) == 2)
error_count = ((fica_out >> 62) & 0x1) + (fica_out >> 63);
- adev->df_funcs->set_fica(adev, ficaa_pie_status_in, 0, 0);
+ adev->df.funcs->set_fica(adev, ficaa_pie_status_in, 0, 0);
return snprintf(buf, PAGE_SIZE, "%d\n", error_count);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/df_v1_7.c b/drivers/gpu/drm/amd/amdgpu/df_v1_7.c
index d6221298b477..03fdeef568d9 100644
--- a/drivers/gpu/drm/amd/amdgpu/df_v1_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/df_v1_7.c
@@ -66,7 +66,7 @@ static u32 df_v1_7_get_hbm_channel_number(struct amdgpu_device *adev)
{
int fb_channel_number;
- fb_channel_number = adev->df_funcs->get_fb_channel_number(adev);
+ fb_channel_number = adev->df.funcs->get_fb_channel_number(adev);
return df_v1_7_channel_number[fb_channel_number];
}
@@ -77,7 +77,7 @@ static void df_v1_7_update_medium_grain_clock_gating(struct amdgpu_device *adev,
u32 tmp;
/* Put DF on broadcast mode */
- adev->df_funcs->enable_broadcast_mode(adev, true);
+ adev->df.funcs->enable_broadcast_mode(adev, true);
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
@@ -92,7 +92,7 @@ static void df_v1_7_update_medium_grain_clock_gating(struct amdgpu_device *adev,
}
/* Exit boradcast mode */
- adev->df_funcs->enable_broadcast_mode(adev, false);
+ adev->df.funcs->enable_broadcast_mode(adev, false);
}
static void df_v1_7_get_clockgating_state(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
index 2f884d941e8d..7bd29d97adfe 100644
--- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
@@ -311,7 +311,7 @@ static u32 df_v3_6_get_hbm_channel_number(struct amdgpu_device *adev)
{
int fb_channel_number;
- fb_channel_number = adev->df_funcs->get_fb_channel_number(adev);
+ fb_channel_number = adev->df.funcs->get_fb_channel_number(adev);
if (fb_channel_number >= ARRAY_SIZE(df_v3_6_channel_number))
fb_channel_number = 0;
@@ -325,7 +325,7 @@ static void df_v3_6_update_medium_grain_clock_gating(struct amdgpu_device *adev,
if (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG) {
/* Put DF on broadcast mode */
- adev->df_funcs->enable_broadcast_mode(adev, true);
+ adev->df.funcs->enable_broadcast_mode(adev, true);
if (enable) {
tmp = RREG32_SOC15(DF, 0,
@@ -344,7 +344,7 @@ static void df_v3_6_update_medium_grain_clock_gating(struct amdgpu_device *adev,
}
/* Exit broadcast mode */
- adev->df_funcs->enable_broadcast_mode(adev, false);
+ adev->df.funcs->enable_broadcast_mode(adev, false);
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 26194ac9af98..b83c8d745f42 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -817,8 +817,8 @@ static int gmc_v9_0_late_init(void *handle)
r = amdgpu_atomfirmware_mem_ecc_supported(adev);
if (!r) {
DRM_INFO("ECC is not present.\n");
- if (adev->df_funcs->enable_ecc_force_par_wr_rmw)
- adev->df_funcs->enable_ecc_force_par_wr_rmw(adev, false);
+ if (adev->df.funcs->enable_ecc_force_par_wr_rmw)
+ adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false);
} else {
DRM_INFO("ECC is active.\n");
}
@@ -1023,7 +1023,7 @@ static int gmc_v9_0_sw_init(void *handle)
else
chansize = 128;
- numchan = adev->df_funcs->get_hbm_channel_number(adev);
+ numchan = adev->df.funcs->get_hbm_channel_number(adev);
adev->gmc.vram_width = numchan * chansize;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 6c75021dda0f..317803f6a561 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -677,9 +677,9 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
}
if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
- adev->df_funcs = &df_v3_6_funcs;
+ adev->df.funcs = &df_v3_6_funcs;
else
- adev->df_funcs = &df_v1_7_funcs;
+ adev->df.funcs = &df_v1_7_funcs;
adev->rev_id = soc15_get_rev_id(adev);
adev->nbio.funcs->detect_hw_virt(adev);
@@ -1247,7 +1247,7 @@ static int soc15_common_sw_init(void *handle)
if (amdgpu_sriov_vf(adev))
xgpu_ai_mailbox_add_irq_id(adev);
- adev->df_funcs->sw_init(adev);
+ adev->df.funcs->sw_init(adev);
return 0;
}
@@ -1257,7 +1257,7 @@ static int soc15_common_sw_fini(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
amdgpu_nbio_ras_fini(adev);
- adev->df_funcs->sw_fini(adev);
+ adev->df.funcs->sw_fini(adev);
return 0;
}
@@ -1478,7 +1478,7 @@ static int soc15_common_set_clockgating_state(void *handle,
state == AMD_CG_STATE_GATE ? true : false);
soc15_update_rom_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE ? true : false);
- adev->df_funcs->update_medium_grain_clock_gating(adev,
+ adev->df.funcs->update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE ? true : false);
break;
case CHIP_RAVEN:
@@ -1536,7 +1536,7 @@ static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
*flags |= AMD_CG_SUPPORT_ROM_MGCG;
- adev->df_funcs->get_clockgating_state(adev, flags);
+ adev->df.funcs->get_clockgating_state(adev, flags);
}
static int soc15_common_set_powergating_state(void *handle,
--
2.19.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/3] drm/amdgpu: add defines for DF and TCP Hashing
2020-01-10 2:02 Rework DF to prepare for VBIOS that turns on channel hashing Joseph Greathouse
2020-01-10 2:02 ` [PATCH 1/3] drm/amdgpu: Create generic DF struct in adev Joseph Greathouse
@ 2020-01-10 2:02 ` Joseph Greathouse
2020-01-10 2:02 ` [PATCH 3/3] drm/amdgpu: Match TC hash settings to DF settings Joseph Greathouse
2 siblings, 0 replies; 5+ messages in thread
From: Joseph Greathouse @ 2020-01-10 2:02 UTC (permalink / raw)
To: amd-gfx; +Cc: Joseph Greathouse
On Arcturus, we need TC channel hashing, which is set by the
driver, to match DF hashing, which is set by VBIOS. To match
these, we plan to query the DF information and then properly
set the TC configuration bits to match them.
This patch adds the required fields to register definitions
in preparation for a future patch which will use them.
Change-Id: Ia405ee9aeec6fc22303a7376ec3d714e3f93af1d
Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com>
---
drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h | 3 +++
drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h | 8 ++++++++
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h | 6 ++++++
3 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h
index f301e5fe2109..32a336a450ae 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h
@@ -27,6 +27,9 @@
#define mmDF_PIE_AON0_DfGlobalClkGater 0x00fc
#define mmDF_PIE_AON0_DfGlobalClkGater_BASE_IDX 0
+#define mmDF_CS_UMC_AON0_DfGlobalCtrl 0x00fe
+#define mmDF_CS_UMC_AON0_DfGlobalCtrl_BASE_IDX 0
+
#define mmDF_CS_UMC_AON0_DramBaseAddress0 0x0044
#define mmDF_CS_UMC_AON0_DramBaseAddress0_BASE_IDX 0
diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h
index 06fac509e987..65e9f756e86e 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h
@@ -33,6 +33,14 @@
#define DF_PIE_AON0_DfGlobalClkGater__MGCGMode__SHIFT 0x0
#define DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK 0x0000000FL
+/* DF_CS_UMC_AON0_DfGlobalCtrl */
+#define DF_CS_UMC_AON0_DfGlobalCtrl__GlbHashIntlvCtl64K__SHIFT 0x14
+#define DF_CS_UMC_AON0_DfGlobalCtrl__GlbHashIntlvCtl2M__SHIFT 0x15
+#define DF_CS_UMC_AON0_DfGlobalCtrl__GlbHashIntlvCtl1G__SHIFT 0x16
+#define DF_CS_UMC_AON0_DfGlobalCtrl__GlbHashIntlvCtl64K_MASK 0x00100000L
+#define DF_CS_UMC_AON0_DfGlobalCtrl__GlbHashIntlvCtl2M_MASK 0x00200000L
+#define DF_CS_UMC_AON0_DfGlobalCtrl__GlbHashIntlvCtl1G_MASK 0x00400000L
+
/* DF_CS_AON0_DramBaseAddress0 */
#define DF_CS_UMC_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0
#define DF_CS_UMC_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
index d4c613a85352..c9e3f6d849a8 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
@@ -8739,10 +8739,16 @@
#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x4
#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x6
#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x9
+#define TCP_ADDR_CONFIG__ENABLE64KHASH__SHIFT 0xb
+#define TCP_ADDR_CONFIG__ENABLE2MHASH__SHIFT 0xc
+#define TCP_ADDR_CONFIG__ENABLE1GHASH__SHIFT 0xd
#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0x0000000FL
#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x00000030L
#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x000001C0L
#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x00000200L
+#define TCP_ADDR_CONFIG__ENABLE64KHASH_MASK 0x00000800L
+#define TCP_ADDR_CONFIG__ENABLE2MHASH_MASK 0x00001000L
+#define TCP_ADDR_CONFIG__ENABLE1GHASH_MASK 0x00002000L
//TCP_CREDIT
#define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x0
#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x10
--
2.19.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 3/3] drm/amdgpu: Match TC hash settings to DF settings
2020-01-10 2:02 Rework DF to prepare for VBIOS that turns on channel hashing Joseph Greathouse
2020-01-10 2:02 ` [PATCH 1/3] drm/amdgpu: Create generic DF struct in adev Joseph Greathouse
2020-01-10 2:02 ` [PATCH 2/3] drm/amdgpu: add defines for DF and TCP Hashing Joseph Greathouse
@ 2020-01-10 2:02 ` Joseph Greathouse
2 siblings, 0 replies; 5+ messages in thread
From: Joseph Greathouse @ 2020-01-10 2:02 UTC (permalink / raw)
To: amd-gfx; +Cc: Joseph Greathouse
On Arcturus, data fabric hashing is set by the VBIOS, and
affects which addresses map to which memory channels. The
gfx core's caches also need to know this mapping, but the
hash settings for these these caches is set by the driver.
This change queries the DF to understand how the VBIOS
configured DF, then matches the TC hash configuration bits
to do the same thing.
Change-Id: I01e9e73ce6c89ea340925b4a1b895889ac152ec3
Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com>
---
drivers/gpu/drm/amd/amdgpu/df_v1_7.c | 3 +++
drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 28 +++++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 19 ++++++++++++++++++
3 files changed, 50 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/df_v1_7.c b/drivers/gpu/drm/amd/amdgpu/df_v1_7.c
index 03fdeef568d9..d6aca1c08068 100644
--- a/drivers/gpu/drm/amd/amdgpu/df_v1_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/df_v1_7.c
@@ -31,6 +31,9 @@ static u32 df_v1_7_channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
static void df_v1_7_sw_init(struct amdgpu_device *adev)
{
+ adev->df.hash_status.hash_64k = false;
+ adev->df.hash_status.hash_2m = false;
+ adev->df.hash_status.hash_1g = false;
}
static void df_v1_7_sw_fini(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
index 7bd29d97adfe..3761c8cc1156 100644
--- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
@@ -262,6 +262,32 @@ static ssize_t df_v3_6_get_df_cntr_avail(struct device *dev,
/* device attr for available perfmon counters */
static DEVICE_ATTR(df_cntr_avail, S_IRUGO, df_v3_6_get_df_cntr_avail, NULL);
+static void df_v3_6_query_hashes(struct amdgpu_device *adev)
+{
+ u32 chan_cfg, tmp;
+
+ adev->df.hash_status.hash_64k = false;
+ adev->df.hash_status.hash_2m = false;
+ adev->df.hash_status.hash_1g = false;
+
+ if (adev->asic_type != CHIP_ARCTURUS)
+ return;
+
+ /* encoding for hash-enabled on Arcturus */
+ if (adev->df.funcs->get_fb_channel_number(adev) == 0xe) {
+ tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DfGlobalCtrl);
+ adev->df.hash_status.hash_64k = REG_GET_FIELD(tmp,
+ DF_CS_UMC_AON0_DfGlobalCtrl,
+ GlbHashIntlvCtl64K);
+ adev->df.hash_status.hash_2m = REG_GET_FIELD(tmp,
+ DF_CS_UMC_AON0_DfGlobalCtrl,
+ GlbHashIntlvCtl2M);
+ adev->df.hash_status.hash_1g = REG_GET_FIELD(tmp,
+ DF_CS_UMC_AON0_DfGlobalCtrl,
+ GlbHashIntlvCtl1G);
+ }
+}
+
/* init perfmons */
static void df_v3_6_sw_init(struct amdgpu_device *adev)
{
@@ -273,6 +299,8 @@ static void df_v3_6_sw_init(struct amdgpu_device *adev)
for (i = 0; i < AMDGPU_MAX_DF_PERFMONS; i++)
adev->df_perfmon_config_assign_mask[i] = 0;
+
+ df_v3_6_query_hashes(adev);
}
static void df_v3_6_sw_fini(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index ce2b02dc7b64..e3d466bd5c4e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3637,6 +3637,23 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
return 0;
}
+static void gfx_v9_0_init_tcp_config(struct amdgpu_device *adev)
+{
+ u32 tmp;
+
+ if (adev->asic_type != CHIP_ARCTURUS)
+ return;
+
+ tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG);
+ tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE64KHASH,
+ adev->df.hash_status.hash_64k);
+ tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE2MHASH,
+ adev->df.hash_status.hash_2m);
+ tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE1GHASH,
+ adev->df.hash_status.hash_1g);
+ WREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG, tmp);
+}
+
static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
{
if (adev->asic_type != CHIP_ARCTURUS)
@@ -3654,6 +3671,8 @@ static int gfx_v9_0_hw_init(void *handle)
gfx_v9_0_constants_init(adev);
+ gfx_v9_0_init_tcp_config(adev);
+
r = adev->gfx.rlc.funcs->resume(adev);
if (r)
return r;
--
2.19.1
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/3] drm/amdgpu: Create generic DF struct in adev
2020-01-10 2:02 ` [PATCH 1/3] drm/amdgpu: Create generic DF struct in adev Joseph Greathouse
@ 2020-01-10 14:39 ` Alex Deucher
0 siblings, 0 replies; 5+ messages in thread
From: Alex Deucher @ 2020-01-10 14:39 UTC (permalink / raw)
To: Joseph Greathouse; +Cc: amd-gfx list
On Thu, Jan 9, 2020 at 9:34 PM Joseph Greathouse
<Joseph.Greathouse@amd.com> wrote:
>
> The only data fabric information the adev struct currently
> contains is a function pointer table. In the near future,
> we will be adding some cached DF information into adev. As
> such, this patch creates a new amdgpu_df struct for adev
> to old. Right now, it only containst the old function pointer
> table, but new stuff will be added soon.
>
> Change-Id: I0359344297a740782efd35e902f9638bc9e67da8
> Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com>
Series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 29 ++---------
> drivers/gpu/drm/amd/amdgpu/amdgpu_df.h | 62 ++++++++++++++++++++++++
> drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c | 12 ++---
> drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 6 +--
> drivers/gpu/drm/amd/amdgpu/df_v1_7.c | 6 +--
> drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 6 +--
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 +--
> drivers/gpu/drm/amd/amdgpu/soc15.c | 12 ++---
> 8 files changed, 90 insertions(+), 49 deletions(-)
> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_df.h
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 863bf45ba198..63eab0c135db 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -91,6 +91,7 @@
> #include "amdgpu_umc.h"
> #include "amdgpu_mmhub.h"
> #include "amdgpu_tmz.h"
> +#include "amdgpu_df.h"
>
> #define MAX_GPU_INSTANCE 16
>
> @@ -670,29 +671,6 @@ struct amdgpu_mmio_remap {
> resource_size_t bus_addr;
> };
>
> -struct amdgpu_df_funcs {
> - void (*sw_init)(struct amdgpu_device *adev);
> - void (*sw_fini)(struct amdgpu_device *adev);
> - void (*enable_broadcast_mode)(struct amdgpu_device *adev,
> - bool enable);
> - u32 (*get_fb_channel_number)(struct amdgpu_device *adev);
> - u32 (*get_hbm_channel_number)(struct amdgpu_device *adev);
> - void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
> - bool enable);
> - void (*get_clockgating_state)(struct amdgpu_device *adev,
> - u32 *flags);
> - void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,
> - bool enable);
> - int (*pmc_start)(struct amdgpu_device *adev, uint64_t config,
> - int is_enable);
> - int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config,
> - int is_disable);
> - void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config,
> - uint64_t *count);
> - uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val);
> - void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val,
> - uint32_t ficadl_val, uint32_t ficadh_val);
> -};
> /* Define the HW IP blocks will be used in driver , add more if necessary */
> enum amd_hw_ip_block_type {
> GC_HWIP = 1,
> @@ -939,6 +917,9 @@ struct amdgpu_device {
> /* tmz */
> struct amdgpu_tmz tmz;
>
> + /* df */
> + struct amdgpu_df df;
> +
> struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
> int num_ip_blocks;
> struct mutex mn_lock;
> @@ -952,8 +933,6 @@ struct amdgpu_device {
> /* soc15 register offset based on ip, instance and segment */
> uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
>
> - const struct amdgpu_df_funcs *df_funcs;
> -
> /* delayed work_func for deferring clockgating during resume */
> struct delayed_work delayed_init_work;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_df.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_df.h
> new file mode 100644
> index 000000000000..61a26c15c8dd
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_df.h
> @@ -0,0 +1,62 @@
> +/*
> + * Copyright 2020 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +
> +#ifndef __AMDGPU_DF_H__
> +#define __AMDGPU_DF_H__
> +
> +struct amdgpu_df_hash_status {
> + bool hash_64k;
> + bool hash_2m;
> + bool hash_1g;
> +};
> +
> +struct amdgpu_df_funcs {
> + void (*sw_init)(struct amdgpu_device *adev);
> + void (*sw_fini)(struct amdgpu_device *adev);
> + void (*enable_broadcast_mode)(struct amdgpu_device *adev,
> + bool enable);
> + u32 (*get_fb_channel_number)(struct amdgpu_device *adev);
> + u32 (*get_hbm_channel_number)(struct amdgpu_device *adev);
> + void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
> + bool enable);
> + void (*get_clockgating_state)(struct amdgpu_device *adev,
> + u32 *flags);
> + void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,
> + bool enable);
> + int (*pmc_start)(struct amdgpu_device *adev, uint64_t config,
> + int is_enable);
> + int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config,
> + int is_disable);
> + void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config,
> + uint64_t *count);
> + uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val);
> + void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val,
> + uint32_t ficadl_val, uint32_t ficadh_val);
> +};
> +
> +struct amdgpu_df {
> + struct amdgpu_df_hash_status hash_status;
> + const struct amdgpu_df_funcs *funcs;
> +};
> +
> +#endif /* __AMDGPU_DF_H__ */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
> index cf21ad0cad9a..07914e34bc25 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
> @@ -74,9 +74,9 @@ static void amdgpu_perf_start(struct perf_event *event, int flags)
> switch (pe->pmu_perf_type) {
> case PERF_TYPE_AMDGPU_DF:
> if (!(flags & PERF_EF_RELOAD))
> - pe->adev->df_funcs->pmc_start(pe->adev, hwc->conf, 1);
> + pe->adev->df.funcs->pmc_start(pe->adev, hwc->conf, 1);
>
> - pe->adev->df_funcs->pmc_start(pe->adev, hwc->conf, 0);
> + pe->adev->df.funcs->pmc_start(pe->adev, hwc->conf, 0);
> break;
> default:
> break;
> @@ -101,7 +101,7 @@ static void amdgpu_perf_read(struct perf_event *event)
>
> switch (pe->pmu_perf_type) {
> case PERF_TYPE_AMDGPU_DF:
> - pe->adev->df_funcs->pmc_get_count(pe->adev, hwc->conf,
> + pe->adev->df.funcs->pmc_get_count(pe->adev, hwc->conf,
> &count);
> break;
> default:
> @@ -126,7 +126,7 @@ static void amdgpu_perf_stop(struct perf_event *event, int flags)
>
> switch (pe->pmu_perf_type) {
> case PERF_TYPE_AMDGPU_DF:
> - pe->adev->df_funcs->pmc_stop(pe->adev, hwc->conf, 0);
> + pe->adev->df.funcs->pmc_stop(pe->adev, hwc->conf, 0);
> break;
> default:
> break;
> @@ -156,7 +156,7 @@ static int amdgpu_perf_add(struct perf_event *event, int flags)
>
> switch (pe->pmu_perf_type) {
> case PERF_TYPE_AMDGPU_DF:
> - retval = pe->adev->df_funcs->pmc_start(pe->adev, hwc->conf, 1);
> + retval = pe->adev->df.funcs->pmc_start(pe->adev, hwc->conf, 1);
> break;
> default:
> return 0;
> @@ -184,7 +184,7 @@ static void amdgpu_perf_del(struct perf_event *event, int flags)
>
> switch (pe->pmu_perf_type) {
> case PERF_TYPE_AMDGPU_DF:
> - pe->adev->df_funcs->pmc_stop(pe->adev, hwc->conf, 1);
> + pe->adev->df.funcs->pmc_stop(pe->adev, hwc->conf, 1);
> break;
> default:
> break;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
> index c626f3e59ff9..a97af422575a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
> @@ -146,16 +146,16 @@ static ssize_t amdgpu_xgmi_show_error(struct device *dev,
> ficaa_pie_ctl_in = AMDGPU_XGMI_SET_FICAA(0x200);
> ficaa_pie_status_in = AMDGPU_XGMI_SET_FICAA(0x208);
>
> - fica_out = adev->df_funcs->get_fica(adev, ficaa_pie_ctl_in);
> + fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_ctl_in);
> if (fica_out != 0x1f)
> pr_err("xGMI error counters not enabled!\n");
>
> - fica_out = adev->df_funcs->get_fica(adev, ficaa_pie_status_in);
> + fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_status_in);
>
> if ((fica_out & 0xffff) == 2)
> error_count = ((fica_out >> 62) & 0x1) + (fica_out >> 63);
>
> - adev->df_funcs->set_fica(adev, ficaa_pie_status_in, 0, 0);
> + adev->df.funcs->set_fica(adev, ficaa_pie_status_in, 0, 0);
>
> return snprintf(buf, PAGE_SIZE, "%d\n", error_count);
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/df_v1_7.c b/drivers/gpu/drm/amd/amdgpu/df_v1_7.c
> index d6221298b477..03fdeef568d9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/df_v1_7.c
> +++ b/drivers/gpu/drm/amd/amdgpu/df_v1_7.c
> @@ -66,7 +66,7 @@ static u32 df_v1_7_get_hbm_channel_number(struct amdgpu_device *adev)
> {
> int fb_channel_number;
>
> - fb_channel_number = adev->df_funcs->get_fb_channel_number(adev);
> + fb_channel_number = adev->df.funcs->get_fb_channel_number(adev);
>
> return df_v1_7_channel_number[fb_channel_number];
> }
> @@ -77,7 +77,7 @@ static void df_v1_7_update_medium_grain_clock_gating(struct amdgpu_device *adev,
> u32 tmp;
>
> /* Put DF on broadcast mode */
> - adev->df_funcs->enable_broadcast_mode(adev, true);
> + adev->df.funcs->enable_broadcast_mode(adev, true);
>
> if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
> tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
> @@ -92,7 +92,7 @@ static void df_v1_7_update_medium_grain_clock_gating(struct amdgpu_device *adev,
> }
>
> /* Exit boradcast mode */
> - adev->df_funcs->enable_broadcast_mode(adev, false);
> + adev->df.funcs->enable_broadcast_mode(adev, false);
> }
>
> static void df_v1_7_get_clockgating_state(struct amdgpu_device *adev,
> diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
> index 2f884d941e8d..7bd29d97adfe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
> +++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
> @@ -311,7 +311,7 @@ static u32 df_v3_6_get_hbm_channel_number(struct amdgpu_device *adev)
> {
> int fb_channel_number;
>
> - fb_channel_number = adev->df_funcs->get_fb_channel_number(adev);
> + fb_channel_number = adev->df.funcs->get_fb_channel_number(adev);
> if (fb_channel_number >= ARRAY_SIZE(df_v3_6_channel_number))
> fb_channel_number = 0;
>
> @@ -325,7 +325,7 @@ static void df_v3_6_update_medium_grain_clock_gating(struct amdgpu_device *adev,
>
> if (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG) {
> /* Put DF on broadcast mode */
> - adev->df_funcs->enable_broadcast_mode(adev, true);
> + adev->df.funcs->enable_broadcast_mode(adev, true);
>
> if (enable) {
> tmp = RREG32_SOC15(DF, 0,
> @@ -344,7 +344,7 @@ static void df_v3_6_update_medium_grain_clock_gating(struct amdgpu_device *adev,
> }
>
> /* Exit broadcast mode */
> - adev->df_funcs->enable_broadcast_mode(adev, false);
> + adev->df.funcs->enable_broadcast_mode(adev, false);
> }
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 26194ac9af98..b83c8d745f42 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -817,8 +817,8 @@ static int gmc_v9_0_late_init(void *handle)
> r = amdgpu_atomfirmware_mem_ecc_supported(adev);
> if (!r) {
> DRM_INFO("ECC is not present.\n");
> - if (adev->df_funcs->enable_ecc_force_par_wr_rmw)
> - adev->df_funcs->enable_ecc_force_par_wr_rmw(adev, false);
> + if (adev->df.funcs->enable_ecc_force_par_wr_rmw)
> + adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false);
> } else {
> DRM_INFO("ECC is active.\n");
> }
> @@ -1023,7 +1023,7 @@ static int gmc_v9_0_sw_init(void *handle)
> else
> chansize = 128;
>
> - numchan = adev->df_funcs->get_hbm_channel_number(adev);
> + numchan = adev->df.funcs->get_hbm_channel_number(adev);
> adev->gmc.vram_width = numchan * chansize;
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 6c75021dda0f..317803f6a561 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -677,9 +677,9 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
> }
>
> if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
> - adev->df_funcs = &df_v3_6_funcs;
> + adev->df.funcs = &df_v3_6_funcs;
> else
> - adev->df_funcs = &df_v1_7_funcs;
> + adev->df.funcs = &df_v1_7_funcs;
>
> adev->rev_id = soc15_get_rev_id(adev);
> adev->nbio.funcs->detect_hw_virt(adev);
> @@ -1247,7 +1247,7 @@ static int soc15_common_sw_init(void *handle)
> if (amdgpu_sriov_vf(adev))
> xgpu_ai_mailbox_add_irq_id(adev);
>
> - adev->df_funcs->sw_init(adev);
> + adev->df.funcs->sw_init(adev);
>
> return 0;
> }
> @@ -1257,7 +1257,7 @@ static int soc15_common_sw_fini(void *handle)
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> amdgpu_nbio_ras_fini(adev);
> - adev->df_funcs->sw_fini(adev);
> + adev->df.funcs->sw_fini(adev);
> return 0;
> }
>
> @@ -1478,7 +1478,7 @@ static int soc15_common_set_clockgating_state(void *handle,
> state == AMD_CG_STATE_GATE ? true : false);
> soc15_update_rom_medium_grain_clock_gating(adev,
> state == AMD_CG_STATE_GATE ? true : false);
> - adev->df_funcs->update_medium_grain_clock_gating(adev,
> + adev->df.funcs->update_medium_grain_clock_gating(adev,
> state == AMD_CG_STATE_GATE ? true : false);
> break;
> case CHIP_RAVEN:
> @@ -1536,7 +1536,7 @@ static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
> if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
> *flags |= AMD_CG_SUPPORT_ROM_MGCG;
>
> - adev->df_funcs->get_clockgating_state(adev, flags);
> + adev->df.funcs->get_clockgating_state(adev, flags);
> }
>
> static int soc15_common_set_powergating_state(void *handle,
> --
> 2.19.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-01-10 14:39 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-01-10 2:02 Rework DF to prepare for VBIOS that turns on channel hashing Joseph Greathouse
2020-01-10 2:02 ` [PATCH 1/3] drm/amdgpu: Create generic DF struct in adev Joseph Greathouse
2020-01-10 14:39 ` Alex Deucher
2020-01-10 2:02 ` [PATCH 2/3] drm/amdgpu: add defines for DF and TCP Hashing Joseph Greathouse
2020-01-10 2:02 ` [PATCH 3/3] drm/amdgpu: Match TC hash settings to DF settings Joseph Greathouse
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