* [xhci:fix_psi_memleak 1/1] drivers/usb/host/xhci-hub.c:136:27: warning: 'port_cap' may be used uninitialized in this function
@ 2020-01-09 23:31 kbuild test robot
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From: kbuild test robot @ 2020-01-09 23:31 UTC (permalink / raw)
To: kbuild-all
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tree: https://git.kernel.org/pub/scm/linux/kernel/git/mnyman/xhci.git fix_psi_memleak
head: f8bafc0a184a2ad3f0c907d88af395f5bc59193b
commit: f8bafc0a184a2ad3f0c907d88af395f5bc59193b [1/1] xhci: Fix memory leak when caching protocol extended capability PSI tables
config: sh-allmodconfig (attached as .config)
compiler: sh4-linux-gcc (GCC) 7.5.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout f8bafc0a184a2ad3f0c907d88af395f5bc59193b
# save the attached .config to linux build tree
GCC_VERSION=7.5.0 make.cross ARCH=sh
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
Note: it may well be a FALSE warning. FWIW you are at least aware of it now.
http://gcc.gnu.org/wiki/Better_Uninitialized_Warnings
All warnings (new ones prefixed by >>):
drivers/usb/host/xhci-hub.c: In function 'xhci_hub_control':
>> drivers/usb/host/xhci-hub.c:136:27: warning: 'port_cap' may be used uninitialized in this function [-Wmaybe-uninitialized]
for (i = 0; i < port_cap->psi_count; i++) {
~~~~~~~~^~~~~~~~~~~
drivers/usb/host/xhci-hub.c:58:24: note: 'port_cap' was declared here
struct xhci_port_cap *port_cap;
^~~~~~~~
vim +/port_cap +136 drivers/usb/host/xhci-hub.c
54
55 static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
56 u16 wLength)
57 {
58 struct xhci_port_cap *port_cap;
59 int i, ssa_count;
60 u32 temp;
61 u16 desc_size, ssp_cap_size, ssa_size = 0;
62 bool usb3_1 = false;
63
64 desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
65 ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
66
67 /* does xhci support USB 3.1 Enhanced SuperSpeed */
68 for (i = 0; i < xhci->num_port_caps; i++) {
69 if (xhci->port_caps[i].maj_rev == 0x03 &&
70 xhci->port_caps[i].min_rev >= 0x01) {
71 usb3_1 = true;
72 port_cap = &xhci->port_caps[i];
73 break;
74 }
75 }
76
77 if (usb3_1) {
78 /* does xhci provide a PSI table for SSA speed attributes? */
79 if (port_cap->psi_count) {
80 /* two SSA entries for each unique PSI ID, RX and TX */
81 ssa_count = port_cap->psi_uid_count * 2;
82 ssa_size = ssa_count * sizeof(u32);
83 ssp_cap_size -= 16; /* skip copying the default SSA */
84 }
85 desc_size += ssp_cap_size;
86 }
87 memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
88
89 if (usb3_1) {
90 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
91 buf[4] += 1;
92 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
93 }
94
95 if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
96 return wLength;
97
98 /* Indicate whether the host has LTM support. */
99 temp = readl(&xhci->cap_regs->hcc_params);
100 if (HCC_LTC(temp))
101 buf[8] |= USB_LTM_SUPPORT;
102
103 /* Set the U1 and U2 exit latencies. */
104 if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
105 temp = readl(&xhci->cap_regs->hcs_params3);
106 buf[12] = HCS_U1_LATENCY(temp);
107 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
108 }
109
110 /* If PSI table exists, add the custom speed attributes from it */
111 if (usb3_1 && port_cap->psi_count) {
112 u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp;
113 int offset;
114
115 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
116
117 if (wLength < desc_size)
118 return wLength;
119 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
120
121 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
122 bm_attrib = (ssa_count - 1) & 0x1f;
123 bm_attrib |= (port_cap->psi_uid_count - 1) << 5;
124 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
125
126 if (wLength < desc_size + ssa_size)
127 return wLength;
128 /*
129 * Create the Sublink Speed Attributes (SSA) array.
130 * The xhci PSI field and USB 3.1 SSA fields are very similar,
131 * but link type bits 7:6 differ for values 01b and 10b.
132 * xhci has also only one PSI entry for a symmetric link when
133 * USB 3.1 requires two SSA entries (RX and TX) for every link
134 */
135 offset = desc_size;
> 136 for (i = 0; i < port_cap->psi_count; i++) {
137 psi = port_cap->psi[i];
138 psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
139 psi_exp = XHCI_EXT_PORT_PSIE(psi);
140 psi_mant = XHCI_EXT_PORT_PSIM(psi);
141
142 /* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */
143 for (; psi_exp < 3; psi_exp++)
144 psi_mant /= 1000;
145 if (psi_mant >= 10)
146 psi |= BIT(14);
147
148 if ((psi & PLT_MASK) == PLT_SYM) {
149 /* Symmetric, create SSA RX and TX from one PSI entry */
150 put_unaligned_le32(psi, &buf[offset]);
151 psi |= 1 << 7; /* turn entry to TX */
152 offset += 4;
153 if (offset >= desc_size + ssa_size)
154 return desc_size + ssa_size;
155 } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
156 /* Asymetric RX, flip bits 7:6 for SSA */
157 psi ^= PLT_MASK;
158 }
159 put_unaligned_le32(psi, &buf[offset]);
160 offset += 4;
161 if (offset >= desc_size + ssa_size)
162 return desc_size + ssa_size;
163 }
164 }
165 /* ssa_size is 0 for other than usb 3.1 hosts */
166 return desc_size + ssa_size;
167 }
168
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org Intel Corporation
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2020-01-09 23:31 [xhci:fix_psi_memleak 1/1] drivers/usb/host/xhci-hub.c:136:27: warning: 'port_cap' may be used uninitialized in this function kbuild test robot
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