* [PATCH v2 17/21] ram: add SDRAM driver for i.MXRT SoCs
2020-01-10 14:51 [PATCH v2 16/21] serial_lpuart: add support for i.MXRT Giulio Benetti
@ 2020-01-10 14:51 ` Giulio Benetti
2020-01-15 12:47 ` sbabic at denx.de
2020-01-28 8:46 ` Lukasz Majewski
2020-01-10 14:51 ` [PATCH v2 18/21] mmc: fsl_esdhc: make if(CONFIG_IS_ENABLED(CLK)) an #if statement Giulio Benetti
` (5 subsequent siblings)
6 siblings, 2 replies; 19+ messages in thread
From: Giulio Benetti @ 2020-01-10 14:51 UTC (permalink / raw)
To: u-boot
Add SDRAM driver for i.MXRT SoCs.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
---
drivers/ram/Kconfig | 8 +
drivers/ram/Makefile | 2 +
drivers/ram/imxrt_sdram.c | 439 +++++++++++++++++++++++
include/dt-bindings/memory/imxrt-sdram.h | 100 ++++++
4 files changed, 549 insertions(+)
create mode 100644 drivers/ram/imxrt_sdram.c
create mode 100644 include/dt-bindings/memory/imxrt-sdram.h
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index b454ceb599..56fea7c94c 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -65,5 +65,13 @@ config K3_J721E_DDRSS
Enabling this config adds support for the DDR memory controller
on J721E family of SoCs.
+config IMXRT_SDRAM
+ bool "Enable i.MXRT SDRAM support"
+ depends on RAM
+ help
+ i.MXRT family devices support smart external memory controller(SEMC)
+ to support external memories like sdram, psram & nand.
+ This driver is for the sdram memory interface with the SEMC.
+
source "drivers/ram/rockchip/Kconfig"
source "drivers/ram/stm32mp1/Kconfig"
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index 4b77969b39..5c897410c6 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -15,3 +15,5 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_K3_AM654_DDRSS) += k3-am654-ddrss.o
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/
+
+obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
diff --git a/drivers/ram/imxrt_sdram.c b/drivers/ram/imxrt_sdram.c
new file mode 100644
index 0000000000..af7400be82
--- /dev/null
+++ b/drivers/ram/imxrt_sdram.c
@@ -0,0 +1,439 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <ram.h>
+#include <asm/io.h>
+
+/* SDRAM Command Code */
+#define SD_CC_ARD 0x0 /* Master Bus (AXI) command - Read */
+#define SD_CC_AWR 0x1 /* Master Bus (AXI) command - Write */
+#define SD_CC_IRD 0x8 /* IP command - Read */
+#define SD_CC_IWR 0x9 /* IP command - Write */
+#define SD_CC_IMS 0xA /* IP command - Set Mode Register */
+#define SD_CC_IACT 0xB /* IP command - ACTIVE */
+#define SD_CC_IAF 0xC /* IP command - Auto Refresh */
+#define SD_CC_ISF 0xD /* IP Command - Self Refresh */
+#define SD_CC_IPRE 0xE /* IP command - Precharge */
+#define SD_CC_IPREA 0xF /* IP command - Precharge ALL */
+
+#define SEMC_MCR_MDIS BIT(1)
+#define SEMC_MCR_DQSMD BIT(2)
+
+#define SEMC_INTR_IPCMDERR BIT(1)
+#define SEMC_INTR_IPCMDDONE BIT(0)
+
+#define SEMC_IPCMD_KEY 0xA55A0000
+
+struct imxrt_semc_regs {
+ /* 0x0 */
+ u32 mcr;
+ u32 iocr;
+ u32 bmcr0;
+ u32 bmcr1;
+ u32 br[9];
+
+ /* 0x34 */
+ u32 res1;
+ u32 inten;
+ u32 intr;
+ /* 0x40 */
+ u32 sdramcr0;
+ u32 sdramcr1;
+ u32 sdramcr2;
+ u32 sdramcr3;
+ /* 0x50 */
+ u32 nandcr0;
+ u32 nandcr1;
+ u32 nandcr2;
+ u32 nandcr3;
+ /* 0x60 */
+ u32 norcr0;
+ u32 norcr1;
+ u32 norcr2;
+ u32 norcr3;
+ /* 0x70 */
+ u32 sramcr0;
+ u32 sramcr1;
+ u32 sramcr2;
+ u32 sramcr3;
+ /* 0x80 */
+ u32 dbicr0;
+ u32 dbicr1;
+ u32 res2[2];
+ /* 0x90 */
+ u32 ipcr0;
+ u32 ipcr1;
+ u32 ipcr2;
+ u32 ipcmd;
+ /* 0xA0 */
+ u32 iptxdat;
+ u32 res3[3];
+ /* 0xB0 */
+ u32 iprxdat;
+ u32 res4[3];
+ /* 0xC0 */
+ u32 sts[16];
+};
+
+#define SEMC_IOCR_MUX_A8_SHIFT 0
+#define SEMC_IOCR_MUX_CSX0_SHIFT 3
+#define SEMC_IOCR_MUX_CSX1_SHIFT 6
+#define SEMC_IOCR_MUX_CSX2_SHIFT 9
+#define SEMC_IOCR_MUX_CSX3_SHIFT 12
+#define SEMC_IOCR_MUX_RDY_SHIFT 15
+
+struct imxrt_sdram_mux {
+ u8 a8;
+ u8 csx0;
+ u8 csx1;
+ u8 csx2;
+ u8 csx3;
+ u8 rdy;
+};
+
+#define SEMC_SDRAMCR0_PS_SHIFT 0
+#define SEMC_SDRAMCR0_BL_SHIFT 4
+#define SEMC_SDRAMCR0_COL_SHIFT 8
+#define SEMC_SDRAMCR0_CL_SHIFT 10
+
+struct imxrt_sdram_control {
+ u8 memory_width;
+ u8 burst_len;
+ u8 no_columns;
+ u8 cas_latency;
+};
+
+#define SEMC_SDRAMCR1_PRE2ACT_SHIFT 0
+#define SEMC_SDRAMCR1_ACT2RW_SHIFT 4
+#define SEMC_SDRAMCR1_RFRC_SHIFT 8
+#define SEMC_SDRAMCR1_WRC_SHIFT 13
+#define SEMC_SDRAMCR1_CKEOFF_SHIFT 16
+#define SEMC_SDRAMCR1_ACT2PRE_SHIFT 20
+
+#define SEMC_SDRAMCR2_SRRC_SHIFT 0
+#define SEMC_SDRAMCR2_REF2REF_SHIFT 8
+#define SEMC_SDRAMCR2_ACT2ACT_SHIFT 16
+#define SEMC_SDRAMCR2_ITO_SHIFT 24
+
+#define SEMC_SDRAMCR3_REN BIT(0)
+#define SEMC_SDRAMCR3_REBL_SHIFT 1
+#define SEMC_SDRAMCR3_PRESCALE_SHIFT 8
+#define SEMC_SDRAMCR3_RT_SHIFT 16
+#define SEMC_SDRAMCR3_UT_SHIFT 24
+
+struct imxrt_sdram_timing {
+ u8 pre2act;
+ u8 act2rw;
+ u8 rfrc;
+ u8 wrc;
+ u8 ckeoff;
+ u8 act2pre;
+
+ u8 srrc;
+ u8 ref2ref;
+ u8 act2act;
+ u8 ito;
+
+ u8 rebl;
+ u8 prescale;
+ u8 rt;
+ u8 ut;
+};
+
+enum imxrt_semc_bank {
+ SDRAM_BANK1,
+ SDRAM_BANK2,
+ SDRAM_BANK3,
+ SDRAM_BANK4,
+ MAX_SDRAM_BANK,
+};
+
+#define SEMC_BR_VLD_MASK 1
+#define SEMC_BR_MS_SHIFT 1
+
+struct bank_params {
+ enum imxrt_semc_bank target_bank;
+ u32 base_address;
+ u32 memory_size;
+};
+
+struct imxrt_sdram_params {
+ struct imxrt_semc_regs *base;
+
+ struct imxrt_sdram_mux *sdram_mux;
+ struct imxrt_sdram_control *sdram_control;
+ struct imxrt_sdram_timing *sdram_timing;
+
+ struct bank_params bank_params[MAX_SDRAM_BANK];
+ u8 no_sdram_banks;
+};
+
+static int imxrt_sdram_wait_ipcmd_done(struct imxrt_semc_regs *regs)
+{
+ do {
+ readl(®s->intr);
+
+ if (regs->intr & SEMC_INTR_IPCMDDONE)
+ return 0;
+ if (regs->intr & SEMC_INTR_IPCMDERR)
+ return -EIO;
+
+ mdelay(50);
+ } while (1);
+}
+
+static int imxrt_sdram_ipcmd(struct imxrt_semc_regs *regs, u32 mem_addr,
+ u32 ipcmd, u32 wd, u32 *rd)
+{
+ int ret;
+
+ if (ipcmd == SD_CC_IWR || ipcmd == SD_CC_IMS)
+ writel(wd, ®s->iptxdat);
+
+ /* set slave address for every command as specified on RM */
+ writel(mem_addr, ®s->ipcr0);
+
+ /* execute command */
+ writel(SEMC_IPCMD_KEY | ipcmd, ®s->ipcmd);
+
+ ret = imxrt_sdram_wait_ipcmd_done(regs);
+ if (ret < 0)
+ return ret;
+
+ if (ipcmd == SD_CC_IRD) {
+ if (!rd)
+ return -EINVAL;
+
+ *rd = readl(®s->iprxdat);
+ }
+
+ return 0;
+}
+
+int imxrt_sdram_init(struct udevice *dev)
+{
+ struct imxrt_sdram_params *params = dev_get_platdata(dev);
+ struct imxrt_sdram_mux *mux = params->sdram_mux;
+ struct imxrt_sdram_control *ctrl = params->sdram_control;
+ struct imxrt_sdram_timing *time = params->sdram_timing;
+ struct imxrt_semc_regs *regs = params->base;
+ struct bank_params *bank_params;
+ u32 rd;
+ int i;
+
+ /* enable the SEMC controller */
+ clrbits_le32(®s->mcr, SEMC_MCR_MDIS);
+ /* set DQS mode from DQS pad */
+ setbits_le32(®s->mcr, SEMC_MCR_DQSMD);
+
+ for (i = 0, bank_params = params->bank_params;
+ i < params->no_sdram_banks; bank_params++,
+ i++)
+ writel((bank_params->base_address & 0xfffff000)
+ | bank_params->memory_size << SEMC_BR_MS_SHIFT
+ | SEMC_BR_VLD_MASK,
+ ®s->br[bank_params->target_bank]);
+
+ writel(mux->a8 << SEMC_IOCR_MUX_A8_SHIFT
+ | mux->csx0 << SEMC_IOCR_MUX_CSX0_SHIFT
+ | mux->csx1 << SEMC_IOCR_MUX_CSX1_SHIFT
+ | mux->csx2 << SEMC_IOCR_MUX_CSX2_SHIFT
+ | mux->csx3 << SEMC_IOCR_MUX_CSX3_SHIFT
+ | mux->rdy << SEMC_IOCR_MUX_RDY_SHIFT,
+ ®s->iocr);
+
+ writel(ctrl->memory_width << SEMC_SDRAMCR0_PS_SHIFT
+ | ctrl->burst_len << SEMC_SDRAMCR0_BL_SHIFT
+ | ctrl->no_columns << SEMC_SDRAMCR0_COL_SHIFT
+ | ctrl->cas_latency << SEMC_SDRAMCR0_CL_SHIFT,
+ ®s->sdramcr0);
+
+ writel(time->pre2act << SEMC_SDRAMCR1_PRE2ACT_SHIFT
+ | time->act2rw << SEMC_SDRAMCR1_ACT2RW_SHIFT
+ | time->rfrc << SEMC_SDRAMCR1_RFRC_SHIFT
+ | time->wrc << SEMC_SDRAMCR1_WRC_SHIFT
+ | time->ckeoff << SEMC_SDRAMCR1_CKEOFF_SHIFT
+ | time->act2pre << SEMC_SDRAMCR1_ACT2PRE_SHIFT,
+ ®s->sdramcr1);
+
+ writel(time->srrc << SEMC_SDRAMCR2_SRRC_SHIFT
+ | time->ref2ref << SEMC_SDRAMCR2_REF2REF_SHIFT
+ | time->act2act << SEMC_SDRAMCR2_ACT2ACT_SHIFT
+ | time->ito << SEMC_SDRAMCR2_ITO_SHIFT,
+ ®s->sdramcr2);
+
+ writel(time->rebl << SEMC_SDRAMCR3_REBL_SHIFT
+ | time->prescale << SEMC_SDRAMCR3_PRESCALE_SHIFT
+ | time->rt << SEMC_SDRAMCR3_RT_SHIFT
+ | time->ut << SEMC_SDRAMCR3_UT_SHIFT
+ | SEMC_SDRAMCR3_REN,
+ ®s->sdramcr3);
+
+ writel(2, ®s->ipcr1);
+
+ for (i = 0, bank_params = params->bank_params;
+ i < params->no_sdram_banks; bank_params++,
+ i++) {
+ mdelay(250);
+ imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IPREA,
+ 0, &rd);
+ imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IAF,
+ 0, &rd);
+ imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IAF,
+ 0, &rd);
+ imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IMS,
+ ctrl->burst_len | (ctrl->cas_latency << 4),
+ &rd);
+ mdelay(250);
+ }
+
+ return 0;
+}
+
+static int imxrt_semc_ofdata_to_platdata(struct udevice *dev)
+{
+ struct imxrt_sdram_params *params = dev_get_platdata(dev);
+ ofnode bank_node;
+ u8 bank = 0;
+
+ params->sdram_mux =
+ (struct imxrt_sdram_mux *)
+ dev_read_u8_array_ptr(dev,
+ "fsl,sdram-mux",
+ sizeof(struct imxrt_sdram_mux));
+ if (!params->sdram_mux) {
+ pr_err("fsl,sdram-mux not found");
+ return -EINVAL;
+ }
+
+ params->sdram_control =
+ (struct imxrt_sdram_control *)
+ dev_read_u8_array_ptr(dev,
+ "fsl,sdram-control",
+ sizeof(struct imxrt_sdram_control));
+ if (!params->sdram_control) {
+ pr_err("fsl,sdram-control not found");
+ return -EINVAL;
+ }
+
+ params->sdram_timing =
+ (struct imxrt_sdram_timing *)
+ dev_read_u8_array_ptr(dev,
+ "fsl,sdram-timing",
+ sizeof(struct imxrt_sdram_timing));
+ if (!params->sdram_timing) {
+ pr_err("fsl,sdram-timing not found");
+ return -EINVAL;
+ }
+
+ dev_for_each_subnode(bank_node, dev) {
+ struct bank_params *bank_params;
+ char *bank_name;
+ int ret;
+
+ /* extract the bank index from DT */
+ bank_name = (char *)ofnode_get_name(bank_node);
+ strsep(&bank_name, "@");
+ if (!bank_name) {
+ pr_err("missing sdram bank index");
+ return -EINVAL;
+ }
+
+ bank_params = ¶ms->bank_params[bank];
+ strict_strtoul(bank_name, 10,
+ (unsigned long *)&bank_params->target_bank);
+ if (bank_params->target_bank >= MAX_SDRAM_BANK) {
+ pr_err("Found bank %d , but only bank 0,1,2,3 are supported",
+ bank_params->target_bank);
+ return -EINVAL;
+ }
+
+ ret = ofnode_read_u32(bank_node,
+ "fsl,memory-size",
+ &bank_params->memory_size);
+ if (ret < 0) {
+ pr_err("fsl,memory-size not found");
+ return -EINVAL;
+ }
+
+ ret = ofnode_read_u32(bank_node,
+ "fsl,base-address",
+ &bank_params->base_address);
+ if (ret < 0) {
+ pr_err("fsl,base-address not found");
+ return -EINVAL;
+ }
+
+ debug("Found bank %s %u\n", bank_name,
+ bank_params->target_bank);
+ bank++;
+ }
+
+ params->no_sdram_banks = bank;
+ debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
+
+ return 0;
+}
+
+static int imxrt_semc_probe(struct udevice *dev)
+{
+ struct imxrt_sdram_params *params = dev_get_platdata(dev);
+ int ret;
+ fdt_addr_t addr;
+
+ addr = dev_read_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ params->base = (struct imxrt_semc_regs *)addr;
+
+#ifdef CONFIG_CLK
+ struct clk clk;
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_enable(&clk);
+
+ if (ret) {
+ dev_err(dev, "failed to enable clock\n");
+ return ret;
+ }
+#endif
+ ret = imxrt_sdram_init(dev);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int imxrt_semc_get_info(struct udevice *dev, struct ram_info *info)
+{
+ return 0;
+}
+
+static struct ram_ops imxrt_semc_ops = {
+ .get_info = imxrt_semc_get_info,
+};
+
+static const struct udevice_id imxrt_semc_ids[] = {
+ { .compatible = "fsl,imxrt-semc", .data = 0 },
+ { }
+};
+
+U_BOOT_DRIVER(imxrt_semc) = {
+ .name = "imxrt_semc",
+ .id = UCLASS_RAM,
+ .of_match = imxrt_semc_ids,
+ .ops = &imxrt_semc_ops,
+ .ofdata_to_platdata = imxrt_semc_ofdata_to_platdata,
+ .probe = imxrt_semc_probe,
+ .platdata_auto_alloc_size = sizeof(struct imxrt_sdram_params),
+};
diff --git a/include/dt-bindings/memory/imxrt-sdram.h b/include/dt-bindings/memory/imxrt-sdram.h
new file mode 100644
index 0000000000..acb35bce27
--- /dev/null
+++ b/include/dt-bindings/memory/imxrt-sdram.h
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef DT_BINDINGS_IMXRT_SDRAM_H
+#define DT_BINDINGS_IMXRT_SDRAM_H
+
+#define MEM_SIZE_4K 0x00
+#define MEM_SIZE_8K 0x01
+#define MEM_SIZE_16K 0x02
+#define MEM_SIZE_32K 0x03
+#define MEM_SIZE_64K 0x04
+#define MEM_SIZE_128K 0x05
+#define MEM_SIZE_256K 0x06
+#define MEM_SIZE_512K 0x07
+#define MEM_SIZE_1M 0x08
+#define MEM_SIZE_2M 0x09
+#define MEM_SIZE_4M 0x0A
+#define MEM_SIZE_8M 0x0B
+#define MEM_SIZE_16M 0x0C
+#define MEM_SIZE_32M 0x0D
+#define MEM_SIZE_64M 0x0E
+#define MEM_SIZE_128M 0x0F
+#define MEM_SIZE_256M 0x10
+#define MEM_SIZE_512M 0x11
+#define MEM_SIZE_1G 0x12
+#define MEM_SIZE_2G 0x13
+#define MEM_SIZE_4G 0x14
+
+#define MUX_A8_SDRAM_A8 0x0
+#define MUX_A8_NAND_CE 0x1
+#define MUX_A8_NOR_CE 0x2
+#define MUX_A8_PSRAM_CE 0x3
+#define MUX_A8_DBI_CSX 0x4
+
+#define MUX_CSX0_NOR_PSRAM_A24 0x0
+#define MUX_CSX0_SDRAM_CS1 0x1
+#define MUX_CSX0_SDRAM_CS2 0x2
+#define MUX_CSX0_SDRAM_CS3 0x3
+#define MUX_CSX0_NAND_CE 0x4
+#define MUX_CSX0_NOR_CE 0x5
+#define MUX_CSX0_PSRAM_CE 0x6
+#define MUX_CSX0_DBI_CSX 0x7
+
+#define MUX_CSX1_NOR_PSRAM_A25 0x0
+#define MUX_CSX1_SDRAM_CS1 0x1
+#define MUX_CSX1_SDRAM_CS2 0x2
+#define MUX_CSX1_SDRAM_CS3 0x3
+#define MUX_CSX1_NAND_CE 0x4
+#define MUX_CSX1_NOR_CE 0x5
+#define MUX_CSX1_PSRAM_CE 0x6
+#define MUX_CSX1_DBI_CSX 0x7
+
+#define MUX_CSX2_NOR_PSRAM_A26 0x0
+#define MUX_CSX2_SDRAM_CS1 0x1
+#define MUX_CSX2_SDRAM_CS2 0x2
+#define MUX_CSX2_SDRAM_CS3 0x3
+#define MUX_CSX2_NAND_CE 0x4
+#define MUX_CSX2_NOR_CE 0x5
+#define MUX_CSX2_PSRAM_CE 0x6
+#define MUX_CSX2_DBI_CSX 0x7
+
+#define MUX_CSX3_NOR_PSRAM_A27 0x0
+#define MUX_CSX3_SDRAM_CS1 0x1
+#define MUX_CSX3_SDRAM_CS2 0x2
+#define MUX_CSX3_SDRAM_CS3 0x3
+#define MUX_CSX3_NAND_CE 0x4
+#define MUX_CSX3_NOR_CE 0x5
+#define MUX_CSX3_PSRAM_CE 0x6
+#define MUX_CSX3_DBI_CSX 0x7
+
+#define MUX_RDY_NAND_RDY_WAIT 0x0
+#define MUX_RDY_SDRAM_CS1 0x1
+#define MUX_RDY_SDRAM_CS2 0x2
+#define MUX_RDY_SDRAM_CS3 0x3
+#define MUX_RDY_NOR_CE 0x4
+#define MUX_RDY_PSRAM_CE 0x5
+#define MUX_RDY_DBI_CSX 0x6
+#define MUX_RDY_NOR_PSRAM_A27 0x7
+
+#define MEM_WIDTH_8BITS 0x0
+#define MEM_WIDTH_16BITS 0x1
+
+#define BL_1 0x0
+#define BL_2 0x1
+#define BL_4 0x2
+#define BL_8 0x3
+
+#define COL_12BITS 0x0
+#define COL_11BITS 0x1
+#define COL_10BITS 0x2
+#define COL_9BITS 0x3
+
+#define CL_1 0x0
+#define CL_2 0x2
+#define CL_3 0x3
+
+#endif
--
2.20.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 17/21] ram: add SDRAM driver for i.MXRT SoCs
2020-01-10 14:51 ` [PATCH v2 17/21] ram: add SDRAM driver for i.MXRT SoCs Giulio Benetti
@ 2020-01-15 12:47 ` sbabic at denx.de
2020-01-28 8:46 ` Lukasz Majewski
1 sibling, 0 replies; 19+ messages in thread
From: sbabic at denx.de @ 2020-01-15 12:47 UTC (permalink / raw)
To: u-boot
> Add SDRAM driver for i.MXRT SoCs.
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
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DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 17/21] ram: add SDRAM driver for i.MXRT SoCs
2020-01-10 14:51 ` [PATCH v2 17/21] ram: add SDRAM driver for i.MXRT SoCs Giulio Benetti
2020-01-15 12:47 ` sbabic at denx.de
@ 2020-01-28 8:46 ` Lukasz Majewski
1 sibling, 0 replies; 19+ messages in thread
From: Lukasz Majewski @ 2020-01-28 8:46 UTC (permalink / raw)
To: u-boot
Hi Giulio,
> Add SDRAM driver for i.MXRT SoCs.
I would prefer more verbose description of this patch. For example
information if this code also performs auto calibration (it seems so)
and types of supported memories.
Is there any recommended tool from NXP, which helps with memory
calibration on a custom board? For example imx6q / Vybrid support auto
calibration in U-Boot (without the need of NXP closed source tooling).
>
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> ---
> drivers/ram/Kconfig | 8 +
> drivers/ram/Makefile | 2 +
> drivers/ram/imxrt_sdram.c | 439
> +++++++++++++++++++++++ include/dt-bindings/memory/imxrt-sdram.h |
> 100 ++++++ 4 files changed, 549 insertions(+)
> create mode 100644 drivers/ram/imxrt_sdram.c
> create mode 100644 include/dt-bindings/memory/imxrt-sdram.h
>
> diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
> index b454ceb599..56fea7c94c 100644
> --- a/drivers/ram/Kconfig
> +++ b/drivers/ram/Kconfig
> @@ -65,5 +65,13 @@ config K3_J721E_DDRSS
> Enabling this config adds support for the DDR memory
> controller on J721E family of SoCs.
>
> +config IMXRT_SDRAM
> + bool "Enable i.MXRT SDRAM support"
> + depends on RAM
> + help
> + i.MXRT family devices support smart external memory
> controller(SEMC)
> + to support external memories like sdram, psram & nand.
> + This driver is for the sdram memory interface with the
> SEMC. +
> source "drivers/ram/rockchip/Kconfig"
> source "drivers/ram/stm32mp1/Kconfig"
> diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
> index 4b77969b39..5c897410c6 100644
> --- a/drivers/ram/Makefile
> +++ b/drivers/ram/Makefile
> @@ -15,3 +15,5 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
> obj-$(CONFIG_K3_AM654_DDRSS) += k3-am654-ddrss.o
> obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
> obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/
> +
> +obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
> diff --git a/drivers/ram/imxrt_sdram.c b/drivers/ram/imxrt_sdram.c
> new file mode 100644
> index 0000000000..af7400be82
> --- /dev/null
> +++ b/drivers/ram/imxrt_sdram.c
> @@ -0,0 +1,439 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019
> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> + */
> +
> +#include <common.h>
> +#include <clk.h>
> +#include <dm.h>
> +#include <ram.h>
> +#include <asm/io.h>
> +
> +/* SDRAM Command Code */
> +#define SD_CC_ARD 0x0 /* Master Bus (AXI) command
> - Read */ +#define SD_CC_AWR 0x1 /* Master Bus
> (AXI) command - Write */ +#define SD_CC_IRD 0x8 /*
> IP command - Read */ +#define SD_CC_IWR 0x9 /* IP
> command - Write */ +#define SD_CC_IMS 0xA /* IP
> command - Set Mode Register */ +#define SD_CC_IACT 0xB
> /* IP command - ACTIVE */ +#define SD_CC_IAF 0xC
> /* IP command - Auto Refresh */ +#define SD_CC_ISF
> 0xD /* IP Command - Self Refresh */ +#define SD_CC_IPRE
> 0xE /* IP command - Precharge */ +#define
> SD_CC_IPREA 0xF /* IP command - Precharge ALL */ +
> +#define SEMC_MCR_MDIS BIT(1)
> +#define SEMC_MCR_DQSMD BIT(2)
> +
> +#define SEMC_INTR_IPCMDERR BIT(1)
> +#define SEMC_INTR_IPCMDDONE BIT(0)
> +
> +#define SEMC_IPCMD_KEY 0xA55A0000
> +
> +struct imxrt_semc_regs {
> + /* 0x0 */
> + u32 mcr;
> + u32 iocr;
> + u32 bmcr0;
> + u32 bmcr1;
> + u32 br[9];
> +
> + /* 0x34 */
> + u32 res1;
> + u32 inten;
> + u32 intr;
> + /* 0x40 */
> + u32 sdramcr0;
> + u32 sdramcr1;
> + u32 sdramcr2;
> + u32 sdramcr3;
> + /* 0x50 */
> + u32 nandcr0;
> + u32 nandcr1;
> + u32 nandcr2;
> + u32 nandcr3;
> + /* 0x60 */
> + u32 norcr0;
> + u32 norcr1;
> + u32 norcr2;
> + u32 norcr3;
> + /* 0x70 */
> + u32 sramcr0;
> + u32 sramcr1;
> + u32 sramcr2;
> + u32 sramcr3;
> + /* 0x80 */
> + u32 dbicr0;
> + u32 dbicr1;
> + u32 res2[2];
> + /* 0x90 */
> + u32 ipcr0;
> + u32 ipcr1;
> + u32 ipcr2;
> + u32 ipcmd;
> + /* 0xA0 */
> + u32 iptxdat;
> + u32 res3[3];
> + /* 0xB0 */
> + u32 iprxdat;
> + u32 res4[3];
> + /* 0xC0 */
> + u32 sts[16];
> +};
> +
> +#define SEMC_IOCR_MUX_A8_SHIFT 0
> +#define SEMC_IOCR_MUX_CSX0_SHIFT 3
> +#define SEMC_IOCR_MUX_CSX1_SHIFT 6
> +#define SEMC_IOCR_MUX_CSX2_SHIFT 9
> +#define SEMC_IOCR_MUX_CSX3_SHIFT 12
> +#define SEMC_IOCR_MUX_RDY_SHIFT 15
> +
> +struct imxrt_sdram_mux {
> + u8 a8;
> + u8 csx0;
> + u8 csx1;
> + u8 csx2;
> + u8 csx3;
> + u8 rdy;
> +};
> +
> +#define SEMC_SDRAMCR0_PS_SHIFT 0
> +#define SEMC_SDRAMCR0_BL_SHIFT 4
> +#define SEMC_SDRAMCR0_COL_SHIFT 8
> +#define SEMC_SDRAMCR0_CL_SHIFT 10
> +
> +struct imxrt_sdram_control {
> + u8 memory_width;
> + u8 burst_len;
> + u8 no_columns;
> + u8 cas_latency;
> +};
> +
> +#define SEMC_SDRAMCR1_PRE2ACT_SHIFT 0
> +#define SEMC_SDRAMCR1_ACT2RW_SHIFT 4
> +#define SEMC_SDRAMCR1_RFRC_SHIFT 8
> +#define SEMC_SDRAMCR1_WRC_SHIFT 13
> +#define SEMC_SDRAMCR1_CKEOFF_SHIFT 16
> +#define SEMC_SDRAMCR1_ACT2PRE_SHIFT 20
> +
> +#define SEMC_SDRAMCR2_SRRC_SHIFT 0
> +#define SEMC_SDRAMCR2_REF2REF_SHIFT 8
> +#define SEMC_SDRAMCR2_ACT2ACT_SHIFT 16
> +#define SEMC_SDRAMCR2_ITO_SHIFT 24
> +
> +#define SEMC_SDRAMCR3_REN BIT(0)
> +#define SEMC_SDRAMCR3_REBL_SHIFT 1
> +#define SEMC_SDRAMCR3_PRESCALE_SHIFT 8
> +#define SEMC_SDRAMCR3_RT_SHIFT 16
> +#define SEMC_SDRAMCR3_UT_SHIFT 24
> +
> +struct imxrt_sdram_timing {
> + u8 pre2act;
> + u8 act2rw;
> + u8 rfrc;
> + u8 wrc;
> + u8 ckeoff;
> + u8 act2pre;
> +
> + u8 srrc;
> + u8 ref2ref;
> + u8 act2act;
> + u8 ito;
> +
> + u8 rebl;
> + u8 prescale;
> + u8 rt;
> + u8 ut;
> +};
> +
> +enum imxrt_semc_bank {
> + SDRAM_BANK1,
> + SDRAM_BANK2,
> + SDRAM_BANK3,
> + SDRAM_BANK4,
> + MAX_SDRAM_BANK,
> +};
> +
> +#define SEMC_BR_VLD_MASK 1
> +#define SEMC_BR_MS_SHIFT 1
> +
> +struct bank_params {
> + enum imxrt_semc_bank target_bank;
> + u32 base_address;
> + u32 memory_size;
> +};
> +
> +struct imxrt_sdram_params {
> + struct imxrt_semc_regs *base;
> +
> + struct imxrt_sdram_mux *sdram_mux;
> + struct imxrt_sdram_control *sdram_control;
> + struct imxrt_sdram_timing *sdram_timing;
> +
> + struct bank_params bank_params[MAX_SDRAM_BANK];
> + u8 no_sdram_banks;
> +};
> +
> +static int imxrt_sdram_wait_ipcmd_done(struct imxrt_semc_regs *regs)
> +{
> + do {
> + readl(®s->intr);
> +
> + if (regs->intr & SEMC_INTR_IPCMDDONE)
> + return 0;
> + if (regs->intr & SEMC_INTR_IPCMDERR)
> + return -EIO;
> +
> + mdelay(50);
> + } while (1);
> +}
> +
> +static int imxrt_sdram_ipcmd(struct imxrt_semc_regs *regs, u32
> mem_addr,
> + u32 ipcmd, u32 wd, u32 *rd)
> +{
> + int ret;
> +
> + if (ipcmd == SD_CC_IWR || ipcmd == SD_CC_IMS)
> + writel(wd, ®s->iptxdat);
> +
> + /* set slave address for every command as specified on RM */
> + writel(mem_addr, ®s->ipcr0);
> +
> + /* execute command */
> + writel(SEMC_IPCMD_KEY | ipcmd, ®s->ipcmd);
> +
> + ret = imxrt_sdram_wait_ipcmd_done(regs);
> + if (ret < 0)
> + return ret;
> +
> + if (ipcmd == SD_CC_IRD) {
> + if (!rd)
> + return -EINVAL;
> +
> + *rd = readl(®s->iprxdat);
> + }
> +
> + return 0;
> +}
> +
> +int imxrt_sdram_init(struct udevice *dev)
> +{
> + struct imxrt_sdram_params *params = dev_get_platdata(dev);
> + struct imxrt_sdram_mux *mux = params->sdram_mux;
> + struct imxrt_sdram_control *ctrl = params->sdram_control;
> + struct imxrt_sdram_timing *time = params->sdram_timing;
> + struct imxrt_semc_regs *regs = params->base;
> + struct bank_params *bank_params;
> + u32 rd;
> + int i;
> +
> + /* enable the SEMC controller */
> + clrbits_le32(®s->mcr, SEMC_MCR_MDIS);
> + /* set DQS mode from DQS pad */
> + setbits_le32(®s->mcr, SEMC_MCR_DQSMD);
> +
> + for (i = 0, bank_params = params->bank_params;
> + i < params->no_sdram_banks; bank_params++,
> + i++)
> + writel((bank_params->base_address & 0xfffff000)
> + | bank_params->memory_size << SEMC_BR_MS_SHIFT
> + | SEMC_BR_VLD_MASK,
> + ®s->br[bank_params->target_bank]);
> +
> + writel(mux->a8 << SEMC_IOCR_MUX_A8_SHIFT
> + | mux->csx0 << SEMC_IOCR_MUX_CSX0_SHIFT
> + | mux->csx1 << SEMC_IOCR_MUX_CSX1_SHIFT
> + | mux->csx2 << SEMC_IOCR_MUX_CSX2_SHIFT
> + | mux->csx3 << SEMC_IOCR_MUX_CSX3_SHIFT
> + | mux->rdy << SEMC_IOCR_MUX_RDY_SHIFT,
> + ®s->iocr);
> +
> + writel(ctrl->memory_width << SEMC_SDRAMCR0_PS_SHIFT
> + | ctrl->burst_len << SEMC_SDRAMCR0_BL_SHIFT
> + | ctrl->no_columns << SEMC_SDRAMCR0_COL_SHIFT
> + | ctrl->cas_latency << SEMC_SDRAMCR0_CL_SHIFT,
> + ®s->sdramcr0);
> +
> + writel(time->pre2act << SEMC_SDRAMCR1_PRE2ACT_SHIFT
> + | time->act2rw << SEMC_SDRAMCR1_ACT2RW_SHIFT
> + | time->rfrc << SEMC_SDRAMCR1_RFRC_SHIFT
> + | time->wrc << SEMC_SDRAMCR1_WRC_SHIFT
> + | time->ckeoff << SEMC_SDRAMCR1_CKEOFF_SHIFT
> + | time->act2pre << SEMC_SDRAMCR1_ACT2PRE_SHIFT,
> + ®s->sdramcr1);
> +
> + writel(time->srrc << SEMC_SDRAMCR2_SRRC_SHIFT
> + | time->ref2ref << SEMC_SDRAMCR2_REF2REF_SHIFT
> + | time->act2act << SEMC_SDRAMCR2_ACT2ACT_SHIFT
> + | time->ito << SEMC_SDRAMCR2_ITO_SHIFT,
> + ®s->sdramcr2);
> +
> + writel(time->rebl << SEMC_SDRAMCR3_REBL_SHIFT
> + | time->prescale << SEMC_SDRAMCR3_PRESCALE_SHIFT
> + | time->rt << SEMC_SDRAMCR3_RT_SHIFT
> + | time->ut << SEMC_SDRAMCR3_UT_SHIFT
> + | SEMC_SDRAMCR3_REN,
> + ®s->sdramcr3);
> +
> + writel(2, ®s->ipcr1);
> +
> + for (i = 0, bank_params = params->bank_params;
> + i < params->no_sdram_banks; bank_params++,
> + i++) {
> + mdelay(250);
> + imxrt_sdram_ipcmd(regs, bank_params->base_address,
> SD_CC_IPREA,
> + 0, &rd);
> + imxrt_sdram_ipcmd(regs, bank_params->base_address,
> SD_CC_IAF,
> + 0, &rd);
> + imxrt_sdram_ipcmd(regs, bank_params->base_address,
> SD_CC_IAF,
> + 0, &rd);
> + imxrt_sdram_ipcmd(regs, bank_params->base_address,
> SD_CC_IMS,
> + ctrl->burst_len |
> (ctrl->cas_latency << 4),
> + &rd);
> + mdelay(250);
> + }
> +
> + return 0;
> +}
> +
> +static int imxrt_semc_ofdata_to_platdata(struct udevice *dev)
> +{
> + struct imxrt_sdram_params *params = dev_get_platdata(dev);
> + ofnode bank_node;
> + u8 bank = 0;
> +
> + params->sdram_mux =
> + (struct imxrt_sdram_mux *)
> + dev_read_u8_array_ptr(dev,
> + "fsl,sdram-mux",
> + sizeof(struct
> imxrt_sdram_mux));
> + if (!params->sdram_mux) {
> + pr_err("fsl,sdram-mux not found");
> + return -EINVAL;
> + }
> +
> + params->sdram_control =
> + (struct imxrt_sdram_control *)
> + dev_read_u8_array_ptr(dev,
> + "fsl,sdram-control",
> + sizeof(struct
> imxrt_sdram_control));
> + if (!params->sdram_control) {
> + pr_err("fsl,sdram-control not found");
> + return -EINVAL;
> + }
> +
> + params->sdram_timing =
> + (struct imxrt_sdram_timing *)
> + dev_read_u8_array_ptr(dev,
> + "fsl,sdram-timing",
> + sizeof(struct
> imxrt_sdram_timing));
> + if (!params->sdram_timing) {
> + pr_err("fsl,sdram-timing not found");
> + return -EINVAL;
> + }
> +
> + dev_for_each_subnode(bank_node, dev) {
> + struct bank_params *bank_params;
> + char *bank_name;
> + int ret;
> +
> + /* extract the bank index from DT */
> + bank_name = (char *)ofnode_get_name(bank_node);
> + strsep(&bank_name, "@");
> + if (!bank_name) {
> + pr_err("missing sdram bank index");
> + return -EINVAL;
> + }
> +
> + bank_params = ¶ms->bank_params[bank];
> + strict_strtoul(bank_name, 10,
> + (unsigned long
> *)&bank_params->target_bank);
> + if (bank_params->target_bank >= MAX_SDRAM_BANK) {
> + pr_err("Found bank %d , but only bank
> 0,1,2,3 are supported",
> + bank_params->target_bank);
> + return -EINVAL;
> + }
> +
> + ret = ofnode_read_u32(bank_node,
> + "fsl,memory-size",
> + &bank_params->memory_size);
> + if (ret < 0) {
> + pr_err("fsl,memory-size not found");
> + return -EINVAL;
> + }
> +
> + ret = ofnode_read_u32(bank_node,
> + "fsl,base-address",
> + &bank_params->base_address);
> + if (ret < 0) {
> + pr_err("fsl,base-address not found");
> + return -EINVAL;
> + }
> +
> + debug("Found bank %s %u\n", bank_name,
> + bank_params->target_bank);
> + bank++;
> + }
> +
> + params->no_sdram_banks = bank;
> + debug("%s, no of banks = %d\n", __func__,
> params->no_sdram_banks); +
> + return 0;
> +}
> +
> +static int imxrt_semc_probe(struct udevice *dev)
> +{
> + struct imxrt_sdram_params *params = dev_get_platdata(dev);
> + int ret;
> + fdt_addr_t addr;
> +
> + addr = dev_read_addr(dev);
> + if (addr == FDT_ADDR_T_NONE)
> + return -EINVAL;
> +
> + params->base = (struct imxrt_semc_regs *)addr;
> +
> +#ifdef CONFIG_CLK
> + struct clk clk;
> +
> + ret = clk_get_by_index(dev, 0, &clk);
> + if (ret < 0)
> + return ret;
> +
> + ret = clk_enable(&clk);
> +
> + if (ret) {
> + dev_err(dev, "failed to enable clock\n");
> + return ret;
> + }
> +#endif
> + ret = imxrt_sdram_init(dev);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +
> +static int imxrt_semc_get_info(struct udevice *dev, struct ram_info
> *info) +{
> + return 0;
> +}
> +
> +static struct ram_ops imxrt_semc_ops = {
> + .get_info = imxrt_semc_get_info,
> +};
> +
> +static const struct udevice_id imxrt_semc_ids[] = {
> + { .compatible = "fsl,imxrt-semc", .data = 0 },
> + { }
> +};
> +
> +U_BOOT_DRIVER(imxrt_semc) = {
> + .name = "imxrt_semc",
> + .id = UCLASS_RAM,
> + .of_match = imxrt_semc_ids,
> + .ops = &imxrt_semc_ops,
> + .ofdata_to_platdata = imxrt_semc_ofdata_to_platdata,
> + .probe = imxrt_semc_probe,
> + .platdata_auto_alloc_size = sizeof(struct
> imxrt_sdram_params), +};
> diff --git a/include/dt-bindings/memory/imxrt-sdram.h
> b/include/dt-bindings/memory/imxrt-sdram.h new file mode 100644
> index 0000000000..acb35bce27
> --- /dev/null
> +++ b/include/dt-bindings/memory/imxrt-sdram.h
> @@ -0,0 +1,100 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2019
> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> + */
> +
> +#ifndef DT_BINDINGS_IMXRT_SDRAM_H
> +#define DT_BINDINGS_IMXRT_SDRAM_H
> +
> +#define MEM_SIZE_4K 0x00
> +#define MEM_SIZE_8K 0x01
> +#define MEM_SIZE_16K 0x02
> +#define MEM_SIZE_32K 0x03
> +#define MEM_SIZE_64K 0x04
> +#define MEM_SIZE_128K 0x05
> +#define MEM_SIZE_256K 0x06
> +#define MEM_SIZE_512K 0x07
> +#define MEM_SIZE_1M 0x08
> +#define MEM_SIZE_2M 0x09
> +#define MEM_SIZE_4M 0x0A
> +#define MEM_SIZE_8M 0x0B
> +#define MEM_SIZE_16M 0x0C
> +#define MEM_SIZE_32M 0x0D
> +#define MEM_SIZE_64M 0x0E
> +#define MEM_SIZE_128M 0x0F
> +#define MEM_SIZE_256M 0x10
> +#define MEM_SIZE_512M 0x11
> +#define MEM_SIZE_1G 0x12
> +#define MEM_SIZE_2G 0x13
> +#define MEM_SIZE_4G 0x14
> +
> +#define MUX_A8_SDRAM_A8 0x0
> +#define MUX_A8_NAND_CE 0x1
> +#define MUX_A8_NOR_CE 0x2
> +#define MUX_A8_PSRAM_CE 0x3
> +#define MUX_A8_DBI_CSX 0x4
> +
> +#define MUX_CSX0_NOR_PSRAM_A24 0x0
> +#define MUX_CSX0_SDRAM_CS1 0x1
> +#define MUX_CSX0_SDRAM_CS2 0x2
> +#define MUX_CSX0_SDRAM_CS3 0x3
> +#define MUX_CSX0_NAND_CE 0x4
> +#define MUX_CSX0_NOR_CE 0x5
> +#define MUX_CSX0_PSRAM_CE 0x6
> +#define MUX_CSX0_DBI_CSX 0x7
> +
> +#define MUX_CSX1_NOR_PSRAM_A25 0x0
> +#define MUX_CSX1_SDRAM_CS1 0x1
> +#define MUX_CSX1_SDRAM_CS2 0x2
> +#define MUX_CSX1_SDRAM_CS3 0x3
> +#define MUX_CSX1_NAND_CE 0x4
> +#define MUX_CSX1_NOR_CE 0x5
> +#define MUX_CSX1_PSRAM_CE 0x6
> +#define MUX_CSX1_DBI_CSX 0x7
> +
> +#define MUX_CSX2_NOR_PSRAM_A26 0x0
> +#define MUX_CSX2_SDRAM_CS1 0x1
> +#define MUX_CSX2_SDRAM_CS2 0x2
> +#define MUX_CSX2_SDRAM_CS3 0x3
> +#define MUX_CSX2_NAND_CE 0x4
> +#define MUX_CSX2_NOR_CE 0x5
> +#define MUX_CSX2_PSRAM_CE 0x6
> +#define MUX_CSX2_DBI_CSX 0x7
> +
> +#define MUX_CSX3_NOR_PSRAM_A27 0x0
> +#define MUX_CSX3_SDRAM_CS1 0x1
> +#define MUX_CSX3_SDRAM_CS2 0x2
> +#define MUX_CSX3_SDRAM_CS3 0x3
> +#define MUX_CSX3_NAND_CE 0x4
> +#define MUX_CSX3_NOR_CE 0x5
> +#define MUX_CSX3_PSRAM_CE 0x6
> +#define MUX_CSX3_DBI_CSX 0x7
> +
> +#define MUX_RDY_NAND_RDY_WAIT 0x0
> +#define MUX_RDY_SDRAM_CS1 0x1
> +#define MUX_RDY_SDRAM_CS2 0x2
> +#define MUX_RDY_SDRAM_CS3 0x3
> +#define MUX_RDY_NOR_CE 0x4
> +#define MUX_RDY_PSRAM_CE 0x5
> +#define MUX_RDY_DBI_CSX 0x6
> +#define MUX_RDY_NOR_PSRAM_A27 0x7
> +
> +#define MEM_WIDTH_8BITS 0x0
> +#define MEM_WIDTH_16BITS 0x1
> +
> +#define BL_1 0x0
> +#define BL_2 0x1
> +#define BL_4 0x2
> +#define BL_8 0x3
> +
> +#define COL_12BITS 0x0
> +#define COL_11BITS 0x1
> +#define COL_10BITS 0x2
> +#define COL_9BITS 0x3
> +
> +#define CL_1 0x0
> +#define CL_2 0x2
> +#define CL_3 0x3
> +
> +#endif
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 18/21] mmc: fsl_esdhc: make if(CONFIG_IS_ENABLED(CLK)) an #if statement
2020-01-10 14:51 [PATCH v2 16/21] serial_lpuart: add support for i.MXRT Giulio Benetti
2020-01-10 14:51 ` [PATCH v2 17/21] ram: add SDRAM driver for i.MXRT SoCs Giulio Benetti
@ 2020-01-10 14:51 ` Giulio Benetti
2020-01-15 12:47 ` sbabic at denx.de
2020-01-28 8:47 ` Lukasz Majewski
2020-01-10 14:51 ` [PATCH v2 19/21] mmc: fsl_esdhc: add compatible for fsl, imxrt-usdhc Giulio Benetti
` (4 subsequent siblings)
6 siblings, 2 replies; 19+ messages in thread
From: Giulio Benetti @ 2020-01-10 14:51 UTC (permalink / raw)
To: u-boot
Not all architectures(i.e. i.MXRT) support mxc_get_clock() and use DM_CLK
instead. So building could result in failure due to missing
mxc_get_clock().
Make if(CONFIG_IS_ENABLED(CLK)) an #if statement.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
---
drivers/mmc/fsl_esdhc_imx.c | 38 ++++++++++++++++++-------------------
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index f7b754bd9d..e015eb9661 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -1515,27 +1515,27 @@ static int fsl_esdhc_probe(struct udevice *dev)
init_clk_usdhc(dev->seq);
- if (CONFIG_IS_ENABLED(CLK)) {
- /* Assigned clock already set clock */
- ret = clk_get_by_name(dev, "per", &priv->per_clk);
- if (ret) {
- printf("Failed to get per_clk\n");
- return ret;
- }
- ret = clk_enable(&priv->per_clk);
- if (ret) {
- printf("Failed to enable per_clk\n");
- return ret;
- }
+#if CONFIG_IS_ENABLED(CLK)
+ /* Assigned clock already set clock */
+ ret = clk_get_by_name(dev, "per", &priv->per_clk);
+ if (ret) {
+ printf("Failed to get per_clk\n");
+ return ret;
+ }
+ ret = clk_enable(&priv->per_clk);
+ if (ret) {
+ printf("Failed to enable per_clk\n");
+ return ret;
+ }
- priv->sdhc_clk = clk_get_rate(&priv->per_clk);
- } else {
- priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
- if (priv->sdhc_clk <= 0) {
- dev_err(dev, "Unable to get clk for %s\n", dev->name);
- return -EINVAL;
- }
+ priv->sdhc_clk = clk_get_rate(&priv->per_clk);
+#else
+ priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
+ if (priv->sdhc_clk <= 0) {
+ dev_err(dev, "Unable to get clk for %s\n", dev->name);
+ return -EINVAL;
}
+#endif
ret = fsl_esdhc_init(priv, plat);
if (ret) {
--
2.20.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 18/21] mmc: fsl_esdhc: make if(CONFIG_IS_ENABLED(CLK)) an #if statement
2020-01-10 14:51 ` [PATCH v2 18/21] mmc: fsl_esdhc: make if(CONFIG_IS_ENABLED(CLK)) an #if statement Giulio Benetti
@ 2020-01-15 12:47 ` sbabic at denx.de
2020-01-28 8:47 ` Lukasz Majewski
1 sibling, 0 replies; 19+ messages in thread
From: sbabic at denx.de @ 2020-01-15 12:47 UTC (permalink / raw)
To: u-boot
> Not all architectures(i.e. i.MXRT) support mxc_get_clock() and use DM_CLK
> instead. So building could result in failure due to missing
> mxc_get_clock().
> Make if(CONFIG_IS_ENABLED(CLK)) an #if statement.
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 18/21] mmc: fsl_esdhc: make if(CONFIG_IS_ENABLED(CLK)) an #if statement
2020-01-10 14:51 ` [PATCH v2 18/21] mmc: fsl_esdhc: make if(CONFIG_IS_ENABLED(CLK)) an #if statement Giulio Benetti
2020-01-15 12:47 ` sbabic at denx.de
@ 2020-01-28 8:47 ` Lukasz Majewski
1 sibling, 0 replies; 19+ messages in thread
From: Lukasz Majewski @ 2020-01-28 8:47 UTC (permalink / raw)
To: u-boot
Hi Giulio,
> Not all architectures(i.e. i.MXRT) support mxc_get_clock() and use
> DM_CLK instead. So building could result in failure due to missing
> mxc_get_clock().
>
> Make if(CONFIG_IS_ENABLED(CLK)) an #if statement.
>
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> ---
> drivers/mmc/fsl_esdhc_imx.c | 38
> ++++++++++++++++++------------------- 1 file changed, 19
> insertions(+), 19 deletions(-)
>
> diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
> index f7b754bd9d..e015eb9661 100644
> --- a/drivers/mmc/fsl_esdhc_imx.c
> +++ b/drivers/mmc/fsl_esdhc_imx.c
> @@ -1515,27 +1515,27 @@ static int fsl_esdhc_probe(struct udevice
> *dev)
> init_clk_usdhc(dev->seq);
>
> - if (CONFIG_IS_ENABLED(CLK)) {
> - /* Assigned clock already set clock */
> - ret = clk_get_by_name(dev, "per", &priv->per_clk);
> - if (ret) {
> - printf("Failed to get per_clk\n");
> - return ret;
> - }
> - ret = clk_enable(&priv->per_clk);
> - if (ret) {
> - printf("Failed to enable per_clk\n");
> - return ret;
> - }
> +#if CONFIG_IS_ENABLED(CLK)
> + /* Assigned clock already set clock */
> + ret = clk_get_by_name(dev, "per", &priv->per_clk);
> + if (ret) {
> + printf("Failed to get per_clk\n");
> + return ret;
> + }
> + ret = clk_enable(&priv->per_clk);
> + if (ret) {
> + printf("Failed to enable per_clk\n");
> + return ret;
> + }
>
> - priv->sdhc_clk = clk_get_rate(&priv->per_clk);
> - } else {
> - priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK +
> dev->seq);
> - if (priv->sdhc_clk <= 0) {
> - dev_err(dev, "Unable to get clk for %s\n",
> dev->name);
> - return -EINVAL;
> - }
> + priv->sdhc_clk = clk_get_rate(&priv->per_clk);
> +#else
> + priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
> + if (priv->sdhc_clk <= 0) {
> + dev_err(dev, "Unable to get clk for %s\n",
> dev->name);
> + return -EINVAL;
> }
> +#endif
>
> ret = fsl_esdhc_init(priv, plat);
> if (ret) {
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 19/21] mmc: fsl_esdhc: add compatible for fsl, imxrt-usdhc
2020-01-10 14:51 [PATCH v2 16/21] serial_lpuart: add support for i.MXRT Giulio Benetti
2020-01-10 14:51 ` [PATCH v2 17/21] ram: add SDRAM driver for i.MXRT SoCs Giulio Benetti
2020-01-10 14:51 ` [PATCH v2 18/21] mmc: fsl_esdhc: make if(CONFIG_IS_ENABLED(CLK)) an #if statement Giulio Benetti
@ 2020-01-10 14:51 ` Giulio Benetti
2020-01-15 12:47 ` sbabic at denx.de
2020-01-28 8:49 ` Lukasz Majewski
2020-01-10 14:51 ` [PATCH v2 20/21] imx: Add basic support for the NXP IMXRT10xx SoC family Giulio Benetti
` (3 subsequent siblings)
6 siblings, 2 replies; 19+ messages in thread
From: Giulio Benetti @ 2020-01-10 14:51 UTC (permalink / raw)
To: u-boot
Add compatible "fsl,imxrt-usdhc" to make mmc working on i.MXRT platforms
with CONFIG_DM_MMC=y.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
---
drivers/mmc/Kconfig | 2 +-
drivers/mmc/fsl_esdhc_imx.c | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 85fd1906bd..2bc19dd56b 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -732,7 +732,7 @@ config FSL_ESDHC_IMX
config FSL_USDHC
bool "Freescale/NXP i.MX uSDHC controller support"
- depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || TARGET_S32V234EVB
+ depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMXRT || TARGET_S32V234EVB
select FSL_ESDHC_IMX
help
This enables the Ultra Secured Digital Host Controller enhancements
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index e015eb9661..551233dd2a 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -78,7 +78,7 @@ struct fsl_esdhc {
uint vendorspec;
uint mmcboot;
uint vendorspec2;
- uint tuning_ctrl; /* on i.MX6/7/8 */
+ uint tuning_ctrl; /* on i.MX6/7/8/RT */
char reserved5[44];
uint hostver; /* Host controller version register */
char reserved6[4]; /* reserved */
@@ -1652,6 +1652,7 @@ static const struct udevice_id fsl_esdhc_ids[] = {
{ .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
{ .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
{ .compatible = "fsl,imx8mq-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
+ { .compatible = "fsl,imxrt-usdhc", },
{ .compatible = "fsl,esdhc", },
{ /* sentinel */ }
};
--
2.20.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 19/21] mmc: fsl_esdhc: add compatible for fsl, imxrt-usdhc
2020-01-10 14:51 ` [PATCH v2 19/21] mmc: fsl_esdhc: add compatible for fsl, imxrt-usdhc Giulio Benetti
@ 2020-01-15 12:47 ` sbabic at denx.de
2020-01-28 8:49 ` Lukasz Majewski
1 sibling, 0 replies; 19+ messages in thread
From: sbabic at denx.de @ 2020-01-15 12:47 UTC (permalink / raw)
To: u-boot
> Add compatible "fsl,imxrt-usdhc" to make mmc working on i.MXRT platforms
> with CONFIG_DM_MMC=y.
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 19/21] mmc: fsl_esdhc: add compatible for fsl, imxrt-usdhc
2020-01-10 14:51 ` [PATCH v2 19/21] mmc: fsl_esdhc: add compatible for fsl, imxrt-usdhc Giulio Benetti
2020-01-15 12:47 ` sbabic at denx.de
@ 2020-01-28 8:49 ` Lukasz Majewski
1 sibling, 0 replies; 19+ messages in thread
From: Lukasz Majewski @ 2020-01-28 8:49 UTC (permalink / raw)
To: u-boot
Hi Giulio,
> Add compatible "fsl,imxrt-usdhc" to make mmc working on i.MXRT
> platforms with CONFIG_DM_MMC=y.
>
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> ---
> drivers/mmc/Kconfig | 2 +-
> drivers/mmc/fsl_esdhc_imx.c | 3 ++-
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
> index 85fd1906bd..2bc19dd56b 100644
> --- a/drivers/mmc/Kconfig
> +++ b/drivers/mmc/Kconfig
> @@ -732,7 +732,7 @@ config FSL_ESDHC_IMX
>
> config FSL_USDHC
> bool "Freescale/NXP i.MX uSDHC controller support"
> - depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M ||
> TARGET_S32V234EVB
> + depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M ||
> IMXRT || TARGET_S32V234EVB select FSL_ESDHC_IMX
> help
> This enables the Ultra Secured Digital Host Controller
> enhancements diff --git a/drivers/mmc/fsl_esdhc_imx.c
> b/drivers/mmc/fsl_esdhc_imx.c index e015eb9661..551233dd2a 100644
> --- a/drivers/mmc/fsl_esdhc_imx.c
> +++ b/drivers/mmc/fsl_esdhc_imx.c
> @@ -78,7 +78,7 @@ struct fsl_esdhc {
> uint vendorspec;
> uint mmcboot;
> uint vendorspec2;
> - uint tuning_ctrl; /* on i.MX6/7/8 */
> + uint tuning_ctrl; /* on i.MX6/7/8/RT */
> char reserved5[44];
> uint hostver; /* Host controller version register
> */ char reserved6[4]; /* reserved */
> @@ -1652,6 +1652,7 @@ static const struct udevice_id fsl_esdhc_ids[]
> = { { .compatible = "fsl,imx8mm-usdhc", .data =
> (ulong)&usdhc_imx8qm_data,}, { .compatible = "fsl,imx8mn-usdhc",
> .data = (ulong)&usdhc_imx8qm_data,}, { .compatible =
> "fsl,imx8mq-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
> + { .compatible = "fsl,imxrt-usdhc", },
> { .compatible = "fsl,esdhc", },
> { /* sentinel */ }
> };
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 20/21] imx: Add basic support for the NXP IMXRT10xx SoC family
2020-01-10 14:51 [PATCH v2 16/21] serial_lpuart: add support for i.MXRT Giulio Benetti
` (2 preceding siblings ...)
2020-01-10 14:51 ` [PATCH v2 19/21] mmc: fsl_esdhc: add compatible for fsl, imxrt-usdhc Giulio Benetti
@ 2020-01-10 14:51 ` Giulio Benetti
2020-01-15 12:46 ` sbabic at denx.de
2020-01-28 8:52 ` Lukasz Majewski
2020-01-10 14:51 ` [PATCH v2 21/21] imx: imxrt1050-evk: Add support for the NXP i.MXRT1050-EVK Giulio Benetti
` (2 subsequent siblings)
6 siblings, 2 replies; 19+ messages in thread
From: Giulio Benetti @ 2020-01-10 14:51 UTC (permalink / raw)
To: u-boot
Add i.IMXRT family basic support.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
---
V1->V2:
* introduced CONFIG_IMXRT
---
arch/arm/Kconfig | 10 ++++++
arch/arm/Makefile | 4 +--
arch/arm/include/asm/arch-imxrt/clock.h | 10 ++++++
arch/arm/include/asm/arch-imxrt/gpio.h | 19 +++++++++++
arch/arm/include/asm/arch-imxrt/imx-regs.h | 20 ++++++++++++
arch/arm/include/asm/arch-imxrt/imxrt.h | 11 +++++++
arch/arm/include/asm/arch-imxrt/sys_proto.h | 11 +++++++
arch/arm/mach-imx/Makefile | 3 +-
arch/arm/mach-imx/imxrt/Kconfig | 13 ++++++++
arch/arm/mach-imx/imxrt/Makefile | 7 +++++
arch/arm/mach-imx/imxrt/soc.c | 35 +++++++++++++++++++++
11 files changed, 140 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/include/asm/arch-imxrt/clock.h
create mode 100644 arch/arm/include/asm/arch-imxrt/gpio.h
create mode 100644 arch/arm/include/asm/arch-imxrt/imx-regs.h
create mode 100644 arch/arm/include/asm/arch-imxrt/imxrt.h
create mode 100644 arch/arm/include/asm/arch-imxrt/sys_proto.h
create mode 100644 arch/arm/mach-imx/imxrt/Kconfig
create mode 100644 arch/arm/mach-imx/imxrt/Makefile
create mode 100644 arch/arm/mach-imx/imxrt/soc.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 76365ef313..4c7d04400a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -797,6 +797,14 @@ config ARCH_IMX8M
select SUPPORT_SPL
imply CMD_DM
+config ARCH_IMXRT
+ bool "NXP i.MXRT platform"
+ select CPU_V7M
+ select DM
+ select DM_SERIAL
+ select SUPPORT_SPL
+ imply CMD_DM
+
config ARCH_MX23
bool "NXP i.MX23 family"
select CPU_ARM926EJS
@@ -1722,6 +1730,8 @@ source "arch/arm/mach-imx/imx8/Kconfig"
source "arch/arm/mach-imx/imx8m/Kconfig"
+source "arch/arm/mach-imx/imxrt/Kconfig"
+
source "arch/arm/mach-imx/mxs/Kconfig"
source "arch/arm/mach-omap2/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 856f2d8608..1e60a9fdd4 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -104,11 +104,11 @@ libs-y += arch/arm/cpu/
libs-y += arch/arm/lib/
ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8))
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imxrt))
libs-y += arch/arm/mach-imx/
endif
else
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 vf610))
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 imxrt vf610))
libs-y += arch/arm/mach-imx/
endif
endif
diff --git a/arch/arm/include/asm/arch-imxrt/clock.h b/arch/arm/include/asm/arch-imxrt/clock.h
new file mode 100644
index 0000000000..7409028b9a
--- /dev/null
+++ b/arch/arm/include/asm/arch-imxrt/clock.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-imxrt/gpio.h b/arch/arm/include/asm/arch-imxrt/gpio.h
new file mode 100644
index 0000000000..da31a7438a
--- /dev/null
+++ b/arch/arm/include/asm/arch-imxrt/gpio.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+/* GPIO registers */
+struct gpio_regs {
+ u32 gpio_dr; /* data */
+ u32 gpio_dir; /* direction */
+ u32 gpio_psr; /* pad satus */
+};
+#endif
+
+#endif /* __ASM_ARCH_GPIO_H__ */
diff --git a/arch/arm/include/asm/arch-imxrt/imx-regs.h b/arch/arm/include/asm/arch-imxrt/imx-regs.h
new file mode 100644
index 0000000000..4f1d439f6f
--- /dev/null
+++ b/arch/arm/include/asm/arch-imxrt/imx-regs.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright(C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef __ASM_ARCH_IMX_REGS_H__
+#define __ASM_ARCH_IMX_REGS_H__
+
+#define ARCH_MXC
+
+#define GPIO1_BASE_ADDR 0x401B8000
+#define GPIO2_BASE_ADDR 0x401BC000
+#define GPIO3_BASE_ADDR 0x401C0000
+#define GPIO4_BASE_ADDR 0x401C4000
+#define GPIO5_BASE_ADDR 0x400C0000
+
+#define ANATOP_BASE_ADDR 0x400d8000
+
+#endif /* __ASM_ARCH_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-imxrt/imxrt.h b/arch/arm/include/asm/arch-imxrt/imxrt.h
new file mode 100644
index 0000000000..1cb2c57d31
--- /dev/null
+++ b/arch/arm/include/asm/arch-imxrt/imxrt.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef _ASM_ARCH_IMXRT_H
+#define _ASM_ARCH_IMXRT_H
+
+#endif /* _ASM_ARCH_IMXRT_H */
+
diff --git a/arch/arm/include/asm/arch-imxrt/sys_proto.h b/arch/arm/include/asm/arch-imxrt/sys_proto.h
new file mode 100644
index 0000000000..eb878e672e
--- /dev/null
+++ b/arch/arm/include/asm/arch-imxrt/sys_proto.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 NXP
+ */
+
+#ifndef _ASM_ARCH_SYS_PROTO_H
+#define _ASM_ARCH_SYS_PROTO_H
+
+#include <asm/mach-imx/sys_proto.h>
+
+#endif /* _ASM_ARCH_SYS_PROTO_H */
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index e14713c5c4..a70d51b5cf 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -27,7 +27,7 @@ endif
obj-$(CONFIG_GPT_TIMER) += timer.o
obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
endif
-ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8))
+ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8 imxrt))
obj-y += misc.o
obj-$(CONFIG_SPL_BUILD) += spl.o
endif
@@ -226,5 +226,6 @@ obj-$(CONFIG_MX7) += mx7/
obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
obj-$(CONFIG_IMX8M) += imx8m/
obj-$(CONFIG_ARCH_IMX8) += imx8/
+obj-$(CONFIG_ARCH_IMXRT) += imxrt/
obj-$(CONFIG_SPL_BOOTROM_SUPPORT) += spl_imx_romapi.o
diff --git a/arch/arm/mach-imx/imxrt/Kconfig b/arch/arm/mach-imx/imxrt/Kconfig
new file mode 100644
index 0000000000..96ad2e988b
--- /dev/null
+++ b/arch/arm/mach-imx/imxrt/Kconfig
@@ -0,0 +1,13 @@
+if ARCH_IMXRT
+
+config IMXRT
+ bool
+
+config IMXRT1050
+ bool
+ select IMXRT
+
+config SYS_SOC
+ default "imxrt"
+
+endif
diff --git a/arch/arm/mach-imx/imxrt/Makefile b/arch/arm/mach-imx/imxrt/Makefile
new file mode 100644
index 0000000000..9621a8335a
--- /dev/null
+++ b/arch/arm/mach-imx/imxrt/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019
+# Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+#
+
+obj-y := soc.o
diff --git a/arch/arm/mach-imx/imxrt/soc.c b/arch/arm/mach-imx/imxrt/soc.c
new file mode 100644
index 0000000000..e1eea23035
--- /dev/null
+++ b/arch/arm/mach-imx/imxrt/soc.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/armv7_mpu.h>
+
+int arch_cpu_init(void)
+{
+ int i;
+
+ struct mpu_region_config imxrt1050_region_config[] = {
+ { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
+ STRONG_ORDER, REGION_4GB },
+ { PHYS_SDRAM, REGION_1, XN_DIS, PRIV_RW_USR_RW,
+ O_I_WB_RD_WR_ALLOC, (ffs(PHYS_SDRAM_SIZE) - 2) },
+ { DMAMEM_BASE,
+ REGION_2, XN_DIS, PRIV_RW_USR_RW,
+ STRONG_ORDER, (ffs(DMAMEM_SZ_ALL) - 2) },
+ };
+
+ /*
+ * Configure the memory protection unit (MPU) to allow full access to
+ * the whole 4GB address space.
+ */
+ disable_mpu();
+ for (i = 0; i < ARRAY_SIZE(imxrt1050_region_config); i++)
+ mpu_config(&imxrt1050_region_config[i]);
+ enable_mpu();
+
+ return 0;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 20/21] imx: Add basic support for the NXP IMXRT10xx SoC family
2020-01-10 14:51 ` [PATCH v2 20/21] imx: Add basic support for the NXP IMXRT10xx SoC family Giulio Benetti
@ 2020-01-15 12:46 ` sbabic at denx.de
2020-01-28 8:52 ` Lukasz Majewski
1 sibling, 0 replies; 19+ messages in thread
From: sbabic at denx.de @ 2020-01-15 12:46 UTC (permalink / raw)
To: u-boot
> Add i.IMXRT family basic support.
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 20/21] imx: Add basic support for the NXP IMXRT10xx SoC family
2020-01-10 14:51 ` [PATCH v2 20/21] imx: Add basic support for the NXP IMXRT10xx SoC family Giulio Benetti
2020-01-15 12:46 ` sbabic at denx.de
@ 2020-01-28 8:52 ` Lukasz Majewski
1 sibling, 0 replies; 19+ messages in thread
From: Lukasz Majewski @ 2020-01-28 8:52 UTC (permalink / raw)
To: u-boot
Hi Giulio,
> Add i.IMXRT family basic support.
>
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> ---
> V1->V2:
> * introduced CONFIG_IMXRT
> ---
> arch/arm/Kconfig | 10 ++++++
> arch/arm/Makefile | 4 +--
> arch/arm/include/asm/arch-imxrt/clock.h | 10 ++++++
> arch/arm/include/asm/arch-imxrt/gpio.h | 19 +++++++++++
> arch/arm/include/asm/arch-imxrt/imx-regs.h | 20 ++++++++++++
> arch/arm/include/asm/arch-imxrt/imxrt.h | 11 +++++++
> arch/arm/include/asm/arch-imxrt/sys_proto.h | 11 +++++++
> arch/arm/mach-imx/Makefile | 3 +-
> arch/arm/mach-imx/imxrt/Kconfig | 13 ++++++++
> arch/arm/mach-imx/imxrt/Makefile | 7 +++++
> arch/arm/mach-imx/imxrt/soc.c | 35
> +++++++++++++++++++++ 11 files changed, 140 insertions(+), 3
> deletions(-) create mode 100644
> arch/arm/include/asm/arch-imxrt/clock.h create mode 100644
> arch/arm/include/asm/arch-imxrt/gpio.h create mode 100644
> arch/arm/include/asm/arch-imxrt/imx-regs.h create mode 100644
> arch/arm/include/asm/arch-imxrt/imxrt.h create mode 100644
> arch/arm/include/asm/arch-imxrt/sys_proto.h create mode 100644
> arch/arm/mach-imx/imxrt/Kconfig create mode 100644
> arch/arm/mach-imx/imxrt/Makefile create mode 100644
> arch/arm/mach-imx/imxrt/soc.c
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 76365ef313..4c7d04400a 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -797,6 +797,14 @@ config ARCH_IMX8M
> select SUPPORT_SPL
> imply CMD_DM
>
> +config ARCH_IMXRT
> + bool "NXP i.MXRT platform"
> + select CPU_V7M
> + select DM
> + select DM_SERIAL
> + select SUPPORT_SPL
> + imply CMD_DM
> +
> config ARCH_MX23
> bool "NXP i.MX23 family"
> select CPU_ARM926EJS
> @@ -1722,6 +1730,8 @@ source "arch/arm/mach-imx/imx8/Kconfig"
>
> source "arch/arm/mach-imx/imx8m/Kconfig"
>
> +source "arch/arm/mach-imx/imxrt/Kconfig"
> +
> source "arch/arm/mach-imx/mxs/Kconfig"
>
> source "arch/arm/mach-omap2/Kconfig"
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index 856f2d8608..1e60a9fdd4 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -104,11 +104,11 @@ libs-y += arch/arm/cpu/
> libs-y += arch/arm/lib/
>
> ifeq ($(CONFIG_SPL_BUILD),y)
> -ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC),
> mx25 mx5 mx6 mx7 mx35 imx8m imx8)) +ifneq
> (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5
> mx6 mx7 mx35 imx8m imx8 imxrt)) libs-y += arch/arm/mach-imx/ endif
> else
> -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs
> imx8m imx8 vf610)) +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7
> mx7ulp mx31 mx35 mxs imx8m imx8 imxrt vf610)) libs-y +=
> arch/arm/mach-imx/ endif
> endif
> diff --git a/arch/arm/include/asm/arch-imxrt/clock.h
> b/arch/arm/include/asm/arch-imxrt/clock.h new file mode 100644
> index 0000000000..7409028b9a
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-imxrt/clock.h
> @@ -0,0 +1,10 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2019
> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> + */
> +
> +#ifndef __ASM_ARCH_CLOCK_H
> +#define __ASM_ARCH_CLOCK_H
> +
> +#endif /* __ASM_ARCH_CLOCK_H */
> diff --git a/arch/arm/include/asm/arch-imxrt/gpio.h
> b/arch/arm/include/asm/arch-imxrt/gpio.h new file mode 100644
> index 0000000000..da31a7438a
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-imxrt/gpio.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2019
> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> + */
> +
> +#ifndef __ASM_ARCH_GPIO_H__
> +#define __ASM_ARCH_GPIO_H__
> +
> +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
> +/* GPIO registers */
> +struct gpio_regs {
> + u32 gpio_dr; /* data */
> + u32 gpio_dir; /* direction */
> + u32 gpio_psr; /* pad satus */
> +};
> +#endif
> +
> +#endif /* __ASM_ARCH_GPIO_H__ */
> diff --git a/arch/arm/include/asm/arch-imxrt/imx-regs.h
> b/arch/arm/include/asm/arch-imxrt/imx-regs.h new file mode 100644
> index 0000000000..4f1d439f6f
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-imxrt/imx-regs.h
> @@ -0,0 +1,20 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright(C) 2019
> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> + */
> +
> +#ifndef __ASM_ARCH_IMX_REGS_H__
> +#define __ASM_ARCH_IMX_REGS_H__
> +
> +#define ARCH_MXC
> +
> +#define GPIO1_BASE_ADDR 0x401B8000
> +#define GPIO2_BASE_ADDR 0x401BC000
> +#define GPIO3_BASE_ADDR 0x401C0000
> +#define GPIO4_BASE_ADDR 0x401C4000
> +#define GPIO5_BASE_ADDR 0x400C0000
> +
> +#define ANATOP_BASE_ADDR 0x400d8000
> +
> +#endif /* __ASM_ARCH_IMX_REGS_H__ */
> diff --git a/arch/arm/include/asm/arch-imxrt/imxrt.h
> b/arch/arm/include/asm/arch-imxrt/imxrt.h new file mode 100644
> index 0000000000..1cb2c57d31
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-imxrt/imxrt.h
> @@ -0,0 +1,11 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2019
> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> + */
> +
> +#ifndef _ASM_ARCH_IMXRT_H
> +#define _ASM_ARCH_IMXRT_H
> +
> +#endif /* _ASM_ARCH_IMXRT_H */
> +
> diff --git a/arch/arm/include/asm/arch-imxrt/sys_proto.h
> b/arch/arm/include/asm/arch-imxrt/sys_proto.h new file mode 100644
> index 0000000000..eb878e672e
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-imxrt/sys_proto.h
> @@ -0,0 +1,11 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2017 NXP
> + */
> +
> +#ifndef _ASM_ARCH_SYS_PROTO_H
> +#define _ASM_ARCH_SYS_PROTO_H
> +
> +#include <asm/mach-imx/sys_proto.h>
> +
> +#endif /* _ASM_ARCH_SYS_PROTO_H */
> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> index e14713c5c4..a70d51b5cf 100644
> --- a/arch/arm/mach-imx/Makefile
> +++ b/arch/arm/mach-imx/Makefile
> @@ -27,7 +27,7 @@ endif
> obj-$(CONFIG_GPT_TIMER) += timer.o
> obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
> endif
> -ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8))
> +ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8 imxrt))
> obj-y += misc.o
> obj-$(CONFIG_SPL_BUILD) += spl.o
> endif
> @@ -226,5 +226,6 @@ obj-$(CONFIG_MX7) += mx7/
> obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
> obj-$(CONFIG_IMX8M) += imx8m/
> obj-$(CONFIG_ARCH_IMX8) += imx8/
> +obj-$(CONFIG_ARCH_IMXRT) += imxrt/
>
> obj-$(CONFIG_SPL_BOOTROM_SUPPORT) += spl_imx_romapi.o
> diff --git a/arch/arm/mach-imx/imxrt/Kconfig
> b/arch/arm/mach-imx/imxrt/Kconfig new file mode 100644
> index 0000000000..96ad2e988b
> --- /dev/null
> +++ b/arch/arm/mach-imx/imxrt/Kconfig
> @@ -0,0 +1,13 @@
> +if ARCH_IMXRT
> +
> +config IMXRT
> + bool
> +
> +config IMXRT1050
> + bool
> + select IMXRT
> +
> +config SYS_SOC
> + default "imxrt"
> +
> +endif
> diff --git a/arch/arm/mach-imx/imxrt/Makefile
> b/arch/arm/mach-imx/imxrt/Makefile new file mode 100644
> index 0000000000..9621a8335a
> --- /dev/null
> +++ b/arch/arm/mach-imx/imxrt/Makefile
> @@ -0,0 +1,7 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# (C) Copyright 2019
> +# Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> +#
> +
> +obj-y := soc.o
> diff --git a/arch/arm/mach-imx/imxrt/soc.c
> b/arch/arm/mach-imx/imxrt/soc.c new file mode 100644
> index 0000000000..e1eea23035
> --- /dev/null
> +++ b/arch/arm/mach-imx/imxrt/soc.c
> @@ -0,0 +1,35 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019
> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/armv7_mpu.h>
> +
> +int arch_cpu_init(void)
> +{
> + int i;
> +
> + struct mpu_region_config imxrt1050_region_config[] = {
> + { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
> + STRONG_ORDER, REGION_4GB },
> + { PHYS_SDRAM, REGION_1, XN_DIS, PRIV_RW_USR_RW,
> + O_I_WB_RD_WR_ALLOC, (ffs(PHYS_SDRAM_SIZE) - 2) },
> + { DMAMEM_BASE,
> + REGION_2, XN_DIS, PRIV_RW_USR_RW,
> + STRONG_ORDER, (ffs(DMAMEM_SZ_ALL) - 2) },
> + };
> +
> + /*
> + * Configure the memory protection unit (MPU) to allow full
> access to
> + * the whole 4GB address space.
> + */
> + disable_mpu();
> + for (i = 0; i < ARRAY_SIZE(imxrt1050_region_config); i++)
> + mpu_config(&imxrt1050_region_config[i]);
> + enable_mpu();
> +
> + return 0;
> +}
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 21/21] imx: imxrt1050-evk: Add support for the NXP i.MXRT1050-EVK
2020-01-10 14:51 [PATCH v2 16/21] serial_lpuart: add support for i.MXRT Giulio Benetti
` (3 preceding siblings ...)
2020-01-10 14:51 ` [PATCH v2 20/21] imx: Add basic support for the NXP IMXRT10xx SoC family Giulio Benetti
@ 2020-01-10 14:51 ` Giulio Benetti
2020-01-15 12:48 ` sbabic at denx.de
2020-01-28 9:02 ` Lukasz Majewski
2020-01-15 12:46 ` [PATCH v2 16/21] serial_lpuart: add support for i.MXRT sbabic at denx.de
2020-01-28 8:40 ` Lukasz Majewski
6 siblings, 2 replies; 19+ messages in thread
From: Giulio Benetti @ 2020-01-10 14:51 UTC (permalink / raw)
To: u-boot
This commit adds board support for i.MXRT1050-EVK from NXP. This board
is an evaluation kit provided by NXP for i.MXRT105x processor family.
More information about this board can be found here:
https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/i.mx-rt1050-evaluation-kit:MIMXRT1050-EVK
The initial supported/tested devices include:
- Debug serial
- SD
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
---
V1->V2:
* introduced CONFIG_IMXRT1050
* added imxrt1050-evk-u-boot.dtsi for imxrt1050-evk.dts
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 44 ++++
arch/arm/dts/imxrt1050-evk.dts | 200 ++++++++++++++++++
arch/arm/mach-imx/imxrt/Kconfig | 12 ++
board/freescale/imxrt1050-evk/Kconfig | 22 ++
board/freescale/imxrt1050-evk/MAINTAINERS | 6 +
board/freescale/imxrt1050-evk/Makefile | 6 +
board/freescale/imxrt1050-evk/README | 31 +++
board/freescale/imxrt1050-evk/imximage.cfg | 36 ++++
board/freescale/imxrt1050-evk/imxrt1050-evk.c | 81 +++++++
configs/imxrt1050-evk_defconfig | 69 ++++++
include/configs/imxrt1050-evk.h | 46 ++++
12 files changed, 555 insertions(+)
create mode 100644 arch/arm/dts/imxrt1050-evk-u-boot.dtsi
create mode 100644 arch/arm/dts/imxrt1050-evk.dts
create mode 100644 board/freescale/imxrt1050-evk/Kconfig
create mode 100644 board/freescale/imxrt1050-evk/MAINTAINERS
create mode 100644 board/freescale/imxrt1050-evk/Makefile
create mode 100644 board/freescale/imxrt1050-evk/README
create mode 100644 board/freescale/imxrt1050-evk/imximage.cfg
create mode 100644 board/freescale/imxrt1050-evk/imxrt1050-evk.c
create mode 100644 configs/imxrt1050-evk_defconfig
create mode 100644 include/configs/imxrt1050-evk.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 983e235f44..0864460751 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -707,6 +707,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-evk.dtb \
imx8mp-evk.dtb
+dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb
+
dtb-$(CONFIG_RCAR_GEN2) += \
r8a7790-lager-u-boot.dtb \
r8a7790-stout-u-boot.dtb \
diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
new file mode 100644
index 0000000000..fb4f7f6f9d
--- /dev/null
+++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+/ {
+ chosen {
+ u-boot,dm-spl;
+ };
+};
+
+&lpuart1 { /* console */
+ u-boot,dm-spl;
+};
+
+&semc {
+ bank1: bank at 0 {
+ u-boot,dm-spl;
+ };
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+
+ imxrt1050-evk {
+ u-boot,dm-spl;
+ pinctrl_lpuart1: lpuart1grp {
+ u-boot,dm-spl;
+ };
+
+ pinctrl_semc: semcgrp {
+ u-boot,dm-spl;
+ };
+
+ pinctrl_usdhc0: usdhc0grp {
+ u-boot,dm-spl;
+ };
+ };
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts
new file mode 100644
index 0000000000..56b75986e2
--- /dev/null
+++ b/arch/arm/dts/imxrt1050-evk.dts
@@ -0,0 +1,200 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+/dts-v1/;
+#include "imxrt1050.dtsi"
+#include "imxrt1050-evk-u-boot.dtsi"
+#include <dt-bindings/pinctrl/pins-imxrt1050.h>
+
+/ {
+ model = "NXP IMXRT1050-evk board";
+ compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
+
+ chosen {
+ bootargs = "root=/dev/ram";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0x80000000 0x2000000>;
+ };
+};
+
+&lpuart1 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart1>;
+ status = "okay";
+};
+
+&semc {
+ /*
+ * Memory configuration from sdram datasheet IS42S16160J-6BLI
+ */
+ fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
+ MUX_CSX0_SDRAM_CS1
+ 0
+ 0
+ 0
+ 0>;
+ fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
+ BL_8
+ COL_9BITS
+ CL_3>;
+ fsl,sdram-timing = /bits/ 8 <0x2
+ 0x2
+ 0x9
+ 0x1
+ 0x5
+ 0x6
+
+ 0x20
+ 0x09
+ 0x01
+ 0x00
+
+ 0x04
+ 0x0A
+ 0x21
+ 0x50>;
+
+ bank1: bank at 0 {
+ fsl,base-address = <0x80000000>;
+ fsl,memory-size = <MEM_SIZE_32M>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart1>;
+
+ imxrt1050-evk {
+ pinctrl_lpuart1: lpuart1grp {
+ fsl,pins = <
+ MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD
+ 0xf1
+ MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD
+ 0xf1
+ >;
+ };
+
+ pinctrl_semc: semcgrp {
+ fsl,pins = <
+ MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
+ 0xf1 /* SEMC_D0 */
+ MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
+ 0xf1 /* SEMC_D1 */
+ MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
+ 0xf1 /* SEMC_D2 */
+ MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
+ 0xf1 /* SEMC_D3 */
+ MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
+ 0xf1 /* SEMC_D4 */
+ MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05
+ 0xf1 /* SEMC_D5 */
+ MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06
+ 0xf1 /* SEMC_D6 */
+ MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07
+ 0xf1 /* SEMC_D7 */
+ MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00
+ 0xf1 /* SEMC_DM0 */
+ MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
+ 0xf1 /* SEMC_A0 */
+ MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01
+ 0xf1 /* SEMC_A1 */
+ MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02
+ 0xf1 /* SEMC_A2 */
+ MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03
+ 0xf1 /* SEMC_A3 */
+ MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04
+ 0xf1 /* SEMC_A4 */
+ MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05
+ 0xf1 /* SEMC_A5 */
+ MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06
+ 0xf1 /* SEMC_A6 */
+ MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07
+ 0xf1 /* SEMC_A7 */
+ MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08
+ 0xf1 /* SEMC_A8 */
+ MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09
+ 0xf1 /* SEMC_A9 */
+ MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11
+ 0xf1 /* SEMC_A11 */
+ MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12
+ 0xf1 /* SEMC_A12 */
+ MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0
+ 0xf1 /* SEMC_BA0 */
+ MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1
+ 0xf1 /* SEMC_BA1 */
+ MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10
+ 0xf1 /* SEMC_A10 */
+ MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS
+ 0xf1 /* SEMC_CAS */
+ MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS
+ 0xf1 /* SEMC_RAS */
+ MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK
+ 0xf1 /* SEMC_CLK */
+ MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE
+ 0xf1 /* SEMC_CKE */
+ MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE
+ 0xf1 /* SEMC_WE */
+ MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0
+ 0xf1 /* SEMC_CS0 */
+ MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08
+ 0xf1 /* SEMC_D8 */
+ MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09
+ 0xf1 /* SEMC_D9 */
+ MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10
+ 0xf1 /* SEMC_D10 */
+ MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11
+ 0xf1 /* SEMC_D11 */
+ MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12
+ 0xf1 /* SEMC_D12 */
+ MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13
+ 0xf1 /* SEMC_D13 */
+ MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14
+ 0xf1 /* SEMC_D14 */
+ MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15
+ 0xf1 /* SEMC_D15 */
+ MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01
+ 0xf1 /* SEMC_DM1 */
+ MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS
+ (IMX_PAD_SION | 0xf1) /* SEMC_DQS */
+ >;
+ };
+
+ pinctrl_usdhc0: usdhc0grp {
+ fsl,pins = <
+ MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B
+ 0x1B000
+ MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT
+ 0xB069
+ MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD
+ 0x17061
+ MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK
+ 0x17061
+ MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3
+ 0x17061
+ MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2
+ 0x17061
+ MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1
+ 0x17061
+ MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0
+ 0x17061
+ >;
+ };
+ };
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc0>;
+ pinctrl-1 = <&pinctrl_usdhc0>;
+ pinctrl-2 = <&pinctrl_usdhc0>;
+ pinctrl-3 = <&pinctrl_usdhc0>;
+ status = "okay";
+
+ cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm/mach-imx/imxrt/Kconfig b/arch/arm/mach-imx/imxrt/Kconfig
index 96ad2e988b..e3aff11d48 100644
--- a/arch/arm/mach-imx/imxrt/Kconfig
+++ b/arch/arm/mach-imx/imxrt/Kconfig
@@ -10,4 +10,16 @@ config IMXRT1050
config SYS_SOC
default "imxrt"
+choice
+ prompt "NXP i.MXRT board select"
+ optional
+
+config TARGET_IMXRT1050_EVK
+ bool "Support imxrt1050 EVK board"
+ select IMXRT1050
+
+endchoice
+
+source "board/freescale/imxrt1050-evk/Kconfig"
+
endif
diff --git a/board/freescale/imxrt1050-evk/Kconfig b/board/freescale/imxrt1050-evk/Kconfig
new file mode 100644
index 0000000000..79e6e4524a
--- /dev/null
+++ b/board/freescale/imxrt1050-evk/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_IMXRT1050_EVK
+
+config SYS_BOARD
+ string
+ default "imxrt1050-evk"
+
+config SYS_VENDOR
+ string
+ default "freescale"
+
+config SYS_SOC
+ string
+ default "imxrt1050"
+
+config SYS_CONFIG_NAME
+ string
+ default "imxrt1050-evk"
+
+config IMX_CONFIG
+ default "board/freescale/imxrt1050-evk/imximage.cfg"
+
+endif
diff --git a/board/freescale/imxrt1050-evk/MAINTAINERS b/board/freescale/imxrt1050-evk/MAINTAINERS
new file mode 100644
index 0000000000..a872855452
--- /dev/null
+++ b/board/freescale/imxrt1050-evk/MAINTAINERS
@@ -0,0 +1,6 @@
+IMXRT1050 EVALUATION KIT
+M: Giulio Benetti <giulio.benetti@benettiengineering.com>
+S: Maintained
+F: board/freescale/imxrt1050-evk
+F: include/configs/imxrt1050-evk.h
+F: configs/imxrt1050-evk_defconfig
diff --git a/board/freescale/imxrt1050-evk/Makefile b/board/freescale/imxrt1050-evk/Makefile
new file mode 100644
index 0000000000..0e984d1d7a
--- /dev/null
+++ b/board/freescale/imxrt1050-evk/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019
+# Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+
+obj-y := imxrt1050-evk.o
diff --git a/board/freescale/imxrt1050-evk/README b/board/freescale/imxrt1050-evk/README
new file mode 100644
index 0000000000..f7e2894025
--- /dev/null
+++ b/board/freescale/imxrt1050-evk/README
@@ -0,0 +1,31 @@
+How to use U-Boot on NXP i.MXRT1050 EVK
+-----------------------------------------------
+
+- Build U-Boot for i.MXRT1050 EVK:
+
+$ make mrproper
+$ make imxrt1050-evk_defconfig
+$ make
+
+This will generate the SPL image called SPL and the u-boot.img.
+
+- Flash the SPL image into the micro SD card:
+
+sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+
+- Flash the u-boot.img image into the micro SD card:
+
+sudo dd if=u-boot.img of=/dev/sdb bs=1k seek=128; sync
+
+- Jumper settings:
+
+SW7: 1 0 1 0
+
+where 0 means bottom position and 1 means top position (from the
+switch label numbers reference).
+
+- Connect the USB cable between the EVK and the PC for the console.
+(The USB console connector is the one close the ethernet connector)
+
+- Insert the micro SD card in the board, power it up and U-Boot messages should
+come up.
diff --git a/board/freescale/imxrt1050-evk/imximage.cfg b/board/freescale/imxrt1050-evk/imximage.cfg
new file mode 100644
index 0000000000..cf1665be61
--- /dev/null
+++ b/board/freescale/imxrt1050-evk/imximage.cfg
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* Set all FlexRAM as OCRAM(01b) */
+DATA 4 0x400AC044 0x55555555
+/* Use FLEXRAM_BANK_CFG to config FlexRAM */
+SET_BIT 4 0x400AC040 0x4
diff --git a/board/freescale/imxrt1050-evk/imxrt1050-evk.c b/board/freescale/imxrt1050-evk/imxrt1050-evk.c
new file mode 100644
index 0000000000..bda03b5ea5
--- /dev/null
+++ b/board/freescale/imxrt1050-evk/imxrt1050-evk.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ram.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/armv7m.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+#ifndef CONFIG_SUPPORT_SPL
+ int rv;
+ struct udevice *dev;
+
+ rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (rv) {
+ debug("DRAM init failed: %d\n", rv);
+ return rv;
+ }
+
+#endif
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ debug("SPL: booting kernel\n");
+ /* break into full u-boot on 'c' */
+ return serial_tstc() && serial_getc() == 'c';
+}
+#endif
+
+int spl_dram_init(void)
+{
+ struct udevice *dev;
+ int rv;
+
+ rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (rv)
+ debug("DRAM init failed: %d\n", rv);
+ return rv;
+}
+
+void spl_board_init(void)
+{
+ spl_dram_init();
+ preloader_console_init();
+ arch_cpu_init(); /* to configure mpu for sdram rw permissions */
+}
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_MMC1;
+}
+#endif
+
+u32 get_board_rev(void)
+{
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+
+ return 0;
+}
diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig
new file mode 100644
index 0000000000..102e663886
--- /dev/null
+++ b/configs/imxrt1050-evk_defconfig
@@ -0,0 +1,69 @@
+CONFIG_ARM=y
+CONFIG_SYS_ICACHE_OFF=y
+CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_IMXRT=y
+CONFIG_SYS_TEXT_BASE=0x80002000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_ENV_OFFSET=0x80000
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_IMXRT1050_EVK=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL_SIZE_LIMIT=131072
+CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x20209000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SD_BOOT=y
+# CONFIG_USE_BOOTCOMMAND is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
+# CONFIG_SPL_CRC32_SUPPORT is not set
+# CONFIG_SPL_DM_GPIO is not set
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_MII is not set
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imxrt1050-evk"
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_TFTP_BLOCKSIZE=512
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+# CONFIG_OF_TRANSLATE is not set
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMXRT1050=y
+CONFIG_CLK_IMXRT1050=y
+CONFIG_MXC_GPIO=y
+# CONFIG_INPUT is not set
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMXRT=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_IMXRT_SDRAM=y
+CONFIG_FSL_LPUART=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_SHA1=y
+CONFIG_SHA256=y
+CONFIG_HEXDUMP=y
diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h
new file mode 100644
index 0000000000..cdec657fb0
--- /dev/null
+++ b/include/configs/imxrt1050-evk.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef __IMXRT1050_EVK_H
+#define __IMXRT1050_EVK_H
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_SYS_INIT_SP_ADDR 0x20280000
+
+#ifdef CONFIG_SUPPORT_SPL
+#define CONFIG_SYS_LOAD_ADDR 0x20209000
+#else
+#define CONFIG_SYS_LOAD_ADDR 0x80000000
+#define CONFIG_LOADADDR 0x80000000
+#endif
+
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 1
+#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1
+
+#define PHYS_SDRAM 0x80000000
+#define PHYS_SDRAM_SIZE (32 * 1024 * 1024)
+
+#define DMAMEM_SZ_ALL (1 * 1024 * 1024)
+#define DMAMEM_BASE (PHYS_SDRAM + PHYS_SDRAM_SIZE - \
+ DMAMEM_SZ_ALL)
+
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
+
+/*
+ * Configuration of the external SDRAM memory
+ */
+#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
+
+/* For SPL */
+#ifdef CONFIG_SUPPORT_SPL
+#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_SPL_LEN 0x00008000
+#define CONFIG_SYS_UBOOT_START 0x800023FD
+#endif
+/* For SPL ends */
+
+#endif /* __IMXRT1050_EVK_H */
--
2.20.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 21/21] imx: imxrt1050-evk: Add support for the NXP i.MXRT1050-EVK
2020-01-10 14:51 ` [PATCH v2 21/21] imx: imxrt1050-evk: Add support for the NXP i.MXRT1050-EVK Giulio Benetti
@ 2020-01-15 12:48 ` sbabic at denx.de
2020-01-28 9:02 ` Lukasz Majewski
1 sibling, 0 replies; 19+ messages in thread
From: sbabic at denx.de @ 2020-01-15 12:48 UTC (permalink / raw)
To: u-boot
> This commit adds board support for i.MXRT1050-EVK from NXP. This board
> is an evaluation kit provided by NXP for i.MXRT105x processor family.
> More information about this board can be found here:
> https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/i.mx-rt1050-evaluation-kit:MIMXRT1050-EVK
> The initial supported/tested devices include:
> - Debug serial
> - SD
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 21/21] imx: imxrt1050-evk: Add support for the NXP i.MXRT1050-EVK
2020-01-10 14:51 ` [PATCH v2 21/21] imx: imxrt1050-evk: Add support for the NXP i.MXRT1050-EVK Giulio Benetti
2020-01-15 12:48 ` sbabic at denx.de
@ 2020-01-28 9:02 ` Lukasz Majewski
2020-01-28 18:54 ` Giulio Benetti
1 sibling, 1 reply; 19+ messages in thread
From: Lukasz Majewski @ 2020-01-28 9:02 UTC (permalink / raw)
To: u-boot
Hi Giulio,
> This commit adds board support for i.MXRT1050-EVK from NXP. This board
> is an evaluation kit provided by NXP for i.MXRT105x processor family.
>
> More information about this board can be found here:
> https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/i.mx-rt1050-evaluation-kit:MIMXRT1050-EVK
>
> The initial supported/tested devices include:
> - Debug serial
> - SD
>
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> ---
> V1->V2:
> * introduced CONFIG_IMXRT1050
> * added imxrt1050-evk-u-boot.dtsi for imxrt1050-evk.dts
> ---
> arch/arm/dts/Makefile | 2 +
> arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 44 ++++
> arch/arm/dts/imxrt1050-evk.dts | 200
> ++++++++++++++++++ arch/arm/mach-imx/imxrt/Kconfig |
> 12 ++ board/freescale/imxrt1050-evk/Kconfig | 22 ++
> board/freescale/imxrt1050-evk/MAINTAINERS | 6 +
> board/freescale/imxrt1050-evk/Makefile | 6 +
> board/freescale/imxrt1050-evk/README | 31 +++
> board/freescale/imxrt1050-evk/imximage.cfg | 36 ++++
> board/freescale/imxrt1050-evk/imxrt1050-evk.c | 81 +++++++
> configs/imxrt1050-evk_defconfig | 69 ++++++
> include/configs/imxrt1050-evk.h | 46 ++++
> 12 files changed, 555 insertions(+)
> create mode 100644 arch/arm/dts/imxrt1050-evk-u-boot.dtsi
> create mode 100644 arch/arm/dts/imxrt1050-evk.dts
> create mode 100644 board/freescale/imxrt1050-evk/Kconfig
> create mode 100644 board/freescale/imxrt1050-evk/MAINTAINERS
> create mode 100644 board/freescale/imxrt1050-evk/Makefile
> create mode 100644 board/freescale/imxrt1050-evk/README
> create mode 100644 board/freescale/imxrt1050-evk/imximage.cfg
> create mode 100644 board/freescale/imxrt1050-evk/imxrt1050-evk.c
> create mode 100644 configs/imxrt1050-evk_defconfig
> create mode 100644 include/configs/imxrt1050-evk.h
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 983e235f44..0864460751 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -707,6 +707,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
> imx8mq-evk.dtb \
> imx8mp-evk.dtb
>
> +dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb
> +
> dtb-$(CONFIG_RCAR_GEN2) += \
> r8a7790-lager-u-boot.dtb \
> r8a7790-stout-u-boot.dtb \
> diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
> b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi new file mode 100644
> index 0000000000..fb4f7f6f9d
> --- /dev/null
> +++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
Ach... Ok, so you have already used the U-Boot specific dtsi.
> @@ -0,0 +1,44 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright (C) 2019
> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> + */
> +
> +/ {
> + chosen {
> + u-boot,dm-spl;
> + };
> +};
> +
> +&lpuart1 { /* console */
> + u-boot,dm-spl;
> +};
> +
> +&semc {
> + bank1: bank at 0 {
> + u-boot,dm-spl;
> + };
> +};
> +
> +&iomuxc {
> + u-boot,dm-spl;
> +
> + imxrt1050-evk {
> + u-boot,dm-spl;
> + pinctrl_lpuart1: lpuart1grp {
> + u-boot,dm-spl;
> + };
> +
> + pinctrl_semc: semcgrp {
> + u-boot,dm-spl;
> + };
> +
> + pinctrl_usdhc0: usdhc0grp {
> + u-boot,dm-spl;
> + };
> + };
> +};
> +
> +&usdhc1 {
> + u-boot,dm-spl;
> +};
> diff --git a/arch/arm/dts/imxrt1050-evk.dts
> b/arch/arm/dts/imxrt1050-evk.dts new file mode 100644
> index 0000000000..56b75986e2
> --- /dev/null
> +++ b/arch/arm/dts/imxrt1050-evk.dts
> @@ -0,0 +1,200 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright (C) 2019
> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> + */
> +
> +/dts-v1/;
> +#include "imxrt1050.dtsi"
> +#include "imxrt1050-evk-u-boot.dtsi"
> +#include <dt-bindings/pinctrl/pins-imxrt1050.h>
> +
> +/ {
> + model = "NXP IMXRT1050-evk board";
> + compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
> +
> + chosen {
> + bootargs = "root=/dev/ram";
> + stdout-path = "serial0:115200n8";
> + };
> +
> + memory {
> + reg = <0x80000000 0x2000000>;
> + };
> +};
> +
> +&lpuart1 { /* console */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_lpuart1>;
> + status = "okay";
> +};
> +
> +&semc {
> + /*
> + * Memory configuration from sdram datasheet IS42S16160J-6BLI
> + */
> + fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
> + MUX_CSX0_SDRAM_CS1
> + 0
> + 0
> + 0
> + 0>;
> + fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
> + BL_8
> + COL_9BITS
> + CL_3>;
> + fsl,sdram-timing = /bits/ 8 <0x2
> + 0x2
> + 0x9
> + 0x1
> + 0x5
> + 0x6
> +
> + 0x20
> + 0x09
> + 0x01
> + 0x00
> +
> + 0x04
> + 0x0A
> + 0x21
> + 0x50>;
> +
> + bank1: bank at 0 {
> + fsl,base-address = <0x80000000>;
> + fsl,memory-size = <MEM_SIZE_32M>;
> + };
> +};
> +
> +&iomuxc {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_lpuart1>;
> +
> + imxrt1050-evk {
> + pinctrl_lpuart1: lpuart1grp {
> + fsl,pins = <
> +
> MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD
> + 0xf1
> +
> MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD
> + 0xf1
> + >;
> + };
> +
> + pinctrl_semc: semcgrp {
> + fsl,pins = <
> + MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
> + 0xf1 /* SEMC_D0 */
> + MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
> + 0xf1 /* SEMC_D1 */
> + MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
> + 0xf1 /* SEMC_D2 */
> + MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
> + 0xf1 /* SEMC_D3 */
> + MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
> + 0xf1 /* SEMC_D4 */
> + MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05
> + 0xf1 /* SEMC_D5 */
> + MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06
> + 0xf1 /* SEMC_D6 */
> + MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07
> + 0xf1 /* SEMC_D7 */
> + MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00
> + 0xf1 /* SEMC_DM0 */
> +
> MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
> + 0xf1 /* SEMC_A0 */
> +
> MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01
> + 0xf1 /* SEMC_A1 */
> +
> MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02
> + 0xf1 /* SEMC_A2 */
> +
> MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03
> + 0xf1 /* SEMC_A3 */
> +
> MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04
> + 0xf1 /* SEMC_A4 */
> +
> MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05
> + 0xf1 /* SEMC_A5 */
> +
> MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06
> + 0xf1 /* SEMC_A6 */
> +
> MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07
> + 0xf1 /* SEMC_A7 */
> +
> MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08
> + 0xf1 /* SEMC_A8 */
> +
> MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09
> + 0xf1 /* SEMC_A9 */
> +
> MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11
> + 0xf1 /* SEMC_A11 */
> +
> MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12
> + 0xf1 /* SEMC_A12 */
> + MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0
> + 0xf1 /* SEMC_BA0 */
> + MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1
> + 0xf1 /* SEMC_BA1 */
> +
> MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10
> + 0xf1 /* SEMC_A10 */
> + MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS
> + 0xf1 /* SEMC_CAS */
> + MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS
> + 0xf1 /* SEMC_RAS */
> + MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK
> + 0xf1 /* SEMC_CLK */
> + MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE
> + 0xf1 /* SEMC_CKE */
> + MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE
> + 0xf1 /* SEMC_WE */
> + MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0
> + 0xf1 /* SEMC_CS0 */
> + MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08
> + 0xf1 /* SEMC_D8 */
> + MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09
> + 0xf1 /* SEMC_D9 */
> + MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10
> + 0xf1 /* SEMC_D10 */
> + MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11
> + 0xf1 /* SEMC_D11 */
> + MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12
> + 0xf1 /* SEMC_D12 */
> + MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13
> + 0xf1 /* SEMC_D13 */
> + MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14
> + 0xf1 /* SEMC_D14 */
> + MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15
> + 0xf1 /* SEMC_D15 */
> + MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01
> + 0xf1 /* SEMC_DM1 */
> + MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS
> + (IMX_PAD_SION | 0xf1)
> /* SEMC_DQS */
> + >;
> + };
> +
> + pinctrl_usdhc0: usdhc0grp {
> + fsl,pins = <
> +
> MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B
> + 0x1B000
> +
> MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT
> + 0xB069
> +
> MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD
> + 0x17061
> +
> MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK
> + 0x17061
> +
> MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3
> + 0x17061
> +
> MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2
> + 0x17061
> +
> MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1
> + 0x17061
> +
> MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0
> + 0x17061
> + >;
> + };
> + };
> +};
> +
> +&usdhc1 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz",
> "sleep";
> + pinctrl-0 = <&pinctrl_usdhc0>;
> + pinctrl-1 = <&pinctrl_usdhc0>;
> + pinctrl-2 = <&pinctrl_usdhc0>;
> + pinctrl-3 = <&pinctrl_usdhc0>;
> + status = "okay";
> +
> + cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
> +};
> diff --git a/arch/arm/mach-imx/imxrt/Kconfig
> b/arch/arm/mach-imx/imxrt/Kconfig index 96ad2e988b..e3aff11d48 100644
> --- a/arch/arm/mach-imx/imxrt/Kconfig
> +++ b/arch/arm/mach-imx/imxrt/Kconfig
> @@ -10,4 +10,16 @@ config IMXRT1050
> config SYS_SOC
> default "imxrt"
>
> +choice
> + prompt "NXP i.MXRT board select"
> + optional
> +
> +config TARGET_IMXRT1050_EVK
> + bool "Support imxrt1050 EVK board"
> + select IMXRT1050
> +
> +endchoice
> +
> +source "board/freescale/imxrt1050-evk/Kconfig"
> +
> endif
> diff --git a/board/freescale/imxrt1050-evk/Kconfig
> b/board/freescale/imxrt1050-evk/Kconfig new file mode 100644
> index 0000000000..79e6e4524a
> --- /dev/null
> +++ b/board/freescale/imxrt1050-evk/Kconfig
> @@ -0,0 +1,22 @@
> +if TARGET_IMXRT1050_EVK
> +
> +config SYS_BOARD
> + string
> + default "imxrt1050-evk"
> +
> +config SYS_VENDOR
> + string
> + default "freescale"
> +
> +config SYS_SOC
> + string
> + default "imxrt1050"
> +
> +config SYS_CONFIG_NAME
> + string
> + default "imxrt1050-evk"
> +
> +config IMX_CONFIG
> + default "board/freescale/imxrt1050-evk/imximage.cfg"
> +
> +endif
> diff --git a/board/freescale/imxrt1050-evk/MAINTAINERS
> b/board/freescale/imxrt1050-evk/MAINTAINERS new file mode 100644
> index 0000000000..a872855452
> --- /dev/null
> +++ b/board/freescale/imxrt1050-evk/MAINTAINERS
> @@ -0,0 +1,6 @@
> +IMXRT1050 EVALUATION KIT
> +M: Giulio Benetti <giulio.benetti@benettiengineering.com>
> +S: Maintained
> +F: board/freescale/imxrt1050-evk
> +F: include/configs/imxrt1050-evk.h
> +F: configs/imxrt1050-evk_defconfig
> diff --git a/board/freescale/imxrt1050-evk/Makefile
> b/board/freescale/imxrt1050-evk/Makefile new file mode 100644
> index 0000000000..0e984d1d7a
> --- /dev/null
> +++ b/board/freescale/imxrt1050-evk/Makefile
> @@ -0,0 +1,6 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# Copyright (C) 2019
> +# Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> +
> +obj-y := imxrt1050-evk.o
> diff --git a/board/freescale/imxrt1050-evk/README
> b/board/freescale/imxrt1050-evk/README new file mode 100644
> index 0000000000..f7e2894025
> --- /dev/null
> +++ b/board/freescale/imxrt1050-evk/README
> @@ -0,0 +1,31 @@
> +How to use U-Boot on NXP i.MXRT1050 EVK
> +-----------------------------------------------
> +
> +- Build U-Boot for i.MXRT1050 EVK:
> +
> +$ make mrproper
> +$ make imxrt1050-evk_defconfig
> +$ make
> +
> +This will generate the SPL image called SPL and the u-boot.img.
> +
> +- Flash the SPL image into the micro SD card:
> +
> +sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
> +
> +- Flash the u-boot.img image into the micro SD card:
> +
> +sudo dd if=u-boot.img of=/dev/sdb bs=1k seek=128; sync
> +
> +- Jumper settings:
> +
> +SW7: 1 0 1 0
> +
> +where 0 means bottom position and 1 means top position (from the
> +switch label numbers reference).
> +
> +- Connect the USB cable between the EVK and the PC for the console.
> +(The USB console connector is the one close the ethernet connector)
> +
> +- Insert the micro SD card in the board, power it up and U-Boot
> messages should +come up.
Thanks for detailed readme, appreciated :-)
> diff --git a/board/freescale/imxrt1050-evk/imximage.cfg
> b/board/freescale/imxrt1050-evk/imximage.cfg new file mode 100644
> index 0000000000..cf1665be61
> --- /dev/null
> +++ b/board/freescale/imxrt1050-evk/imximage.cfg
> @@ -0,0 +1,36 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2019
> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> + */
> +
> +#define __ASSEMBLY__
> +#include <config.h>
> +
> +/* image version */
> +
> +IMAGE_VERSION 2
> +
> +/*
> + * Boot Device : one of
> + * spi/sd/nand/onenand, qspi/nor
> + */
> +
> +BOOT_FROM sd
> +
> +/*
> + * Device Configuration Data (DCD)
> + *
> + * Each entry must have the format:
> + * Addr-type Address Value
> + *
> + * where:
> + * Addr-type register length (1,2 or 4 bytes)
> + * Address absolute address of the register
> + * value value to be stored in the register
> + */
> +
> +/* Set all FlexRAM as OCRAM(01b) */
> +DATA 4 0x400AC044 0x55555555
> +/* Use FLEXRAM_BANK_CFG to config FlexRAM */
> +SET_BIT 4 0x400AC040 0x4
> diff --git a/board/freescale/imxrt1050-evk/imxrt1050-evk.c
> b/board/freescale/imxrt1050-evk/imxrt1050-evk.c new file mode 100644
> index 0000000000..bda03b5ea5
> --- /dev/null
> +++ b/board/freescale/imxrt1050-evk/imxrt1050-evk.c
> @@ -0,0 +1,81 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019
If you would prepare next version of this patch - please update the
date.
> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <ram.h>
> +#include <spl.h>
> +#include <asm/io.h>
> +#include <asm/armv7m.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int dram_init(void)
> +{
> +#ifndef CONFIG_SUPPORT_SPL
> + int rv;
> + struct udevice *dev;
> +
> + rv = uclass_get_device(UCLASS_RAM, 0, &dev);
> + if (rv) {
> + debug("DRAM init failed: %d\n", rv);
> + return rv;
> + }
> +
> +#endif
> + return fdtdec_setup_mem_size_base();
> +}
> +
> +int dram_init_banksize(void)
> +{
> + return fdtdec_setup_memory_banksize();
> +}
> +
> +#ifdef CONFIG_SPL_BUILD
> +#ifdef CONFIG_SPL_OS_BOOT
> +int spl_start_uboot(void)
> +{
> + debug("SPL: booting kernel\n");
> + /* break into full u-boot on 'c' */
> + return serial_tstc() && serial_getc() == 'c';
> +}
> +#endif
> +
> +int spl_dram_init(void)
> +{
> + struct udevice *dev;
> + int rv;
> +
> + rv = uclass_get_device(UCLASS_RAM, 0, &dev);
> + if (rv)
> + debug("DRAM init failed: %d\n", rv);
> + return rv;
> +}
> +
> +void spl_board_init(void)
> +{
> + spl_dram_init();
> + preloader_console_init();
> + arch_cpu_init(); /* to configure mpu for sdram rw
> permissions */ +}
> +
> +u32 spl_boot_device(void)
> +{
> + return BOOT_DEVICE_MMC1;
> +}
> +#endif
> +
> +u32 get_board_rev(void)
> +{
> + return 0;
> +}
> +
> +int board_init(void)
> +{
> + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
> +
> + return 0;
> +}
> diff --git a/configs/imxrt1050-evk_defconfig
> b/configs/imxrt1050-evk_defconfig new file mode 100644
> index 0000000000..102e663886
> --- /dev/null
> +++ b/configs/imxrt1050-evk_defconfig
> @@ -0,0 +1,69 @@
> +CONFIG_ARM=y
> +CONFIG_SYS_ICACHE_OFF=y
> +CONFIG_SYS_DCACHE_OFF=y
Isn't there any cache available on this SoC? Or is it handled
differently and requires special CONFIG_ option?
Enabling caches brings significant speed improvement also in U-Boot.
> +CONFIG_ARCH_IMXRT=y
> +CONFIG_SYS_TEXT_BASE=0x80002000
> +CONFIG_SPL_GPIO_SUPPORT=y
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_SYS_MALLOC_F_LEN=0x8000
> +CONFIG_ENV_OFFSET=0x80000
> +CONFIG_DM_GPIO=y
> +CONFIG_TARGET_IMXRT1050_EVK=y
> +CONFIG_SPL_MMC_SUPPORT=y
> +CONFIG_SPL_SERIAL_SUPPORT=y
> +CONFIG_NR_DRAM_BANKS=1
> +CONFIG_SPL_SIZE_LIMIT=131072
> +CONFIG_SPL=y
> +CONFIG_SPL_TEXT_BASE=0x20209000
> +CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_SD_BOOT=y
> +# CONFIG_USE_BOOTCOMMAND is not set
> +# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_SPL_BOARD_INIT=y
> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> +CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
> +# CONFIG_SPL_CRC32_SUPPORT is not set
> +# CONFIG_SPL_DM_GPIO is not set
> +# CONFIG_BOOTM_NETBSD is not set
> +# CONFIG_BOOTM_PLAN9 is not set
> +# CONFIG_BOOTM_RTEMS is not set
> +# CONFIG_BOOTM_VXWORKS is not set
> +# CONFIG_CMD_MII is not set
> +# CONFIG_DOS_PARTITION is not set
> +# CONFIG_ISO_PARTITION is not set
> +# CONFIG_EFI_PARTITION is not set
> +CONFIG_OF_CONTROL=y
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_DEFAULT_DEVICE_TREE="imxrt1050-evk"
> +CONFIG_ENV_IS_NOWHERE=y
> +CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
> +CONFIG_TFTP_BLOCKSIZE=512
> +CONFIG_SPL_DM=y
> +CONFIG_SPL_DM_SEQ_ALIAS=y
> +# CONFIG_OF_TRANSLATE is not set
> +CONFIG_SPL_CLK_COMPOSITE_CCF=y
> +CONFIG_CLK_COMPOSITE_CCF=y
> +CONFIG_SPL_CLK_IMXRT1050=y
> +CONFIG_CLK_IMXRT1050=y
> +CONFIG_MXC_GPIO=y
> +# CONFIG_INPUT is not set
> +CONFIG_DM_MMC=y
> +CONFIG_FSL_USDHC=y
> +CONFIG_DM_ETH=y
> +CONFIG_PINCTRL=y
> +CONFIG_SPL_PINCTRL=y
> +CONFIG_PINCTRL_IMXRT=y
> +CONFIG_RAM=y
> +CONFIG_SPL_RAM=y
> +CONFIG_IMXRT_SDRAM=y
> +CONFIG_FSL_LPUART=y
> +CONFIG_TIMER=y
> +CONFIG_SPL_TIMER=y
> +CONFIG_SHA1=y
> +CONFIG_SHA256=y
> +CONFIG_HEXDUMP=y
> diff --git a/include/configs/imxrt1050-evk.h
> b/include/configs/imxrt1050-evk.h new file mode 100644
> index 0000000000..cdec657fb0
> --- /dev/null
> +++ b/include/configs/imxrt1050-evk.h
> @@ -0,0 +1,46 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2019
> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> + */
> +
> +#ifndef __IMXRT1050_EVK_H
> +#define __IMXRT1050_EVK_H
> +
> +#include <asm/arch/imx-regs.h>
> +
> +#define CONFIG_SYS_INIT_SP_ADDR 0x20280000
> +
> +#ifdef CONFIG_SUPPORT_SPL
> +#define CONFIG_SYS_LOAD_ADDR 0x20209000
> +#else
> +#define CONFIG_SYS_LOAD_ADDR 0x80000000
> +#define CONFIG_LOADADDR 0x80000000
> +#endif
> +
> +#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 1
> +#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1
> +
> +#define PHYS_SDRAM 0x80000000
> +#define PHYS_SDRAM_SIZE (32 * 1024 * 1024)
> +
> +#define DMAMEM_SZ_ALL (1 * 1024 * 1024)
> +#define DMAMEM_BASE (PHYS_SDRAM +
> PHYS_SDRAM_SIZE - \
> + DMAMEM_SZ_ALL)
> +
> +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
> +
> +/*
> + * Configuration of the external SDRAM memory
> + */
> +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
> +
> +/* For SPL */
> +#ifdef CONFIG_SUPPORT_SPL
> +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
> +#define CONFIG_SYS_SPL_LEN 0x00008000
> +#define CONFIG_SYS_UBOOT_START 0x800023FD
> +#endif
> +/* For SPL ends */
> +
> +#endif /* __IMXRT1050_EVK_H */
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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^ permalink raw reply [flat|nested] 19+ messages in thread* [PATCH v2 21/21] imx: imxrt1050-evk: Add support for the NXP i.MXRT1050-EVK
2020-01-28 9:02 ` Lukasz Majewski
@ 2020-01-28 18:54 ` Giulio Benetti
0 siblings, 0 replies; 19+ messages in thread
From: Giulio Benetti @ 2020-01-28 18:54 UTC (permalink / raw)
To: u-boot
On 1/28/20 10:02 AM, Lukasz Majewski wrote:
> Hi Giulio,
>
>> This commit adds board support for i.MXRT1050-EVK from NXP. This board
>> is an evaluation kit provided by NXP for i.MXRT105x processor family.
>>
>> More information about this board can be found here:
>> https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/i.mx-rt1050-evaluation-kit:MIMXRT1050-EVK
>>
>> The initial supported/tested devices include:
>> - Debug serial
>> - SD
>>
>> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
>> ---
>> V1->V2:
>> * introduced CONFIG_IMXRT1050
>> * added imxrt1050-evk-u-boot.dtsi for imxrt1050-evk.dts
>> ---
>> arch/arm/dts/Makefile | 2 +
>> arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 44 ++++
>> arch/arm/dts/imxrt1050-evk.dts | 200
>> ++++++++++++++++++ arch/arm/mach-imx/imxrt/Kconfig |
>> 12 ++ board/freescale/imxrt1050-evk/Kconfig | 22 ++
>> board/freescale/imxrt1050-evk/MAINTAINERS | 6 +
>> board/freescale/imxrt1050-evk/Makefile | 6 +
>> board/freescale/imxrt1050-evk/README | 31 +++
>> board/freescale/imxrt1050-evk/imximage.cfg | 36 ++++
>> board/freescale/imxrt1050-evk/imxrt1050-evk.c | 81 +++++++
>> configs/imxrt1050-evk_defconfig | 69 ++++++
>> include/configs/imxrt1050-evk.h | 46 ++++
>> 12 files changed, 555 insertions(+)
>> create mode 100644 arch/arm/dts/imxrt1050-evk-u-boot.dtsi
>> create mode 100644 arch/arm/dts/imxrt1050-evk.dts
>> create mode 100644 board/freescale/imxrt1050-evk/Kconfig
>> create mode 100644 board/freescale/imxrt1050-evk/MAINTAINERS
>> create mode 100644 board/freescale/imxrt1050-evk/Makefile
>> create mode 100644 board/freescale/imxrt1050-evk/README
>> create mode 100644 board/freescale/imxrt1050-evk/imximage.cfg
>> create mode 100644 board/freescale/imxrt1050-evk/imxrt1050-evk.c
>> create mode 100644 configs/imxrt1050-evk_defconfig
>> create mode 100644 include/configs/imxrt1050-evk.h
>>
>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>> index 983e235f44..0864460751 100644
>> --- a/arch/arm/dts/Makefile
>> +++ b/arch/arm/dts/Makefile
>> @@ -707,6 +707,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
>> imx8mq-evk.dtb \
>> imx8mp-evk.dtb
>>
>> +dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb
>> +
>> dtb-$(CONFIG_RCAR_GEN2) += \
>> r8a7790-lager-u-boot.dtb \
>> r8a7790-stout-u-boot.dtb \
>> diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
>> b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi new file mode 100644
>> index 0000000000..fb4f7f6f9d
>> --- /dev/null
>> +++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
>
> Ach... Ok, so you have already used the U-Boot specific dtsi.
Yep, did it just before sending :-)
Best regards
--
Giulio Benetti
Benetti Engineering sas
>> @@ -0,0 +1,44 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
>> +/*
>> + * Copyright (C) 2019
>> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
>> + */
>> +
>> +/ {
>> + chosen {
>> + u-boot,dm-spl;
>> + };
>> +};
>> +
>> +&lpuart1 { /* console */
>> + u-boot,dm-spl;
>> +};
>> +
>> +&semc {
>> + bank1: bank at 0 {
>> + u-boot,dm-spl;
>> + };
>> +};
>> +
>> +&iomuxc {
>> + u-boot,dm-spl;
>> +
>> + imxrt1050-evk {
>> + u-boot,dm-spl;
>> + pinctrl_lpuart1: lpuart1grp {
>> + u-boot,dm-spl;
>> + };
>> +
>> + pinctrl_semc: semcgrp {
>> + u-boot,dm-spl;
>> + };
>> +
>> + pinctrl_usdhc0: usdhc0grp {
>> + u-boot,dm-spl;
>> + };
>> + };
>> +};
>> +
>> +&usdhc1 {
>> + u-boot,dm-spl;
>> +};
>> diff --git a/arch/arm/dts/imxrt1050-evk.dts
>> b/arch/arm/dts/imxrt1050-evk.dts new file mode 100644
>> index 0000000000..56b75986e2
>> --- /dev/null
>> +++ b/arch/arm/dts/imxrt1050-evk.dts
>> @@ -0,0 +1,200 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
>> +/*
>> + * Copyright (C) 2019
>> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
>> + */
>> +
>> +/dts-v1/;
>> +#include "imxrt1050.dtsi"
>> +#include "imxrt1050-evk-u-boot.dtsi"
>> +#include <dt-bindings/pinctrl/pins-imxrt1050.h>
>> +
>> +/ {
>> + model = "NXP IMXRT1050-evk board";
>> + compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
>> +
>> + chosen {
>> + bootargs = "root=/dev/ram";
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + memory {
>> + reg = <0x80000000 0x2000000>;
>> + };
>> +};
>> +
>> +&lpuart1 { /* console */
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_lpuart1>;
>> + status = "okay";
>> +};
>> +
>> +&semc {
>> + /*
>> + * Memory configuration from sdram datasheet IS42S16160J-6BLI
>> + */
>> + fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
>> + MUX_CSX0_SDRAM_CS1
>> + 0
>> + 0
>> + 0
>> + 0>;
>> + fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
>> + BL_8
>> + COL_9BITS
>> + CL_3>;
>> + fsl,sdram-timing = /bits/ 8 <0x2
>> + 0x2
>> + 0x9
>> + 0x1
>> + 0x5
>> + 0x6
>> +
>> + 0x20
>> + 0x09
>> + 0x01
>> + 0x00
>> +
>> + 0x04
>> + 0x0A
>> + 0x21
>> + 0x50>;
>> +
>> + bank1: bank at 0 {
>> + fsl,base-address = <0x80000000>;
>> + fsl,memory-size = <MEM_SIZE_32M>;
>> + };
>> +};
>> +
>> +&iomuxc {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_lpuart1>;
>> +
>> + imxrt1050-evk {
>> + pinctrl_lpuart1: lpuart1grp {
>> + fsl,pins = <
>> +
>> MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD
>> + 0xf1
>> +
>> MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD
>> + 0xf1
>> + >;
>> + };
>> +
>> + pinctrl_semc: semcgrp {
>> + fsl,pins = <
>> + MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
>> + 0xf1 /* SEMC_D0 */
>> + MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
>> + 0xf1 /* SEMC_D1 */
>> + MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
>> + 0xf1 /* SEMC_D2 */
>> + MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
>> + 0xf1 /* SEMC_D3 */
>> + MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
>> + 0xf1 /* SEMC_D4 */
>> + MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05
>> + 0xf1 /* SEMC_D5 */
>> + MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06
>> + 0xf1 /* SEMC_D6 */
>> + MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07
>> + 0xf1 /* SEMC_D7 */
>> + MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00
>> + 0xf1 /* SEMC_DM0 */
>> +
>> MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
>> + 0xf1 /* SEMC_A0 */
>> +
>> MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01
>> + 0xf1 /* SEMC_A1 */
>> +
>> MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02
>> + 0xf1 /* SEMC_A2 */
>> +
>> MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03
>> + 0xf1 /* SEMC_A3 */
>> +
>> MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04
>> + 0xf1 /* SEMC_A4 */
>> +
>> MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05
>> + 0xf1 /* SEMC_A5 */
>> +
>> MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06
>> + 0xf1 /* SEMC_A6 */
>> +
>> MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07
>> + 0xf1 /* SEMC_A7 */
>> +
>> MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08
>> + 0xf1 /* SEMC_A8 */
>> +
>> MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09
>> + 0xf1 /* SEMC_A9 */
>> +
>> MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11
>> + 0xf1 /* SEMC_A11 */
>> +
>> MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12
>> + 0xf1 /* SEMC_A12 */
>> + MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0
>> + 0xf1 /* SEMC_BA0 */
>> + MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1
>> + 0xf1 /* SEMC_BA1 */
>> +
>> MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10
>> + 0xf1 /* SEMC_A10 */
>> + MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS
>> + 0xf1 /* SEMC_CAS */
>> + MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS
>> + 0xf1 /* SEMC_RAS */
>> + MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK
>> + 0xf1 /* SEMC_CLK */
>> + MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE
>> + 0xf1 /* SEMC_CKE */
>> + MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE
>> + 0xf1 /* SEMC_WE */
>> + MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0
>> + 0xf1 /* SEMC_CS0 */
>> + MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08
>> + 0xf1 /* SEMC_D8 */
>> + MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09
>> + 0xf1 /* SEMC_D9 */
>> + MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10
>> + 0xf1 /* SEMC_D10 */
>> + MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11
>> + 0xf1 /* SEMC_D11 */
>> + MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12
>> + 0xf1 /* SEMC_D12 */
>> + MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13
>> + 0xf1 /* SEMC_D13 */
>> + MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14
>> + 0xf1 /* SEMC_D14 */
>> + MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15
>> + 0xf1 /* SEMC_D15 */
>> + MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01
>> + 0xf1 /* SEMC_DM1 */
>> + MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS
>> + (IMX_PAD_SION | 0xf1)
>> /* SEMC_DQS */
>> + >;
>> + };
>> +
>> + pinctrl_usdhc0: usdhc0grp {
>> + fsl,pins = <
>> +
>> MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B
>> + 0x1B000
>> +
>> MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT
>> + 0xB069
>> +
>> MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD
>> + 0x17061
>> +
>> MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK
>> + 0x17061
>> +
>> MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3
>> + 0x17061
>> +
>> MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2
>> + 0x17061
>> +
>> MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1
>> + 0x17061
>> +
>> MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0
>> + 0x17061
>> + >;
>> + };
>> + };
>> +};
>> +
>> +&usdhc1 {
>> + pinctrl-names = "default", "state_100mhz", "state_200mhz",
>> "sleep";
>> + pinctrl-0 = <&pinctrl_usdhc0>;
>> + pinctrl-1 = <&pinctrl_usdhc0>;
>> + pinctrl-2 = <&pinctrl_usdhc0>;
>> + pinctrl-3 = <&pinctrl_usdhc0>;
>> + status = "okay";
>> +
>> + cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
>> +};
>> diff --git a/arch/arm/mach-imx/imxrt/Kconfig
>> b/arch/arm/mach-imx/imxrt/Kconfig index 96ad2e988b..e3aff11d48 100644
>> --- a/arch/arm/mach-imx/imxrt/Kconfig
>> +++ b/arch/arm/mach-imx/imxrt/Kconfig
>> @@ -10,4 +10,16 @@ config IMXRT1050
>> config SYS_SOC
>> default "imxrt"
>>
>> +choice
>> + prompt "NXP i.MXRT board select"
>> + optional
>> +
>> +config TARGET_IMXRT1050_EVK
>> + bool "Support imxrt1050 EVK board"
>> + select IMXRT1050
>> +
>> +endchoice
>> +
>> +source "board/freescale/imxrt1050-evk/Kconfig"
>> +
>> endif
>> diff --git a/board/freescale/imxrt1050-evk/Kconfig
>> b/board/freescale/imxrt1050-evk/Kconfig new file mode 100644
>> index 0000000000..79e6e4524a
>> --- /dev/null
>> +++ b/board/freescale/imxrt1050-evk/Kconfig
>> @@ -0,0 +1,22 @@
>> +if TARGET_IMXRT1050_EVK
>> +
>> +config SYS_BOARD
>> + string
>> + default "imxrt1050-evk"
>> +
>> +config SYS_VENDOR
>> + string
>> + default "freescale"
>> +
>> +config SYS_SOC
>> + string
>> + default "imxrt1050"
>> +
>> +config SYS_CONFIG_NAME
>> + string
>> + default "imxrt1050-evk"
>> +
>> +config IMX_CONFIG
>> + default "board/freescale/imxrt1050-evk/imximage.cfg"
>> +
>> +endif
>> diff --git a/board/freescale/imxrt1050-evk/MAINTAINERS
>> b/board/freescale/imxrt1050-evk/MAINTAINERS new file mode 100644
>> index 0000000000..a872855452
>> --- /dev/null
>> +++ b/board/freescale/imxrt1050-evk/MAINTAINERS
>> @@ -0,0 +1,6 @@
>> +IMXRT1050 EVALUATION KIT
>> +M: Giulio Benetti <giulio.benetti@benettiengineering.com>
>> +S: Maintained
>> +F: board/freescale/imxrt1050-evk
>> +F: include/configs/imxrt1050-evk.h
>> +F: configs/imxrt1050-evk_defconfig
>> diff --git a/board/freescale/imxrt1050-evk/Makefile
>> b/board/freescale/imxrt1050-evk/Makefile new file mode 100644
>> index 0000000000..0e984d1d7a
>> --- /dev/null
>> +++ b/board/freescale/imxrt1050-evk/Makefile
>> @@ -0,0 +1,6 @@
>> +# SPDX-License-Identifier: GPL-2.0+
>> +#
>> +# Copyright (C) 2019
>> +# Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
>> +
>> +obj-y := imxrt1050-evk.o
>> diff --git a/board/freescale/imxrt1050-evk/README
>> b/board/freescale/imxrt1050-evk/README new file mode 100644
>> index 0000000000..f7e2894025
>> --- /dev/null
>> +++ b/board/freescale/imxrt1050-evk/README
>> @@ -0,0 +1,31 @@
>> +How to use U-Boot on NXP i.MXRT1050 EVK
>> +-----------------------------------------------
>> +
>> +- Build U-Boot for i.MXRT1050 EVK:
>> +
>> +$ make mrproper
>> +$ make imxrt1050-evk_defconfig
>> +$ make
>> +
>> +This will generate the SPL image called SPL and the u-boot.img.
>> +
>> +- Flash the SPL image into the micro SD card:
>> +
>> +sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
>> +
>> +- Flash the u-boot.img image into the micro SD card:
>> +
>> +sudo dd if=u-boot.img of=/dev/sdb bs=1k seek=128; sync
>> +
>> +- Jumper settings:
>> +
>> +SW7: 1 0 1 0
>> +
>> +where 0 means bottom position and 1 means top position (from the
>> +switch label numbers reference).
>> +
>> +- Connect the USB cable between the EVK and the PC for the console.
>> +(The USB console connector is the one close the ethernet connector)
>> +
>> +- Insert the micro SD card in the board, power it up and U-Boot
>> messages should +come up.
>
>
> Thanks for detailed readme, appreciated :-)
>
>> diff --git a/board/freescale/imxrt1050-evk/imximage.cfg
>> b/board/freescale/imxrt1050-evk/imximage.cfg new file mode 100644
>> index 0000000000..cf1665be61
>> --- /dev/null
>> +++ b/board/freescale/imxrt1050-evk/imximage.cfg
>> @@ -0,0 +1,36 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Copyright (C) 2019
>> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
>> + */
>> +
>> +#define __ASSEMBLY__
>> +#include <config.h>
>> +
>> +/* image version */
>> +
>> +IMAGE_VERSION 2
>> +
>> +/*
>> + * Boot Device : one of
>> + * spi/sd/nand/onenand, qspi/nor
>> + */
>> +
>> +BOOT_FROM sd
>> +
>> +/*
>> + * Device Configuration Data (DCD)
>> + *
>> + * Each entry must have the format:
>> + * Addr-type Address Value
>> + *
>> + * where:
>> + * Addr-type register length (1,2 or 4 bytes)
>> + * Address absolute address of the register
>> + * value value to be stored in the register
>> + */
>> +
>> +/* Set all FlexRAM as OCRAM(01b) */
>> +DATA 4 0x400AC044 0x55555555
>> +/* Use FLEXRAM_BANK_CFG to config FlexRAM */
>> +SET_BIT 4 0x400AC040 0x4
>> diff --git a/board/freescale/imxrt1050-evk/imxrt1050-evk.c
>> b/board/freescale/imxrt1050-evk/imxrt1050-evk.c new file mode 100644
>> index 0000000000..bda03b5ea5
>> --- /dev/null
>> +++ b/board/freescale/imxrt1050-evk/imxrt1050-evk.c
>> @@ -0,0 +1,81 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright (C) 2019
>
> If you would prepare next version of this patch - please update the
> date.
>
>> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
>> + */
>> +
>> +#include <common.h>
>> +#include <dm.h>
>> +#include <ram.h>
>> +#include <spl.h>
>> +#include <asm/io.h>
>> +#include <asm/armv7m.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +int dram_init(void)
>> +{
>> +#ifndef CONFIG_SUPPORT_SPL
>> + int rv;
>> + struct udevice *dev;
>> +
>> + rv = uclass_get_device(UCLASS_RAM, 0, &dev);
>> + if (rv) {
>> + debug("DRAM init failed: %d\n", rv);
>> + return rv;
>> + }
>> +
>> +#endif
>> + return fdtdec_setup_mem_size_base();
>> +}
>> +
>> +int dram_init_banksize(void)
>> +{
>> + return fdtdec_setup_memory_banksize();
>> +}
>> +
>> +#ifdef CONFIG_SPL_BUILD
>> +#ifdef CONFIG_SPL_OS_BOOT
>> +int spl_start_uboot(void)
>> +{
>> + debug("SPL: booting kernel\n");
>> + /* break into full u-boot on 'c' */
>> + return serial_tstc() && serial_getc() == 'c';
>> +}
>> +#endif
>> +
>> +int spl_dram_init(void)
>> +{
>> + struct udevice *dev;
>> + int rv;
>> +
>> + rv = uclass_get_device(UCLASS_RAM, 0, &dev);
>> + if (rv)
>> + debug("DRAM init failed: %d\n", rv);
>> + return rv;
>> +}
>> +
>> +void spl_board_init(void)
>> +{
>> + spl_dram_init();
>> + preloader_console_init();
>> + arch_cpu_init(); /* to configure mpu for sdram rw
>> permissions */ +}
>> +
>> +u32 spl_boot_device(void)
>> +{
>> + return BOOT_DEVICE_MMC1;
>> +}
>> +#endif
>> +
>> +u32 get_board_rev(void)
>> +{
>> + return 0;
>> +}
>> +
>> +int board_init(void)
>> +{
>> + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
>> +
>> + return 0;
>> +}
>> diff --git a/configs/imxrt1050-evk_defconfig
>> b/configs/imxrt1050-evk_defconfig new file mode 100644
>> index 0000000000..102e663886
>> --- /dev/null
>> +++ b/configs/imxrt1050-evk_defconfig
>> @@ -0,0 +1,69 @@
>> +CONFIG_ARM=y
>> +CONFIG_SYS_ICACHE_OFF=y
>> +CONFIG_SYS_DCACHE_OFF=y
>
> Isn't there any cache available on this SoC? Or is it handled
> differently and requires special CONFIG_ option?
>
> Enabling caches brings significant speed improvement also in U-Boot.
>
>> +CONFIG_ARCH_IMXRT=y
>> +CONFIG_SYS_TEXT_BASE=0x80002000
>> +CONFIG_SPL_GPIO_SUPPORT=y
>> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
>> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
>> +CONFIG_SYS_MALLOC_F_LEN=0x8000
>> +CONFIG_ENV_OFFSET=0x80000
>> +CONFIG_DM_GPIO=y
>> +CONFIG_TARGET_IMXRT1050_EVK=y
>> +CONFIG_SPL_MMC_SUPPORT=y
>> +CONFIG_SPL_SERIAL_SUPPORT=y
>> +CONFIG_NR_DRAM_BANKS=1
>> +CONFIG_SPL_SIZE_LIMIT=131072
>> +CONFIG_SPL=y
>> +CONFIG_SPL_TEXT_BASE=0x20209000
>> +CONFIG_DISTRO_DEFAULTS=y
>> +CONFIG_SD_BOOT=y
>> +# CONFIG_USE_BOOTCOMMAND is not set
>> +# CONFIG_DISPLAY_CPUINFO is not set
>> +CONFIG_SPL_BOARD_INIT=y
>> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
>> +CONFIG_SPL_SYS_MALLOC_SIMPLE=y
>> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
>> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
>> +# CONFIG_SPL_CRC32_SUPPORT is not set
>> +# CONFIG_SPL_DM_GPIO is not set
>> +# CONFIG_BOOTM_NETBSD is not set
>> +# CONFIG_BOOTM_PLAN9 is not set
>> +# CONFIG_BOOTM_RTEMS is not set
>> +# CONFIG_BOOTM_VXWORKS is not set
>> +# CONFIG_CMD_MII is not set
>> +# CONFIG_DOS_PARTITION is not set
>> +# CONFIG_ISO_PARTITION is not set
>> +# CONFIG_EFI_PARTITION is not set
>> +CONFIG_OF_CONTROL=y
>> +CONFIG_SPL_OF_CONTROL=y
>> +CONFIG_DEFAULT_DEVICE_TREE="imxrt1050-evk"
>> +CONFIG_ENV_IS_NOWHERE=y
>> +CONFIG_ENV_IS_IN_MMC=y
>> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
>> +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
>> +CONFIG_TFTP_BLOCKSIZE=512
>> +CONFIG_SPL_DM=y
>> +CONFIG_SPL_DM_SEQ_ALIAS=y
>> +# CONFIG_OF_TRANSLATE is not set
>> +CONFIG_SPL_CLK_COMPOSITE_CCF=y
>> +CONFIG_CLK_COMPOSITE_CCF=y
>> +CONFIG_SPL_CLK_IMXRT1050=y
>> +CONFIG_CLK_IMXRT1050=y
>> +CONFIG_MXC_GPIO=y
>> +# CONFIG_INPUT is not set
>> +CONFIG_DM_MMC=y
>> +CONFIG_FSL_USDHC=y
>> +CONFIG_DM_ETH=y
>> +CONFIG_PINCTRL=y
>> +CONFIG_SPL_PINCTRL=y
>> +CONFIG_PINCTRL_IMXRT=y
>> +CONFIG_RAM=y
>> +CONFIG_SPL_RAM=y
>> +CONFIG_IMXRT_SDRAM=y
>> +CONFIG_FSL_LPUART=y
>> +CONFIG_TIMER=y
>> +CONFIG_SPL_TIMER=y
>> +CONFIG_SHA1=y
>> +CONFIG_SHA256=y
>> +CONFIG_HEXDUMP=y
>> diff --git a/include/configs/imxrt1050-evk.h
>> b/include/configs/imxrt1050-evk.h new file mode 100644
>> index 0000000000..cdec657fb0
>> --- /dev/null
>> +++ b/include/configs/imxrt1050-evk.h
>> @@ -0,0 +1,46 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Copyright (C) 2019
>> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
>> + */
>> +
>> +#ifndef __IMXRT1050_EVK_H
>> +#define __IMXRT1050_EVK_H
>> +
>> +#include <asm/arch/imx-regs.h>
>> +
>> +#define CONFIG_SYS_INIT_SP_ADDR 0x20280000
>> +
>> +#ifdef CONFIG_SUPPORT_SPL
>> +#define CONFIG_SYS_LOAD_ADDR 0x20209000
>> +#else
>> +#define CONFIG_SYS_LOAD_ADDR 0x80000000
>> +#define CONFIG_LOADADDR 0x80000000
>> +#endif
>> +
>> +#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 1
>> +#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1
>> +
>> +#define PHYS_SDRAM 0x80000000
>> +#define PHYS_SDRAM_SIZE (32 * 1024 * 1024)
>> +
>> +#define DMAMEM_SZ_ALL (1 * 1024 * 1024)
>> +#define DMAMEM_BASE (PHYS_SDRAM +
>> PHYS_SDRAM_SIZE - \
>> + DMAMEM_SZ_ALL)
>> +
>> +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
>> +
>> +/*
>> + * Configuration of the external SDRAM memory
>> + */
>> +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
>> +
>> +/* For SPL */
>> +#ifdef CONFIG_SUPPORT_SPL
>> +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
>> +#define CONFIG_SYS_SPL_LEN 0x00008000
>> +#define CONFIG_SYS_UBOOT_START 0x800023FD
>> +#endif
>> +/* For SPL ends */
>> +
>> +#endif /* __IMXRT1050_EVK_H */
>
>
>
>
> Best regards,
>
> Lukasz Majewski
>
> --
>
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 16/21] serial_lpuart: add support for i.MXRT
2020-01-10 14:51 [PATCH v2 16/21] serial_lpuart: add support for i.MXRT Giulio Benetti
` (4 preceding siblings ...)
2020-01-10 14:51 ` [PATCH v2 21/21] imx: imxrt1050-evk: Add support for the NXP i.MXRT1050-EVK Giulio Benetti
@ 2020-01-15 12:46 ` sbabic at denx.de
2020-01-28 8:40 ` Lukasz Majewski
6 siblings, 0 replies; 19+ messages in thread
From: sbabic at denx.de @ 2020-01-15 12:46 UTC (permalink / raw)
To: u-boot
> Add i.MXRT compatible string and cpu type support to lpuart driver,
> to use little endian 32 bits configurations.
> Also according to RM, the Receive RX FIFO Enable (RXFE) field in LPUART
> FIFO register is bit 3, so this definition should change to 0x08 as done
> for i.MX8. It needs also to set baudrate the same way as i.MX8 does.
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 19+ messages in thread* [PATCH v2 16/21] serial_lpuart: add support for i.MXRT
2020-01-10 14:51 [PATCH v2 16/21] serial_lpuart: add support for i.MXRT Giulio Benetti
` (5 preceding siblings ...)
2020-01-15 12:46 ` [PATCH v2 16/21] serial_lpuart: add support for i.MXRT sbabic at denx.de
@ 2020-01-28 8:40 ` Lukasz Majewski
6 siblings, 0 replies; 19+ messages in thread
From: Lukasz Majewski @ 2020-01-28 8:40 UTC (permalink / raw)
To: u-boot
On Fri, 10 Jan 2020 15:51:43 +0100
Giulio Benetti <giulio.benetti@benettiengineering.com> wrote:
> Add i.MXRT compatible string and cpu type support to lpuart driver,
> to use little endian 32 bits configurations.
>
> Also according to RM, the Receive RX FIFO Enable (RXFE) field in
> LPUART FIFO register is bit 3, so this definition should change to
> 0x08 as done for i.MX8. It needs also to set baudrate the same way as
> i.MX8 does.
>
> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
> ---
> drivers/serial/serial_lpuart.c | 15 +++++++++++----
> include/fsl_lpuart.h | 3 ++-
> 2 files changed, 13 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/serial/serial_lpuart.c
> b/drivers/serial/serial_lpuart.c index b2ec56172e..ccb3ce6701 100644
> --- a/drivers/serial/serial_lpuart.c
> +++ b/drivers/serial/serial_lpuart.c
> @@ -49,7 +49,7 @@
> #define FIFO_RXSIZE_MASK 0x7
> #define FIFO_RXSIZE_OFF 0
> #define FIFO_TXFE 0x80
> -#ifdef CONFIG_ARCH_IMX8
> +#if defined(CONFIG_ARCH_IMX8) || defined(CONFIG_ARCH_IMXRT)
> #define FIFO_RXFE 0x08
> #else
> #define FIFO_RXFE 0x40
> @@ -67,7 +67,8 @@ enum lpuart_devtype {
> DEV_VF610 = 1,
> DEV_LS1021A,
> DEV_MX7ULP,
> - DEV_IMX8
> + DEV_IMX8,
> + DEV_IMXRT,
> };
>
> struct lpuart_serial_platdata {
> @@ -409,7 +410,8 @@ static int _lpuart32_serial_init(struct udevice
> *dev)
> lpuart_write32(plat->flags, &base->match, 0);
>
> - if (plat->devtype == DEV_MX7ULP || plat->devtype ==
> DEV_IMX8) {
> + if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8
> ||
> + plat->devtype == DEV_IMXRT) {
> _lpuart32_serial_setbrg_7ulp(dev, gd->baudrate);
> } else {
> /* provide data bits, parity, stop bit, etc */
> @@ -426,7 +428,8 @@ static int lpuart_serial_setbrg(struct udevice
> *dev, int baudrate) struct lpuart_serial_platdata *plat =
> dev_get_platdata(dev);
> if (is_lpuart32(dev)) {
> - if (plat->devtype == DEV_MX7ULP || plat->devtype ==
> DEV_IMX8)
> + if (plat->devtype == DEV_MX7ULP || plat->devtype ==
> DEV_IMX8 ||
> + plat->devtype == DEV_IMXRT)
> _lpuart32_serial_setbrg_7ulp(dev, baudrate);
> else
> _lpuart32_serial_setbrg(dev, baudrate);
> @@ -530,6 +533,8 @@ static int
> lpuart_serial_ofdata_to_platdata(struct udevice *dev) plat->devtype =
> DEV_VF610; else if (!fdt_node_check_compatible(blob, node,
> "fsl,imx8qm-lpuart")) plat->devtype = DEV_IMX8;
> + else if (!fdt_node_check_compatible(blob, node,
> "fsl,imxrt-lpuart"))
> + plat->devtype = DEV_IMXRT;
>
> return 0;
> }
> @@ -549,6 +554,8 @@ static const struct udevice_id
> lpuart_serial_ids[] = { { .compatible = "fsl,vf610-lpuart"},
> { .compatible = "fsl,imx8qm-lpuart",
> .data = LPUART_FLAG_REGMAP_32BIT_REG },
> + { .compatible = "fsl,imxrt-lpuart",
> + .data = LPUART_FLAG_REGMAP_32BIT_REG },
> { }
> };
>
> diff --git a/include/fsl_lpuart.h b/include/fsl_lpuart.h
> index fc517d4b7f..511fb84367 100644
> --- a/include/fsl_lpuart.h
> +++ b/include/fsl_lpuart.h
> @@ -4,7 +4,8 @@
> *
> */
>
> -#if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8)
> +#if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8) || \
> + defined(CONFIG_ARCH_IMXRT)
> struct lpuart_fsl_reg32 {
> u32 verid;
> u32 param;
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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