* [PATCH] drm/amdgpu/display: fix logic inversion in program_timing_sync()
@ 2020-01-10 20:11 Alex Deucher
2020-02-03 21:07 ` Alex Deucher
0 siblings, 1 reply; 7+ messages in thread
From: Alex Deucher @ 2020-01-10 20:11 UTC (permalink / raw)
To: amd-gfx, Wenjing.Liu, Bhawanpreet.Lakha; +Cc: Alex Deucher
It looks like we should be reducing the group size when we don't
have a plane rather than when we do.
Bug: https://gitlab.freedesktop.org/drm/amd/issues/781
Fixes: 5fc0cbfad45648 ("drm/amd/display: determine if a pipe is synced by plane state")
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 3d89904003f0..01b27726d9c5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1003,9 +1003,9 @@ static void program_timing_sync(
status->timing_sync_info.master = false;
}
- /* remove any other pipes with plane as they have already been synced */
+ /* remove any other pipes without plane as they have already been synced */
for (j = j + 1; j < group_size; j++) {
- if (pipe_set[j]->plane_state) {
+ if (!pipe_set[j]->plane_state) {
group_size--;
pipe_set[j] = pipe_set[group_size];
j--;
--
2.24.1
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amd-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/amdgpu/display: fix logic inversion in program_timing_sync()
2020-01-10 20:11 [PATCH] drm/amdgpu/display: fix logic inversion in program_timing_sync() Alex Deucher
@ 2020-02-03 21:07 ` Alex Deucher
2020-02-04 14:06 ` Kazlauskas, Nicholas
0 siblings, 1 reply; 7+ messages in thread
From: Alex Deucher @ 2020-02-03 21:07 UTC (permalink / raw)
To: amd-gfx list, Wenjing Liu, Bhawanpreet Lakha, Harry Wentland; +Cc: Alex Deucher
Ping?
On Fri, Jan 10, 2020 at 3:11 PM Alex Deucher <alexdeucher@gmail.com> wrote:
>
> It looks like we should be reducing the group size when we don't
> have a plane rather than when we do.
>
> Bug: https://gitlab.freedesktop.org/drm/amd/issues/781
> Fixes: 5fc0cbfad45648 ("drm/amd/display: determine if a pipe is synced by plane state")
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
> index 3d89904003f0..01b27726d9c5 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
> @@ -1003,9 +1003,9 @@ static void program_timing_sync(
> status->timing_sync_info.master = false;
>
> }
> - /* remove any other pipes with plane as they have already been synced */
> + /* remove any other pipes without plane as they have already been synced */
> for (j = j + 1; j < group_size; j++) {
> - if (pipe_set[j]->plane_state) {
> + if (!pipe_set[j]->plane_state) {
> group_size--;
> pipe_set[j] = pipe_set[group_size];
> j--;
> --
> 2.24.1
>
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/amdgpu/display: fix logic inversion in program_timing_sync()
2020-02-03 21:07 ` Alex Deucher
@ 2020-02-04 14:06 ` Kazlauskas, Nicholas
2020-02-20 13:27 ` Alex Deucher
0 siblings, 1 reply; 7+ messages in thread
From: Kazlauskas, Nicholas @ 2020-02-04 14:06 UTC (permalink / raw)
To: Alex Deucher, amd-gfx list, Wenjing Liu, Bhawanpreet Lakha,
Harry Wentland, Laktyushkin, Dmytro
Cc: Alex Deucher
Comments inline.
On 2020-02-03 4:07 p.m., Alex Deucher wrote:
> Ping?
>
> On Fri, Jan 10, 2020 at 3:11 PM Alex Deucher <alexdeucher@gmail.com> wrote:
>>
>> It looks like we should be reducing the group size when we don't
>> have a plane rather than when we do.
>>
>> Bug: https://gitlab.freedesktop.org/drm/amd/issues/781
>> Fixes: 5fc0cbfad45648 ("drm/amd/display: determine if a pipe is synced by plane state")
>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>> ---
>> drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
>> index 3d89904003f0..01b27726d9c5 100644
>> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
>> @@ -1003,9 +1003,9 @@ static void program_timing_sync(
>> status->timing_sync_info.master = false;
>>
>> }
>> - /* remove any other pipes with plane as they have already been synced */
>> + /* remove any other pipes without plane as they have already been synced */
This took a while to wrap my head around but I think I understand what
this was originally trying to do.
The original logic seems to have been checking for blanked streams and
trying to remove anything that was blanked from the group to try and
avoid having to enable timing synchronization.
However, the logic for blanked is *not* the same as having a
plane_state. Technically you can drive an OTG without anything connected
in the front end and it'll just draw out the back color - which is
distinct from having the OTG be blanked.
The problem is really this iteration below:
>> for (j = j + 1; j < group_size; j++) {
There could still be pipes in here (depending on the ordering) that have
planes and could be synchronized with the master OTG. I think starting
at j + 1 is a mistake for this logic as well.
I wonder if we can just drop this loop altogether. If we add planes or
unblank the OTG later then we'll still want the synchronization.
Dymtro, Wenjing - feel free to correct my understanding if I'm mistaken
about this.
Regards,
Nicholas Kazlauskas
>> - if (pipe_set[j]->plane_state) {
>> + if (!pipe_set[j]->plane_state) {
>> group_size--;
>> pipe_set[j] = pipe_set[group_size];
>> j--;
>> --
>> 2.24.1
>>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/amdgpu/display: fix logic inversion in program_timing_sync()
2020-02-04 14:06 ` Kazlauskas, Nicholas
@ 2020-02-20 13:27 ` Alex Deucher
2020-04-06 14:44 ` Alex Deucher
0 siblings, 1 reply; 7+ messages in thread
From: Alex Deucher @ 2020-02-20 13:27 UTC (permalink / raw)
To: Kazlauskas, Nicholas
Cc: Bhawanpreet Lakha, Wenjing Liu, amd-gfx list, Laktyushkin,
Dmytro, Alex Deucher, Harry Wentland
On Tue, Feb 4, 2020 at 9:06 AM Kazlauskas, Nicholas
<nicholas.kazlauskas@amd.com> wrote:
>
> Comments inline.
>
> On 2020-02-03 4:07 p.m., Alex Deucher wrote:
> > Ping?
> >
> > On Fri, Jan 10, 2020 at 3:11 PM Alex Deucher <alexdeucher@gmail.com> wrote:
> >>
> >> It looks like we should be reducing the group size when we don't
> >> have a plane rather than when we do.
> >>
> >> Bug: https://gitlab.freedesktop.org/drm/amd/issues/781
> >> Fixes: 5fc0cbfad45648 ("drm/amd/display: determine if a pipe is synced by plane state")
> >> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> >> ---
> >> drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++--
> >> 1 file changed, 2 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
> >> index 3d89904003f0..01b27726d9c5 100644
> >> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
> >> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
> >> @@ -1003,9 +1003,9 @@ static void program_timing_sync(
> >> status->timing_sync_info.master = false;
> >>
> >> }
> >> - /* remove any other pipes with plane as they have already been synced */
> >> + /* remove any other pipes without plane as they have already been synced */
>
> This took a while to wrap my head around but I think I understand what
> this was originally trying to do.
>
> The original logic seems to have been checking for blanked streams and
> trying to remove anything that was blanked from the group to try and
> avoid having to enable timing synchronization.
>
> However, the logic for blanked is *not* the same as having a
> plane_state. Technically you can drive an OTG without anything connected
> in the front end and it'll just draw out the back color - which is
> distinct from having the OTG be blanked.
>
> The problem is really this iteration below:
>
> >> for (j = j + 1; j < group_size; j++) {
>
> There could still be pipes in here (depending on the ordering) that have
> planes and could be synchronized with the master OTG. I think starting
> at j + 1 is a mistake for this logic as well.
>
> I wonder if we can just drop this loop altogether. If we add planes or
> unblank the OTG later then we'll still want the synchronization.
>
> Dymtro, Wenjing - feel free to correct my understanding if I'm mistaken
> about this.
Ping? Any thoughts on this? It would be nice to get this fixed.
Alex
>
> Regards,
> Nicholas Kazlauskas
>
> >> - if (pipe_set[j]->plane_state) {
> >> + if (!pipe_set[j]->plane_state) {
> >> group_size--;
> >> pipe_set[j] = pipe_set[group_size];
> >> j--;
> >> --
> >> 2.24.1
> >>
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> >
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/amdgpu/display: fix logic inversion in program_timing_sync()
2020-02-20 13:27 ` Alex Deucher
@ 2020-04-06 14:44 ` Alex Deucher
2020-05-27 20:51 ` Alex Deucher
0 siblings, 1 reply; 7+ messages in thread
From: Alex Deucher @ 2020-04-06 14:44 UTC (permalink / raw)
To: Kazlauskas, Nicholas
Cc: Bhawanpreet Lakha, Wenjing Liu, amd-gfx list, Laktyushkin,
Dmytro, Alex Deucher, Harry Wentland
Ping again?
Alex
On Thu, Feb 20, 2020 at 8:27 AM Alex Deucher <alexdeucher@gmail.com> wrote:
>
> On Tue, Feb 4, 2020 at 9:06 AM Kazlauskas, Nicholas
> <nicholas.kazlauskas@amd.com> wrote:
> >
> > Comments inline.
> >
> > On 2020-02-03 4:07 p.m., Alex Deucher wrote:
> > > Ping?
> > >
> > > On Fri, Jan 10, 2020 at 3:11 PM Alex Deucher <alexdeucher@gmail.com> wrote:
> > >>
> > >> It looks like we should be reducing the group size when we don't
> > >> have a plane rather than when we do.
> > >>
> > >> Bug: https://gitlab.freedesktop.org/drm/amd/issues/781
> > >> Fixes: 5fc0cbfad45648 ("drm/amd/display: determine if a pipe is synced by plane state")
> > >> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > >> ---
> > >> drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++--
> > >> 1 file changed, 2 insertions(+), 2 deletions(-)
> > >>
> > >> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
> > >> index 3d89904003f0..01b27726d9c5 100644
> > >> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
> > >> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
> > >> @@ -1003,9 +1003,9 @@ static void program_timing_sync(
> > >> status->timing_sync_info.master = false;
> > >>
> > >> }
> > >> - /* remove any other pipes with plane as they have already been synced */
> > >> + /* remove any other pipes without plane as they have already been synced */
> >
> > This took a while to wrap my head around but I think I understand what
> > this was originally trying to do.
> >
> > The original logic seems to have been checking for blanked streams and
> > trying to remove anything that was blanked from the group to try and
> > avoid having to enable timing synchronization.
> >
> > However, the logic for blanked is *not* the same as having a
> > plane_state. Technically you can drive an OTG without anything connected
> > in the front end and it'll just draw out the back color - which is
> > distinct from having the OTG be blanked.
> >
> > The problem is really this iteration below:
> >
> > >> for (j = j + 1; j < group_size; j++) {
> >
> > There could still be pipes in here (depending on the ordering) that have
> > planes and could be synchronized with the master OTG. I think starting
> > at j + 1 is a mistake for this logic as well.
> >
> > I wonder if we can just drop this loop altogether. If we add planes or
> > unblank the OTG later then we'll still want the synchronization.
> >
> > Dymtro, Wenjing - feel free to correct my understanding if I'm mistaken
> > about this.
>
> Ping? Any thoughts on this? It would be nice to get this fixed.
>
> Alex
>
>
> >
> > Regards,
> > Nicholas Kazlauskas
> >
> > >> - if (pipe_set[j]->plane_state) {
> > >> + if (!pipe_set[j]->plane_state) {
> > >> group_size--;
> > >> pipe_set[j] = pipe_set[group_size];
> > >> j--;
> > >> --
> > >> 2.24.1
> > >>
> > > _______________________________________________
> > > amd-gfx mailing list
> > > amd-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> > >
> >
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/amdgpu/display: fix logic inversion in program_timing_sync()
2020-04-06 14:44 ` Alex Deucher
@ 2020-05-27 20:51 ` Alex Deucher
2020-05-28 13:14 ` Kazlauskas, Nicholas
0 siblings, 1 reply; 7+ messages in thread
From: Alex Deucher @ 2020-05-27 20:51 UTC (permalink / raw)
To: Kazlauskas, Nicholas
Cc: Bhawanpreet Lakha, Wenjing Liu, amd-gfx list, Laktyushkin,
Dmytro, Alex Deucher, Harry Wentland
Can we apply this for now until we can get further analysis on the
actual root cause?
Alex
On Mon, Apr 6, 2020 at 10:44 AM Alex Deucher <alexdeucher@gmail.com> wrote:
>
> Ping again?
>
> Alex
>
> On Thu, Feb 20, 2020 at 8:27 AM Alex Deucher <alexdeucher@gmail.com> wrote:
> >
> > On Tue, Feb 4, 2020 at 9:06 AM Kazlauskas, Nicholas
> > <nicholas.kazlauskas@amd.com> wrote:
> > >
> > > Comments inline.
> > >
> > > On 2020-02-03 4:07 p.m., Alex Deucher wrote:
> > > > Ping?
> > > >
> > > > On Fri, Jan 10, 2020 at 3:11 PM Alex Deucher <alexdeucher@gmail.com> wrote:
> > > >>
> > > >> It looks like we should be reducing the group size when we don't
> > > >> have a plane rather than when we do.
> > > >>
> > > >> Bug: https://gitlab.freedesktop.org/drm/amd/issues/781
> > > >> Fixes: 5fc0cbfad45648 ("drm/amd/display: determine if a pipe is synced by plane state")
> > > >> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > > >> ---
> > > >> drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++--
> > > >> 1 file changed, 2 insertions(+), 2 deletions(-)
> > > >>
> > > >> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
> > > >> index 3d89904003f0..01b27726d9c5 100644
> > > >> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
> > > >> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
> > > >> @@ -1003,9 +1003,9 @@ static void program_timing_sync(
> > > >> status->timing_sync_info.master = false;
> > > >>
> > > >> }
> > > >> - /* remove any other pipes with plane as they have already been synced */
> > > >> + /* remove any other pipes without plane as they have already been synced */
> > >
> > > This took a while to wrap my head around but I think I understand what
> > > this was originally trying to do.
> > >
> > > The original logic seems to have been checking for blanked streams and
> > > trying to remove anything that was blanked from the group to try and
> > > avoid having to enable timing synchronization.
> > >
> > > However, the logic for blanked is *not* the same as having a
> > > plane_state. Technically you can drive an OTG without anything connected
> > > in the front end and it'll just draw out the back color - which is
> > > distinct from having the OTG be blanked.
> > >
> > > The problem is really this iteration below:
> > >
> > > >> for (j = j + 1; j < group_size; j++) {
> > >
> > > There could still be pipes in here (depending on the ordering) that have
> > > planes and could be synchronized with the master OTG. I think starting
> > > at j + 1 is a mistake for this logic as well.
> > >
> > > I wonder if we can just drop this loop altogether. If we add planes or
> > > unblank the OTG later then we'll still want the synchronization.
> > >
> > > Dymtro, Wenjing - feel free to correct my understanding if I'm mistaken
> > > about this.
> >
> > Ping? Any thoughts on this? It would be nice to get this fixed.
> >
> > Alex
> >
> >
> > >
> > > Regards,
> > > Nicholas Kazlauskas
> > >
> > > >> - if (pipe_set[j]->plane_state) {
> > > >> + if (!pipe_set[j]->plane_state) {
> > > >> group_size--;
> > > >> pipe_set[j] = pipe_set[group_size];
> > > >> j--;
> > > >> --
> > > >> 2.24.1
> > > >>
> > > > _______________________________________________
> > > > amd-gfx mailing list
> > > > amd-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> > > >
> > >
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/amdgpu/display: fix logic inversion in program_timing_sync()
2020-05-27 20:51 ` Alex Deucher
@ 2020-05-28 13:14 ` Kazlauskas, Nicholas
0 siblings, 0 replies; 7+ messages in thread
From: Kazlauskas, Nicholas @ 2020-05-28 13:14 UTC (permalink / raw)
To: Alex Deucher
Cc: Bhawanpreet Lakha, Wenjing Liu, amd-gfx list, Laktyushkin,
Dmytro, Alex Deucher, Harry Wentland
I still think we should just drop the reduction loop.
The problem with checking plane_state at all is that this logic will
always be broken - plane_state isn't a good indicator of whether the
stream is blanked or not since we can leave an OTG running with no
planes at all while unblanked.
Regards,
Nicholas Kazlauskas
On 2020-05-27 4:51 p.m., Alex Deucher wrote:
> Can we apply this for now until we can get further analysis on the
> actual root cause?
>
> Alex
>
> On Mon, Apr 6, 2020 at 10:44 AM Alex Deucher <alexdeucher@gmail.com> wrote:
>>
>> Ping again?
>>
>> Alex
>>
>> On Thu, Feb 20, 2020 at 8:27 AM Alex Deucher <alexdeucher@gmail.com> wrote:
>>>
>>> On Tue, Feb 4, 2020 at 9:06 AM Kazlauskas, Nicholas
>>> <nicholas.kazlauskas@amd.com> wrote:
>>>>
>>>> Comments inline.
>>>>
>>>> On 2020-02-03 4:07 p.m., Alex Deucher wrote:
>>>>> Ping?
>>>>>
>>>>> On Fri, Jan 10, 2020 at 3:11 PM Alex Deucher <alexdeucher@gmail.com> wrote:
>>>>>>
>>>>>> It looks like we should be reducing the group size when we don't
>>>>>> have a plane rather than when we do.
>>>>>>
>>>>>> Bug: https://gitlab.freedesktop.org/drm/amd/issues/781
>>>>>> Fixes: 5fc0cbfad45648 ("drm/amd/display: determine if a pipe is synced by plane state")
>>>>>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>>>>>> ---
>>>>>> drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++--
>>>>>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
>>>>>> index 3d89904003f0..01b27726d9c5 100644
>>>>>> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
>>>>>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
>>>>>> @@ -1003,9 +1003,9 @@ static void program_timing_sync(
>>>>>> status->timing_sync_info.master = false;
>>>>>>
>>>>>> }
>>>>>> - /* remove any other pipes with plane as they have already been synced */
>>>>>> + /* remove any other pipes without plane as they have already been synced */
>>>>
>>>> This took a while to wrap my head around but I think I understand what
>>>> this was originally trying to do.
>>>>
>>>> The original logic seems to have been checking for blanked streams and
>>>> trying to remove anything that was blanked from the group to try and
>>>> avoid having to enable timing synchronization.
>>>>
>>>> However, the logic for blanked is *not* the same as having a
>>>> plane_state. Technically you can drive an OTG without anything connected
>>>> in the front end and it'll just draw out the back color - which is
>>>> distinct from having the OTG be blanked.
>>>>
>>>> The problem is really this iteration below:
>>>>
>>>>>> for (j = j + 1; j < group_size; j++) {
>>>>
>>>> There could still be pipes in here (depending on the ordering) that have
>>>> planes and could be synchronized with the master OTG. I think starting
>>>> at j + 1 is a mistake for this logic as well.
>>>>
>>>> I wonder if we can just drop this loop altogether. If we add planes or
>>>> unblank the OTG later then we'll still want the synchronization.
>>>>
>>>> Dymtro, Wenjing - feel free to correct my understanding if I'm mistaken
>>>> about this.
>>>
>>> Ping? Any thoughts on this? It would be nice to get this fixed.
>>>
>>> Alex
>>>
>>>
>>>>
>>>> Regards,
>>>> Nicholas Kazlauskas
>>>>
>>>>>> - if (pipe_set[j]->plane_state) {
>>>>>> + if (!pipe_set[j]->plane_state) {
>>>>>> group_size--;
>>>>>> pipe_set[j] = pipe_set[group_size];
>>>>>> j--;
>>>>>> --
>>>>>> 2.24.1
>>>>>>
>>>>> _______________________________________________
>>>>> amd-gfx mailing list
>>>>> amd-gfx@lists.freedesktop.org
>>>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>>>>>
>>>>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-05-28 13:15 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
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2020-01-10 20:11 [PATCH] drm/amdgpu/display: fix logic inversion in program_timing_sync() Alex Deucher
2020-02-03 21:07 ` Alex Deucher
2020-02-04 14:06 ` Kazlauskas, Nicholas
2020-02-20 13:27 ` Alex Deucher
2020-04-06 14:44 ` Alex Deucher
2020-05-27 20:51 ` Alex Deucher
2020-05-28 13:14 ` Kazlauskas, Nicholas
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