* [PATCH 00/22] DC Patches 16 Jan 2020
@ 2020-01-16 20:10 Bhawanpreet Lakha
2020-01-16 20:10 ` [PATCH 01/22] drm/amd/display: update MSA and VSC SDP on video test pattern request Bhawanpreet Lakha
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Bhawanpreet Lakha @ 2020-01-16 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: sunpeng.li, rodrigo.siqueira, Bhawanpreet Lakha, harry.wentland
Summary Of Changes
* Code fixes/cleanups
* i2c frequency refactor
* DMCUB changes
* Update type fix
Anthony Koo (1):
drm/amd/display: Refactor to remove diags specific rgam func
Aric Cyr (1):
drm/amd/display: 3.2.69
Brandon Syu (1):
drm/amd/display: fix rotation_angle to use enum values
Haiyi Zhou (1):
drm/amd/display: Fixed comment styling
Isabel Zhang (1):
drm/amd/display: changed max_downscale_src_width to 4096.
Jerry (Fangzhi) Zuo (1):
drm/amd/display: Fix DML dummyinteger types mismatch
Lewis Huang (2):
drm/amd/display: Refine i2c frequency calculating sequence
drm/amd/display: init hw i2c speed
Nicholas Kazlauskas (7):
drm/amd/display: Get fb base and fb offset for DMUB from registers
drm/amd/display: Fallback to DMCUB when command table is missing
drm/amd/display: Do DMCUB hw_init before DC
drm/amd/display: Add hardware reset interface for DMUB service
drm/amd/display: Call ATOM_INIT instead of ATOM_ENABLE for DMCUB
drm/amd/display: Reset inbox rptr/wptr when resetting DMCUB
drm/amd/display: Check hw_init state when determining if DMCUB is
initialized
Paul Hsieh (1):
drm/amd/display: check pipe_ctx is split pipe or not
Roman Li (1):
drm/amd/display: Fix update type for multiple planes
Sung Lee (1):
drm/amd/display: Do not send training pattern if VS Different
Wenjing Liu (4):
drm/amd/display: update MSA and VSC SDP on video test pattern request
drm/amd/display: Add debug option to disable DSC support
drm/amd/display: support VSC SDP update on video test pattern request
drm/amd/display: use odm combine for YCbCr420 timing with h_active
greater than 4096
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 68 ++--
.../drm/amd/display/dc/bios/command_table2.c | 78 ++++-
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 17 +-
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 34 +-
drivers/gpu/drm/amd/display/dc/dc.h | 3 +-
.../gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 73 +----
.../gpu/drm/amd/display/dc/dce/dce_i2c_hw.h | 1 -
.../gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 12 +-
.../drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +-
.../dc/dml/dcn20/display_mode_vba_20.c | 19 +-
.../dc/dml/dcn20/display_mode_vba_20v2.c | 24 +-
.../dc/dml/dcn21/display_mode_vba_21.c | 24 +-
.../drm/amd/display/dc/dml/display_mode_vba.h | 4 +-
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 3 +-
.../gpu/drm/amd/display/dmub/inc/dmub_srv.h | 17 +
.../gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 25 +-
.../gpu/drm/amd/display/dmub/src/dmub_dcn20.h | 8 +-
.../gpu/drm/amd/display/dmub/src/dmub_srv.c | 19 ++
.../amd/display/modules/color/color_gamma.c | 307 ++++++++----------
.../amd/display/modules/color/color_gamma.h | 4 -
.../amd/display/modules/freesync/freesync.c | 2 +-
21 files changed, 426 insertions(+), 318 deletions(-)
--
2.17.1
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 01/22] drm/amd/display: update MSA and VSC SDP on video test pattern request
2020-01-16 20:10 [PATCH 00/22] DC Patches 16 Jan 2020 Bhawanpreet Lakha
@ 2020-01-16 20:10 ` Bhawanpreet Lakha
2020-01-16 20:10 ` [PATCH 02/22] drm/amd/display: Do not send training pattern if VS Different Bhawanpreet Lakha
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Bhawanpreet Lakha @ 2020-01-16 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: sunpeng.li, rodrigo.siqueira, harry.wentland, Wenjing Liu
From: Wenjing Liu <Wenjing.Liu@amd.com>
[why]
On video test pattern request we need to update MSA and VSC so
it will match the requested test pattern dynamic range field.
[how]
Update dynamic range field in MSA and disable VSC as updating VSC
info packet is complicated and not required for test pattern purpose.
Change-Id: Ie49c1d3b1c219aaff88f8185371a252e492e1697
Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
IP-reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 37 ++++++++++++++++++-
1 file changed, 36 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 6ab298c65247..1bd0946829e3 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -3925,8 +3925,43 @@ bool dc_link_dp_set_test_pattern(
sizeof(training_pattern));
}
} else {
- /* CRTC Patterns */
+ enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
+ struct encoder_info_frame info_frame = pipe_ctx->stream_res.encoder_info_frame;
+
+ switch (test_pattern_color_space) {
+ case DP_TEST_PATTERN_COLOR_SPACE_RGB:
+ color_space = COLOR_SPACE_SRGB;
+ if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
+ color_space = COLOR_SPACE_SRGB_LIMITED;
+ break;
+
+ case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
+ color_space = COLOR_SPACE_YCBCR601;
+ if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
+ color_space = COLOR_SPACE_YCBCR601_LIMITED;
+ break;
+ case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
+ color_space = COLOR_SPACE_YCBCR709;
+ if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
+ color_space = COLOR_SPACE_YCBCR709_LIMITED;
+ break;
+ default:
+ break;
+ }
+ /* update MSA to requested color space */
+ pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(pipe_ctx->stream_res.stream_enc,
+ &pipe_ctx->stream->timing,
+ color_space, false, link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
+
+ /* disable vsc so no need to update it based on request */
+ info_frame.vsc.valid = false;
+ pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
+ pipe_ctx->stream_res.stream_enc,
+ &info_frame);
+
+ /* CRTC Patterns */
set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
+
/* Set Test Pattern state */
link->test_pattern_enabled = true;
}
--
2.17.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 02/22] drm/amd/display: Do not send training pattern if VS Different
2020-01-16 20:10 [PATCH 00/22] DC Patches 16 Jan 2020 Bhawanpreet Lakha
2020-01-16 20:10 ` [PATCH 01/22] drm/amd/display: update MSA and VSC SDP on video test pattern request Bhawanpreet Lakha
@ 2020-01-16 20:10 ` Bhawanpreet Lakha
2020-01-16 20:10 ` [PATCH 03/22] drm/amd/display: Add debug option to disable DSC support Bhawanpreet Lakha
2020-01-16 20:10 ` [PATCH 04/22] drm/amd/display: Get fb base and fb offset for DMUB from registers Bhawanpreet Lakha
3 siblings, 0 replies; 6+ messages in thread
From: Bhawanpreet Lakha @ 2020-01-16 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: sunpeng.li, rodrigo.siqueira, Sung Lee, harry.wentland
From: Sung Lee <sung.lee@amd.com>
[Why]
The DP 1.4a Spec requires that training pattern only under certain
specific conditions. Currently driver will re-send
training pattern every time voltage swing value changes,
but that should not be the case.
[How]
Do not re-send training pattern every time VS values
are different. Only send it on the first iteration.
Change-Id: I5d98439de574c73c98edf21fe1741b947a365bf5
Signed-off-by: Sung Lee <sung.lee@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Abdoulaye Berthe <Abdoulaye.Berthe@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
IP-reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 1bd0946829e3..3bb1b481451b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -983,7 +983,7 @@ static enum link_training_result perform_clock_recovery_sequence(
offset);
/* 2. update DPCD of the receiver*/
- if (!retries_cr)
+ if (!retry_count)
/* EPR #361076 - write as a 5-byte burst,
* but only for the 1-st iteration.*/
dpcd_set_lt_pattern_and_lane_settings(
--
2.17.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 03/22] drm/amd/display: Add debug option to disable DSC support
2020-01-16 20:10 [PATCH 00/22] DC Patches 16 Jan 2020 Bhawanpreet Lakha
2020-01-16 20:10 ` [PATCH 01/22] drm/amd/display: update MSA and VSC SDP on video test pattern request Bhawanpreet Lakha
2020-01-16 20:10 ` [PATCH 02/22] drm/amd/display: Do not send training pattern if VS Different Bhawanpreet Lakha
@ 2020-01-16 20:10 ` Bhawanpreet Lakha
2020-01-16 20:10 ` [PATCH 04/22] drm/amd/display: Get fb base and fb offset for DMUB from registers Bhawanpreet Lakha
3 siblings, 0 replies; 6+ messages in thread
From: Bhawanpreet Lakha @ 2020-01-16 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: sunpeng.li, rodrigo.siqueira, harry.wentland, Wenjing Liu
From: Wenjing Liu <Wenjing.Liu@amd.com>
[how]
Empty dsc enc caps when debug option is set to disable DSC.
Change-Id: I95e63c63bb0513a80144087c8327dcdcfa23c494
Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
IP-reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 3fa85a54360f..7d31dcb9e37f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -425,6 +425,7 @@ struct dc_debug_options {
bool validate_dml_output;
bool enable_dmcub_surface_flip;
bool usbc_combo_phy_reset_wa;
+ bool disable_dsc;
};
struct dc_debug_data {
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index 8b78fcbfe746..87d682d25278 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -224,7 +224,8 @@ static void get_dsc_enc_caps(
memset(dsc_enc_caps, 0, sizeof(struct dsc_enc_caps));
if (dsc) {
- dsc->funcs->dsc_get_enc_caps(dsc_enc_caps, pixel_clock_100Hz);
+ if (!dsc->ctx->dc->debug.disable_dsc)
+ dsc->funcs->dsc_get_enc_caps(dsc_enc_caps, pixel_clock_100Hz);
if (dsc->ctx->dc->debug.native422_support)
dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1;
}
--
2.17.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 04/22] drm/amd/display: Get fb base and fb offset for DMUB from registers
2020-01-16 20:10 [PATCH 00/22] DC Patches 16 Jan 2020 Bhawanpreet Lakha
` (2 preceding siblings ...)
2020-01-16 20:10 ` [PATCH 03/22] drm/amd/display: Add debug option to disable DSC support Bhawanpreet Lakha
@ 2020-01-16 20:10 ` Bhawanpreet Lakha
3 siblings, 0 replies; 6+ messages in thread
From: Bhawanpreet Lakha @ 2020-01-16 20:10 UTC (permalink / raw)
To: amd-gfx; +Cc: sunpeng.li, rodrigo.siqueira, harry.wentland, Nicholas Kazlauskas
From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
[Why]
Under some hardware initialization sequences the fb base/fb offset
provided can be zero or hardwareinit can happen too late.
We want to ensure that we always have the correct fb_base/fb_offset
when performing DMCUB hardware initialization so we can do DMCUB
command table offloading during first dc hardware init.
[How]
Read from the DCN registers. VBIOS already filled these in for us.
Change-Id: Iea84fd8bda3bff750e6aada75175711c01c6a256
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
IP-reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
---
.../gpu/drm/amd/display/dmub/inc/dmub_srv.h | 2 ++
.../gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 21 +++++++++++++++++--
.../gpu/drm/amd/display/dmub/src/dmub_dcn20.h | 8 +++++--
3 files changed, 27 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
index 8e23a7017588..287fb9a36a64 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
@@ -231,6 +231,8 @@ struct dmub_srv_base_funcs {
struct dmub_srv_hw_funcs {
/* private: internal use only */
+ void (*init)(struct dmub_srv *dmub);
+
void (*reset)(struct dmub_srv *dmub);
void (*reset_release)(struct dmub_srv *dmub);
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
index cd51c6138894..9229012b93e2 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
@@ -54,6 +54,19 @@ const struct dmub_srv_common_regs dmub_srv_dcn20_regs = {
/* Shared functions. */
+static void dmub_dcn20_get_fb_base_offset(struct dmub_srv *dmub,
+ uint64_t *fb_base,
+ uint64_t *fb_offset)
+{
+ uint32_t tmp;
+
+ REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
+ *fb_base = (uint64_t)tmp << 24;
+
+ REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
+ *fb_offset = (uint64_t)tmp << 24;
+}
+
static inline void dmub_dcn20_translate_addr(const union dmub_addr *addr_in,
uint64_t fb_base,
uint64_t fb_offset,
@@ -82,7 +95,9 @@ void dmub_dcn20_backdoor_load(struct dmub_srv *dmub,
const struct dmub_window *cw1)
{
union dmub_addr offset;
- uint64_t fb_base = dmub->fb_base, fb_offset = dmub->fb_offset;
+ uint64_t fb_base, fb_offset;
+
+ dmub_dcn20_get_fb_base_offset(dmub, &fb_base, &fb_offset);
REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x3,
@@ -118,7 +133,9 @@ void dmub_dcn20_setup_windows(struct dmub_srv *dmub,
const struct dmub_window *cw6)
{
union dmub_addr offset;
- uint64_t fb_base = dmub->fb_base, fb_offset = dmub->fb_offset;
+ uint64_t fb_base, fb_offset;
+
+ dmub_dcn20_get_fb_base_offset(dmub, &fb_base, &fb_offset);
dmub_dcn20_translate_addr(&cw2->offset, fb_base, fb_offset, &offset);
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
index 53bfd4da69ad..04b0fa13153d 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
@@ -92,7 +92,9 @@ struct dmub_srv;
DMUB_SR(DMCUB_SCRATCH14) \
DMUB_SR(DMCUB_SCRATCH15) \
DMUB_SR(CC_DC_PIPE_DIS) \
- DMUB_SR(MMHUBBUB_SOFT_RESET)
+ DMUB_SR(MMHUBBUB_SOFT_RESET) \
+ DMUB_SR(DCN_VM_FB_LOCATION_BASE) \
+ DMUB_SR(DCN_VM_FB_OFFSET)
#define DMUB_COMMON_FIELDS() \
DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \
@@ -121,7 +123,9 @@ struct dmub_srv;
DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_ENABLE) \
DMUB_SF(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE) \
- DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET)
+ DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET) \
+ DMUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE) \
+ DMUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET)
struct dmub_srv_common_reg_offset {
#define DMUB_SR(reg) uint32_t reg;
--
2.17.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 01/22] drm/amd/display: update MSA and VSC SDP on video test pattern request
2020-01-16 20:13 [PATCH 00/22] DC Patches 16 Jan 2020 Bhawanpreet Lakha
@ 2020-01-16 20:13 ` Bhawanpreet Lakha
0 siblings, 0 replies; 6+ messages in thread
From: Bhawanpreet Lakha @ 2020-01-16 20:13 UTC (permalink / raw)
To: amd-gfx; +Cc: sunpeng.li, rodrigo.siqueira, harry.wentland, Wenjing Liu
From: Wenjing Liu <Wenjing.Liu@amd.com>
[why]
On video test pattern request we need to update MSA and VSC so
it will match the requested test pattern dynamic range field.
[how]
Update dynamic range field in MSA and disable VSC as updating VSC
info packet is complicated and not required for test pattern purpose.
Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 37 ++++++++++++++++++-
1 file changed, 36 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 6ab298c65247..1bd0946829e3 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -3925,8 +3925,43 @@ bool dc_link_dp_set_test_pattern(
sizeof(training_pattern));
}
} else {
- /* CRTC Patterns */
+ enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
+ struct encoder_info_frame info_frame = pipe_ctx->stream_res.encoder_info_frame;
+
+ switch (test_pattern_color_space) {
+ case DP_TEST_PATTERN_COLOR_SPACE_RGB:
+ color_space = COLOR_SPACE_SRGB;
+ if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
+ color_space = COLOR_SPACE_SRGB_LIMITED;
+ break;
+
+ case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
+ color_space = COLOR_SPACE_YCBCR601;
+ if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
+ color_space = COLOR_SPACE_YCBCR601_LIMITED;
+ break;
+ case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
+ color_space = COLOR_SPACE_YCBCR709;
+ if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
+ color_space = COLOR_SPACE_YCBCR709_LIMITED;
+ break;
+ default:
+ break;
+ }
+ /* update MSA to requested color space */
+ pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(pipe_ctx->stream_res.stream_enc,
+ &pipe_ctx->stream->timing,
+ color_space, false, link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
+
+ /* disable vsc so no need to update it based on request */
+ info_frame.vsc.valid = false;
+ pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
+ pipe_ctx->stream_res.stream_enc,
+ &info_frame);
+
+ /* CRTC Patterns */
set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
+
/* Set Test Pattern state */
link->test_pattern_enabled = true;
}
--
2.17.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread
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Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2020-01-16 20:10 [PATCH 00/22] DC Patches 16 Jan 2020 Bhawanpreet Lakha
2020-01-16 20:10 ` [PATCH 01/22] drm/amd/display: update MSA and VSC SDP on video test pattern request Bhawanpreet Lakha
2020-01-16 20:10 ` [PATCH 02/22] drm/amd/display: Do not send training pattern if VS Different Bhawanpreet Lakha
2020-01-16 20:10 ` [PATCH 03/22] drm/amd/display: Add debug option to disable DSC support Bhawanpreet Lakha
2020-01-16 20:10 ` [PATCH 04/22] drm/amd/display: Get fb base and fb offset for DMUB from registers Bhawanpreet Lakha
2020-01-16 20:13 [PATCH 00/22] DC Patches 16 Jan 2020 Bhawanpreet Lakha
2020-01-16 20:13 ` [PATCH 01/22] drm/amd/display: update MSA and VSC SDP on video test pattern request Bhawanpreet Lakha
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