Re: [PATCH v7 4/5] drm/tidss: New driver for TI Keystone platform Display SubSystem

[Benoit Parrot <bparrot@ti.com>]

Jyri Sarha <jsarha@ti.com> wrote on Fri [2020-Jan-17 00:09:29 +0200]:
> This patch adds a new DRM driver for Texas Instruments DSS IPs used on
> Texas Instruments Keystone K2G, AM65x, and J721e SoCs. The new DSS IP is
> a major change to the older DSS IP versions, which are supported by
> the omapdrm driver. While on higher level the Keystone DSS resembles
> the older DSS versions, the registers are completely different and the
> internal pipelines differ a lot.
> 
> DSS IP found on K2G is an "ultra-light" version, and has only a single
> plane and a single output. The K3 DSS IPs are found on AM65x and J721E
> SoCs. AM65x DSS has two video ports, one full video plane, and another
> "lite" plane without scaling support. J721E has 4 video ports, 2 video
> planes and 2 lite planes. AM65x DSS has also an integrated OLDI (LVDS)
> output.
> 
> Version history:
> 
> v2: - rebased on top of drm-next-2019-11-27
>     - sort all include lines in all files
>     - remove all include <drm/drmP.h>
>     - remove select "select VIDEOMODE_HELPERS"
>     - call dispc_vp_setup() later in tidss_crtc_atomic_flush() (there is no
>       to call it in new modeset case as it is also called in vp_enable())
>     - change probe sequence and drm_device allocation (follow example in
>       drm_drv.c)
>     - use __maybe_unused instead of #ifdef for pm functions
>     - remove "struct drm_fbdev_cma *fbdev;" from driver data
>     - check panel connector type before connecting it
> 
> v3: no change
> 
> v4: no change
> 
> v5: - remove fifo underflow irq handling, it is not an error and
>       it should be used for debug purposes only
>     - memory tuning, prefetch plane fifo up to high-threshold value to
>       minimize possibility of underflows.
> 
> v6: - Check CTM and gamma support from dispc_features when creating crtc
>     - Implement CTM support for k2g and fix k3 CTM implementation
>     - Remove gamma property persistence and always write color properties
>       in a new modeset
> 
> v7: - Fix checkpatch.pl --strict issues
>     - Rebase on top of drm-misc-next-2020-01-10
> 
> Co-developed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
> Signed-off-by: Jyri Sarha <jsarha@ti.com>
> Acked-by: Sam Ravnborg <sam@ravnborg.org>
> ---

<snip>

> +
> +int dispc_init(struct tidss_device *tidss)
> +{
> +	struct device *dev = tidss->dev;
> +	struct platform_device *pdev = to_platform_device(dev);
> +	struct dispc_device *dispc;
> +	const struct dispc_features *feat;
> +	unsigned int i, num_fourccs;
> +	int r = 0;
> +
> +	dev_dbg(dev, "%s\n", __func__);
> +
> +	feat = tidss->feat;
> +
> +	if (feat->subrev != DISPC_K2G) {
> +		r = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48));
> +		if (r)
> +			dev_warn(dev, "cannot set DMA masks to 48-bit\n");
> +	}
> +
> +	dispc = devm_kzalloc(dev, sizeof(*dispc), GFP_KERNEL);
> +	if (!dispc)
> +		return -ENOMEM;
> +
> +	dispc->fourccs = devm_kcalloc(dev, ARRAY_SIZE(dispc_color_formats),
> +				      sizeof(*dispc->fourccs), GFP_KERNEL);
> +	if (!dispc->fourccs)
> +		return -ENOMEM;
> +
> +	num_fourccs = 0;
> +	for (i = 0; i < ARRAY_SIZE(dispc_color_formats); ++i) {
> +		if (feat->errata.i2000 &&
> +		    dispc_fourcc_is_yuv(dispc_color_formats[i].fourcc))
> +			continue;
> +		dispc->fourccs[num_fourccs++] = dispc_color_formats[i].fourcc;
> +	}
> +	dispc->num_fourccs = num_fourccs;
> +	dispc->tidss = tidss;
> +	dispc->dev = dev;
> +	dispc->feat = feat;
> +
> +	dispc_common_regmap = dispc->feat->common_regs;
> +
> +	r = dispc_iomap_resource(pdev, dispc->feat->common,
> +				 &dispc->base_common);
> +	if (r)
> +		return r;
> +
> +	for (i = 0; i < dispc->feat->num_planes; i++) {
> +		r = dispc_iomap_resource(pdev, dispc->feat->vid_name[i],
> +					 &dispc->base_vid[i]);
> +		dev_dbg(dev, "%s: %u %s %d\n", __func__,
> +			i, dispc->feat->vid_name[i], r);

dispc_iomap_resource() already print an error trace when something is
wrong. Not sure this dev_dbg add any info.

> +		if (r)
> +			return r;
> +	}
> +
> +	for (i = 0; i < dispc->feat->num_vps; i++) {
> +		u32 gamma_size = dispc->feat->vp_feat.color.gamma_size;
> +		u32 *gamma_table;
> +		struct clk *clk;
> +
> +		r = dispc_iomap_resource(pdev, dispc->feat->ovr_name[i],
> +					 &dispc->base_ovr[i]);
> +		dev_dbg(dev, "%s: %u %s %d\n", __func__,
> +			i, dispc->feat->ovr_name[i], r);

Same here.

> +		if (r)
> +			return r;
> +
> +		r = dispc_iomap_resource(pdev, dispc->feat->vp_name[i],
> +					 &dispc->base_vp[i]);
> +		dev_dbg(dev, "%s: %u %s %d\n", __func__,
> +			i, dispc->feat->vp_name[i], r);

And here.

But with or without this change

Reviewed-by: Benoit Parrot <bparrot@ti.com>

> +		if (r)
> +			return r;
> +
> +		clk = devm_clk_get(dev, dispc->feat->vpclk_name[i]);
> +		if (IS_ERR(clk)) {
> +			dev_err(dev, "%s: Failed to get clk %s:%ld\n", __func__,
> +				dispc->feat->vpclk_name[i], PTR_ERR(clk));
> +			return PTR_ERR(clk);
> +		}
> +		dispc->vp_clk[i] = clk;
> +
> +		gamma_table = devm_kmalloc_array(dev, gamma_size,
> +						 sizeof(*gamma_table),
> +						 GFP_KERNEL);
> +		if (!gamma_table)
> +			return -ENOMEM;
> +		dispc->vp_data[i].gamma_table = gamma_table;
> +	}
> +
> +	if (feat->subrev == DISPC_AM65X) {
> +		r = dispc_init_am65x_oldi_io_ctrl(dev, dispc);
> +		if (r)
> +			return r;
> +	}
> +
> +	dispc->fclk = devm_clk_get(dev, "fck");
> +	if (IS_ERR(dispc->fclk)) {
> +		dev_err(dev, "%s: Failed to get fclk: %ld\n",
> +			__func__, PTR_ERR(dispc->fclk));
> +		return PTR_ERR(dispc->fclk);
> +	}
> +	dev_dbg(dev, "DSS fclk %lu Hz\n", clk_get_rate(dispc->fclk));
> +
> +	of_property_read_u32(dispc->dev->of_node, "max-memory-bandwidth",
> +			     &dispc->memory_bandwidth_limit);
> +
> +	tidss->dispc = dispc;
> +
> +	return 0;
> +}