From: Palmer Dabbelt <palmerdabbelt@google.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
Pan Nengyuan <pannengyuan@huawei.com>,
Euler Robot <euler.robot@huawei.com>,
ilippe=20Mathieu-Daud=C3=A9?= <philmd@redhat.com>,
Alistair Francis <alistair.francis@wdc.com>,
Palmer Dabbelt <palmerdabbelt@google.com>
Subject: [PULL 1/5] riscv/sifive_u: fix a memory leak in soc_realize()
Date: Tue, 21 Jan 2020 14:56:58 -0800 [thread overview]
Message-ID: <20200121225703.148465-2-palmerdabbelt@google.com> (raw)
In-Reply-To: <20200121225703.148465-1-palmerdabbelt@google.com>
From: Pan Nengyuan <pannengyuan@huawei.com>
Fix a minor memory leak in riscv_sifive_u_soc_realize()
Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
---
hw/riscv/sifive_u.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 0140e95732..0e12b3ccef 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -542,6 +542,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
SIFIVE_U_PLIC_CONTEXT_BASE,
SIFIVE_U_PLIC_CONTEXT_STRIDE,
memmap[SIFIVE_U_PLIC].size);
+ g_free(plic_hart_config);
sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
--
2.25.0.341.g760bfbb309-goog
next prev parent reply other threads:[~2020-01-21 23:43 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-21 22:56 [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1 Palmer Dabbelt
2020-01-21 22:56 ` Palmer Dabbelt [this message]
2020-01-21 22:56 ` [PULL 2/5] riscv: Set xPIE to 1 after xRET Palmer Dabbelt
2020-01-21 22:57 ` [PULL 3/5] target/riscv: Fix tb->flags FS status Palmer Dabbelt
2020-01-21 22:57 ` [PULL 4/5] target/riscv: fsd/fsw doesn't dirty FP state Palmer Dabbelt
2020-01-21 22:57 ` [PULL 5/5] target/riscv: update mstatus.SD when FS is set dirty Palmer Dabbelt
2020-01-23 14:38 ` [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1 Peter Maydell
2020-01-23 14:38 ` Peter Maydell
2020-01-23 18:43 ` Palmer Dabbelt
2020-01-24 12:35 ` Peter Maydell
2020-01-27 19:23 ` Palmer Dabbelt
2020-01-24 13:22 ` Peter Maydell
2020-01-24 13:22 ` Peter Maydell
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