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From: Palmer Dabbelt <palmerdabbelt@google.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org,       qemu-riscv@nongnu.org,
	ShihPo Hung <shihpo.hung@sifive.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	 Palmer Dabbelt <palmerdabbelt@google.com>
Subject: [PULL 3/5] target/riscv: Fix tb->flags FS status
Date: Tue, 21 Jan 2020 14:57:00 -0800	[thread overview]
Message-ID: <20200121225703.148465-4-palmerdabbelt@google.com> (raw)
In-Reply-To: <20200121225703.148465-1-palmerdabbelt@google.com>

From: ShihPo Hung <shihpo.hung@sifive.com>

It was found that running libquantum on riscv-linux qemu produced an
incorrect result. After investigation, FP registers are not saved
during context switch due to incorrect mstatus.FS.

In current implementation tb->flags merges all non-disabled state to
dirty. This means the code in mark_fs_dirty in translate.c that
handles initial and clean states is unreachable.

This patch fixes it and is successfully tested with:
  libquantum

Thanks to Richard for pointing out the actual bug.

v3: remove the redundant condition
v2: root cause FS problem

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: ShihPo Hung <shihpo.hung@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
---
 target/riscv/cpu.h | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index e59343e13c..de0a8d893a 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -293,10 +293,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
 #ifdef CONFIG_USER_ONLY
     *flags = TB_FLAGS_MSTATUS_FS;
 #else
-    *flags = cpu_mmu_index(env, 0);
-    if (riscv_cpu_fp_enabled(env)) {
-        *flags |= TB_FLAGS_MSTATUS_FS;
-    }
+    *flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS);
 #endif
 }
 
-- 
2.25.0.341.g760bfbb309-goog



  parent reply	other threads:[~2020-01-21 23:45 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-21 22:56 [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1 Palmer Dabbelt
2020-01-21 22:56 ` [PULL 1/5] riscv/sifive_u: fix a memory leak in soc_realize() Palmer Dabbelt
2020-01-21 22:56 ` [PULL 2/5] riscv: Set xPIE to 1 after xRET Palmer Dabbelt
2020-01-21 22:57 ` Palmer Dabbelt [this message]
2020-01-21 22:57 ` [PULL 4/5] target/riscv: fsd/fsw doesn't dirty FP state Palmer Dabbelt
2020-01-21 22:57 ` [PULL 5/5] target/riscv: update mstatus.SD when FS is set dirty Palmer Dabbelt
2020-01-23 14:38 ` [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1 Peter Maydell
2020-01-23 14:38   ` Peter Maydell
2020-01-23 18:43 ` Palmer Dabbelt
2020-01-24 12:35   ` Peter Maydell
2020-01-27 19:23   ` Palmer Dabbelt
2020-01-24 13:22 ` Peter Maydell
2020-01-24 13:22   ` Peter Maydell

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