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From: Pragnesh Patel <pragnesh.patel@sifive.com>
To: u-boot@lists.denx.de
Subject: [PATCH v3 04/10] riscv: sifive: dts: fu540: Add board -u-boot.dtsi files
Date: Fri, 24 Jan 2020 11:20:17 +0530	[thread overview]
Message-ID: <20200124055026.30787-5-pragnesh.patel@sifive.com> (raw)
In-Reply-To: <20200124055026.30787-1-pragnesh.patel@sifive.com>

Devicetree files in FU540 platform is synced from Linux, like other
platforms does. Apart from these u-boot in FU540 would also require
some u-boot specific node like clint.

So, create board specific -u-boot.dtsi files. This would help of
maintain u-boot specific changes separately without touching Linux
dts(i) files which indeed easy for syncing from Linux between
releases.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
---
 arch/riscv/dts/fu540-c000-u-boot.dtsi         | 42 +++++++++++++++++++
 .../dts/hifive-unleashed-a00-u-boot.dtsi      | 16 +++++++
 2 files changed, 58 insertions(+)

diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index 615a68c0e9..7a7abc7cce 100644
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -4,10 +4,52 @@
  */
 
 / {
+	cpus {
+		u-boot,dm-spl;
+		cpu0: cpu at 0 {
+			u-boot,dm-spl;
+			status = "okay";
+			cpu0_intc: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+		cpu1: cpu at 1 {
+			u-boot,dm-spl;
+		};
+		cpu2: cpu at 2 {
+			u-boot,dm-spl;
+		};
+		cpu3: cpu at 3 {
+			u-boot,dm-spl;
+		};
+		cpu4: cpu at 4 {
+			u-boot,dm-spl;
+		};
+	};
+
 	soc {
+		u-boot,dm-spl;
 		otp: otp at 10070000 {
 			compatible = "sifive,fu540-otp";
 			reg = <0x0 0x10070000 0x0 0x0FFF>;
 		};
+		clint at 2000000 {
+			compatible = "riscv,clint0";
+			interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 >;
+			reg = <0x0 0x2000000 0x0 0xc0000>;
+			u-boot,dm-spl;
+		};
 	};
 };
+
+&prci {
+	u-boot,dm-spl;
+};
+
+&uart0 {
+	u-boot,dm-spl;
+};
+
+&qspi2 {
+	u-boot,dm-spl;
+};
diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
index bec0d19134..cce1bd943e 100644
--- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
@@ -4,3 +4,19 @@
  */
 
 #include "fu540-c000-u-boot.dtsi"
+
+/ {
+	hfclk {
+		u-boot,dm-spl;
+	};
+
+	rtcclk {
+		u-boot,dm-spl;
+	};
+};
+
+&qspi2 {
+	mmc at 0 {
+		u-boot,dm-spl;
+	};
+};
-- 
2.17.1

  parent reply	other threads:[~2020-01-24  5:50 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-24  5:50 [PATCH v3 00/10] RISC-V SiFive FU540 support SPL Pragnesh Patel
2020-01-24  5:50 ` [PATCH v3 01/10] misc: add driver for the Sifive otp controller Pragnesh Patel
2020-01-24  6:41   ` Jagan Teki
2020-01-27 10:18     ` Pragnesh Patel
2020-02-10 12:44       ` Pragnesh Patel
2020-01-24  5:50 ` [PATCH v3 02/10] riscv: Add _image_binary_end for SPL Pragnesh Patel
2020-01-24  6:44   ` Jagan Teki
2020-01-24  5:50 ` [PATCH v3 03/10] lib: Makefile: build crc7.c when CONFIG_MMC_SPI Pragnesh Patel
2020-01-24  6:27   ` Jagan Teki
2020-01-24  8:06     ` Pragnesh Patel
2020-01-27  7:58       ` Jagan Teki
2020-01-24  5:50 ` Pragnesh Patel [this message]
2020-01-24  5:50 ` [PATCH v3 05/10] riscv: sifive: fu540: add DDR4 info Pragnesh Patel
2020-01-25  8:31   ` Anup Patel
2020-01-27  7:51   ` Jagan Teki
2020-01-28  6:41     ` Pragnesh Patel
2020-02-04 15:19       ` Bin Meng
2020-01-24  5:50 ` [PATCH v3 06/10] riscv: sifive: fu540: add SPL configuration Pragnesh Patel
2020-01-25  8:35   ` Anup Patel
2020-01-24  5:50 ` [PATCH v3 07/10] configs: fu540: Add config file for U-boot SPL Pragnesh Patel
2020-01-24  6:50   ` Jagan Teki
2020-01-25  8:41     ` Anup Patel
2020-01-27  7:49       ` Pragnesh Patel
2020-01-27 12:45         ` Anup Patel
2020-01-27  6:50     ` Pragnesh Patel
2020-01-27  7:38       ` Anup Patel
2020-01-27  7:41         ` Pragnesh Patel
2020-01-24  5:50 ` [PATCH v3 08/10] riscv: sifive: fu540: enable all cache ways from u-boot proper Pragnesh Patel
2020-01-25  8:36   ` Anup Patel
2020-01-24  5:50 ` [PATCH v3 09/10] sifive: fix palmer's email address and add sifive_fu540_spl_defconfig Pragnesh Patel
2020-01-25  8:37   ` Anup Patel
2020-01-24  5:50 ` [PATCH v3 10/10] doc: update FU540 RISC-V documentation Pragnesh Patel

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