* [PATCH v3 1/3] clk: composite: add _register_composite_pdata() variants
@ 2020-01-02 23:10 Michael Walle
2020-01-02 23:11 ` [PATCH v3 2/3] dt-bindings: clock: document the fsl-sai driver Michael Walle
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Michael Walle @ 2020-01-02 23:10 UTC (permalink / raw)
To: linux-clk, devicetree, linux-kernel
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland,
Michael Walle
Add support for the new way of specifying the clock parents. Add the
two new functions
clk_hw_register_composite_pdata()
clk_register_composite_pdata()
to let the driver provide parent_data instead of the parent_names.
Signed-off-by: Michael Walle <michael@walle.cc>
---
New patch in v3 of this series. Thus no changelog.
drivers/clk/clk-composite.c | 56 ++++++++++++++++++++++++++++++++++--
include/linux/clk-provider.h | 13 +++++++++
2 files changed, 66 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index 3e9c3e608769..7376f573bfdb 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -199,8 +199,9 @@ static void clk_composite_disable(struct clk_hw *hw)
gate_ops->disable(gate_hw);
}
-struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
- const char * const *parent_names, int num_parents,
+static struct clk_hw *__clk_hw_register_composite(struct device *dev,
+ const char *name, const char * const *parent_names,
+ const struct clk_parent_data *pdata, int num_parents,
struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
@@ -218,7 +219,10 @@ struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
init.name = name;
init.flags = flags;
- init.parent_names = parent_names;
+ if (parent_names)
+ init.parent_names = parent_names;
+ else
+ init.parent_data = pdata;
init.num_parents = num_parents;
hw = &composite->hw;
@@ -312,6 +316,34 @@ struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
return hw;
}
+struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
+ const char * const *parent_names, int num_parents,
+ struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
+ struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
+ struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
+ unsigned long flags)
+{
+ return __clk_hw_register_composite(dev, name, parent_names, NULL,
+ num_parents, mux_hw, mux_ops,
+ rate_hw, rate_ops, gate_hw,
+ gate_ops, flags);
+}
+
+struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
+ const char *name,
+ const struct clk_parent_data *parent_data,
+ int num_parents,
+ struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
+ struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
+ struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
+ unsigned long flags)
+{
+ return __clk_hw_register_composite(dev, name, NULL, parent_data,
+ num_parents, mux_hw, mux_ops,
+ rate_hw, rate_ops, gate_hw,
+ gate_ops, flags);
+}
+
struct clk *clk_register_composite(struct device *dev, const char *name,
const char * const *parent_names, int num_parents,
struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
@@ -329,6 +361,24 @@ struct clk *clk_register_composite(struct device *dev, const char *name,
return hw->clk;
}
+struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
+ const struct clk_parent_data *parent_data,
+ int num_parents,
+ struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
+ struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
+ struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
+ unsigned long flags)
+{
+ struct clk_hw *hw;
+
+ hw = clk_hw_register_composite_pdata(dev, name, parent_data,
+ num_parents, mux_hw, mux_ops, rate_hw, rate_ops,
+ gate_hw, gate_ops, flags);
+ if (IS_ERR(hw))
+ return ERR_CAST(hw);
+ return hw->clk;
+}
+
void clk_unregister_composite(struct clk *clk)
{
struct clk_composite *composite;
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index caf4b9df16eb..e2e9d867df36 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -743,6 +743,12 @@ struct clk *clk_register_composite(struct device *dev, const char *name,
struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
unsigned long flags);
+struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
+ const struct clk_parent_data *parent_data, int num_parents,
+ struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
+ struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
+ struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
+ unsigned long flags);
void clk_unregister_composite(struct clk *clk);
struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
const char * const *parent_names, int num_parents,
@@ -750,6 +756,13 @@ struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
unsigned long flags);
+struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
+ const char *name,
+ const struct clk_parent_data *parent_data, int num_parents,
+ struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
+ struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
+ struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
+ unsigned long flags);
void clk_hw_unregister_composite(struct clk_hw *hw);
/**
--
2.20.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v3 2/3] dt-bindings: clock: document the fsl-sai driver
2020-01-02 23:10 [PATCH v3 1/3] clk: composite: add _register_composite_pdata() variants Michael Walle
@ 2020-01-02 23:11 ` Michael Walle
2020-01-28 22:04 ` Stephen Boyd
2020-01-02 23:11 ` [PATCH v3 3/3] clk: fsl-sai: new driver Michael Walle
2020-01-28 22:04 ` [PATCH v3 1/3] clk: composite: add _register_composite_pdata() variants Stephen Boyd
2 siblings, 1 reply; 7+ messages in thread
From: Michael Walle @ 2020-01-02 23:11 UTC (permalink / raw)
To: linux-clk, devicetree, linux-kernel
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland,
Michael Walle, Rob Herring
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Rob Herring <robh@kernel.org>
---
changes since v2:
- add Reviewed-by tag
changes since v1:
- dual license gpl-2.0-only and bsd-2-clause
- add "additionalProperties: false"
- wrap example in soc {} node with correct #address-cells and #size-cells
.../bindings/clock/fsl,sai-clock.yaml | 55 +++++++++++++++++++
1 file changed, 55 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml
diff --git a/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml b/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml
new file mode 100644
index 000000000000..8fb2060ac47f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/clock/fsl,sai-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale SAI bitclock-as-a-clock binding
+
+maintainers:
+ - Michael Walle <michael@walle.cc>
+
+description: |
+ It is possible to use the BCLK pin of a SAI module as a generic clock
+ output. Some SoC are very constrained in their pin multiplexer
+ configuration. Eg. pins can only be changed groups. For example, on the
+ LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,
+ the second pins are wasted. Using this binding it is possible to use the
+ clock of the second SAI as a MCLK clock for an audio codec, for example.
+
+ This is a composite of a gated clock and a divider clock.
+
+properties:
+ compatible:
+ const: fsl,vf610-sai-clock
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ mclk: clock-mclk@f130080 {
+ compatible = "fsl,vf610-sai-clock";
+ reg = <0x0 0xf130080 0x0 0x80>;
+ #clock-cells = <0>;
+ clocks = <&parentclk>;
+ };
+ };
--
2.20.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v3 3/3] clk: fsl-sai: new driver
2020-01-02 23:10 [PATCH v3 1/3] clk: composite: add _register_composite_pdata() variants Michael Walle
2020-01-02 23:11 ` [PATCH v3 2/3] dt-bindings: clock: document the fsl-sai driver Michael Walle
@ 2020-01-02 23:11 ` Michael Walle
2020-01-14 15:55 ` Michael Walle
2020-01-28 22:04 ` Stephen Boyd
2020-01-28 22:04 ` [PATCH v3 1/3] clk: composite: add _register_composite_pdata() variants Stephen Boyd
2 siblings, 2 replies; 7+ messages in thread
From: Michael Walle @ 2020-01-02 23:11 UTC (permalink / raw)
To: linux-clk, devicetree, linux-kernel
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland,
Michael Walle
With this driver it is possible to use the BCLK pin of the SAI module as
a generic clock output. This is esp. useful if you want to drive a clock
to an audio codec. Because the output only allows integer divider values
the audio codec needs an integrated PLL.
Signed-off-by: Michael Walle <michael@walle.cc>
---
changes since v2:
- convert to platform driver, thus also use devm_ functions
- use new style to get the parent clock by using parent_data
and the new clk_hw_register_composite_pdata()
changes since v1:
- none
drivers/clk/Kconfig | 12 +++++
drivers/clk/Makefile | 1 +
drivers/clk/clk-fsl-sai.c | 92 +++++++++++++++++++++++++++++++++++++++
3 files changed, 105 insertions(+)
create mode 100644 drivers/clk/clk-fsl-sai.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 45653a0e6ecd..dd1a5abc4ce8 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -174,6 +174,18 @@ config COMMON_CLK_CS2000_CP
help
If you say yes here you get support for the CS2000 clock multiplier.
+config COMMON_CLK_FSL_SAI
+ bool "Clock driver for BCLK of Freescale SAI cores"
+ depends on ARCH_LAYERSCAPE || COMPILE_TEST
+ help
+ This driver supports the Freescale SAI (Synchronous Audio Interface)
+ to be used as a generic clock output. Some SoCs have restrictions
+ regarding the possible pin multiplexer settings. Eg. on some SoCs
+ two SAI interfaces can only be enabled together. If just one is
+ needed, the BCLK pin of the second one can be used as general
+ purpose clock output. Ideally, it can be used to drive an audio
+ codec (sometimes known as MCLK).
+
config COMMON_CLK_GEMINI
bool "Clock driver for Cortina Systems Gemini SoC"
depends on ARCH_GEMINI || COMPILE_TEST
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 0696a0c1ab58..ec23fd956228 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o
obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o
obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o
+obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o
obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o
obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o
obj-$(CONFIG_MACH_ASPEED_G6) += clk-ast2600.o
diff --git a/drivers/clk/clk-fsl-sai.c b/drivers/clk/clk-fsl-sai.c
new file mode 100644
index 000000000000..0221180a4dd7
--- /dev/null
+++ b/drivers/clk/clk-fsl-sai.c
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Freescale SAI BCLK as a generic clock driver
+ *
+ * Copyright 2020 Michael Walle <michael@walle.cc>
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+
+#define I2S_CSR 0x00
+#define I2S_CR2 0x08
+#define CSR_BCE_BIT 28
+#define CR2_BCD BIT(24)
+#define CR2_DIV_SHIFT 0
+#define CR2_DIV_WIDTH 8
+
+struct fsl_sai_clk {
+ struct clk_divider div;
+ struct clk_gate gate;
+ spinlock_t lock;
+};
+
+static int fsl_sai_clk_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct fsl_sai_clk *sai_clk;
+ struct clk_parent_data pdata = { .index = 0 };
+ void __iomem *base;
+ struct clk_hw *hw;
+ struct resource *res;
+
+ sai_clk = devm_kzalloc(dev, sizeof(*sai_clk), GFP_KERNEL);
+ if (!sai_clk)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ spin_lock_init(&sai_clk->lock);
+
+ sai_clk->gate.reg = base + I2S_CSR;
+ sai_clk->gate.bit_idx = CSR_BCE_BIT;
+ sai_clk->gate.lock = &sai_clk->lock;
+
+ sai_clk->div.reg = base + I2S_CR2;
+ sai_clk->div.shift = CR2_DIV_SHIFT;
+ sai_clk->div.width = CR2_DIV_WIDTH;
+ sai_clk->div.lock = &sai_clk->lock;
+
+ /* set clock direction, we are the BCLK master */
+ writel(CR2_BCD, base + I2S_CR2);
+
+ hw = clk_hw_register_composite_pdata(dev, dev->of_node->name,
+ &pdata, 1, NULL, NULL,
+ &sai_clk->div.hw,
+ &clk_divider_ops,
+ &sai_clk->gate.hw,
+ &clk_gate_ops,
+ CLK_SET_RATE_GATE);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+
+ return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
+}
+
+static const struct of_device_id of_fsl_sai_clk_ids[] = {
+ { .compatible = "fsl,vf610-sai-clock" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, of_fsl_sai_clk_ids);
+
+static struct platform_driver fsl_sai_clk_driver = {
+ .probe = fsl_sai_clk_probe,
+ .driver = {
+ .name = "fsl-sai-clk",
+ .of_match_table = of_fsl_sai_clk_ids,
+ },
+};
+module_platform_driver(fsl_sai_clk_driver);
+
+MODULE_DESCRIPTION("Freescale SAI bitclock-as-a-clock driver");
+MODULE_AUTHOR("Michael Walle <michael@walle.cc>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:fsl-sai-clk");
--
2.20.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v3 3/3] clk: fsl-sai: new driver
2020-01-02 23:11 ` [PATCH v3 3/3] clk: fsl-sai: new driver Michael Walle
@ 2020-01-14 15:55 ` Michael Walle
2020-01-28 22:04 ` Stephen Boyd
1 sibling, 0 replies; 7+ messages in thread
From: Michael Walle @ 2020-01-14 15:55 UTC (permalink / raw)
To: linux-clk, devicetree, linux-kernel
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland
Am 2020-01-03 00:11, schrieb Michael Walle:
> With this driver it is possible to use the BCLK pin of the SAI module
> as
> a generic clock output. This is esp. useful if you want to drive a
> clock
> to an audio codec. Because the output only allows integer divider
> values
> the audio codec needs an integrated PLL.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
Ping :)
> ---
> changes since v2:
> - convert to platform driver, thus also use devm_ functions
> - use new style to get the parent clock by using parent_data
> and the new clk_hw_register_composite_pdata()
>
> changes since v1:
> - none
>
> drivers/clk/Kconfig | 12 +++++
> drivers/clk/Makefile | 1 +
> drivers/clk/clk-fsl-sai.c | 92 +++++++++++++++++++++++++++++++++++++++
> 3 files changed, 105 insertions(+)
> create mode 100644 drivers/clk/clk-fsl-sai.c
>
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 45653a0e6ecd..dd1a5abc4ce8 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -174,6 +174,18 @@ config COMMON_CLK_CS2000_CP
> help
> If you say yes here you get support for the CS2000 clock
> multiplier.
>
> +config COMMON_CLK_FSL_SAI
> + bool "Clock driver for BCLK of Freescale SAI cores"
> + depends on ARCH_LAYERSCAPE || COMPILE_TEST
> + help
> + This driver supports the Freescale SAI (Synchronous Audio
> Interface)
> + to be used as a generic clock output. Some SoCs have restrictions
> + regarding the possible pin multiplexer settings. Eg. on some SoCs
> + two SAI interfaces can only be enabled together. If just one is
> + needed, the BCLK pin of the second one can be used as general
> + purpose clock output. Ideally, it can be used to drive an audio
> + codec (sometimes known as MCLK).
> +
> config COMMON_CLK_GEMINI
> bool "Clock driver for Cortina Systems Gemini SoC"
> depends on ARCH_GEMINI || COMPILE_TEST
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index 0696a0c1ab58..ec23fd956228 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -29,6 +29,7 @@ obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o
> obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o
> obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
> obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o
> +obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o
> obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o
> obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o
> obj-$(CONFIG_MACH_ASPEED_G6) += clk-ast2600.o
> diff --git a/drivers/clk/clk-fsl-sai.c b/drivers/clk/clk-fsl-sai.c
> new file mode 100644
> index 000000000000..0221180a4dd7
> --- /dev/null
> +++ b/drivers/clk/clk-fsl-sai.c
> @@ -0,0 +1,92 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Freescale SAI BCLK as a generic clock driver
> + *
> + * Copyright 2020 Michael Walle <michael@walle.cc>
> + */
> +
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/clk-provider.h>
> +#include <linux/err.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/slab.h>
> +
> +#define I2S_CSR 0x00
> +#define I2S_CR2 0x08
> +#define CSR_BCE_BIT 28
> +#define CR2_BCD BIT(24)
> +#define CR2_DIV_SHIFT 0
> +#define CR2_DIV_WIDTH 8
> +
> +struct fsl_sai_clk {
> + struct clk_divider div;
> + struct clk_gate gate;
> + spinlock_t lock;
> +};
> +
> +static int fsl_sai_clk_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct fsl_sai_clk *sai_clk;
> + struct clk_parent_data pdata = { .index = 0 };
> + void __iomem *base;
> + struct clk_hw *hw;
> + struct resource *res;
> +
> + sai_clk = devm_kzalloc(dev, sizeof(*sai_clk), GFP_KERNEL);
> + if (!sai_clk)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + spin_lock_init(&sai_clk->lock);
> +
> + sai_clk->gate.reg = base + I2S_CSR;
> + sai_clk->gate.bit_idx = CSR_BCE_BIT;
> + sai_clk->gate.lock = &sai_clk->lock;
> +
> + sai_clk->div.reg = base + I2S_CR2;
> + sai_clk->div.shift = CR2_DIV_SHIFT;
> + sai_clk->div.width = CR2_DIV_WIDTH;
> + sai_clk->div.lock = &sai_clk->lock;
> +
> + /* set clock direction, we are the BCLK master */
> + writel(CR2_BCD, base + I2S_CR2);
> +
> + hw = clk_hw_register_composite_pdata(dev, dev->of_node->name,
> + &pdata, 1, NULL, NULL,
> + &sai_clk->div.hw,
> + &clk_divider_ops,
> + &sai_clk->gate.hw,
> + &clk_gate_ops,
> + CLK_SET_RATE_GATE);
> + if (IS_ERR(hw))
> + return PTR_ERR(hw);
> +
> + return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
> +}
> +
> +static const struct of_device_id of_fsl_sai_clk_ids[] = {
> + { .compatible = "fsl,vf610-sai-clock" },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, of_fsl_sai_clk_ids);
> +
> +static struct platform_driver fsl_sai_clk_driver = {
> + .probe = fsl_sai_clk_probe,
> + .driver = {
> + .name = "fsl-sai-clk",
> + .of_match_table = of_fsl_sai_clk_ids,
> + },
> +};
> +module_platform_driver(fsl_sai_clk_driver);
> +
> +MODULE_DESCRIPTION("Freescale SAI bitclock-as-a-clock driver");
> +MODULE_AUTHOR("Michael Walle <michael@walle.cc>");
> +MODULE_LICENSE("GPL");
> +MODULE_ALIAS("platform:fsl-sai-clk");
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3 1/3] clk: composite: add _register_composite_pdata() variants
2020-01-02 23:10 [PATCH v3 1/3] clk: composite: add _register_composite_pdata() variants Michael Walle
2020-01-02 23:11 ` [PATCH v3 2/3] dt-bindings: clock: document the fsl-sai driver Michael Walle
2020-01-02 23:11 ` [PATCH v3 3/3] clk: fsl-sai: new driver Michael Walle
@ 2020-01-28 22:04 ` Stephen Boyd
2 siblings, 0 replies; 7+ messages in thread
From: Stephen Boyd @ 2020-01-28 22:04 UTC (permalink / raw)
To: Michael Walle, devicetree, linux-clk, linux-kernel
Cc: Michael Turquette, Rob Herring, Mark Rutland, Michael Walle
Quoting Michael Walle (2020-01-02 15:10:59)
> Add support for the new way of specifying the clock parents. Add the
> two new functions
> clk_hw_register_composite_pdata()
> clk_register_composite_pdata()
> to let the driver provide parent_data instead of the parent_names.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: clock: document the fsl-sai driver
2020-01-02 23:11 ` [PATCH v3 2/3] dt-bindings: clock: document the fsl-sai driver Michael Walle
@ 2020-01-28 22:04 ` Stephen Boyd
0 siblings, 0 replies; 7+ messages in thread
From: Stephen Boyd @ 2020-01-28 22:04 UTC (permalink / raw)
To: Michael Walle, devicetree, linux-clk, linux-kernel
Cc: Michael Turquette, Rob Herring, Mark Rutland, Michael Walle, Rob Herring
Quoting Michael Walle (2020-01-02 15:11:00)
> Signed-off-by: Michael Walle <michael@walle.cc>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3 3/3] clk: fsl-sai: new driver
2020-01-02 23:11 ` [PATCH v3 3/3] clk: fsl-sai: new driver Michael Walle
2020-01-14 15:55 ` Michael Walle
@ 2020-01-28 22:04 ` Stephen Boyd
1 sibling, 0 replies; 7+ messages in thread
From: Stephen Boyd @ 2020-01-28 22:04 UTC (permalink / raw)
To: Michael Walle, devicetree, linux-clk, linux-kernel
Cc: Michael Turquette, Rob Herring, Mark Rutland, Michael Walle
Quoting Michael Walle (2020-01-02 15:11:01)
> With this driver it is possible to use the BCLK pin of the SAI module as
> a generic clock output. This is esp. useful if you want to drive a clock
> to an audio codec. Because the output only allows integer divider values
> the audio codec needs an integrated PLL.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-01-28 22:04 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-01-02 23:10 [PATCH v3 1/3] clk: composite: add _register_composite_pdata() variants Michael Walle
2020-01-02 23:11 ` [PATCH v3 2/3] dt-bindings: clock: document the fsl-sai driver Michael Walle
2020-01-28 22:04 ` Stephen Boyd
2020-01-02 23:11 ` [PATCH v3 3/3] clk: fsl-sai: new driver Michael Walle
2020-01-14 15:55 ` Michael Walle
2020-01-28 22:04 ` Stephen Boyd
2020-01-28 22:04 ` [PATCH v3 1/3] clk: composite: add _register_composite_pdata() variants Stephen Boyd
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