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* [Intel-gfx] [PATCH] drm/i915/gt: Trim default context register state for gen9
@ 2020-01-28 23:07 Chris Wilson
  2020-01-29  2:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
  2020-01-29  2:56 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
  0 siblings, 2 replies; 4+ messages in thread
From: Chris Wilson @ 2020-01-28 23:07 UTC (permalink / raw)
  To: intel-gfx

Now that it appears we have tamed the mystery hang on module reload, we
can relax some of the counter-measures we employed to help stabilise and
debug gen9. As we have aggressive poisoning of the context image, we can
confidently reduce the default context state in gen9 to match the limits
of the ring regs as laid out on other platforms.

References: 9c6527116e8f ("drm/i915: Restore the kernel context after verifying the w/a")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 98 +----------------------------
 1 file changed, 2 insertions(+), 96 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index cf6c43bd540a..7470dad9afff 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -631,54 +631,7 @@ static const u8 gen9_xcs_offsets[] = {
 	LRI(1, POSTED),
 	REG16(0x200),
 
-	NOP(13),
-	LRI(44, POSTED),
-	REG(0x028),
-	REG(0x09c),
-	REG(0x0c0),
-	REG(0x178),
-	REG(0x17c),
-	REG16(0x358),
-	REG(0x170),
-	REG(0x150),
-	REG(0x154),
-	REG(0x158),
-	REG16(0x41c),
-	REG16(0x600),
-	REG16(0x604),
-	REG16(0x608),
-	REG16(0x60c),
-	REG16(0x610),
-	REG16(0x614),
-	REG16(0x618),
-	REG16(0x61c),
-	REG16(0x620),
-	REG16(0x624),
-	REG16(0x628),
-	REG16(0x62c),
-	REG16(0x630),
-	REG16(0x634),
-	REG16(0x638),
-	REG16(0x63c),
-	REG16(0x640),
-	REG16(0x644),
-	REG16(0x648),
-	REG16(0x64c),
-	REG16(0x650),
-	REG16(0x654),
-	REG16(0x658),
-	REG16(0x65c),
-	REG16(0x660),
-	REG16(0x664),
-	REG16(0x668),
-	REG16(0x66c),
-	REG16(0x670),
-	REG16(0x674),
-	REG16(0x678),
-	REG16(0x67c),
-	REG(0x068),
-
-	END(176)
+	END(80)
 };
 
 static const u8 gen12_xcs_offsets[] = {
@@ -784,54 +737,7 @@ static const u8 gen9_rcs_offsets[] = {
 	LRI(1, 0),
 	REG(0xc8),
 
-	NOP(13),
-	LRI(44, POSTED),
-	REG(0x28),
-	REG(0x9c),
-	REG(0xc0),
-	REG(0x178),
-	REG(0x17c),
-	REG16(0x358),
-	REG(0x170),
-	REG(0x150),
-	REG(0x154),
-	REG(0x158),
-	REG16(0x41c),
-	REG16(0x600),
-	REG16(0x604),
-	REG16(0x608),
-	REG16(0x60c),
-	REG16(0x610),
-	REG16(0x614),
-	REG16(0x618),
-	REG16(0x61c),
-	REG16(0x620),
-	REG16(0x624),
-	REG16(0x628),
-	REG16(0x62c),
-	REG16(0x630),
-	REG16(0x634),
-	REG16(0x638),
-	REG16(0x63c),
-	REG16(0x640),
-	REG16(0x644),
-	REG16(0x648),
-	REG16(0x64c),
-	REG16(0x650),
-	REG16(0x654),
-	REG16(0x658),
-	REG16(0x65c),
-	REG16(0x660),
-	REG16(0x664),
-	REG16(0x668),
-	REG16(0x66c),
-	REG16(0x670),
-	REG16(0x674),
-	REG16(0x678),
-	REG16(0x67c),
-	REG(0x68),
-
-	END(176)
+	END(80)
 };
 
 static const u8 gen11_rcs_offsets[] = {
-- 
2.25.0

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-- links below jump to the message on this page --
2020-01-28 23:07 [Intel-gfx] [PATCH] drm/i915/gt: Trim default context register state for gen9 Chris Wilson
2020-01-29  2:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2020-01-29  2:56 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-01-29  8:04   ` Chris Wilson

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