[igt-dev] [PATCH i-g-t 0/7] Add tests for HDR metadata interfaces and bpc switch

[igt-dev] [PATCH i-g-t 0/7] Add tests for HDR metadata interfaces and bpc switch

[Swati Sharma]

This series contains tests to validate HDR metadata interfaces
and bpc switch test cases (8bpc<->10bpc).
Minor changes are made in the original patch series 
https://patchwork.freedesktop.org/patch/255755/

Changes made to the original series:

*Current version is made compatible for both amd and intel driver,
earlier it could be used by amd driver only.
*No assumption is made regarding output. Tests will execute on
all availabe outputs, since there is no ROI to execute
tests on all the pipes; tests will execute on single pipe.
*To make tests generic, moved tests from tests/amdgpu/amd_hdr.c to
tests/kms_hdr.c.
*Also, splitted the hdr igt into multiple patches so that subtests
can be easily reviewed.
*Renaming of functions, addition of new flags, igt_describe(), etc
*Added function to detect whether panel connected is HDR or not,
if non-HDR then tests will be skipped.
*Dropped test case using luminance sensor

Also, amd exposes max_bpc as a debugfs entry..so it's asserted for their
driver. i915 drives misses that.
TODO: Expose max_bpc as debugfs entry in i915 driver too, if required.

Nicholas Kazlauskas (6):
  headers: Bump drm uapi headers
  lib/igt_kms: Add max bpc connector property
  lib/igt_kms: Add HDR_OUTPUT_METADATA connector property
  tests/kms_hdr: Add bpc switch subtests
  tests/kms_hdr: Add static toggle SDR->HDR mode subtests
  tests/kms_hdr: Add subtest to swap static HDR metadata

Swati Sharma (1):
  tests/kms_hdr: Add function to check HDR panel

 include/drm-uapi/drm_mode.h | 121 ++++++-
 lib/igt_kms.c               |   7 +
 lib/igt_kms.h               |   2 +
 tests/Makefile.sources      |   1 +
 tests/kms_hdr.c             | 655 ++++++++++++++++++++++++++++++++++++
 tests/meson.build           |   1 +
 6 files changed, 785 insertions(+), 2 deletions(-)
 create mode 100644 tests/kms_hdr.c

-- 
2.24.1

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[igt-dev] [PATCH i-g-t 1/7] headers: Bump drm uapi headers

[Swati Sharma]

From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>

Updating them to the latest version from drm-next for HDR static
metadata uapi structures:

 commit a09db883e5d9 ("drm: Fix docbook warnings in hdr metadata
 helper structures")

v2: Bumped to latest drm-next headers

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 include/drm-uapi/drm_mode.h | 121 +++++++++++++++++++++++++++++++++++-
 1 file changed, 119 insertions(+), 2 deletions(-)

diff --git a/include/drm-uapi/drm_mode.h b/include/drm-uapi/drm_mode.h
index a439c2e6..5ab331e5 100644
--- a/include/drm-uapi/drm_mode.h
+++ b/include/drm-uapi/drm_mode.h
@@ -33,7 +33,15 @@
 extern "C" {
 #endif
 
-#define DRM_DISPLAY_INFO_LEN	32
+/**
+ * DOC: overview
+ *
+ * DRM exposes many UAPI and structure definition to have a consistent
+ * and standardized interface with user.
+ * Userspace can refer to these structure definitions and UAPI formats
+ * to communicate to driver
+ */
+
 #define DRM_CONNECTOR_NAME_LEN	32
 #define DRM_DISPLAY_MODE_LEN	32
 #define DRM_PROP_NAME_LEN	32
@@ -622,7 +630,8 @@ struct drm_color_ctm {
 
 struct drm_color_lut {
 	/*
-	 * Data is U0.16 fixed point format.
+	 * Values are mapped linearly to 0.0 - 1.0 range, with 0x0 == 0.0 and
+	 * 0xffff == 1.0.
 	 */
 	__u16 red;
 	__u16 green;
@@ -630,6 +639,92 @@ struct drm_color_lut {
 	__u16 reserved;
 };
 
+/**
+ * struct hdr_metadata_infoframe - HDR Metadata Infoframe Data.
+ *
+ * HDR Metadata Infoframe as per CTA 861.G spec. This is expected
+ * to match exactly with the spec.
+ *
+ * Userspace is expected to pass the metadata information as per
+ * the format described in this structure.
+ */
+struct hdr_metadata_infoframe {
+	/**
+	 * @eotf: Electro-Optical Transfer Function (EOTF)
+	 * used in the stream.
+	 */
+	__u8 eotf;
+	/**
+	 * @metadata_type: Static_Metadata_Descriptor_ID.
+	 */
+	__u8 metadata_type;
+	/**
+	 * @display_primaries: Color Primaries of the Data.
+	 * These are coded as unsigned 16-bit values in units of
+	 * 0.00002, where 0x0000 represents zero and 0xC350
+	 * represents 1.0000.
+	 * @display_primaries.x: X cordinate of color primary.
+	 * @display_primaries.y: Y cordinate of color primary.
+	 */
+	struct {
+		__u16 x, y;
+		} display_primaries[3];
+	/**
+	 * @white_point: White Point of Colorspace Data.
+	 * These are coded as unsigned 16-bit values in units of
+	 * 0.00002, where 0x0000 represents zero and 0xC350
+	 * represents 1.0000.
+	 * @white_point.x: X cordinate of whitepoint of color primary.
+	 * @white_point.y: Y cordinate of whitepoint of color primary.
+	 */
+	struct {
+		__u16 x, y;
+		} white_point;
+	/**
+	 * @max_display_mastering_luminance: Max Mastering Display Luminance.
+	 * This value is coded as an unsigned 16-bit value in units of 1 cd/m2,
+	 * where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2.
+	 */
+	__u16 max_display_mastering_luminance;
+	/**
+	 * @min_display_mastering_luminance: Min Mastering Display Luminance.
+	 * This value is coded as an unsigned 16-bit value in units of
+	 * 0.0001 cd/m2, where 0x0001 represents 0.0001 cd/m2 and 0xFFFF
+	 * represents 6.5535 cd/m2.
+	 */
+	__u16 min_display_mastering_luminance;
+	/**
+	 * @max_cll: Max Content Light Level.
+	 * This value is coded as an unsigned 16-bit value in units of 1 cd/m2,
+	 * where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2.
+	 */
+	__u16 max_cll;
+	/**
+	 * @max_fall: Max Frame Average Light Level.
+	 * This value is coded as an unsigned 16-bit value in units of 1 cd/m2,
+	 * where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2.
+	 */
+	__u16 max_fall;
+};
+
+/**
+ * struct hdr_output_metadata - HDR output metadata
+ *
+ * Metadata Information to be passed from userspace
+ */
+struct hdr_output_metadata {
+	/**
+	 * @metadata_type: Static_Metadata_Descriptor_ID.
+	 */
+	__u32 metadata_type;
+	/**
+	 * @hdmi_metadata_type1: HDR Metadata Infoframe.
+	 */
+	union {
+		struct hdr_metadata_infoframe hdmi_metadata_type1;
+	};
+};
+
 #define DRM_MODE_PAGE_FLIP_EVENT 0x01
 #define DRM_MODE_PAGE_FLIP_ASYNC 0x02
 #define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
@@ -803,6 +898,10 @@ struct drm_format_modifier {
 };
 
 /**
+ * struct drm_mode_create_blob - Create New block property
+ * @data: Pointer to data to copy.
+ * @length: Length of data to copy.
+ * @blob_id: new property ID.
  * Create a new 'blob' data property, copying length bytes from data pointer,
  * and returning new blob ID.
  */
@@ -816,6 +915,8 @@ struct drm_mode_create_blob {
 };
 
 /**
+ * struct drm_mode_destroy_blob - Destroy user blob
+ * @blob_id: blob_id to destroy
  * Destroy a user-created blob property.
  */
 struct drm_mode_destroy_blob {
@@ -823,6 +924,12 @@ struct drm_mode_destroy_blob {
 };
 
 /**
+ * struct drm_mode_create_lease - Create lease
+ * @object_ids: Pointer to array of object ids.
+ * @object_count: Number of object ids.
+ * @flags: flags for new FD.
+ * @lessee_id: unique identifier for lessee.
+ * @fd: file descriptor to new drm_master file.
  * Lease mode resources, creating another drm_master.
  */
 struct drm_mode_create_lease {
@@ -840,6 +947,10 @@ struct drm_mode_create_lease {
 };
 
 /**
+ * struct drm_mode_list_lessees - List lessees
+ * @count_lessees: Number of lessees.
+ * @pad: pad.
+ * @lessees_ptr: Pointer to lessess.
  * List lesses from a drm_master
  */
 struct drm_mode_list_lessees {
@@ -860,6 +971,10 @@ struct drm_mode_list_lessees {
 };
 
 /**
+ * struct drm_mode_get_lease - Get Lease
+ * @count_objects: Number of leased objects.
+ * @pad: pad.
+ * @objects_ptr: Pointer to objects.
  * Get leased objects
  */
 struct drm_mode_get_lease {
@@ -880,6 +995,8 @@ struct drm_mode_get_lease {
 };
 
 /**
+ * struct drm_mode_revoke_lease - Revoke lease
+ * @lessee_id: Unique ID of lessee.
  * Revoke lease
  */
 struct drm_mode_revoke_lease {
-- 
2.24.1

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[igt-dev] [PATCH i-g-t 2/7] lib/igt_kms: Add max bpc connector property

[Swati Sharma]

From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>

It's been in DRM for a while but was never added to IGT's internal list.

This property should be reset along with other properties between tests
since output color depth can affect CRC calculation... but it's not
really feasible since it's driver specific for what the value should
be reset to.

v2: rebase
v3: rebase

Cc: Leo Li <sunpeng.li@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 lib/igt_kms.c | 1 +
 lib/igt_kms.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index d20daaad..b0b064c9 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -416,6 +416,7 @@ const char * const igt_connector_prop_names[IGT_NUM_CONNECTOR_PROPS] = {
 	[IGT_CONNECTOR_VRR_CAPABLE] = "vrr_capable",
 	[IGT_CONNECTOR_HDCP_CONTENT_TYPE] = "HDCP Content Type",
 	[IGT_CONNECTOR_LINK_STATUS] = "link-status",
+	[IGT_CONNECTOR_MAX_BPC] = "max bpc",
 };
 
 /*
diff --git a/lib/igt_kms.h b/lib/igt_kms.h
index 6c919e92..36077d41 100644
--- a/lib/igt_kms.h
+++ b/lib/igt_kms.h
@@ -125,6 +125,7 @@ enum igt_atomic_connector_properties {
        IGT_CONNECTOR_VRR_CAPABLE,
        IGT_CONNECTOR_HDCP_CONTENT_TYPE,
        IGT_CONNECTOR_LINK_STATUS,
+       IGT_CONNECTOR_MAX_BPC,
        IGT_NUM_CONNECTOR_PROPS
 };
 
-- 
2.24.1

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[igt-dev] [PATCH i-g-t 3/7] lib/igt_kms: Add HDR_OUTPUT_METADATA connector property

[Swati Sharma]

From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>

...and also reset it when resetting outputs since that can definitely
affect CRC output on other tests when not reset.

v2: rebase
v3: rebase
v4: Updated doc for igt_display_reset [Petri]

Cc: Leo Li <sunpeng.li@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 lib/igt_kms.c | 6 ++++++
 lib/igt_kms.h | 1 +
 2 files changed, 7 insertions(+)

diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index b0b064c9..b636b86f 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -417,6 +417,7 @@ const char * const igt_connector_prop_names[IGT_NUM_CONNECTOR_PROPS] = {
 	[IGT_CONNECTOR_HDCP_CONTENT_TYPE] = "HDCP Content Type",
 	[IGT_CONNECTOR_LINK_STATUS] = "link-status",
 	[IGT_CONNECTOR_MAX_BPC] = "max bpc",
+	[IGT_CONNECTOR_HDR_OUTPUT_METADATA] = "HDR_OUTPUT_METADATA",
 };
 
 /*
@@ -1794,6 +1795,10 @@ static void igt_output_reset(igt_output_t *output)
 	if (igt_output_has_prop(output, IGT_CONNECTOR_CONTENT_PROTECTION))
 		igt_output_set_prop_enum(output, IGT_CONNECTOR_CONTENT_PROTECTION,
 					 "Undesired");
+
+	if (igt_output_has_prop(output, IGT_CONNECTOR_HDR_OUTPUT_METADATA))
+		igt_output_set_prop_value(output,
+					  IGT_CONNECTOR_HDR_OUTPUT_METADATA, 0);
 }
 
 /**
@@ -1807,6 +1812,7 @@ static void igt_output_reset(igt_output_t *output)
  * - %IGT_CONNECTOR_CRTC_ID
  * - %IGT_CONNECTOR_BROADCAST_RGB (if applicable)
  *   %IGT_CONNECTOR_CONTENT_PROTECTION (if applicable)
+ *   %IGT_CONNECTOR_HDR_OUTPUT_METADATA (if applicable)
  * - igt_output_override_mode() to default.
  *
  * For pipes:
diff --git a/lib/igt_kms.h b/lib/igt_kms.h
index 36077d41..4766bfce 100644
--- a/lib/igt_kms.h
+++ b/lib/igt_kms.h
@@ -126,6 +126,7 @@ enum igt_atomic_connector_properties {
        IGT_CONNECTOR_HDCP_CONTENT_TYPE,
        IGT_CONNECTOR_LINK_STATUS,
        IGT_CONNECTOR_MAX_BPC,
+       IGT_CONNECTOR_HDR_OUTPUT_METADATA,
        IGT_NUM_CONNECTOR_PROPS
 };
 
-- 
2.24.1

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[igt-dev] [PATCH i-g-t 4/7] tests/kms_hdr: Add bpc switch subtests

[Swati Sharma]

From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>

Add subtests to validate transitions between 8bpc and 10bpc. Test is
made compatible for both amd and intel drivers. The test requires
the "output_bpc" debugfs entry to read current and maximum bpc.
This is exposed by amd driver, however intel driver doesn't expose it,
so made that restriction to assert output bpc only for amd driver.

v2: -Limiting plane size to 512x512 since regression observed in hsw
     because of plane scaling restriction.
    -Minor alignment fix [Uma]

Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 tests/Makefile.sources |   1 +
 tests/kms_hdr.c        | 296 +++++++++++++++++++++++++++++++++++++++++
 tests/meson.build      |   1 +
 3 files changed, 298 insertions(+)
 create mode 100644 tests/kms_hdr.c

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 2893f9bc..e8fcddf5 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -55,6 +55,7 @@ TESTS_progs = \
 	kms_frontbuffer_tracking \
 	kms_getfb \
 	kms_hdmi_inject \
+	kms_hdr \
 	kms_invalid_dotclock \
 	kms_lease \
 	kms_legacy_colorkey \
diff --git a/tests/kms_hdr.c b/tests/kms_hdr.c
new file mode 100644
index 00000000..c48e43e9
--- /dev/null
+++ b/tests/kms_hdr.c
@@ -0,0 +1,296 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+#include <fcntl.h>
+#include <termios.h>
+#include <unistd.h>
+
+IGT_TEST_DESCRIPTION("Test HDR metadata interfaces and bpc switch");
+
+/* Test flags. */
+enum {
+	TEST_NONE = 0,
+	TEST_DPMS = 1 << 0,
+	TEST_SUSPEND = 1 << 1,
+};
+
+/* BPC connector state. */
+typedef struct output_bpc {
+	unsigned int current;
+	unsigned int maximum;
+} output_bpc_t;
+
+/* Common test data. */
+typedef struct data {
+	igt_display_t display;
+	igt_plane_t *primary;
+	igt_output_t *output;
+	igt_pipe_t *pipe;
+	igt_pipe_crc_t *pipe_crc;
+	drmModeModeInfo *mode;
+	enum pipe pipe_id;
+	int fd;
+	int w;
+	int h;
+} data_t;
+
+/* Common test cleanup. */
+static void test_fini(data_t *data)
+{
+	igt_pipe_crc_free(data->pipe_crc);
+	igt_display_reset(&data->display);
+}
+
+static void test_cycle_flags(data_t *data, uint32_t test_flags)
+{
+	if (test_flags & TEST_DPMS) {
+		kmstest_set_connector_dpms(data->fd,
+					   data->output->config.connector,
+					   DRM_MODE_DPMS_OFF);
+		kmstest_set_connector_dpms(data->fd,
+					   data->output->config.connector,
+					   DRM_MODE_DPMS_ON);
+	}
+
+	if (test_flags & TEST_SUSPEND)
+		igt_system_suspend_autoresume(SUSPEND_STATE_MEM,
+					      SUSPEND_TEST_NONE);
+}
+
+/* Returns the current and maximum bpc from the connector debugfs. */
+static output_bpc_t get_output_bpc(data_t *data)
+{
+	char buf[256];
+	char *start_loc;
+	int fd, res;
+	output_bpc_t info;
+
+	fd = igt_debugfs_connector_dir(data->fd, data->output->name, O_RDONLY);
+	igt_assert(fd >= 0);
+
+	res = igt_debugfs_simple_read(fd, "output_bpc", buf, sizeof(buf));
+
+	igt_require(res > 0);
+
+	close(fd);
+
+	igt_assert(start_loc = strstr(buf, "Current: "));
+	igt_assert_eq(sscanf(start_loc, "Current: %u", &info.current), 1);
+
+	igt_assert(start_loc = strstr(buf, "Maximum: "));
+	igt_assert_eq(sscanf(start_loc, "Maximum: %u", &info.maximum), 1);
+
+	return info;
+}
+
+/* Verifies that connector has the correct output bpc. */
+static void assert_output_bpc(data_t *data, unsigned int bpc)
+{
+	output_bpc_t info = get_output_bpc(data);
+
+	igt_require_f(info.maximum >= bpc,
+		      "Monitor doesn't support %u bpc, max is %u\n", bpc,
+		      info.maximum);
+
+	igt_assert_eq(info.current, bpc);
+}
+
+/* Fills the FB with a test HDR pattern. */
+static void draw_hdr_pattern(igt_fb_t *fb)
+{
+	cairo_t *cr = igt_get_cairo_ctx(fb->fd, fb);
+
+	igt_paint_color(cr, 0, 0, fb->width, fb->height, 1.0, 1.0, 1.0);
+	igt_paint_test_pattern(cr, fb->width, fb->height);
+
+	igt_put_cairo_ctx(fb->fd, fb, cr);
+}
+
+/* Prepare test data. */
+static void prepare_test(data_t *data, igt_output_t *output, enum pipe pipe)
+{
+	igt_display_t *display = &data->display;
+
+	data->pipe_id = pipe;
+	data->pipe = &data->display.pipes[data->pipe_id];
+	igt_assert(data->pipe);
+
+	igt_display_reset(display);
+
+	data->output = output;
+	igt_assert(data->output);
+
+	data->mode = igt_output_get_mode(data->output);
+	igt_assert(data->mode);
+
+	data->primary =
+		igt_pipe_get_plane_type(data->pipe, DRM_PLANE_TYPE_PRIMARY);
+
+	data->pipe_crc = igt_pipe_crc_new(data->fd, data->pipe_id,
+					  INTEL_PIPE_CRC_SOURCE_AUTO);
+
+	igt_output_set_pipe(data->output, data->pipe_id);
+
+	data->w = data->mode->hdisplay;
+	data->h = data->mode->vdisplay;
+}
+
+static bool igt_pipe_is_free(igt_display_t *display, enum pipe pipe)
+{
+	int i;
+
+	for (i = 0; i < display->n_outputs; i++)
+		if (display->outputs[i].pending_pipe == pipe)
+			return false;
+
+	return true;
+}
+
+static void test_bpc_switch_on_output(data_t *data, igt_output_t *output,
+				      uint32_t flags)
+{
+	igt_display_t *display = &data->display;
+	igt_crc_t ref_crc, new_crc;
+	enum pipe pipe;
+	igt_fb_t afb;
+	int afb_id;
+
+	for_each_pipe(display, pipe) {
+		if (!igt_pipe_connector_valid(pipe, output))
+			continue;
+
+		/*
+		 * If previous subtest of connector failed, pipe
+		 * attached to that connector is not released.
+		 * Because of that we have to choose the non
+		 * attached pipe for this subtest.
+		 */
+		if (!igt_pipe_is_free(display, pipe))
+			continue;
+
+		prepare_test(data, output, pipe);
+
+		/* 10-bit formats are slow, so limit the size. */
+		afb_id = igt_create_fb(data->fd, 512, 512, DRM_FORMAT_XRGB2101010, 0, &afb);
+		igt_assert(afb_id);
+
+		draw_hdr_pattern(&afb);
+
+		/* Start in 8bpc. */
+		igt_plane_set_fb(data->primary, &afb);
+		/*
+		 * Limiting plane size aswell, since most of gen7 and all of
+		 * gen8 doesn't support plane scaling at all.
+		 */
+		igt_plane_set_size(data->primary, 512, 512);
+		igt_output_set_prop_value(data->output, IGT_CONNECTOR_MAX_BPC, 8);
+		igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
+		/*
+		 * i915 driver doesn't expose max bpc as debugfs entry,
+		 * so limiting assert only for amd driver.
+		 */
+		if (is_amdgpu_device(data->fd))
+			assert_output_bpc(data, 8);
+
+		/* Switch to 10bpc. */
+		igt_output_set_prop_value(data->output, IGT_CONNECTOR_MAX_BPC, 10);
+		igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
+		if (is_amdgpu_device(data->fd))
+			assert_output_bpc(data, 10);
+
+		/* Verify that the CRC are equal after DPMS or suspend. */
+		igt_pipe_crc_collect_crc(data->pipe_crc, &ref_crc);
+		test_cycle_flags(data, flags);
+		igt_pipe_crc_collect_crc(data->pipe_crc, &new_crc);
+
+		/* Drop back to 8bpc. */
+		igt_output_set_prop_value(data->output, IGT_CONNECTOR_MAX_BPC, 8);
+		igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
+		if (is_amdgpu_device(data->fd))
+			assert_output_bpc(data, 8);
+
+		/* CRC capture is clamped to 8bpc, so capture should match. */
+		igt_assert_crc_equal(&ref_crc, &new_crc);
+
+		test_fini(data);
+		igt_remove_fb(data->fd, &afb);
+
+		/*
+		 * Testing a output with a pipe is enough for HDR
+		 * testing. No ROI in testing the connector with other
+		 * pipes. So break the loop on pipe.
+		 */
+		break;
+	}
+}
+
+/* Returns true if an output supports max bpc property */
+static bool has_max_bpc(igt_output_t *output)
+{
+	return igt_output_has_prop(output, IGT_CONNECTOR_MAX_BPC) &&
+	       igt_output_get_prop(output, IGT_CONNECTOR_MAX_BPC);
+}
+
+static void test_bpc_switch(data_t *data, uint32_t flags)
+{
+	igt_output_t *output;
+	int valid_tests = 0;
+
+	for_each_connected_output(&data->display, output) {
+		if (!has_max_bpc(output))
+			continue;
+
+		igt_info("BPC switch test execution on %s\n", output->name);
+		test_bpc_switch_on_output(data, output, flags);
+		valid_tests++;
+	}
+
+	igt_require_f(valid_tests, "No connector found with MAX BPC connector property\n");
+}
+
+igt_main
+{
+	data_t data = { 0 };
+
+	igt_fixture {
+		data.fd = drm_open_driver_master(DRIVER_AMDGPU | DRIVER_INTEL);
+
+		kmstest_set_vt_graphics_mode();
+
+		igt_display_require(&data.display, data.fd);
+		igt_require(data.display.is_atomic);
+
+		igt_display_require_output(&data.display);
+	}
+
+	igt_describe("Tests switching between different display output bpc modes");
+	igt_subtest("bpc-switch") test_bpc_switch(&data, TEST_NONE);
+	igt_describe("Tests bpc switch with dpms");
+	igt_subtest("bpc-switch-dpms") test_bpc_switch(&data, TEST_DPMS);
+	igt_describe("Tests bpc switch with suspend");
+	igt_subtest("bpc-switch-suspend") test_bpc_switch(&data, TEST_SUSPEND);
+
+	igt_fixture {
+		igt_display_fini(&data.display);
+	}
+}
diff --git a/tests/meson.build b/tests/meson.build
index d931cc37..eed5e38f 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -39,6 +39,7 @@ test_progs = [
 	'kms_frontbuffer_tracking',
 	'kms_getfb',
 	'kms_hdmi_inject',
+	'kms_hdr',
 	'kms_invalid_dotclock',
 	'kms_lease',
 	'kms_legacy_colorkey',
-- 
2.24.1

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[igt-dev] [PATCH i-g-t 5/7] tests/kms_hdr: Add function to check HDR panel

[Swati Sharma]

EDID of connected panel needs to be parsed to detect whether
panel can drive hdr or not. Added new function is_panel_hdr(),
to know about hdr capabilities of panel. If panel supports hdr
then only tests will get executed else skipped.

v2: continue instead of break [Kunal]

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Suggested-by: Kunal Joshi <kunal1.joshi@intel.com>
---
 tests/kms_hdr.c | 87 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 87 insertions(+)

diff --git a/tests/kms_hdr.c b/tests/kms_hdr.c
index c48e43e9..5615ac35 100644
--- a/tests/kms_hdr.c
+++ b/tests/kms_hdr.c
@@ -24,9 +24,22 @@
 #include <fcntl.h>
 #include <termios.h>
 #include <unistd.h>
+#include "igt_edid.h"
 
 IGT_TEST_DESCRIPTION("Test HDR metadata interfaces and bpc switch");
 
+/* HDR EDID parsing. */
+#define CTA_EXTENSION_VERSION		0x03
+#define HDR_STATIC_METADATA_BLOCK       0x06
+#define USE_EXTENDED_TAG		0x07
+
+/* DRM HDR definitions. Not in the UAPI header, unfortunately. */
+enum hdmi_eotf {
+	HDMI_EOTF_TRADITIONAL_GAMMA_SDR,
+	HDMI_EOTF_TRADITIONAL_GAMMA_HDR,
+	HDMI_EOTF_SMPTE_ST2084,
+};
+
 /* Test flags. */
 enum {
 	TEST_NONE = 0,
@@ -268,6 +281,80 @@ static void test_bpc_switch(data_t *data, uint32_t flags)
 	igt_require_f(valid_tests, "No connector found with MAX BPC connector property\n");
 }
 
+static bool cta_block(const char *edid_ext)
+{
+	/*
+	 * Byte 1: 0x07 indicates Extended Tag
+	 * Byte 2: 0x06 indicates HDMI Static Metadata Block
+	 * Byte 3: bits 0 to 5 identify EOTF functions supported by sink
+	 *	       where ET_0: Traditional Gamma - SDR Luminance Range
+	 *	             ET_1: Traditional Gamma - HDR Luminance Range
+	 *	             ET_2: SMPTE ST 2084
+	 *	             ET_3: Hybrid Log-Gamma (HLG)
+	 *	             ET_4 to ET_5: Reserved for future use
+	 */
+
+	if ((((edid_ext[0] & 0xe0) >> 5 == USE_EXTENDED_TAG) &&
+	      (edid_ext[1] == HDR_STATIC_METADATA_BLOCK)) &&
+	     ((edid_ext[2] & HDMI_EOTF_TRADITIONAL_GAMMA_HDR) ||
+	      (edid_ext[2] & HDMI_EOTF_SMPTE_ST2084)))
+			return true;
+
+	return false;
+}
+
+/* Returns true if panel supports hdr */
+static bool is_panel_hdr(data_t *data, igt_output_t *output)
+{
+	bool ok;
+	int i, j, offset;
+	uint64_t edid_blob_id;
+	drmModePropertyBlobRes *edid_blob;
+	const struct edid_ext *edid_ext;
+	const struct edid *edid;
+	const struct edid_cea *edid_cea;
+	const char *cea_data;
+	bool ret = false;
+
+	ok = kmstest_get_property(data->fd, output->id,
+			DRM_MODE_OBJECT_CONNECTOR, "EDID",
+			NULL, &edid_blob_id, NULL);
+
+	if (!ok || !edid_blob_id)
+		return ret;
+
+	edid_blob = drmModeGetPropertyBlob(data->fd, edid_blob_id);
+	igt_assert(edid_blob);
+
+	edid = (const struct edid *) edid_blob->data;
+	igt_assert(edid);
+
+	drmModeFreePropertyBlob(edid_blob);
+
+	for (i = 0; i < edid->extensions_len; i++) {
+		edid_ext = &edid->extensions[i];
+		edid_cea = &edid_ext->data.cea;
+
+		/* HDR not defined in CTA Extension Version < 3 */
+		if ((edid_ext->tag != EDID_EXT_CEA) ||
+		    (edid_cea->revision != CTA_EXTENSION_VERSION))
+				continue;
+		else {
+			offset = edid_cea->dtd_start;
+			cea_data = edid_cea->data;
+
+			for (j = 0; j < offset; j += (cea_data[j] & 0x1f) + 1) {
+				ret = cta_block(cea_data + j);
+
+				if (ret)
+					break;
+			}
+		}
+	}
+
+	return ret;
+}
+
 igt_main
 {
 	data_t data = { 0 };
-- 
2.24.1

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[igt-dev] [PATCH i-g-t 6/7] tests/kms_hdr: Add static toggle SDR->HDR mode subtests

[Swati Sharma]

From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>

Add subtests to toggle between SDR to HDR mode with suspend
and dpms scenarios. Tests are made compatible for both amd
and intel drivers.

v2: Added additional check to validate whether panel is
    HDR or not. If it's a non-HDR panel, test will skip [Uma]

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
---
 tests/kms_hdr.c | 163 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 163 insertions(+)

diff --git a/tests/kms_hdr.c b/tests/kms_hdr.c
index 5615ac35..c604fdc6 100644
--- a/tests/kms_hdr.c
+++ b/tests/kms_hdr.c
@@ -34,6 +34,10 @@ IGT_TEST_DESCRIPTION("Test HDR metadata interfaces and bpc switch");
 #define USE_EXTENDED_TAG		0x07
 
 /* DRM HDR definitions. Not in the UAPI header, unfortunately. */
+enum hdmi_metadata_type {
+	HDMI_STATIC_METADATA_TYPE1 = 1,
+};
+
 enum hdmi_eotf {
 	HDMI_EOTF_TRADITIONAL_GAMMA_SDR,
 	HDMI_EOTF_TRADITIONAL_GAMMA_HDR,
@@ -355,6 +359,158 @@ static bool is_panel_hdr(data_t *data, igt_output_t *output)
 	return ret;
 }
 
+/* Sets the HDR output metadata prop. */
+static void set_hdr_output_metadata(data_t *data,
+				    struct hdr_output_metadata const *meta)
+{
+	igt_output_replace_prop_blob(data->output,
+				     IGT_CONNECTOR_HDR_OUTPUT_METADATA, meta,
+				     meta ? sizeof(*meta) : 0);
+}
+
+/* Converts a double to 861-G spec FP format. */
+static uint16_t calc_hdr_float(double val)
+{
+	return (uint16_t)(val * 50000.0);
+}
+
+/* Fills some test values for ST2048 HDR output metadata.
+ *
+ * Note: there isn't really a standard for what the metadata is supposed
+ * to do on the display side of things. The display is free to ignore it
+ * and clip the output, use it to help tonemap to the content range,
+ * or do anything they want, really.
+ */
+static void fill_hdr_output_metadata_st2048(struct hdr_output_metadata *meta)
+{
+	memset(meta, 0, sizeof(*meta));
+
+	meta->metadata_type = HDMI_STATIC_METADATA_TYPE1;
+	meta->hdmi_metadata_type1.eotf = HDMI_EOTF_SMPTE_ST2084;
+
+	/* Rec. 2020 */
+	meta->hdmi_metadata_type1.display_primaries[0].x =
+		calc_hdr_float(0.708); /* Red */
+	meta->hdmi_metadata_type1.display_primaries[0].y =
+		calc_hdr_float(0.292);
+	meta->hdmi_metadata_type1.display_primaries[1].x =
+		calc_hdr_float(0.170); /* Green */
+	meta->hdmi_metadata_type1.display_primaries[1].y =
+		calc_hdr_float(0.797);
+	meta->hdmi_metadata_type1.display_primaries[2].x =
+		calc_hdr_float(0.131); /* Blue */
+	meta->hdmi_metadata_type1.display_primaries[2].y =
+		calc_hdr_float(0.046);
+	meta->hdmi_metadata_type1.white_point.x = calc_hdr_float(0.3127);
+	meta->hdmi_metadata_type1.white_point.y = calc_hdr_float(0.3290);
+
+	meta->hdmi_metadata_type1.max_display_mastering_luminance =
+		1000; /* 1000 nits */
+	meta->hdmi_metadata_type1.min_display_mastering_luminance =
+		500;				   /* 0.05 nits */
+	meta->hdmi_metadata_type1.max_fall = 1000; /* 1000 nits */
+	meta->hdmi_metadata_type1.max_cll = 500;   /* 500 nits */
+}
+
+static void test_static_toggle(data_t *data, igt_output_t *output,
+			       uint32_t flags)
+{
+	igt_display_t *display = &data->display;
+	struct hdr_output_metadata hdr;
+	igt_crc_t ref_crc, new_crc;
+	enum pipe pipe;
+	igt_fb_t afb;
+	int afb_id;
+
+	for_each_pipe(display, pipe) {
+		if (!igt_pipe_connector_valid(pipe, output))
+			continue;
+
+		if (!igt_pipe_is_free(display, pipe))
+			continue;
+
+		prepare_test(data, output, pipe);
+
+		/* 10-bit formats are slow, so limit the size. */
+		afb_id = igt_create_fb(data->fd, 512, 512, DRM_FORMAT_XRGB2101010, 0, &afb);
+		igt_assert(afb_id);
+
+		draw_hdr_pattern(&afb);
+
+		fill_hdr_output_metadata_st2048(&hdr);
+
+		/* Start with no metadata. */
+		igt_plane_set_fb(data->primary, &afb);
+		igt_plane_set_size(data->primary, data->w, data->h);
+		set_hdr_output_metadata(data, NULL);
+		igt_output_set_prop_value(data->output, IGT_CONNECTOR_MAX_BPC, 8);
+		igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
+		if (is_amdgpu_device(data->fd))
+			assert_output_bpc(data, 8);
+
+		/* Apply HDR metadata and 10bpc. We expect a modeset for entering. */
+		set_hdr_output_metadata(data, &hdr);
+		igt_output_set_prop_value(data->output, IGT_CONNECTOR_MAX_BPC, 10);
+		igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
+		if (is_amdgpu_device(data->fd))
+			assert_output_bpc(data, 10);
+
+		/* Verify that the CRC are equal after DPMS or suspend. */
+		igt_pipe_crc_collect_crc(data->pipe_crc, &ref_crc);
+		test_cycle_flags(data, flags);
+		igt_pipe_crc_collect_crc(data->pipe_crc, &new_crc);
+
+		/* Disable HDR metadata and drop back to 8bpc. We expect a modeset for exiting. */
+		set_hdr_output_metadata(data, NULL);
+		igt_output_set_prop_value(data->output, IGT_CONNECTOR_MAX_BPC, 8);
+		igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
+		if (is_amdgpu_device(data->fd))
+			assert_output_bpc(data, 8);
+
+		igt_assert_crc_equal(&ref_crc, &new_crc);
+
+		test_fini(data);
+		igt_remove_fb(data->fd, &afb);
+
+		break;
+	}
+}
+
+/* Returns true if an output supports hdr metadata property */
+static bool has_hdr(igt_output_t *output)
+{
+	return igt_output_has_prop(output, IGT_CONNECTOR_HDR_OUTPUT_METADATA);
+}
+
+static void test_hdr(data_t *data, const char *test_name, uint32_t flags)
+{
+	igt_output_t *output;
+	int valid_tests = 0;
+
+	for_each_connected_output(&data->display, output) {
+		/* To test HDR, 10 bpc is required, so we need to
+		 * set MAX_BPC property to 10bpc prior to setting
+		 * HDR metadata property. Therefore, checking.
+		 */
+		if (!has_max_bpc(output))
+			continue;
+
+		if (!has_hdr(output))
+			continue;
+
+		if (!is_panel_hdr(data, output))
+			continue;
+
+		igt_info("HDR %s test execution on %s\n", test_name, output->name);
+		if (flags & TEST_NONE || flags & TEST_DPMS || flags & TEST_SUSPEND)
+			test_static_toggle(data, output, flags);
+		valid_tests++;
+	}
+
+	igt_require_f(valid_tests, "No connector found with HDR metadata/MAX BPC\
+				    connector property/panel is Non-HDR\n");
+}
+
 igt_main
 {
 	data_t data = { 0 };
@@ -377,6 +533,13 @@ igt_main
 	igt_describe("Tests bpc switch with suspend");
 	igt_subtest("bpc-switch-suspend") test_bpc_switch(&data, TEST_SUSPEND);
 
+	igt_describe("Tests entering and exiting HDR mode");
+	igt_subtest("static-toggle") test_hdr(&data, "static-toggle", TEST_NONE);
+	igt_describe("Tests static toggle with dpms");
+	igt_subtest("static-toggle-dpms") test_hdr(&data, "static-toggle-dpms", TEST_DPMS);
+	igt_describe("Tests static toggle with suspend");
+	igt_subtest("static-toggle-suspend") test_hdr(&data, "static-toggle-suspend", TEST_SUSPEND);
+
 	igt_fixture {
 		igt_display_fini(&data.display);
 	}
-- 
2.24.1

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[igt-dev] [PATCH i-g-t 7/7] tests/kms_hdr: Add subtest to swap static HDR metadata

[Swati Sharma]

From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>

Add subtest to enable fast static metadata switches.

v2: Allow modeset for intel driver [Uma]

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
 tests/kms_hdr.c | 109 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 109 insertions(+)

diff --git a/tests/kms_hdr.c b/tests/kms_hdr.c
index c604fdc6..cca08fcb 100644
--- a/tests/kms_hdr.c
+++ b/tests/kms_hdr.c
@@ -49,6 +49,7 @@ enum {
 	TEST_NONE = 0,
 	TEST_DPMS = 1 << 0,
 	TEST_SUSPEND = 1 << 1,
+	TEST_SWAP = 1 << 2,
 };
 
 /* BPC connector state. */
@@ -476,6 +477,110 @@ static void test_static_toggle(data_t *data, igt_output_t *output,
 	}
 }
 
+/* Fills some test values for HDR metadata targeting SDR. */
+static void fill_hdr_output_metadata_sdr(struct hdr_output_metadata *meta)
+{
+	memset(meta, 0, sizeof(*meta));
+
+	meta->metadata_type = HDMI_STATIC_METADATA_TYPE1;
+	meta->hdmi_metadata_type1.eotf = HDMI_EOTF_TRADITIONAL_GAMMA_SDR;
+
+	/* Rec. 709 */
+	meta->hdmi_metadata_type1.display_primaries[0].x =
+		calc_hdr_float(0.640); /* Red */
+	meta->hdmi_metadata_type1.display_primaries[0].y =
+		calc_hdr_float(0.330);
+	meta->hdmi_metadata_type1.display_primaries[1].x =
+		calc_hdr_float(0.300); /* Green */
+	meta->hdmi_metadata_type1.display_primaries[1].y =
+		calc_hdr_float(0.600);
+	meta->hdmi_metadata_type1.display_primaries[2].x =
+		calc_hdr_float(0.150); /* Blue */
+	meta->hdmi_metadata_type1.display_primaries[2].y =
+		calc_hdr_float(0.006);
+	meta->hdmi_metadata_type1.white_point.x = calc_hdr_float(0.3127);
+	meta->hdmi_metadata_type1.white_point.y = calc_hdr_float(0.3290);
+
+	meta->hdmi_metadata_type1.max_display_mastering_luminance = 0;
+	meta->hdmi_metadata_type1.min_display_mastering_luminance = 0;
+	meta->hdmi_metadata_type1.max_fall = 0;
+	meta->hdmi_metadata_type1.max_cll = 0;
+}
+
+static void test_static_swap(data_t *data, igt_output_t *output)
+{
+	igt_display_t *display = &data->display;
+	igt_crc_t ref_crc, new_crc;
+	enum pipe pipe;
+	igt_fb_t afb;
+	int afb_id;
+	struct hdr_output_metadata hdr;
+
+	for_each_pipe(display, pipe) {
+		if (!igt_pipe_connector_valid(pipe, output))
+			continue;
+
+		if (!igt_pipe_is_free(display, pipe))
+			continue;
+
+		prepare_test(data, output, pipe);
+
+		/* 10-bit formats are slow, so limit the size. */
+		afb_id = igt_create_fb(data->fd, 512, 512, DRM_FORMAT_XRGB2101010, 0, &afb);
+		igt_assert(afb_id);
+
+		draw_hdr_pattern(&afb);
+
+		/* Start in SDR. */
+		igt_plane_set_fb(data->primary, &afb);
+		igt_plane_set_size(data->primary, data->w, data->h);
+		igt_output_set_prop_value(data->output, IGT_CONNECTOR_MAX_BPC, 8);
+		igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
+		if (is_amdgpu_device(data->fd))
+			assert_output_bpc(data, 8);
+
+		/* Enter HDR, a modeset is allowed here. */
+		fill_hdr_output_metadata_st2048(&hdr);
+		set_hdr_output_metadata(data, &hdr);
+		igt_output_set_prop_value(data->output, IGT_CONNECTOR_MAX_BPC, 10);
+		igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
+		if (is_amdgpu_device(data->fd))
+			assert_output_bpc(data, 10);
+
+		igt_pipe_crc_collect_crc(data->pipe_crc, &ref_crc);
+
+		/* Change the mastering information, no modeset allowed. */
+		hdr.hdmi_metadata_type1.max_display_mastering_luminance = 200;
+		hdr.hdmi_metadata_type1.max_fall = 200;
+		hdr.hdmi_metadata_type1.max_cll = 100;
+
+		set_hdr_output_metadata(data, &hdr);
+		igt_display_commit_atomic(display, 0, NULL);
+
+		/* Enter SDR via metadata, no modeset allowed. */
+		fill_hdr_output_metadata_sdr(&hdr);
+		set_hdr_output_metadata(data, &hdr);
+		igt_display_commit_atomic(display, 0, NULL);
+
+		igt_pipe_crc_collect_crc(data->pipe_crc, &new_crc);
+
+		/* Exit SDR and enter 8bpc, cleanup. */
+		set_hdr_output_metadata(data, NULL);
+		igt_output_set_prop_value(data->output, IGT_CONNECTOR_MAX_BPC, 8);
+		igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
+		if (is_amdgpu_device(data->fd))
+			assert_output_bpc(data, 8);
+
+		/* Verify that the CRC didn't change while cycling metadata. */
+		igt_assert_crc_equal(&ref_crc, &new_crc);
+
+		test_fini(data);
+		igt_remove_fb(data->fd, &afb);
+
+		break;
+	}
+}
+
 /* Returns true if an output supports hdr metadata property */
 static bool has_hdr(igt_output_t *output)
 {
@@ -504,6 +609,8 @@ static void test_hdr(data_t *data, const char *test_name, uint32_t flags)
 		igt_info("HDR %s test execution on %s\n", test_name, output->name);
 		if (flags & TEST_NONE || flags & TEST_DPMS || flags & TEST_SUSPEND)
 			test_static_toggle(data, output, flags);
+		if (flags & TEST_SWAP)
+			test_static_swap(data, output);
 		valid_tests++;
 	}
 
@@ -540,6 +647,8 @@ igt_main
 	igt_describe("Tests static toggle with suspend");
 	igt_subtest("static-toggle-suspend") test_hdr(&data, "static-toggle-suspend", TEST_SUSPEND);
 
+	igt_describe("Tests swapping static HDR metadata");
+	igt_subtest("static-swap") test_hdr(&data, "static-swap", TEST_SWAP);
 	igt_fixture {
 		igt_display_fini(&data.display);
 	}
-- 
2.24.1

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[igt-dev] ✓ Fi.CI.BAT: success for Add tests for HDR metadata interfaces and bpc switch (rev3)

[Patchwork]

== Series Details ==

Series: Add tests for HDR metadata interfaces and bpc switch (rev3)
URL   : https://patchwork.freedesktop.org/series/71524/
State : success

== Summary ==

CI Bug Log - changes from IGT_5396 -> IGTPW_4024
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/index.html

Known issues
------------

  Here are the changes found in IGTPW_4024 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_parallel@fds:
    - fi-byt-n2820:       [PASS][1] -> [TIMEOUT][2] ([fdo#112271])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/fi-byt-n2820/igt@gem_exec_parallel@fds.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/fi-byt-n2820/igt@gem_exec_parallel@fds.html

  * igt@i915_module_load@reload-with-fault-injection:
    - fi-icl-guc:         [PASS][3] -> [DMESG-WARN][4] ([i915#109])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/fi-icl-guc/igt@i915_module_load@reload-with-fault-injection.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/fi-icl-guc/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_selftest@live_gem_contexts:
    - fi-byt-n2820:       [PASS][5] -> [DMESG-FAIL][6] ([i915#722])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html

  * igt@i915_selftest@live_gt_heartbeat:
    - fi-bsw-n3050:       [PASS][7] -> [DMESG-FAIL][8] ([i915#541])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/fi-bsw-n3050/igt@i915_selftest@live_gt_heartbeat.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/fi-bsw-n3050/igt@i915_selftest@live_gt_heartbeat.html

  
#### Possible fixes ####

  * igt@i915_selftest@live_blt:
    - fi-hsw-4770r:       [DMESG-FAIL][9] ([i915#725]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/fi-hsw-4770r/igt@i915_selftest@live_blt.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/fi-hsw-4770r/igt@i915_selftest@live_blt.html
    - fi-ivb-3770:        [DMESG-FAIL][11] ([i915#563]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/fi-ivb-3770/igt@i915_selftest@live_blt.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/fi-ivb-3770/igt@i915_selftest@live_blt.html

  * igt@kms_chamelium@dp-edid-read:
    - fi-cml-u2:          [FAIL][13] ([i915#217]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/fi-cml-u2/igt@kms_chamelium@dp-edid-read.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/fi-cml-u2/igt@kms_chamelium@dp-edid-read.html

  
#### Warnings ####

  * igt@i915_selftest@live_blt:
    - fi-hsw-4770:        [DMESG-FAIL][15] ([i915#725]) -> [DMESG-FAIL][16] ([i915#553] / [i915#725])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/fi-hsw-4770/igt@i915_selftest@live_blt.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/fi-hsw-4770/igt@i915_selftest@live_blt.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
  [i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
  [i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217
  [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
  [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
  [i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563
  [i915#722]: https://gitlab.freedesktop.org/drm/intel/issues/722
  [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
  [i915#937]: https://gitlab.freedesktop.org/drm/intel/issues/937


Participating hosts (49 -> 37)
------------------------------

  Missing    (12): fi-ilk-m540 fi-byt-j1900 fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-snb-2520m fi-ctg-p8600 fi-gdg-551 fi-blb-e6850 fi-byt-clapper fi-bsw-nick fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5396 -> IGTPW_4024

  CI-20190529: 20190529
  CI_DRM_7833: 8210f0f999e2d396a8611e0cabc2f6c6a52468de @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_4024: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/index.html
  IGT_5396: b85f96d6aa71795684b14d3b3d4c752dd61ff62e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools



== Testlist changes ==

+igt@kms_hdr@bpc-switch
+igt@kms_hdr@bpc-switch-dpms
+igt@kms_hdr@bpc-switch-suspend
+igt@kms_hdr@static-swap
+igt@kms_hdr@static-toggle
+igt@kms_hdr@static-toggle-dpms
+igt@kms_hdr@static-toggle-suspend

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/index.html
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Re: [igt-dev] [PATCH i-g-t 5/7] tests/kms_hdr: Add function to check HDR panel

[Kunal Joshi]

On 2020-01-29 at 12:20:16 +0530, Swati Sharma wrote:
> EDID of connected panel needs to be parsed to detect whether
> panel can drive hdr or not. Added new function is_panel_hdr(),
> to know about hdr capabilities of panel. If panel supports hdr
> then only tests will get executed else skipped.
> 
> v2: continue instead of break [Kunal]
> 
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> Suggested-by: Kunal Joshi <kunal1.joshi@intel.com>
> ---
>  tests/kms_hdr.c | 87 +++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 87 insertions(+)
> 
> diff --git a/tests/kms_hdr.c b/tests/kms_hdr.c
> index c48e43e9..5615ac35 100644
> --- a/tests/kms_hdr.c
> +++ b/tests/kms_hdr.c
> @@ -24,9 +24,22 @@
>  #include <fcntl.h>
>  #include <termios.h>
>  #include <unistd.h>
> +#include "igt_edid.h"
>  
>  IGT_TEST_DESCRIPTION("Test HDR metadata interfaces and bpc switch");
>  
> +/* HDR EDID parsing. */
> +#define CTA_EXTENSION_VERSION		0x03
> +#define HDR_STATIC_METADATA_BLOCK       0x06
> +#define USE_EXTENDED_TAG		0x07
> +
> +/* DRM HDR definitions. Not in the UAPI header, unfortunately. */
> +enum hdmi_eotf {
> +	HDMI_EOTF_TRADITIONAL_GAMMA_SDR,
> +	HDMI_EOTF_TRADITIONAL_GAMMA_HDR,
> +	HDMI_EOTF_SMPTE_ST2084,
> +};
> +
>  /* Test flags. */
>  enum {
>  	TEST_NONE = 0,
> @@ -268,6 +281,80 @@ static void test_bpc_switch(data_t *data, uint32_t flags)
>  	igt_require_f(valid_tests, "No connector found with MAX BPC connector property\n");
>  }
>  
> +static bool cta_block(const char *edid_ext)
> +{
> +	/*
> +	 * Byte 1: 0x07 indicates Extended Tag
> +	 * Byte 2: 0x06 indicates HDMI Static Metadata Block
> +	 * Byte 3: bits 0 to 5 identify EOTF functions supported by sink
> +	 *	       where ET_0: Traditional Gamma - SDR Luminance Range
> +	 *	             ET_1: Traditional Gamma - HDR Luminance Range
> +	 *	             ET_2: SMPTE ST 2084
> +	 *	             ET_3: Hybrid Log-Gamma (HLG)
> +	 *	             ET_4 to ET_5: Reserved for future use
> +	 */
> +
> +	if ((((edid_ext[0] & 0xe0) >> 5 == USE_EXTENDED_TAG) &&
> +	      (edid_ext[1] == HDR_STATIC_METADATA_BLOCK)) &&
> +	     ((edid_ext[2] & HDMI_EOTF_TRADITIONAL_GAMMA_HDR) ||
> +	      (edid_ext[2] & HDMI_EOTF_SMPTE_ST2084)))
> +			return true;
> +
> +	return false;
> +}
> +
> +/* Returns true if panel supports hdr */
> +static bool is_panel_hdr(data_t *data, igt_output_t *output)
> +{
> +	bool ok;
> +	int i, j, offset;
> +	uint64_t edid_blob_id;
> +	drmModePropertyBlobRes *edid_blob;
> +	const struct edid_ext *edid_ext;
> +	const struct edid *edid;
> +	const struct edid_cea *edid_cea;
> +	const char *cea_data;
> +	bool ret = false;
> +
> +	ok = kmstest_get_property(data->fd, output->id,
> +			DRM_MODE_OBJECT_CONNECTOR, "EDID",
> +			NULL, &edid_blob_id, NULL);
> +
> +	if (!ok || !edid_blob_id)
> +		return ret;
> +
> +	edid_blob = drmModeGetPropertyBlob(data->fd, edid_blob_id);
> +	igt_assert(edid_blob);
> +
> +	edid = (const struct edid *) edid_blob->data;
> +	igt_assert(edid);
> +
> +	drmModeFreePropertyBlob(edid_blob);
> +
> +	for (i = 0; i < edid->extensions_len; i++) {
> +		edid_ext = &edid->extensions[i];
> +		edid_cea = &edid_ext->data.cea;
> +
> +		/* HDR not defined in CTA Extension Version < 3 */
> +		if ((edid_ext->tag != EDID_EXT_CEA) ||
> +		    (edid_cea->revision != CTA_EXTENSION_VERSION))
> +				continue;
> +		else {
> +			offset = edid_cea->dtd_start;
> +			cea_data = edid_cea->data;
> +
> +			for (j = 0; j < offset; j += (cea_data[j] & 0x1f) + 1) {
> +				ret = cta_block(cea_data + j);
> +
> +				if (ret)
> +					break;
> +			}
> +		}
> +	}
> +
> +	return ret;
> +}
> +
>  igt_main
>  {
>  	data_t data = { 0 };
> -- 
> 2.24.1
>
Reviewed-by: Kunal Joshi <kunal1.joshi@intel.com>
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[igt-dev] ✗ Fi.CI.IGT: failure for Add tests for HDR metadata interfaces and bpc switch (rev3)

[Patchwork]

== Series Details ==

Series: Add tests for HDR metadata interfaces and bpc switch (rev3)
URL   : https://patchwork.freedesktop.org/series/71524/
State : failure

== Summary ==

CI Bug Log - changes from IGT_5396_full -> IGTPW_4024_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_4024_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_4024_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_4024_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_exec_suspend@basic-s0:
    - shard-iclb:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-iclb5/igt@gem_exec_suspend@basic-s0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-iclb1/igt@gem_exec_suspend@basic-s0.html

  * {igt@kms_hdr@bpc-switch-dpms} (NEW):
    - shard-hsw:          NOTRUN -> [FAIL][3] +2 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-hsw5/igt@kms_hdr@bpc-switch-dpms.html

  * {igt@kms_hdr@static-toggle} (NEW):
    - shard-iclb:         NOTRUN -> [SKIP][4] +3 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-iclb1/igt@kms_hdr@static-toggle.html

  * {igt@kms_hdr@static-toggle-dpms} (NEW):
    - shard-tglb:         NOTRUN -> [SKIP][5] +3 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-tglb7/igt@kms_hdr@static-toggle-dpms.html

  
New tests
---------

  New tests have been introduced between IGT_5396_full and IGTPW_4024_full:

### New IGT tests (7) ###

  * igt@kms_hdr@bpc-switch:
    - Statuses : 1 fail(s) 5 pass(s)
    - Exec time: [0.65, 3.65] s

  * igt@kms_hdr@bpc-switch-dpms:
    - Statuses : 1 fail(s) 5 pass(s) 1 skip(s)
    - Exec time: [0.0, 4.82] s

  * igt@kms_hdr@bpc-switch-suspend:
    - Statuses : 1 fail(s) 5 pass(s) 1 skip(s)
    - Exec time: [0.0, 6.59] s

  * igt@kms_hdr@static-swap:
    - Statuses : 7 skip(s)
    - Exec time: [0.0, 0.00] s

  * igt@kms_hdr@static-toggle:
    - Statuses : 7 skip(s)
    - Exec time: [0.0, 0.00] s

  * igt@kms_hdr@static-toggle-dpms:
    - Statuses : 7 skip(s)
    - Exec time: [0.0, 0.00] s

  * igt@kms_hdr@static-toggle-suspend:
    - Statuses : 7 skip(s)
    - Exec time: [0.0, 0.00] s

  

Known issues
------------

  Here are the changes found in IGTPW_4024_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@rcs0-s3:
    - shard-kbl:          [PASS][6] -> [DMESG-WARN][7] ([i915#180]) +2 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-kbl1/igt@gem_ctx_isolation@rcs0-s3.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-kbl4/igt@gem_ctx_isolation@rcs0-s3.html

  * igt@gem_ctx_shared@exec-shared-gtt-blt:
    - shard-tglb:         [PASS][8] -> [FAIL][9] ([i915#616])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-tglb7/igt@gem_ctx_shared@exec-shared-gtt-blt.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-tglb3/igt@gem_ctx_shared@exec-shared-gtt-blt.html

  * igt@gem_exec_parallel@vcs1-fds:
    - shard-iclb:         [PASS][10] -> [SKIP][11] ([fdo#112080]) +7 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-iclb4/igt@gem_exec_parallel@vcs1-fds.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-iclb8/igt@gem_exec_parallel@vcs1-fds.html

  * igt@gem_exec_schedule@pi-distinct-iova-bsd:
    - shard-iclb:         [PASS][12] -> [SKIP][13] ([i915#677])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-iclb7/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-iclb2/igt@gem_exec_schedule@pi-distinct-iova-bsd.html

  * igt@gem_exec_schedule@preempt-other-chain-bsd:
    - shard-iclb:         [PASS][14] -> [SKIP][15] ([fdo#112146]) +4 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-iclb3/igt@gem_exec_schedule@preempt-other-chain-bsd.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-iclb4/igt@gem_exec_schedule@preempt-other-chain-bsd.html

  * igt@gem_partial_pwrite_pread@reads-snoop:
    - shard-hsw:          [PASS][16] -> [FAIL][17] ([i915#694])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-hsw8/igt@gem_partial_pwrite_pread@reads-snoop.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-hsw1/igt@gem_partial_pwrite_pread@reads-snoop.html

  * igt@i915_pm_rps@waitboost:
    - shard-iclb:         [PASS][18] -> [FAIL][19] ([i915#413])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-iclb8/igt@i915_pm_rps@waitboost.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-iclb2/igt@i915_pm_rps@waitboost.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-apl:          [PASS][20] -> [DMESG-WARN][21] ([i915#180]) +2 similar issues
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-apl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-xtiled:
    - shard-snb:          [PASS][22] -> [SKIP][23] ([fdo#109271])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-snb1/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-xtiled.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-snb2/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-xtiled.html

  * igt@kms_psr@psr2_primary_mmap_cpu:
    - shard-iclb:         [PASS][24] -> [SKIP][25] ([fdo#109441]) +1 similar issue
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-iclb5/igt@kms_psr@psr2_primary_mmap_cpu.html

  * igt@prime_mmap_coherency@ioctl-errors:
    - shard-hsw:          [PASS][26] -> [FAIL][27] ([i915#831])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-hsw8/igt@prime_mmap_coherency@ioctl-errors.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-hsw1/igt@prime_mmap_coherency@ioctl-errors.html

  * igt@prime_vgem@fence-wait-bsd2:
    - shard-iclb:         [PASS][28] -> [SKIP][29] ([fdo#109276]) +16 similar issues
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-iclb4/igt@prime_vgem@fence-wait-bsd2.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-iclb3/igt@prime_vgem@fence-wait-bsd2.html

  
#### Possible fixes ####

  * igt@gem_ctx_persistence@vcs1-cleanup:
    - shard-iclb:         [SKIP][30] ([fdo#109276] / [fdo#112080]) -> [PASS][31] +1 similar issue
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-iclb7/igt@gem_ctx_persistence@vcs1-cleanup.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-iclb4/igt@gem_ctx_persistence@vcs1-cleanup.html

  * igt@gem_ctx_shared@exec-shared-gtt-bsd:
    - shard-tglb:         [FAIL][32] ([i915#616]) -> [PASS][33]
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-tglb1/igt@gem_ctx_shared@exec-shared-gtt-bsd.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-tglb3/igt@gem_ctx_shared@exec-shared-gtt-bsd.html

  * igt@gem_ctx_shared@exec-single-timeline-bsd:
    - shard-iclb:         [SKIP][34] ([fdo#110841]) -> [PASS][35]
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-iclb6/igt@gem_ctx_shared@exec-single-timeline-bsd.html

  * igt@gem_exec_parallel@rcs0-fds:
    - shard-hsw:          [INCOMPLETE][36] ([i915#61]) -> [PASS][37]
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-hsw2/igt@gem_exec_parallel@rcs0-fds.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-hsw6/igt@gem_exec_parallel@rcs0-fds.html

  * igt@gem_exec_schedule@pi-shared-iova-bsd:
    - shard-iclb:         [SKIP][38] ([i915#677]) -> [PASS][39]
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-iclb2/igt@gem_exec_schedule@pi-shared-iova-bsd.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-iclb5/igt@gem_exec_schedule@pi-shared-iova-bsd.html

  * igt@gem_exec_schedule@preempt-bsd:
    - shard-iclb:         [SKIP][40] ([fdo#112146]) -> [PASS][41] +7 similar issues
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-iclb4/igt@gem_exec_schedule@preempt-bsd.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-iclb8/igt@gem_exec_schedule@preempt-bsd.html

  * igt@gem_exec_schedule@promotion-bsd1:
    - shard-iclb:         [SKIP][42] ([fdo#109276]) -> [PASS][43] +18 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-iclb5/igt@gem_exec_schedule@promotion-bsd1.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-iclb2/igt@gem_exec_schedule@promotion-bsd1.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-snoop:
    - shard-hsw:          [FAIL][44] ([i915#694]) -> [PASS][45] +1 similar issue
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-hsw1/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-hsw4/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html

  * igt@gem_softpin@noreloc-s3:
    - shard-apl:          [DMESG-WARN][46] ([i915#180]) -> [PASS][47] +1 similar issue
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-apl6/igt@gem_softpin@noreloc-s3.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-apl4/igt@gem_softpin@noreloc-s3.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-snb:          [DMESG-WARN][48] ([fdo#111870] / [i915#478]) -> [PASS][49]
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-snb2/igt@gem_userptr_blits@dmabuf-sync.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-snb6/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-glk:          [INCOMPLETE][50] ([i915#58] / [k.org#198133]) -> [PASS][51]
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-glk8/igt@gen9_exec_parse@allowed-all.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-glk8/igt@gen9_exec_parse@allowed-all.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
    - shard-glk:          [FAIL][52] ([i915#79]) -> [PASS][53]
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - shard-kbl:          [DMESG-WARN][54] ([i915#180]) -> [PASS][55] +5 similar issues
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-kbl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         [SKIP][56] ([fdo#109441]) -> [PASS][57] +1 similar issue
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-iclb8/igt@kms_psr@psr2_sprite_plane_move.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html

  * igt@kms_setmode@basic:
    - shard-apl:          [FAIL][58] ([i915#31]) -> [PASS][59]
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-apl7/igt@kms_setmode@basic.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-apl6/igt@kms_setmode@basic.html

  * igt@perf@disabled-read-error:
    - shard-iclb:         [DMESG-WARN][60] ([i915#645]) -> [PASS][61]
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-iclb2/igt@perf@disabled-read-error.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-iclb1/igt@perf@disabled-read-error.html

  * igt@perf_pmu@busy-accuracy-2-vcs1:
    - shard-iclb:         [SKIP][62] ([fdo#112080]) -> [PASS][63] +8 similar issues
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-iclb3/igt@perf_pmu@busy-accuracy-2-vcs1.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-iclb2/igt@perf_pmu@busy-accuracy-2-vcs1.html

  * igt@prime_mmap_coherency@read:
    - shard-hsw:          [FAIL][64] ([i915#914]) -> [PASS][65]
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-hsw1/igt@prime_mmap_coherency@read.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-hsw7/igt@prime_mmap_coherency@read.html

  
#### Warnings ####

  * igt@gem_eio@in-flight-10ms:
    - shard-apl:          [INCOMPLETE][66] ([CI#80] / [fdo#103927]) -> [TIMEOUT][67] ([fdo#112271])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-apl4/igt@gem_eio@in-flight-10ms.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-apl6/igt@gem_eio@in-flight-10ms.html

  * igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing:
    - shard-snb:          [DMESG-FAIL][68] ([i915#1045]) -> [FAIL][69] ([i915#1045])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-snb2/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-snb5/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing.html

  * igt@gem_tiled_blits@interruptible:
    - shard-hsw:          [FAIL][70] ([i915#694]) -> [FAIL][71] ([i915#818])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-hsw2/igt@gem_tiled_blits@interruptible.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-hsw1/igt@gem_tiled_blits@interruptible.html

  * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
    - shard-snb:          [DMESG-WARN][72] ([fdo#110789] / [fdo#111870] / [i915#478]) -> [DMESG-WARN][73] ([fdo#111870] / [i915#478])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-snb2/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-snb1/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html

  * igt@i915_pm_rpm@cursor-dpms:
    - shard-snb:          [SKIP][74] ([fdo#109271]) -> [INCOMPLETE][75] ([i915#82])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-snb6/igt@i915_pm_rpm@cursor-dpms.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-snb6/igt@i915_pm_rpm@cursor-dpms.html

  * igt@i915_suspend@debugfs-reader:
    - shard-kbl:          [DMESG-WARN][76] ([i915#180]) -> [INCOMPLETE][77] ([fdo#103665])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-kbl4/igt@i915_suspend@debugfs-reader.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-kbl1/igt@i915_suspend@debugfs-reader.html

  * igt@perf@gen12-mi-rpc:
    - shard-tglb:         [TIMEOUT][78] ([fdo#112271] / [i915#472]) -> [TIMEOUT][79] ([fdo#112271] / [i915#1085] / [i915#472])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5396/shard-tglb2/igt@perf@gen12-mi-rpc.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/shard-tglb7/igt@perf@gen12-mi-rpc.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110789]: https://bugs.freedesktop.org/show_bug.cgi?id=110789
  [fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
  [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
  [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
  [i915#1045]: https://gitlab.freedesktop.org/drm/intel/issues/1045
  [i915#1085]: https://gitlab.freedesktop.org/drm/intel/issues/1085
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
  [i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413
  [i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472
  [i915#478]: https://gitlab.freedesktop.org/drm/intel/issues/478
  [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58
  [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
  [i915#616]: https://gitlab.freedesktop.org/drm/intel/issues/616
  [i915#645]: https://gitlab.freedesktop.org/drm/intel/issues/645
  [i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
  [i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#818]: https://gitlab.freedesktop.org/drm/intel/issues/818
  [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
  [i915#831]: https://gitlab.freedesktop.org/drm/intel/issues/831
  [i915#914]: https://gitlab.freedesktop.org/drm/intel/issues/914
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (8 -> 8)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5396 -> IGTPW_4024

  CI-20190529: 20190529
  CI_DRM_7833: 8210f0f999e2d396a8611e0cabc2f6c6a52468de @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_4024: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/index.html
  IGT_5396: b85f96d6aa71795684b14d3b3d4c752dd61ff62e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4024/index.html
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[igt-dev] [PATCH i-g-t 5/7] tests/kms_hdr: Add function to check HDR panel

[Swati Sharma]

EDID of connected panel needs to be parsed to detect whether
panel can drive hdr or not. Added new function is_panel_hdr(),
to know about hdr capabilities of panel. If panel supports hdr
then only tests will get executed else skipped.

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Suggested-by: Kunal Joshi <kunal1.joshi@intel.com>
---
 tests/kms_hdr.c | 87 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 87 insertions(+)

diff --git a/tests/kms_hdr.c b/tests/kms_hdr.c
index c48e43e9..7e48f5a2 100644
--- a/tests/kms_hdr.c
+++ b/tests/kms_hdr.c
@@ -24,9 +24,22 @@
 #include <fcntl.h>
 #include <termios.h>
 #include <unistd.h>
+#include "igt_edid.h"
 
 IGT_TEST_DESCRIPTION("Test HDR metadata interfaces and bpc switch");
 
+/* HDR EDID parsing. */
+#define CTA_EXTENSION_VERSION		0x03
+#define HDR_STATIC_METADATA_BLOCK       0x06
+#define USE_EXTENDED_TAG		0x07
+
+/* DRM HDR definitions. Not in the UAPI header, unfortunately. */
+enum hdmi_eotf {
+	HDMI_EOTF_TRADITIONAL_GAMMA_SDR,
+	HDMI_EOTF_TRADITIONAL_GAMMA_HDR,
+	HDMI_EOTF_SMPTE_ST2084,
+};
+
 /* Test flags. */
 enum {
 	TEST_NONE = 0,
@@ -268,6 +281,80 @@ static void test_bpc_switch(data_t *data, uint32_t flags)
 	igt_require_f(valid_tests, "No connector found with MAX BPC connector property\n");
 }
 
+static bool cta_block(const char *edid_ext)
+{
+	/*
+	 * Byte 1: 0x07 indicates Extended Tag
+	 * Byte 2: 0x06 indicates HDMI Static Metadata Block
+	 * Byte 3: bits 0 to 5 identify EOTF functions supported by sink
+	 *	       where ET_0: Traditional Gamma - SDR Luminance Range
+	 *	             ET_1: Traditional Gamma - HDR Luminance Range
+	 *	             ET_2: SMPTE ST 2084
+	 *	             ET_3: Hybrid Log-Gamma (HLG)
+	 *	             ET_4 to ET_5: Reserved for future use
+	 */
+
+	if ((((edid_ext[0] & 0xe0) >> 5 == USE_EXTENDED_TAG) &&
+	      (edid_ext[1] == HDR_STATIC_METADATA_BLOCK)) &&
+	     ((edid_ext[2] & HDMI_EOTF_TRADITIONAL_GAMMA_HDR) ||
+	      (edid_ext[2] & HDMI_EOTF_SMPTE_ST2084)))
+			return true;
+
+	return false;
+}
+
+/* Returns true if panel supports hdr */
+static bool is_panel_hdr(data_t *data, igt_output_t *output)
+{
+	bool ok;
+	int i, j, offset;
+	uint64_t edid_blob_id;
+	drmModePropertyBlobRes *edid_blob;
+	const struct edid_ext *edid_ext;
+	const struct edid *edid;
+	const struct edid_cea *edid_cea;
+	const char *cea_data;
+	bool ret = false;
+
+	ok = kmstest_get_property(data->fd, output->id,
+			DRM_MODE_OBJECT_CONNECTOR, "EDID",
+			NULL, &edid_blob_id, NULL);
+
+	if (!ok || !edid_blob_id)
+		return ret;
+
+	edid_blob = drmModeGetPropertyBlob(data->fd, edid_blob_id);
+	igt_assert(edid_blob);
+
+	edid = (const struct edid *) edid_blob->data;
+	igt_assert(edid);
+
+	drmModeFreePropertyBlob(edid_blob);
+
+	for (i = 0; i < edid->extensions_len; i++) {
+		edid_ext = &edid->extensions[i];
+		edid_cea = &edid_ext->data.cea;
+
+		/* HDR not defined in CTA Extension Version < 3 */
+		if ((edid_ext->tag != EDID_EXT_CEA) ||
+		    (edid_cea->revision != CTA_EXTENSION_VERSION))
+			return ret;
+		else {
+			offset = edid_cea->dtd_start;
+			cea_data = edid_cea->data;
+
+			for (j = 0; j < offset; j += (cea_data[j] & 0x1f) + 1) {
+				ret = cta_block(cea_data + j);
+
+				if (ret)
+					break;
+			}
+		}
+	}
+
+	return ret;
+}
+
 igt_main
 {
 	data_t data = { 0 };
-- 
2.24.1

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